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    drm/i915/gen9: Add framework to whitelist specific GPU registers · 33136b06
    Arun Siluvery 提交于
    Some of the HW registers are privileged and cannot be written to from
    non-privileged batch buffers coming from userspace unless they are added to
    the HW whitelist. This whitelist is maintained by HW and it is different from
    SW whitelist. Userspace need write access to them to implement preemption
    related WA.
    
    The reason for using this approach is, the register bits that control
    preemption granularity at the HW level are not context save/restored; so even
    if we set these bits always in kernel they are going to change once the
    context is switched out.  We can consider making them non-privileged by
    default but these registers also contain other chicken bits which should not
    be allowed to be modified.
    
    In the later revisions controlling bits are save/restored at context level but
    in the existing revisions these are exported via other debug registers and
    should be on the whitelist. This patch adds changes to provide HW with a list
    of registers to be whitelisted. HW checks this list during execution and
    provides access accordingly.
    
    HW imposes a limit on the number of registers on whitelist and it is
    per-engine.  At this point we are only enabling whitelist for RCS and we don't
    foresee any requirement for other engines.
    
    The registers to be whitelisted are added using generic workaround list
    mechanism, even these are only enablers for userspace workarounds. But by
    sharing this mechanism we get some test assets without additional cost (Mika).
    
    v2: rebase
    
    v3: parameterize RING_FORCE_TO_NONPRIV() as _MMIO() should be limited to
    i915_reg.h (Ville), drop inline for wa_ring_whitelist_reg (Mika).
    
    v4: improvements suggested by Chris Wilson.
    Clarify that this is HW whitelist and different from the one maintained in
    driver. This list is engine specific but it gets initialized along with other
    WA which is RCS specific thing, so make it clear that we are not doing any
    cross engine setup during initialization.
    Make HW whitelist count of each engine available in debugfs.
    Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
    Reviewed-by: NMika Kuoppala <mika.kuoppala@intel.com>
    Cc: Mika Kuoppala <mika.kuoppala@intel.com>
    Cc: Chris Wilson <chris@chris-wilson.co.uk>
    Signed-off-by: NArun Siluvery <arun.siluvery@linux.intel.com>
    Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-2-git-send-email-arun.siluvery@linux.intel.comSigned-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
    33136b06
intel_ringbuffer.c 85.1 KB