The "data" region of the PolarFire SoC's system controller mailbox is
not one continuous register space - the system controller's QSPI sits
between the control and data registers. Split the "data" reg into two
parts: "data" & "control". Optionally get the "data" register address
from the 3rd reg property in the devicetree & fall back to using the
old base + MAILBOX_REG_OFFSET that the current code uses.

Fixes: 83d7b156 ("mbox: add polarfire soc system controller mailbox")
Signed-off-by: NConor Dooley <conor.dooley@microchip.com>
Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>