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    clk: rockchip: Fix PLL bandwidth · 2bbfe001
    Douglas Anderson 提交于
    In the TRM we see that BWADJ is "a 12-bit bus that selects the values
    1-4096 for the bandwidth divider (NB)":
     NB = BWADJ[11:0] + 1
    The recommended setting of NB: NB = NF / 2.
    
    So:
      NB = NF / 2
      BWADJ[11:0] + 1 = NF / 2
      BWADJ[11:0] = NF / 2 - 1
    
    Right now, we have:
    
    {                                               \
            .rate   = _rate##U,                     \
            .nr = _nr,                              \
            .nf = _nf,                              \
            .no = _no,                              \
            .bwadj = (_nf >> 1),                    \
    }
    
    That means we set bwadj to NF / 2, not NF / 2 - 1
    
    All of this is a bit confusing because we specify "NR" (the 1-based
    value), "NF" (the 1-based value), "NO" (the 1-based value), but
    "BWADJ" (the 0-based value) instead of "NB" (the 1-based value).
    
    Let's change to working with "NB" and fix the off by one error.  This
    may affect PLL jitter in a small way (hopefully for the better).
    Signed-off-by: NDouglas Anderson <dianders@chromium.org>
    Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
    Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
    2bbfe001
clk-rk3188.c 32.7 KB