1. Bump top level address-cells/size-cells nodes to 2 (to ensure all
   down stream addresses are 64-bits, unless explicitly specified
   otherwise (in "soc" bus with all peripherals)

2. "memory" also specified with address/size 2

3. Add a commented reference for PAE40 region beyond 4GB physical
   address space
Signed-off-by: NVineet Gupta <vgupta@synopsys.com>