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由 Mugunthan V N 提交于
In CPSW NAPI, after processing all interrupts IRQ is enabled and then book keeping irq_enabled is updated. In random cases when a packet is transmitted or received between processing packets and IRQ enabled, then just after enabled IRQ and before irq_enabled is updated, ISR is called so IRQs are not disabled as irq_enabled is still false and CPU gets locked in CPSW ISR. By changing the sequence as update the irq_enabled and then enable IRQ fixes the issue. This issue is not captured always as it is a timing issue whether Tx or Rx IRQ is invoked between packet processing and enable IRQ. Cc: Sebastian Siewior <bigeasy@linutronix.de> Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com> Acked-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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