Since the SDMMC controller registers are accessed via the APB,
the APB must be flushed before gating the SDMMC clocks to prevent
register accesses to the SDMMC controllers after their clocks are
gated.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>