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    drm/i915/dp: Validate cached link rate and lane count before retraining · 14c562c0
    Manasi Navare 提交于
    Currently intel_dp_check_link_status() tries to retrain the link if
    Clock recovery or Channel EQ for any of the lanes indicated by
    intel_dp->lane_count is not set. However these values cached in intel_dp
    structure can be stale if link training has failed for these values
    during previous modeset. Or these values can get stale since we have
    now re read the DPCD registers or it can be 0 in case of connected boot
    case.
    
    This patch validates these values against the max link rate and max lane
    count values.
    
    This is absolutely required incase the common_rates or max lane count
    are now different due to link fallback.
    
    v2:
    * Include the FIXME commnet inside the function (Ville Syrjala)
    * Remove the redundant parenthesis (Ville Syrjala)
    
    v3 by Jani:
    * rebase on the DP refactoring series
    * rename intel_dp_link_params_is_valid to intel_dp_link_params_valid
    * minor stylistic changes
    
    v4:
    * Compare the link rate against max link rate not the
    common_rates since common_rates does not account for the
    lowered fallback link rate value. (Ville Syrjala)
    
    v5:
    * Fixed a warning for unused variable (Manasi)
    
    Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
    Cc: Jani Nikula <jani.nikula@linux.intel.com>
    Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
    Signed-off-by: NManasi Navare <manasi.d.navare@intel.com>
    Signed-off-by: NJani Nikula <jani.nikula@intel.com>
    Link: http://patchwork.freedesktop.org/patch/msgid/1491512412-30016-1-git-send-email-manasi.d.navare@intel.com
    14c562c0
intel_dp.c 170.2 KB