NPS device got 256 cores and each got 16 HW threads (SMT).
We use EZchip dedicated ISA to trigger HW scheduler of the
core that current HW thread belongs to.
This scheduling makes sure that data beyond barrier is available
to all HW threads in core and by that to all in device (4K).
Signed-off-by: NNoam Camus <noamc@ezchip.com>
Cc: Peter Zijlstra <peterz@infradead.org>