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由 Aaron Brice 提交于
- The DMA error interrupt bit is in a different position as compared to the sdhci standard. This is accounted for in many cases, but not handled in the case of clearing the INT_STATUS register by writing a 1 to that location. - The HOST_CONTROL register is very different as compared to the sdhci standard. This is accounted for in the write case, but not when read back out (which it is in the sdhci code). Signed-off-by: NDave Russell <david.russell@datasoft.com> Signed-off-by: NAaron Brice <aaron.brice@datasoft.com> Acked-by: NDong Aisheng <aisheng.dong@nxp.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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