• S
    ARM: imx: clk-vf610: fix SAI clock tree · 3b60a26f
    Stefan Agner 提交于
    The Synchronous Audio Interface (SAI) instances are clocked by
    independent clocks: The bus clock and the audio clock (as shown in
    Figure 51-1 in the Vybrid Reference Manual). The clock gates in
    CCGR0/CCGR1 for SAI0 through SAI3 are bus clock gates, as access
    tests to the registers with/without gating those clocks have shown.
    The audio clock is gated by the SAIx_EN gates in CCM_CSCDR1,
    followed by a clock divider (SAIx_DIV). Currently, the parent of
    the bus clock gates has been assigned to SAIx_DIV, which is not
    involved in the bus clock path for the SAI instances (see chapter
    9.10.12, SAI clocking in the Vybrid Reference Manual).
    
    Fix this by define the parent clock of VF610_CLK_SAIx to be the bus
    clock.
    
    If the driver needs the audio clock (when used in master mode), a
    fixed device tree is required which assign the audio clock properly
    to VF610_CLK_SAIx_DIV.
    Signed-off-by: NStefan Agner <stefan@agner.ch>
    Acked-by: NStephen Boyd <sboyd@codeaurora.org>
    Signed-off-by: NShawn Guo <shawnguo@kernel.org>
    3b60a26f
clk-vf610.c 24.2 KB