• M
    mach64: detect the dot clock divider correctly on sparc · 76ebebd2
    Mikulas Patocka 提交于
    On Sun Ultra 5, it happens that the dot clock is not set up properly for
    some videomodes. For example, if we set the videomode "r1024x768x60" in
    the firmware, Linux would incorrectly set a videomode with refresh rate
    180Hz when booting (suprisingly, my LCD monitor can display it, although
    display quality is very low).
    
    The reason is this: Older mach64 cards set the divider in the register
    VCLK_POST_DIV. The register has four 2-bit fields (the field that is
    actually used is specified in the lowest two bits of the register
    CLOCK_CNTL). The 2 bits select divider "1, 2, 4, 8". On newer mach64 cards,
    there's another bit added - the top four bits of PLL_EXT_CNTL extend the
    divider selection, so we have possible dividers "1, 2, 4, 8, 3, 5, 6, 12".
    The Linux driver clears the top four bits of PLL_EXT_CNTL and never sets
    them, so it can work regardless if the card supports them. However, the
    sparc64 firmware may set these extended dividers during boot - and the
    mach64 driver detects incorrect dot clock in this case.
    
    This patch makes the driver read the additional divider bit from
    PLL_EXT_CNTL and calculate the initial refresh rate properly.
    Signed-off-by: NMikulas Patocka <mpatocka@redhat.com>
    Cc: stable@vger.kernel.org
    Acked-by: NDavid S. Miller <davem@davemloft.net>
    Reviewed-by: NVille Syrjälä <syrjala@sci.fi>
    Signed-off-by: NDavid S. Miller <davem@davemloft.net>
    76ebebd2
atyfb_base.c 108.6 KB