The HiSilicon ZIP accelerator implements the zlib and gzip algorithm. It
uses Hisilicon QM as the interface to the CPU.

This patch provides PCIe driver to the accelerator and registers it to
crypto acomp interface. It also uses sgl as data input/output interface.
Signed-off-by: NZhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: NShiju Jose <shiju.jose@huawei.com>
Signed-off-by: NKenneth Lee <liguozhu@hisilicon.com>
Signed-off-by: NHao Fang <fanghao11@huawei.com>
Reviewed-by: NJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: NJohn Garry <john.garry@huawei.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>