pciehp_hpc.c 23.5 KB
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/*
 * PCI Express PCI Hot Plug Driver
 *
 * Copyright (C) 1995,2001 Compaq Computer Corporation
 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
 * Copyright (C) 2001 IBM Corp.
 * Copyright (C) 2003-2004 Intel Corporation
 *
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 * NON INFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
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 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
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 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
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#include <linux/signal.h>
#include <linux/jiffies.h>
#include <linux/timer.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/slab.h>
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#include "../pci.h"
#include "pciehp.h"

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static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
{
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	struct pci_dev *dev = ctrl->pcie->port;
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	return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
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}

static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
{
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	struct pci_dev *dev = ctrl->pcie->port;
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	return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
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}

static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
{
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	struct pci_dev *dev = ctrl->pcie->port;
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	return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
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}

static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
{
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	struct pci_dev *dev = ctrl->pcie->port;
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	return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
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}
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/* Power Control Command */
#define POWER_ON	0
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#define POWER_OFF	PCI_EXP_SLTCTL_PCC
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static irqreturn_t pcie_isr(int irq, void *dev_id);
static void start_int_poll_timer(struct controller *ctrl, int sec);
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/* This is the interrupt polling timeout function. */
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static void int_poll_timeout(unsigned long data)
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{
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	struct controller *ctrl = (struct controller *)data;
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	/* Poll for interrupt events.  regs == NULL => polling */
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	pcie_isr(0, ctrl);
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	init_timer(&ctrl->poll_timer);
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	if (!pciehp_poll_time)
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		pciehp_poll_time = 2; /* default polling interval is 2 sec */
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	start_int_poll_timer(ctrl, pciehp_poll_time);
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}

/* This function starts the interrupt polling timer. */
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static void start_int_poll_timer(struct controller *ctrl, int sec)
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{
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	/* Clamp to sane value */
	if ((sec <= 0) || (sec > 60))
        	sec = 2;

	ctrl->poll_timer.function = &int_poll_timeout;
	ctrl->poll_timer.data = (unsigned long)ctrl;
	ctrl->poll_timer.expires = jiffies + sec * HZ;
	add_timer(&ctrl->poll_timer);
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}

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static inline int pciehp_request_irq(struct controller *ctrl)
{
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	int retval, irq = ctrl->pcie->irq;
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	/* Install interrupt polling timer. Start with 10 sec delay */
	if (pciehp_poll_mode) {
		init_timer(&ctrl->poll_timer);
		start_int_poll_timer(ctrl, 10);
		return 0;
	}

	/* Installs the interrupt handler */
	retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
	if (retval)
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		ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
			 irq);
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	return retval;
}

static inline void pciehp_free_irq(struct controller *ctrl)
{
	if (pciehp_poll_mode)
		del_timer_sync(&ctrl->poll_timer);
	else
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		free_irq(ctrl->pcie->irq, ctrl);
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}

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static int pcie_poll_cmd(struct controller *ctrl)
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{
	u16 slot_status;
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	int err, timeout = 1000;
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	err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
	if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
		pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
		return 1;
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	}
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	while (timeout > 0) {
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		msleep(10);
		timeout -= 10;
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		err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
		if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
			pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
			return 1;
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		}
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	}
	return 0;	/* timeout */
}

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static void pcie_wait_cmd(struct controller *ctrl, int poll)
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{
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	unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
	unsigned long timeout = msecs_to_jiffies(msecs);
	int rc;

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	if (poll)
		rc = pcie_poll_cmd(ctrl);
	else
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		rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
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	if (!rc)
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		ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
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}

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/**
 * pcie_write_cmd - Issue controller command
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 * @ctrl: controller to which the command is issued
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 * @cmd:  command value written to slot control register
 * @mask: bitmask of slot control register to be modified
 */
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static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
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{
	int retval = 0;
	u16 slot_status;
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	u16 slot_ctrl;
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	mutex_lock(&ctrl->ctrl_lock);

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	retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
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	if (retval) {
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		ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
			 __func__);
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		goto out;
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	}

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	if (slot_status & PCI_EXP_SLTSTA_CC) {
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		if (!ctrl->no_cmd_complete) {
			/*
			 * After 1 sec and CMD_COMPLETED still not set, just
			 * proceed forward to issue the next command according
			 * to spec. Just print out the error message.
			 */
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			ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
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		} else if (!NO_CMD_CMPL(ctrl)) {
			/*
			 * This controller semms to notify of command completed
			 * event even though it supports none of power
			 * controller, attention led, power led and EMI.
			 */
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			ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
				 "wait for command completed event.\n");
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			ctrl->no_cmd_complete = 0;
		} else {
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			ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
				 "the controller is broken.\n");
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		}
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	}

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	retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
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	if (retval) {
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		ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
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		goto out;
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	}

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	slot_ctrl &= ~mask;
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	slot_ctrl |= (cmd & mask);
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	ctrl->cmd_busy = 1;
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	smp_mb();
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	retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
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	if (retval)
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		ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
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	/*
	 * Wait for command completion.
	 */
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	if (!retval && !ctrl->no_cmd_complete) {
		int poll = 0;
		/*
		 * if hotplug interrupt is not enabled or command
		 * completed interrupt is not enabled, we need to poll
		 * command completed event.
		 */
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		if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
		    !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
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			poll = 1;
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                pcie_wait_cmd(ctrl, poll);
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	}
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 out:
	mutex_unlock(&ctrl->ctrl_lock);
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	return retval;
}

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static inline int check_link_active(struct controller *ctrl)
{
	u16 link_status;

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	if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
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		return 0;
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	return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
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}

static void pcie_wait_link_active(struct controller *ctrl)
{
	int timeout = 1000;

	if (check_link_active(ctrl))
		return;
	while (timeout > 0) {
		msleep(10);
		timeout -= 10;
		if (check_link_active(ctrl))
			return;
	}
	ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
}

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int pciehp_check_link_status(struct controller *ctrl)
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{
	u16 lnk_status;
	int retval = 0;

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        /*
         * Data Link Layer Link Active Reporting must be capable for
         * hot-plug capable downstream port. But old controller might
         * not implement it. In this case, we wait for 1000 ms.
         */
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        if (ctrl->link_active_reporting)
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                pcie_wait_link_active(ctrl);
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        else
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                msleep(1000);

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	/*
	 * Need to wait for 1000 ms after Data Link Layer Link Active
	 * (DLLLA) bit reads 1b before sending configuration request.
	 * We need it before checking Link Training (LT) bit becuase
	 * LT is still set even after DLLLA bit is set on some platform.
	 */
	msleep(1000);

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	retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
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	if (retval) {
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		ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
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		return retval;
	}

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	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
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	if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
	    !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
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		ctrl_err(ctrl, "Link Training Error occurs \n");
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		retval = -1;
		return retval;
	}

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	/*
	 * If the port supports Link speeds greater than 5.0 GT/s, we
	 * must wait for 100 ms after Link training completes before
	 * sending configuration request.
	 */
	if (ctrl->pcie->port->subordinate->max_bus_speed > PCIE_SPEED_5_0GT)
		msleep(100);

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	pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);

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	return retval;
}

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int pciehp_get_attention_status(struct slot *slot, u8 *status)
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{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_ctrl;
	u8 atten_led_state;
	int retval = 0;

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	retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
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	if (retval) {
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		ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
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		return retval;
	}

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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
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	atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
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	switch (atten_led_state) {
	case 0:
		*status = 0xFF;	/* Reserved */
		break;
	case 1:
		*status = 1;	/* On */
		break;
	case 2:
		*status = 2;	/* Blink */
		break;
	case 3:
		*status = 0;	/* Off */
		break;
	default:
		*status = 0xFF;
		break;
	}

	return 0;
}

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int pciehp_get_power_status(struct slot *slot, u8 *status)
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{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_ctrl;
	u8 pwr_state;
	int	retval = 0;

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	retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
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	if (retval) {
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		ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
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		return retval;
	}
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
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	pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
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	switch (pwr_state) {
	case 0:
		*status = 1;
		break;
	case 1:
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		*status = 0;
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		break;
	default:
		*status = 0xFF;
		break;
	}

	return retval;
}

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int pciehp_get_latch_status(struct slot *slot, u8 *status)
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{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_status;
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	int retval;
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	retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
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	if (retval) {
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		ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
			 __func__);
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		return retval;
	}
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	*status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
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	return 0;
}

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int pciehp_get_adapter_status(struct slot *slot, u8 *status)
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{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_status;
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	int retval;
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	retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
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	if (retval) {
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		ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
			 __func__);
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		return retval;
	}
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	*status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
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	return 0;
}

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int pciehp_query_power_fault(struct slot *slot)
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{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_status;
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	int retval;
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	retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
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	if (retval) {
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		ctrl_err(ctrl, "Cannot check for power fault\n");
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		return retval;
	}
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	return !!(slot_status & PCI_EXP_SLTSTA_PFD);
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}

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int pciehp_set_attention_status(struct slot *slot, u8 value)
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{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_cmd;
	u16 cmd_mask;
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	cmd_mask = PCI_EXP_SLTCTL_AIC;
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	switch (value) {
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	case 0 :	/* turn off */
		slot_cmd = 0x00C0;
		break;
	case 1:		/* turn on */
		slot_cmd = 0x0040;
		break;
	case 2:		/* turn blink */
		slot_cmd = 0x0080;
		break;
	default:
		return -EINVAL;
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	}
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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	return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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}

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void pciehp_green_led_on(struct slot *slot)
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{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_cmd;
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	u16 cmd_mask;
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	slot_cmd = 0x0100;
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	cmd_mask = PCI_EXP_SLTCTL_PIC;
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	pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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}

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void pciehp_green_led_off(struct slot *slot)
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{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_cmd;
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	u16 cmd_mask;
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	slot_cmd = 0x0300;
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	cmd_mask = PCI_EXP_SLTCTL_PIC;
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	pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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}

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void pciehp_green_led_blink(struct slot *slot)
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{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_cmd;
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	u16 cmd_mask;
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	slot_cmd = 0x0200;
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	cmd_mask = PCI_EXP_SLTCTL_PIC;
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	pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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}

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int pciehp_power_on_slot(struct slot * slot)
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{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_cmd;
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	u16 cmd_mask;
	u16 slot_status;
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	int retval = 0;

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	/* Clear sticky power-fault bit from previous power failures */
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	retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
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	if (retval) {
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		ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
			 __func__);
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		return retval;
	}
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	slot_status &= PCI_EXP_SLTSTA_PFD;
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	if (slot_status) {
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		retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
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		if (retval) {
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			ctrl_err(ctrl,
				 "%s: Cannot write to SLOTSTATUS register\n",
				 __func__);
521 522 523
			return retval;
		}
	}
524
	ctrl->power_fault_detected = 0;
L
Linus Torvalds 已提交
525

526
	slot_cmd = POWER_ON;
527
	cmd_mask = PCI_EXP_SLTCTL_PCC;
528
	retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
L
Linus Torvalds 已提交
529
	if (retval) {
530
		ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
531
		return retval;
L
Linus Torvalds 已提交
532
	}
K
Kenji Kaneshige 已提交
533 534
	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
L
Linus Torvalds 已提交
535 536 537 538

	return retval;
}

K
Kenji Kaneshige 已提交
539
int pciehp_power_off_slot(struct slot * slot)
L
Linus Torvalds 已提交
540
{
541
	struct controller *ctrl = slot->ctrl;
L
Linus Torvalds 已提交
542
	u16 slot_cmd;
543
	u16 cmd_mask;
544
	int retval;
545

546
	slot_cmd = POWER_OFF;
547
	cmd_mask = PCI_EXP_SLTCTL_PCC;
548
	retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
L
Linus Torvalds 已提交
549
	if (retval) {
550
		ctrl_err(ctrl, "Write command failed!\n");
551
		return retval;
L
Linus Torvalds 已提交
552
	}
K
Kenji Kaneshige 已提交
553 554
	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
555
	return 0;
L
Linus Torvalds 已提交
556 557
}

558
static irqreturn_t pcie_isr(int irq, void *dev_id)
L
Linus Torvalds 已提交
559
{
560
	struct controller *ctrl = (struct controller *)dev_id;
561
	struct slot *slot = ctrl->slot;
562
	u16 detected, intr_loc;
L
Linus Torvalds 已提交
563

564 565 566 567 568 569 570
	/*
	 * In order to guarantee that all interrupt events are
	 * serviced, we need to re-inspect Slot Status register after
	 * clearing what is presumed to be the last pending interrupt.
	 */
	intr_loc = 0;
	do {
571
		if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
572 573
			ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
				 __func__);
L
Linus Torvalds 已提交
574 575 576
			return IRQ_NONE;
		}

577 578 579
		detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
			     PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
			     PCI_EXP_SLTSTA_CC);
580
		detected &= ~intr_loc;
581 582
		intr_loc |= detected;
		if (!intr_loc)
L
Linus Torvalds 已提交
583
			return IRQ_NONE;
584
		if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
585 586
			ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
				 __func__);
L
Linus Torvalds 已提交
587 588
			return IRQ_NONE;
		}
589
	} while (detected);
590

591
	ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
592

593
	/* Check Command Complete Interrupt Pending */
594
	if (intr_loc & PCI_EXP_SLTSTA_CC) {
595
		ctrl->cmd_busy = 0;
596
		smp_mb();
597
		wake_up(&ctrl->queue);
L
Linus Torvalds 已提交
598 599
	}

600
	if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
601 602
		return IRQ_HANDLED;

603
	/* Check MRL Sensor Changed */
604
	if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
605
		pciehp_handle_switch_change(slot);
606

607
	/* Check Attention Button Pressed */
608
	if (intr_loc & PCI_EXP_SLTSTA_ABP)
609
		pciehp_handle_attention_button(slot);
610

611
	/* Check Presence Detect Changed */
612
	if (intr_loc & PCI_EXP_SLTSTA_PDC)
613
		pciehp_handle_presence_change(slot);
614

615
	/* Check Power Fault Detected */
616 617
	if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
		ctrl->power_fault_detected = 1;
618
		pciehp_handle_power_fault(slot);
619
	}
L
Linus Torvalds 已提交
620 621 622
	return IRQ_HANDLED;
}

K
Kenji Kaneshige 已提交
623
int pciehp_get_max_lnk_width(struct slot *slot,
624
				 enum pcie_link_width *value)
L
Linus Torvalds 已提交
625
{
626
	struct controller *ctrl = slot->ctrl;
L
Linus Torvalds 已提交
627 628 629 630
	enum pcie_link_width lnk_wdth;
	u32	lnk_cap;
	int retval = 0;

631
	retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
L
Linus Torvalds 已提交
632
	if (retval) {
633
		ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
L
Linus Torvalds 已提交
634 635 636
		return retval;
	}

637
	switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
L
Linus Torvalds 已提交
638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667
	case 0:
		lnk_wdth = PCIE_LNK_WIDTH_RESRV;
		break;
	case 1:
		lnk_wdth = PCIE_LNK_X1;
		break;
	case 2:
		lnk_wdth = PCIE_LNK_X2;
		break;
	case 4:
		lnk_wdth = PCIE_LNK_X4;
		break;
	case 8:
		lnk_wdth = PCIE_LNK_X8;
		break;
	case 12:
		lnk_wdth = PCIE_LNK_X12;
		break;
	case 16:
		lnk_wdth = PCIE_LNK_X16;
		break;
	case 32:
		lnk_wdth = PCIE_LNK_X32;
		break;
	default:
		lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
		break;
	}

	*value = lnk_wdth;
668
	ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
K
Kenji Kaneshige 已提交
669

L
Linus Torvalds 已提交
670 671 672
	return retval;
}

K
Kenji Kaneshige 已提交
673
int pciehp_get_cur_lnk_width(struct slot *slot,
674
				 enum pcie_link_width *value)
L
Linus Torvalds 已提交
675
{
676
	struct controller *ctrl = slot->ctrl;
L
Linus Torvalds 已提交
677 678 679 680
	enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
	int retval = 0;
	u16 lnk_status;

681
	retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
L
Linus Torvalds 已提交
682
	if (retval) {
683 684
		ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
			 __func__);
L
Linus Torvalds 已提交
685 686
		return retval;
	}
687

688
	switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
L
Linus Torvalds 已提交
689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718
	case 0:
		lnk_wdth = PCIE_LNK_WIDTH_RESRV;
		break;
	case 1:
		lnk_wdth = PCIE_LNK_X1;
		break;
	case 2:
		lnk_wdth = PCIE_LNK_X2;
		break;
	case 4:
		lnk_wdth = PCIE_LNK_X4;
		break;
	case 8:
		lnk_wdth = PCIE_LNK_X8;
		break;
	case 12:
		lnk_wdth = PCIE_LNK_X12;
		break;
	case 16:
		lnk_wdth = PCIE_LNK_X16;
		break;
	case 32:
		lnk_wdth = PCIE_LNK_X32;
		break;
	default:
		lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
		break;
	}

	*value = lnk_wdth;
719
	ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
K
Kenji Kaneshige 已提交
720

L
Linus Torvalds 已提交
721 722 723
	return retval;
}

724
int pcie_enable_notification(struct controller *ctrl)
M
Mark Lord 已提交
725
{
726
	u16 cmd, mask;
L
Linus Torvalds 已提交
727

728 729 730 731 732 733 734 735 736 737
	/*
	 * TBD: Power fault detected software notification support.
	 *
	 * Power fault detected software notification is not enabled
	 * now, because it caused power fault detected interrupt storm
	 * on some machines. On those machines, power fault detected
	 * bit in the slot status register was set again immediately
	 * when it is cleared in the interrupt service routine, and
	 * next power fault detected interrupt was notified again.
	 */
738
	cmd = PCI_EXP_SLTCTL_PDCE;
739
	if (ATTN_BUTTN(ctrl))
740
		cmd |= PCI_EXP_SLTCTL_ABPE;
741
	if (MRL_SENS(ctrl))
742
		cmd |= PCI_EXP_SLTCTL_MRLSCE;
743
	if (!pciehp_poll_mode)
744
		cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
745

746 747 748
	mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
		PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
		PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
749 750

	if (pcie_write_cmd(ctrl, cmd, mask)) {
751
		ctrl_err(ctrl, "Cannot enable software notification\n");
752
		return -1;
L
Linus Torvalds 已提交
753
	}
754 755 756 757 758 759
	return 0;
}

static void pcie_disable_notification(struct controller *ctrl)
{
	u16 mask;
760 761
	mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
		PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
762 763
		PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
		PCI_EXP_SLTCTL_DLLSCE);
764
	if (pcie_write_cmd(ctrl, 0, mask))
765
		ctrl_warn(ctrl, "Cannot disable software notification\n");
766 767
}

768
int pcie_init_notification(struct controller *ctrl)
769 770 771 772 773 774 775
{
	if (pciehp_request_irq(ctrl))
		return -1;
	if (pcie_enable_notification(ctrl)) {
		pciehp_free_irq(ctrl);
		return -1;
	}
776
	ctrl->notification_enabled = 1;
777 778 779 780 781
	return 0;
}

static void pcie_shutdown_notification(struct controller *ctrl)
{
782 783 784 785 786
	if (ctrl->notification_enabled) {
		pcie_disable_notification(ctrl);
		pciehp_free_irq(ctrl);
		ctrl->notification_enabled = 0;
	}
787 788 789 790 791 792 793 794 795 796 797 798 799
}

static int pcie_init_slot(struct controller *ctrl)
{
	struct slot *slot;

	slot = kzalloc(sizeof(*slot), GFP_KERNEL);
	if (!slot)
		return -ENOMEM;

	slot->ctrl = ctrl;
	mutex_init(&slot->lock);
	INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
800
	ctrl->slot = slot;
L
Linus Torvalds 已提交
801 802
	return 0;
}
803

804 805
static void pcie_cleanup_slot(struct controller *ctrl)
{
806
	struct slot *slot = ctrl->slot;
807 808 809 810 811
	cancel_delayed_work(&slot->work);
	flush_workqueue(pciehp_wq);
	kfree(slot);
}

K
Kenji Kaneshige 已提交
812
static inline void dbg_ctrl(struct controller *ctrl)
813
{
K
Kenji Kaneshige 已提交
814 815
	int i;
	u16 reg16;
816
	struct pci_dev *pdev = ctrl->pcie->port;
817

K
Kenji Kaneshige 已提交
818 819
	if (!pciehp_debug)
		return;
820

821 822 823 824 825 826 827 828 829
	ctrl_info(ctrl, "Hotplug Controller:\n");
	ctrl_info(ctrl, "  Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
		  pci_name(pdev), pdev->irq);
	ctrl_info(ctrl, "  Vendor ID            : 0x%04x\n", pdev->vendor);
	ctrl_info(ctrl, "  Device ID            : 0x%04x\n", pdev->device);
	ctrl_info(ctrl, "  Subsystem ID         : 0x%04x\n",
		  pdev->subsystem_device);
	ctrl_info(ctrl, "  Subsystem Vendor ID  : 0x%04x\n",
		  pdev->subsystem_vendor);
K
Kenji Kaneshige 已提交
830 831
	ctrl_info(ctrl, "  PCIe Cap offset      : 0x%02x\n",
		  pci_pcie_cap(pdev));
K
Kenji Kaneshige 已提交
832 833 834
	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
		if (!pci_resource_len(pdev, i))
			continue;
835 836
		ctrl_info(ctrl, "  PCI resource [%d]     : %pR\n",
			  i, &pdev->resource[i]);
837
	}
838
	ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
839
	ctrl_info(ctrl, "  Physical Slot Number : %d\n", PSN(ctrl));
840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855
	ctrl_info(ctrl, "  Attention Button     : %3s\n",
		  ATTN_BUTTN(ctrl) ? "yes" : "no");
	ctrl_info(ctrl, "  Power Controller     : %3s\n",
		  POWER_CTRL(ctrl) ? "yes" : "no");
	ctrl_info(ctrl, "  MRL Sensor           : %3s\n",
		  MRL_SENS(ctrl)   ? "yes" : "no");
	ctrl_info(ctrl, "  Attention Indicator  : %3s\n",
		  ATTN_LED(ctrl)   ? "yes" : "no");
	ctrl_info(ctrl, "  Power Indicator      : %3s\n",
		  PWR_LED(ctrl)    ? "yes" : "no");
	ctrl_info(ctrl, "  Hot-Plug Surprise    : %3s\n",
		  HP_SUPR_RM(ctrl) ? "yes" : "no");
	ctrl_info(ctrl, "  EMI Present          : %3s\n",
		  EMI(ctrl)        ? "yes" : "no");
	ctrl_info(ctrl, "  Command Completed    : %3s\n",
		  NO_CMD_CMPL(ctrl) ? "no" : "yes");
856
	pciehp_readw(ctrl, PCI_EXP_SLTSTA, &reg16);
857
	ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
858
	pciehp_readw(ctrl, PCI_EXP_SLTCTL, &reg16);
859
	ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
K
Kenji Kaneshige 已提交
860
}
861

862
struct controller *pcie_init(struct pcie_device *dev)
K
Kenji Kaneshige 已提交
863
{
864
	struct controller *ctrl;
865
	u32 slot_cap, link_cap;
K
Kenji Kaneshige 已提交
866
	struct pci_dev *pdev = dev->port;
867

868 869
	ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
	if (!ctrl) {
870
		dev_err(&dev->device, "%s: Out of memory\n", __func__);
871 872
		goto abort;
	}
873
	ctrl->pcie = dev;
K
Kenji Kaneshige 已提交
874
	if (!pci_pcie_cap(pdev)) {
875
		ctrl_err(ctrl, "Cannot find PCI Express capability\n");
876
		goto abort_ctrl;
877
	}
878
	if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
879
		ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
880
		goto abort_ctrl;
881 882
	}

K
Kenji Kaneshige 已提交
883
	ctrl->slot_cap = slot_cap;
884 885
	mutex_init(&ctrl->ctrl_lock);
	init_waitqueue_head(&ctrl->queue);
K
Kenji Kaneshige 已提交
886
	dbg_ctrl(ctrl);
K
Kenji Kaneshige 已提交
887 888 889 890 891 892 893 894 895
	/*
	 * Controller doesn't notify of command completion if the "No
	 * Command Completed Support" bit is set in Slot Capability
	 * register or the controller supports none of power
	 * controller, attention led, power led and EMI.
	 */
	if (NO_CMD_CMPL(ctrl) ||
	    !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
	    ctrl->no_cmd_complete = 1;
896

897
        /* Check if Data Link Layer Link Active Reporting is implemented */
898
        if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
899 900 901
                ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
                goto abort_ctrl;
        }
902
        if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
903 904 905 906
                ctrl_dbg(ctrl, "Link Active Reporting supported\n");
                ctrl->link_active_reporting = 1;
        }

907
	/* Clear all remaining event bits in Slot Status register */
908
	if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
909
		goto abort_ctrl;
910

911 912
	/* Disable sotfware notification */
	pcie_disable_notification(ctrl);
M
Mark Lord 已提交
913

914 915 916
	ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
		  pdev->vendor, pdev->device, pdev->subsystem_vendor,
		  pdev->subsystem_device);
917 918 919

	if (pcie_init_slot(ctrl))
		goto abort_ctrl;
K
Kenji Kaneshige 已提交
920

921 922 923 924
	return ctrl;

abort_ctrl:
	kfree(ctrl);
925
abort:
926 927 928
	return NULL;
}

K
Kenji Kaneshige 已提交
929
void pciehp_release_ctrl(struct controller *ctrl)
930 931 932 933
{
	pcie_shutdown_notification(ctrl);
	pcie_cleanup_slot(ctrl);
	kfree(ctrl);
934
}