ethoc.c 32.0 KB
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/*
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 * linux/drivers/net/ethernet/ethoc.c
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 *
 * Copyright (C) 2007-2008 Avionic Design Development GmbH
 * Copyright (C) 2008-2009 Avionic Design GmbH
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Written by Thierry Reding <thierry.reding@avionic-design.de>
 */

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#include <linux/dma-mapping.h>
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#include <linux/etherdevice.h>
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#include <linux/clk.h>
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#include <linux/crc32.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
#include <linux/mii.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/module.h>
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#include <net/ethoc.h>

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static int buffer_size = 0x8000; /* 32 KBytes */
module_param(buffer_size, int, 0);
MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");

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/* register offsets */
#define	MODER		0x00
#define	INT_SOURCE	0x04
#define	INT_MASK	0x08
#define	IPGT		0x0c
#define	IPGR1		0x10
#define	IPGR2		0x14
#define	PACKETLEN	0x18
#define	COLLCONF	0x1c
#define	TX_BD_NUM	0x20
#define	CTRLMODER	0x24
#define	MIIMODER	0x28
#define	MIICOMMAND	0x2c
#define	MIIADDRESS	0x30
#define	MIITX_DATA	0x34
#define	MIIRX_DATA	0x38
#define	MIISTATUS	0x3c
#define	MAC_ADDR0	0x40
#define	MAC_ADDR1	0x44
#define	ETH_HASH0	0x48
#define	ETH_HASH1	0x4c
#define	ETH_TXCTRL	0x50
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#define	ETH_END		0x54
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/* mode register */
#define	MODER_RXEN	(1 <<  0) /* receive enable */
#define	MODER_TXEN	(1 <<  1) /* transmit enable */
#define	MODER_NOPRE	(1 <<  2) /* no preamble */
#define	MODER_BRO	(1 <<  3) /* broadcast address */
#define	MODER_IAM	(1 <<  4) /* individual address mode */
#define	MODER_PRO	(1 <<  5) /* promiscuous mode */
#define	MODER_IFG	(1 <<  6) /* interframe gap for incoming frames */
#define	MODER_LOOP	(1 <<  7) /* loopback */
#define	MODER_NBO	(1 <<  8) /* no back-off */
#define	MODER_EDE	(1 <<  9) /* excess defer enable */
#define	MODER_FULLD	(1 << 10) /* full duplex */
#define	MODER_RESET	(1 << 11) /* FIXME: reset (undocumented) */
#define	MODER_DCRC	(1 << 12) /* delayed CRC enable */
#define	MODER_CRC	(1 << 13) /* CRC enable */
#define	MODER_HUGE	(1 << 14) /* huge packets enable */
#define	MODER_PAD	(1 << 15) /* padding enabled */
#define	MODER_RSM	(1 << 16) /* receive small packets */

/* interrupt source and mask registers */
#define	INT_MASK_TXF	(1 << 0) /* transmit frame */
#define	INT_MASK_TXE	(1 << 1) /* transmit error */
#define	INT_MASK_RXF	(1 << 2) /* receive frame */
#define	INT_MASK_RXE	(1 << 3) /* receive error */
#define	INT_MASK_BUSY	(1 << 4)
#define	INT_MASK_TXC	(1 << 5) /* transmit control frame */
#define	INT_MASK_RXC	(1 << 6) /* receive control frame */

#define	INT_MASK_TX	(INT_MASK_TXF | INT_MASK_TXE)
#define	INT_MASK_RX	(INT_MASK_RXF | INT_MASK_RXE)

#define	INT_MASK_ALL ( \
		INT_MASK_TXF | INT_MASK_TXE | \
		INT_MASK_RXF | INT_MASK_RXE | \
		INT_MASK_TXC | INT_MASK_RXC | \
		INT_MASK_BUSY \
	)

/* packet length register */
#define	PACKETLEN_MIN(min)		(((min) & 0xffff) << 16)
#define	PACKETLEN_MAX(max)		(((max) & 0xffff) <<  0)
#define	PACKETLEN_MIN_MAX(min, max)	(PACKETLEN_MIN(min) | \
					PACKETLEN_MAX(max))

/* transmit buffer number register */
#define	TX_BD_NUM_VAL(x)	(((x) <= 0x80) ? (x) : 0x80)

/* control module mode register */
#define	CTRLMODER_PASSALL	(1 << 0) /* pass all receive frames */
#define	CTRLMODER_RXFLOW	(1 << 1) /* receive control flow */
#define	CTRLMODER_TXFLOW	(1 << 2) /* transmit control flow */

/* MII mode register */
#define	MIIMODER_CLKDIV(x)	((x) & 0xfe) /* needs to be an even number */
#define	MIIMODER_NOPRE		(1 << 8) /* no preamble */

/* MII command register */
#define	MIICOMMAND_SCAN		(1 << 0) /* scan status */
#define	MIICOMMAND_READ		(1 << 1) /* read status */
#define	MIICOMMAND_WRITE	(1 << 2) /* write control data */

/* MII address register */
#define	MIIADDRESS_FIAD(x)		(((x) & 0x1f) << 0)
#define	MIIADDRESS_RGAD(x)		(((x) & 0x1f) << 8)
#define	MIIADDRESS_ADDR(phy, reg)	(MIIADDRESS_FIAD(phy) | \
					MIIADDRESS_RGAD(reg))

/* MII transmit data register */
#define	MIITX_DATA_VAL(x)	((x) & 0xffff)

/* MII receive data register */
#define	MIIRX_DATA_VAL(x)	((x) & 0xffff)

/* MII status register */
#define	MIISTATUS_LINKFAIL	(1 << 0)
#define	MIISTATUS_BUSY		(1 << 1)
#define	MIISTATUS_INVALID	(1 << 2)

/* TX buffer descriptor */
#define	TX_BD_CS		(1 <<  0) /* carrier sense lost */
#define	TX_BD_DF		(1 <<  1) /* defer indication */
#define	TX_BD_LC		(1 <<  2) /* late collision */
#define	TX_BD_RL		(1 <<  3) /* retransmission limit */
#define	TX_BD_RETRY_MASK	(0x00f0)
#define	TX_BD_RETRY(x)		(((x) & 0x00f0) >>  4)
#define	TX_BD_UR		(1 <<  8) /* transmitter underrun */
#define	TX_BD_CRC		(1 << 11) /* TX CRC enable */
#define	TX_BD_PAD		(1 << 12) /* pad enable for short packets */
#define	TX_BD_WRAP		(1 << 13)
#define	TX_BD_IRQ		(1 << 14) /* interrupt request enable */
#define	TX_BD_READY		(1 << 15) /* TX buffer ready */
#define	TX_BD_LEN(x)		(((x) & 0xffff) << 16)
#define	TX_BD_LEN_MASK		(0xffff << 16)

#define	TX_BD_STATS		(TX_BD_CS | TX_BD_DF | TX_BD_LC | \
				TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)

/* RX buffer descriptor */
#define	RX_BD_LC	(1 <<  0) /* late collision */
#define	RX_BD_CRC	(1 <<  1) /* RX CRC error */
#define	RX_BD_SF	(1 <<  2) /* short frame */
#define	RX_BD_TL	(1 <<  3) /* too long */
#define	RX_BD_DN	(1 <<  4) /* dribble nibble */
#define	RX_BD_IS	(1 <<  5) /* invalid symbol */
#define	RX_BD_OR	(1 <<  6) /* receiver overrun */
#define	RX_BD_MISS	(1 <<  7)
#define	RX_BD_CF	(1 <<  8) /* control frame */
#define	RX_BD_WRAP	(1 << 13)
#define	RX_BD_IRQ	(1 << 14) /* interrupt request enable */
#define	RX_BD_EMPTY	(1 << 15)
#define	RX_BD_LEN(x)	(((x) & 0xffff) << 16)

#define	RX_BD_STATS	(RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
			RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)

#define	ETHOC_BUFSIZ		1536
#define	ETHOC_ZLEN		64
#define	ETHOC_BD_BASE		0x400
#define	ETHOC_TIMEOUT		(HZ / 2)
#define	ETHOC_MII_TIMEOUT	(1 + (HZ / 5))

/**
 * struct ethoc - driver-private device structure
 * @iobase:	pointer to I/O memory region
 * @membase:	pointer to buffer memory region
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 * @dma_alloc:	dma allocated buffer size
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 * @io_region_size:	I/O memory region size
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 * @num_bd:	number of buffer descriptors
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 * @num_tx:	number of send buffers
 * @cur_tx:	last send buffer written
 * @dty_tx:	last buffer actually sent
 * @num_rx:	number of receive buffers
 * @cur_rx:	current receive buffer
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 * @vma:        pointer to array of virtual memory addresses for buffers
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 * @netdev:	pointer to network device structure
 * @napi:	NAPI structure
 * @msg_enable:	device state flags
 * @lock:	device lock
 * @phy:	attached PHY
 * @mdio:	MDIO bus for PHY access
 * @phy_id:	address of attached PHY
 */
struct ethoc {
	void __iomem *iobase;
	void __iomem *membase;
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	int dma_alloc;
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	resource_size_t io_region_size;
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	bool big_endian;
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	unsigned int num_bd;
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	unsigned int num_tx;
	unsigned int cur_tx;
	unsigned int dty_tx;

	unsigned int num_rx;
	unsigned int cur_rx;

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	void **vma;
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	struct net_device *netdev;
	struct napi_struct napi;
	u32 msg_enable;

	spinlock_t lock;

	struct phy_device *phy;
	struct mii_bus *mdio;
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	struct clk *clk;
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	s8 phy_id;
};

/**
 * struct ethoc_bd - buffer descriptor
 * @stat:	buffer statistics
 * @addr:	physical memory address
 */
struct ethoc_bd {
	u32 stat;
	u32 addr;
};

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static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
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{
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	if (dev->big_endian)
		return ioread32be(dev->iobase + offset);
	else
		return ioread32(dev->iobase + offset);
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}

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static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
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{
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	if (dev->big_endian)
		iowrite32be(data, dev->iobase + offset);
	else
		iowrite32(data, dev->iobase + offset);
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}

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static inline void ethoc_read_bd(struct ethoc *dev, int index,
		struct ethoc_bd *bd)
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{
	loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
	bd->stat = ethoc_read(dev, offset + 0);
	bd->addr = ethoc_read(dev, offset + 4);
}

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static inline void ethoc_write_bd(struct ethoc *dev, int index,
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		const struct ethoc_bd *bd)
{
	loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
	ethoc_write(dev, offset + 0, bd->stat);
	ethoc_write(dev, offset + 4, bd->addr);
}

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static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
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{
	u32 imask = ethoc_read(dev, INT_MASK);
	imask |= mask;
	ethoc_write(dev, INT_MASK, imask);
}

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static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
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{
	u32 imask = ethoc_read(dev, INT_MASK);
	imask &= ~mask;
	ethoc_write(dev, INT_MASK, imask);
}

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static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
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{
	ethoc_write(dev, INT_SOURCE, mask);
}

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static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
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{
	u32 mode = ethoc_read(dev, MODER);
	mode |= MODER_RXEN | MODER_TXEN;
	ethoc_write(dev, MODER, mode);
}

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static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
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{
	u32 mode = ethoc_read(dev, MODER);
	mode &= ~(MODER_RXEN | MODER_TXEN);
	ethoc_write(dev, MODER, mode);
}

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static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start)
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{
	struct ethoc_bd bd;
	int i;
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	void *vma;
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	dev->cur_tx = 0;
	dev->dty_tx = 0;
	dev->cur_rx = 0;

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	ethoc_write(dev, TX_BD_NUM, dev->num_tx);

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	/* setup transmission buffers */
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	bd.addr = mem_start;
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	bd.stat = TX_BD_IRQ | TX_BD_CRC;
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	vma = dev->membase;
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	for (i = 0; i < dev->num_tx; i++) {
		if (i == dev->num_tx - 1)
			bd.stat |= TX_BD_WRAP;

		ethoc_write_bd(dev, i, &bd);
		bd.addr += ETHOC_BUFSIZ;
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		dev->vma[i] = vma;
		vma += ETHOC_BUFSIZ;
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	}

	bd.stat = RX_BD_EMPTY | RX_BD_IRQ;

	for (i = 0; i < dev->num_rx; i++) {
		if (i == dev->num_rx - 1)
			bd.stat |= RX_BD_WRAP;

		ethoc_write_bd(dev, dev->num_tx + i, &bd);
		bd.addr += ETHOC_BUFSIZ;
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		dev->vma[dev->num_tx + i] = vma;
		vma += ETHOC_BUFSIZ;
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	}

	return 0;
}

static int ethoc_reset(struct ethoc *dev)
{
	u32 mode;

	/* TODO: reset controller? */

	ethoc_disable_rx_and_tx(dev);

	/* TODO: setup registers */

	/* enable FCS generation and automatic padding */
	mode = ethoc_read(dev, MODER);
	mode |= MODER_CRC | MODER_PAD;
	ethoc_write(dev, MODER, mode);

	/* set full-duplex mode */
	mode = ethoc_read(dev, MODER);
	mode |= MODER_FULLD;
	ethoc_write(dev, MODER, mode);
	ethoc_write(dev, IPGT, 0x15);

	ethoc_ack_irq(dev, INT_MASK_ALL);
	ethoc_enable_irq(dev, INT_MASK_ALL);
	ethoc_enable_rx_and_tx(dev);
	return 0;
}

static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
		struct ethoc_bd *bd)
{
	struct net_device *netdev = dev->netdev;
	unsigned int ret = 0;

	if (bd->stat & RX_BD_TL) {
		dev_err(&netdev->dev, "RX: frame too long\n");
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		netdev->stats.rx_length_errors++;
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		ret++;
	}

	if (bd->stat & RX_BD_SF) {
		dev_err(&netdev->dev, "RX: frame too short\n");
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		netdev->stats.rx_length_errors++;
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		ret++;
	}

	if (bd->stat & RX_BD_DN) {
		dev_err(&netdev->dev, "RX: dribble nibble\n");
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		netdev->stats.rx_frame_errors++;
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	}

	if (bd->stat & RX_BD_CRC) {
		dev_err(&netdev->dev, "RX: wrong CRC\n");
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		netdev->stats.rx_crc_errors++;
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		ret++;
	}

	if (bd->stat & RX_BD_OR) {
		dev_err(&netdev->dev, "RX: overrun\n");
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		netdev->stats.rx_over_errors++;
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		ret++;
	}

	if (bd->stat & RX_BD_MISS)
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		netdev->stats.rx_missed_errors++;
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	if (bd->stat & RX_BD_LC) {
		dev_err(&netdev->dev, "RX: late collision\n");
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		netdev->stats.collisions++;
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		ret++;
	}

	return ret;
}

static int ethoc_rx(struct net_device *dev, int limit)
{
	struct ethoc *priv = netdev_priv(dev);
	int count;

	for (count = 0; count < limit; ++count) {
		unsigned int entry;
		struct ethoc_bd bd;

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		entry = priv->num_tx + priv->cur_rx;
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		ethoc_read_bd(priv, entry, &bd);
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		if (bd.stat & RX_BD_EMPTY) {
			ethoc_ack_irq(priv, INT_MASK_RX);
			/* If packet (interrupt) came in between checking
			 * BD_EMTPY and clearing the interrupt source, then we
			 * risk missing the packet as the RX interrupt won't
			 * trigger right away when we reenable it; hence, check
			 * BD_EMTPY here again to make sure there isn't such a
			 * packet waiting for us...
			 */
			ethoc_read_bd(priv, entry, &bd);
			if (bd.stat & RX_BD_EMPTY)
				break;
		}
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		if (ethoc_update_rx_stats(priv, &bd) == 0) {
			int size = bd.stat >> 16;
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			struct sk_buff *skb;
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			size -= 4; /* strip the CRC */
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			skb = netdev_alloc_skb_ip_align(dev, size);
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			if (likely(skb)) {
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				void *src = priv->vma[entry];
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				memcpy_fromio(skb_put(skb, size), src, size);
				skb->protocol = eth_type_trans(skb, dev);
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				dev->stats.rx_packets++;
				dev->stats.rx_bytes += size;
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				netif_receive_skb(skb);
			} else {
				if (net_ratelimit())
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					dev_warn(&dev->dev,
					    "low on memory - packet dropped\n");
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				dev->stats.rx_dropped++;
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				break;
			}
		}

		/* clear the buffer descriptor so it can be reused */
		bd.stat &= ~RX_BD_STATS;
		bd.stat |=  RX_BD_EMPTY;
		ethoc_write_bd(priv, entry, &bd);
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		if (++priv->cur_rx == priv->num_rx)
			priv->cur_rx = 0;
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	}

	return count;
}

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static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
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{
	struct net_device *netdev = dev->netdev;

	if (bd->stat & TX_BD_LC) {
		dev_err(&netdev->dev, "TX: late collision\n");
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		netdev->stats.tx_window_errors++;
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	}

	if (bd->stat & TX_BD_RL) {
		dev_err(&netdev->dev, "TX: retransmit limit\n");
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		netdev->stats.tx_aborted_errors++;
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	}

	if (bd->stat & TX_BD_UR) {
		dev_err(&netdev->dev, "TX: underrun\n");
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		netdev->stats.tx_fifo_errors++;
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	}

	if (bd->stat & TX_BD_CS) {
		dev_err(&netdev->dev, "TX: carrier sense lost\n");
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		netdev->stats.tx_carrier_errors++;
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	}

	if (bd->stat & TX_BD_STATS)
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		netdev->stats.tx_errors++;
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	netdev->stats.collisions += (bd->stat >> 4) & 0xf;
	netdev->stats.tx_bytes += bd->stat >> 16;
	netdev->stats.tx_packets++;
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}

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static int ethoc_tx(struct net_device *dev, int limit)
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{
	struct ethoc *priv = netdev_priv(dev);
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	int count;
	struct ethoc_bd bd;
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	for (count = 0; count < limit; ++count) {
		unsigned int entry;
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		entry = priv->dty_tx & (priv->num_tx-1);
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		ethoc_read_bd(priv, entry, &bd);

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		if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) {
			ethoc_ack_irq(priv, INT_MASK_TX);
			/* If interrupt came in between reading in the BD
			 * and clearing the interrupt source, then we risk
			 * missing the event as the TX interrupt won't trigger
			 * right away when we reenable it; hence, check
			 * BD_EMPTY here again to make sure there isn't such an
			 * event pending...
			 */
			ethoc_read_bd(priv, entry, &bd);
			if (bd.stat & TX_BD_READY ||
			    (priv->dty_tx == priv->cur_tx))
				break;
		}

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		ethoc_update_tx_stats(priv, &bd);
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		priv->dty_tx++;
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	}

	if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
		netif_wake_queue(dev);

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	return count;
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}

static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
{
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	struct net_device *dev = dev_id;
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	struct ethoc *priv = netdev_priv(dev);
	u32 pending;
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	u32 mask;

	/* Figure out what triggered the interrupt...
	 * The tricky bit here is that the interrupt source bits get
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	 * set in INT_SOURCE for an event regardless of whether that
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	 * event is masked or not.  Thus, in order to figure out what
	 * triggered the interrupt, we need to remove the sources
	 * for all events that are currently masked.  This behaviour
	 * is not particularly well documented but reasonable...
	 */
	mask = ethoc_read(priv, INT_MASK);
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	pending = ethoc_read(priv, INT_SOURCE);
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	pending &= mask;

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	if (unlikely(pending == 0))
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		return IRQ_NONE;

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	ethoc_ack_irq(priv, pending);
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	/* We always handle the dropped packet interrupt */
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	if (pending & INT_MASK_BUSY) {
		dev_err(&dev->dev, "packet dropped\n");
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		dev->stats.rx_dropped++;
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	}

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581 582 583 584
	/* Handle receive/transmit event by switching to polling */
	if (pending & (INT_MASK_TX | INT_MASK_RX)) {
		ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
		napi_schedule(&priv->napi);
585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611
	}

	return IRQ_HANDLED;
}

static int ethoc_get_mac_address(struct net_device *dev, void *addr)
{
	struct ethoc *priv = netdev_priv(dev);
	u8 *mac = (u8 *)addr;
	u32 reg;

	reg = ethoc_read(priv, MAC_ADDR0);
	mac[2] = (reg >> 24) & 0xff;
	mac[3] = (reg >> 16) & 0xff;
	mac[4] = (reg >>  8) & 0xff;
	mac[5] = (reg >>  0) & 0xff;

	reg = ethoc_read(priv, MAC_ADDR1);
	mac[0] = (reg >>  8) & 0xff;
	mac[1] = (reg >>  0) & 0xff;

	return 0;
}

static int ethoc_poll(struct napi_struct *napi, int budget)
{
	struct ethoc *priv = container_of(napi, struct ethoc, napi);
J
Jonas Bonn 已提交
612 613 614 615 616
	int rx_work_done = 0;
	int tx_work_done = 0;

	rx_work_done = ethoc_rx(priv->netdev, budget);
	tx_work_done = ethoc_tx(priv->netdev, budget);
617

J
Jonas Bonn 已提交
618
	if (rx_work_done < budget && tx_work_done < budget) {
619
		napi_complete(napi);
J
Jonas Bonn 已提交
620
		ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
621 622
	}

J
Jonas Bonn 已提交
623
	return rx_work_done;
624 625 626 627 628
}

static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
{
	struct ethoc *priv = bus->priv;
J
Jonas Bonn 已提交
629
	int i;
630 631 632 633

	ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
	ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);

B
Barry Grussling 已提交
634
	for (i = 0; i < 5; i++) {
635 636 637 638 639 640 641
		u32 status = ethoc_read(priv, MIISTATUS);
		if (!(status & MIISTATUS_BUSY)) {
			u32 data = ethoc_read(priv, MIIRX_DATA);
			/* reset MII command register */
			ethoc_write(priv, MIICOMMAND, 0);
			return data;
		}
B
Barry Grussling 已提交
642
		usleep_range(100, 200);
643 644 645 646 647 648 649 650
	}

	return -EBUSY;
}

static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
{
	struct ethoc *priv = bus->priv;
J
Jonas Bonn 已提交
651
	int i;
652 653 654 655 656

	ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
	ethoc_write(priv, MIITX_DATA, val);
	ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);

B
Barry Grussling 已提交
657
	for (i = 0; i < 5; i++) {
658
		u32 stat = ethoc_read(priv, MIISTATUS);
659 660 661
		if (!(stat & MIISTATUS_BUSY)) {
			/* reset MII command register */
			ethoc_write(priv, MIICOMMAND, 0);
662
			return 0;
663
		}
B
Barry Grussling 已提交
664
		usleep_range(100, 200);
665 666 667 668 669 670 671 672 673
	}

	return -EBUSY;
}

static void ethoc_mdio_poll(struct net_device *dev)
{
}

674
static int ethoc_mdio_probe(struct net_device *dev)
675 676 677
{
	struct ethoc *priv = netdev_priv(dev);
	struct phy_device *phy;
J
Jonas Bonn 已提交
678
	int err;
679

B
Barry Grussling 已提交
680
	if (priv->phy_id != -1)
681
		phy = mdiobus_get_phy(priv->mdio, priv->phy_id);
B
Barry Grussling 已提交
682
	else
J
Jonas Bonn 已提交
683
		phy = phy_find_first(priv->mdio);
684 685 686 687 688 689

	if (!phy) {
		dev_err(&dev->dev, "no PHY found\n");
		return -ENXIO;
	}

690 691
	err = phy_connect_direct(dev, phy, ethoc_mdio_poll,
				 PHY_INTERFACE_MODE_GMII);
J
Jonas Bonn 已提交
692
	if (err) {
693
		dev_err(&dev->dev, "could not attach to PHY\n");
J
Jonas Bonn 已提交
694
		return err;
695 696 697
	}

	priv->phy = phy;
698 699 700 701 702
	phy->advertising &= ~(ADVERTISED_1000baseT_Full |
			      ADVERTISED_1000baseT_Half);
	phy->supported &= ~(SUPPORTED_1000baseT_Full |
			    SUPPORTED_1000baseT_Half);

703 704 705 706 707 708 709 710 711 712 713 714 715
	return 0;
}

static int ethoc_open(struct net_device *dev)
{
	struct ethoc *priv = netdev_priv(dev);
	int ret;

	ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
			dev->name, dev);
	if (ret)
		return ret;

716
	ethoc_init_ring(priv, dev->mem_start);
717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768
	ethoc_reset(priv);

	if (netif_queue_stopped(dev)) {
		dev_dbg(&dev->dev, " resuming queue\n");
		netif_wake_queue(dev);
	} else {
		dev_dbg(&dev->dev, " starting queue\n");
		netif_start_queue(dev);
	}

	phy_start(priv->phy);
	napi_enable(&priv->napi);

	if (netif_msg_ifup(priv)) {
		dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
				dev->base_addr, dev->mem_start, dev->mem_end);
	}

	return 0;
}

static int ethoc_stop(struct net_device *dev)
{
	struct ethoc *priv = netdev_priv(dev);

	napi_disable(&priv->napi);

	if (priv->phy)
		phy_stop(priv->phy);

	ethoc_disable_rx_and_tx(priv);
	free_irq(dev->irq, dev);

	if (!netif_queue_stopped(dev))
		netif_stop_queue(dev);

	return 0;
}

static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
	struct ethoc *priv = netdev_priv(dev);
	struct mii_ioctl_data *mdio = if_mii(ifr);
	struct phy_device *phy = NULL;

	if (!netif_running(dev))
		return -EINVAL;

	if (cmd != SIOCGMIIPHY) {
		if (mdio->phy_id >= PHY_MAX_ADDR)
			return -ERANGE;

769
		phy = mdiobus_get_phy(priv->mdio, mdio->phy_id);
770 771 772 773 774 775
		if (!phy)
			return -ENODEV;
	} else {
		phy = priv->phy;
	}

776
	return phy_mii_ioctl(phy, ifr, cmd);
777 778
}

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Jiri Pirko 已提交
779
static void ethoc_do_set_mac_address(struct net_device *dev)
780 781
{
	struct ethoc *priv = netdev_priv(dev);
J
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782
	unsigned char *mac = dev->dev_addr;
783

784 785 786
	ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
				     (mac[4] <<  8) | (mac[5] <<  0));
	ethoc_write(priv, MAC_ADDR1, (mac[0] <<  8) | (mac[1] <<  0));
J
Jiri Pirko 已提交
787
}
788

J
Jiri Pirko 已提交
789 790 791
static int ethoc_set_mac_address(struct net_device *dev, void *p)
{
	const struct sockaddr *addr = p;
792

J
Jiri Pirko 已提交
793 794 795 796
	if (!is_valid_ether_addr(addr->sa_data))
		return -EADDRNOTAVAIL;
	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
	ethoc_do_set_mac_address(dev);
797 798 799 800 801 802 803
	return 0;
}

static void ethoc_set_multicast_list(struct net_device *dev)
{
	struct ethoc *priv = netdev_priv(dev);
	u32 mode = ethoc_read(priv, MODER);
804
	struct netdev_hw_addr *ha;
805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831
	u32 hash[2] = { 0, 0 };

	/* set loopback mode if requested */
	if (dev->flags & IFF_LOOPBACK)
		mode |=  MODER_LOOP;
	else
		mode &= ~MODER_LOOP;

	/* receive broadcast frames if requested */
	if (dev->flags & IFF_BROADCAST)
		mode &= ~MODER_BRO;
	else
		mode |=  MODER_BRO;

	/* enable promiscuous mode if requested */
	if (dev->flags & IFF_PROMISC)
		mode |=  MODER_PRO;
	else
		mode &= ~MODER_PRO;

	ethoc_write(priv, MODER, mode);

	/* receive multicast frames */
	if (dev->flags & IFF_ALLMULTI) {
		hash[0] = 0xffffffff;
		hash[1] = 0xffffffff;
	} else {
832 833
		netdev_for_each_mc_addr(ha, dev) {
			u32 crc = ether_crc(ETH_ALEN, ha->addr);
834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855
			int bit = (crc >> 26) & 0x3f;
			hash[bit >> 5] |= 1 << (bit & 0x1f);
		}
	}

	ethoc_write(priv, ETH_HASH0, hash[0]);
	ethoc_write(priv, ETH_HASH1, hash[1]);
}

static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
{
	return -ENOSYS;
}

static void ethoc_tx_timeout(struct net_device *dev)
{
	struct ethoc *priv = netdev_priv(dev);
	u32 pending = ethoc_read(priv, INT_SOURCE);
	if (likely(pending))
		ethoc_interrupt(dev->irq, dev);
}

856
static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
857 858 859 860 861 862
{
	struct ethoc *priv = netdev_priv(dev);
	struct ethoc_bd bd;
	unsigned int entry;
	void *dest;

863 864 865 866 867
	if (skb_put_padto(skb, ETHOC_ZLEN)) {
		dev->stats.tx_errors++;
		goto out_no_free;
	}

868
	if (unlikely(skb->len > ETHOC_BUFSIZ)) {
869
		dev->stats.tx_errors++;
870
		goto out;
871 872 873 874 875 876 877 878 879 880 881 882
	}

	entry = priv->cur_tx % priv->num_tx;
	spin_lock_irq(&priv->lock);
	priv->cur_tx++;

	ethoc_read_bd(priv, entry, &bd);
	if (unlikely(skb->len < ETHOC_ZLEN))
		bd.stat |=  TX_BD_PAD;
	else
		bd.stat &= ~TX_BD_PAD;

883
	dest = priv->vma[entry];
884 885 886 887 888 889 890 891 892 893 894 895 896 897 898
	memcpy_toio(dest, skb->data, skb->len);

	bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
	bd.stat |= TX_BD_LEN(skb->len);
	ethoc_write_bd(priv, entry, &bd);

	bd.stat |= TX_BD_READY;
	ethoc_write_bd(priv, entry, &bd);

	if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
		dev_dbg(&dev->dev, "stopping queue\n");
		netif_stop_queue(dev);
	}

	spin_unlock_irq(&priv->lock);
899
	skb_tx_timestamp(skb);
900 901
out:
	dev_kfree_skb(skb);
902
out_no_free:
903 904 905
	return NETDEV_TX_OK;
}

906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927
static int ethoc_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct ethoc *priv = netdev_priv(dev);
	struct phy_device *phydev = priv->phy;

	if (!phydev)
		return -EOPNOTSUPP;

	return phy_ethtool_gset(phydev, cmd);
}

static int ethoc_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct ethoc *priv = netdev_priv(dev);
	struct phy_device *phydev = priv->phy;

	if (!phydev)
		return -EOPNOTSUPP;

	return phy_ethtool_sset(phydev, cmd);
}

928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944
static int ethoc_get_regs_len(struct net_device *netdev)
{
	return ETH_END;
}

static void ethoc_get_regs(struct net_device *dev, struct ethtool_regs *regs,
			   void *p)
{
	struct ethoc *priv = netdev_priv(dev);
	u32 *regs_buff = p;
	unsigned i;

	regs->version = 0;
	for (i = 0; i < ETH_END / sizeof(u32); ++i)
		regs_buff[i] = ethoc_read(priv, i * sizeof(u32));
}

945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990
static void ethoc_get_ringparam(struct net_device *dev,
				struct ethtool_ringparam *ring)
{
	struct ethoc *priv = netdev_priv(dev);

	ring->rx_max_pending = priv->num_bd - 1;
	ring->rx_mini_max_pending = 0;
	ring->rx_jumbo_max_pending = 0;
	ring->tx_max_pending = priv->num_bd - 1;

	ring->rx_pending = priv->num_rx;
	ring->rx_mini_pending = 0;
	ring->rx_jumbo_pending = 0;
	ring->tx_pending = priv->num_tx;
}

static int ethoc_set_ringparam(struct net_device *dev,
			       struct ethtool_ringparam *ring)
{
	struct ethoc *priv = netdev_priv(dev);

	if (ring->tx_pending < 1 || ring->rx_pending < 1 ||
	    ring->tx_pending + ring->rx_pending > priv->num_bd)
		return -EINVAL;
	if (ring->rx_mini_pending || ring->rx_jumbo_pending)
		return -EINVAL;

	if (netif_running(dev)) {
		netif_tx_disable(dev);
		ethoc_disable_rx_and_tx(priv);
		ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
		synchronize_irq(dev->irq);
	}

	priv->num_tx = rounddown_pow_of_two(ring->tx_pending);
	priv->num_rx = ring->rx_pending;
	ethoc_init_ring(priv, dev->mem_start);

	if (netif_running(dev)) {
		ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
		ethoc_enable_rx_and_tx(priv);
		netif_wake_queue(dev);
	}
	return 0;
}

991
const struct ethtool_ops ethoc_ethtool_ops = {
992 993
	.get_settings = ethoc_get_settings,
	.set_settings = ethoc_set_settings,
994 995
	.get_regs_len = ethoc_get_regs_len,
	.get_regs = ethoc_get_regs,
996
	.get_link = ethtool_op_get_link,
997 998
	.get_ringparam = ethoc_get_ringparam,
	.set_ringparam = ethoc_set_ringparam,
999 1000 1001
	.get_ts_info = ethtool_op_get_ts_info,
};

1002 1003 1004 1005 1006
static const struct net_device_ops ethoc_netdev_ops = {
	.ndo_open = ethoc_open,
	.ndo_stop = ethoc_stop,
	.ndo_do_ioctl = ethoc_ioctl,
	.ndo_set_mac_address = ethoc_set_mac_address,
1007
	.ndo_set_rx_mode = ethoc_set_multicast_list,
1008 1009 1010 1011 1012 1013
	.ndo_change_mtu = ethoc_change_mtu,
	.ndo_tx_timeout = ethoc_tx_timeout,
	.ndo_start_xmit = ethoc_start_xmit,
};

/**
1014
 * ethoc_probe - initialize OpenCores ethernet MAC
1015 1016
 * pdev:	platform device
 */
1017
static int ethoc_probe(struct platform_device *pdev)
1018 1019 1020 1021 1022 1023
{
	struct net_device *netdev = NULL;
	struct resource *res = NULL;
	struct resource *mmio = NULL;
	struct resource *mem = NULL;
	struct ethoc *priv = NULL;
1024
	int num_bd;
1025
	int ret = 0;
1026
	bool random_mac = false;
1027 1028
	struct ethoc_platform_data *pdata = dev_get_platdata(&pdev->dev);
	u32 eth_clkfreq = pdata ? pdata->eth_clkfreq : 0;
1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048

	/* allocate networking device */
	netdev = alloc_etherdev(sizeof(struct ethoc));
	if (!netdev) {
		ret = -ENOMEM;
		goto out;
	}

	SET_NETDEV_DEV(netdev, &pdev->dev);
	platform_set_drvdata(pdev, netdev);

	/* obtain I/O memory space */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
		ret = -ENXIO;
		goto free;
	}

	mmio = devm_request_mem_region(&pdev->dev, res->start,
T
Tobias Klauser 已提交
1049
			resource_size(res), res->name);
1050
	if (!mmio) {
1051 1052 1053 1054 1055 1056 1057 1058 1059
		dev_err(&pdev->dev, "cannot request I/O memory space\n");
		ret = -ENXIO;
		goto free;
	}

	netdev->base_addr = mmio->start;

	/* obtain buffer memory space */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
T
Thomas Chou 已提交
1060 1061
	if (res) {
		mem = devm_request_mem_region(&pdev->dev, res->start,
T
Tobias Klauser 已提交
1062
			resource_size(res), res->name);
T
Thomas Chou 已提交
1063 1064 1065 1066 1067 1068 1069 1070
		if (!mem) {
			dev_err(&pdev->dev, "cannot request memory space\n");
			ret = -ENXIO;
			goto free;
		}

		netdev->mem_start = mem->start;
		netdev->mem_end   = mem->end;
1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086
	}


	/* obtain device IRQ number */
	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res) {
		dev_err(&pdev->dev, "cannot obtain IRQ\n");
		ret = -ENXIO;
		goto free;
	}

	netdev->irq = res->start;

	/* setup driver-private data */
	priv = netdev_priv(netdev);
	priv->netdev = netdev;
T
Thomas Chou 已提交
1087
	priv->dma_alloc = 0;
1088
	priv->io_region_size = resource_size(mmio);
1089 1090

	priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
T
Tobias Klauser 已提交
1091
			resource_size(mmio));
1092 1093 1094
	if (!priv->iobase) {
		dev_err(&pdev->dev, "cannot remap I/O memory space\n");
		ret = -ENXIO;
1095
		goto free;
1096 1097
	}

T
Thomas Chou 已提交
1098 1099
	if (netdev->mem_end) {
		priv->membase = devm_ioremap_nocache(&pdev->dev,
T
Tobias Klauser 已提交
1100
			netdev->mem_start, resource_size(mem));
T
Thomas Chou 已提交
1101 1102 1103
		if (!priv->membase) {
			dev_err(&pdev->dev, "cannot remap memory space\n");
			ret = -ENXIO;
1104
			goto free;
T
Thomas Chou 已提交
1105 1106 1107
		}
	} else {
		/* Allocate buffer memory */
1108
		priv->membase = dmam_alloc_coherent(&pdev->dev,
T
Thomas Chou 已提交
1109 1110 1111 1112 1113 1114
			buffer_size, (void *)&netdev->mem_start,
			GFP_KERNEL);
		if (!priv->membase) {
			dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
				buffer_size);
			ret = -ENOMEM;
1115
			goto free;
T
Thomas Chou 已提交
1116 1117 1118
		}
		netdev->mem_end = netdev->mem_start + buffer_size;
		priv->dma_alloc = buffer_size;
1119 1120
	}

1121 1122 1123
	priv->big_endian = pdata ? pdata->big_endian :
		of_device_is_big_endian(pdev->dev.of_node);

1124 1125 1126
	/* calculate the number of TX/RX buffers, maximum 128 supported */
	num_bd = min_t(unsigned int,
		128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
J
Jonas Bonn 已提交
1127 1128
	if (num_bd < 4) {
		ret = -ENODEV;
1129
		goto free;
J
Jonas Bonn 已提交
1130
	}
1131
	priv->num_bd = num_bd;
J
Jonas Bonn 已提交
1132 1133
	/* num_tx must be a power of two */
	priv->num_tx = rounddown_pow_of_two(num_bd >> 1);
1134 1135
	priv->num_rx = num_bd - priv->num_tx;

J
Jonas Bonn 已提交
1136 1137 1138
	dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n",
		priv->num_tx, priv->num_rx);

B
Barry Grussling 已提交
1139
	priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void *), GFP_KERNEL);
1140 1141
	if (!priv->vma) {
		ret = -ENOMEM;
1142
		goto free;
1143 1144
	}

1145
	/* Allow the platform setup code to pass in a MAC address. */
1146
	if (pdata) {
1147 1148
		memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
		priv->phy_id = pdata->phy_id;
J
Jonas Bonn 已提交
1149
	} else {
B
Barry Grussling 已提交
1150
		const uint8_t *mac;
J
Jonas Bonn 已提交
1151 1152 1153 1154 1155 1156

		mac = of_get_property(pdev->dev.of_node,
				      "local-mac-address",
				      NULL);
		if (mac)
			memcpy(netdev->dev_addr, mac, IFHWADDRLEN);
1157
		priv->phy_id = -1;
1158 1159 1160
	}

	/* Check that the given MAC address is valid. If it isn't, read the
B
Barry Grussling 已提交
1161 1162
	 * current MAC from the controller.
	 */
1163 1164 1165 1166
	if (!is_valid_ether_addr(netdev->dev_addr))
		ethoc_get_mac_address(netdev, netdev->dev_addr);

	/* Check the MAC again for validity, if it still isn't choose and
B
Barry Grussling 已提交
1167 1168
	 * program a random one.
	 */
1169
	if (!is_valid_ether_addr(netdev->dev_addr)) {
J
Joe Perches 已提交
1170
		eth_random_addr(netdev->dev_addr);
1171 1172 1173
		random_mac = true;
	}

J
Jiri Pirko 已提交
1174
	ethoc_do_set_mac_address(netdev);
1175

1176
	if (random_mac)
1177
		netdev->addr_assign_type = NET_ADDR_RANDOM;
1178

1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199
	/* Allow the platform setup code to adjust MII management bus clock. */
	if (!eth_clkfreq) {
		struct clk *clk = devm_clk_get(&pdev->dev, NULL);

		if (!IS_ERR(clk)) {
			priv->clk = clk;
			clk_prepare_enable(clk);
			eth_clkfreq = clk_get_rate(clk);
		}
	}
	if (eth_clkfreq) {
		u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1);

		if (!clkdiv)
			clkdiv = 2;
		dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv);
		ethoc_write(priv, MIIMODER,
			    (ethoc_read(priv, MIIMODER) & MIIMODER_NOPRE) |
			    clkdiv);
	}

1200 1201 1202 1203
	/* register MII bus */
	priv->mdio = mdiobus_alloc();
	if (!priv->mdio) {
		ret = -ENOMEM;
1204
		goto free2;
1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216
	}

	priv->mdio->name = "ethoc-mdio";
	snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
			priv->mdio->name, pdev->id);
	priv->mdio->read = ethoc_mdio_read;
	priv->mdio->write = ethoc_mdio_write;
	priv->mdio->priv = priv;

	ret = mdiobus_register(priv->mdio);
	if (ret) {
		dev_err(&netdev->dev, "failed to register MDIO bus\n");
1217
		goto free2;
1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229
	}

	ret = ethoc_mdio_probe(netdev);
	if (ret) {
		dev_err(&netdev->dev, "failed to probe MDIO bus\n");
		goto error;
	}

	/* setup the net_device structure */
	netdev->netdev_ops = &ethoc_netdev_ops;
	netdev->watchdog_timeo = ETHOC_TIMEOUT;
	netdev->features |= 0;
1230
	netdev->ethtool_ops = &ethoc_ethtool_ops;
1231 1232 1233 1234 1235 1236 1237 1238 1239

	/* setup NAPI */
	netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);

	spin_lock_init(&priv->lock);

	ret = register_netdev(netdev);
	if (ret < 0) {
		dev_err(&netdev->dev, "failed to register interface\n");
1240
		goto error2;
1241 1242 1243 1244
	}

	goto out;

1245 1246
error2:
	netif_napi_del(&priv->napi);
1247 1248 1249
error:
	mdiobus_unregister(priv->mdio);
	mdiobus_free(priv->mdio);
1250
free2:
1251 1252
	if (priv->clk)
		clk_disable_unprepare(priv->clk);
1253
free:
1254 1255 1256 1257 1258 1259
	free_netdev(netdev);
out:
	return ret;
}

/**
1260
 * ethoc_remove - shutdown OpenCores ethernet MAC
1261 1262
 * @pdev:	platform device
 */
1263
static int ethoc_remove(struct platform_device *pdev)
1264 1265 1266 1267 1268
{
	struct net_device *netdev = platform_get_drvdata(pdev);
	struct ethoc *priv = netdev_priv(netdev);

	if (netdev) {
1269
		netif_napi_del(&priv->napi);
1270 1271 1272 1273 1274 1275 1276
		phy_disconnect(priv->phy);
		priv->phy = NULL;

		if (priv->mdio) {
			mdiobus_unregister(priv->mdio);
			mdiobus_free(priv->mdio);
		}
1277 1278
		if (priv->clk)
			clk_disable_unprepare(priv->clk);
1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300
		unregister_netdev(netdev);
		free_netdev(netdev);
	}

	return 0;
}

#ifdef CONFIG_PM
static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
{
	return -ENOSYS;
}

static int ethoc_resume(struct platform_device *pdev)
{
	return -ENOSYS;
}
#else
# define ethoc_suspend NULL
# define ethoc_resume  NULL
#endif

1301
static const struct of_device_id ethoc_match[] = {
1302
	{ .compatible = "opencores,ethoc", },
J
Jonas Bonn 已提交
1303 1304 1305 1306
	{},
};
MODULE_DEVICE_TABLE(of, ethoc_match);

1307 1308
static struct platform_driver ethoc_driver = {
	.probe   = ethoc_probe,
1309
	.remove  = ethoc_remove,
1310 1311 1312 1313
	.suspend = ethoc_suspend,
	.resume  = ethoc_resume,
	.driver  = {
		.name = "ethoc",
J
Jonas Bonn 已提交
1314
		.of_match_table = ethoc_match,
1315 1316 1317
	},
};

1318
module_platform_driver(ethoc_driver);
1319 1320 1321 1322 1323

MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
MODULE_LICENSE("GPL v2");