dbri.c 78.1 KB
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/*
 * Driver for DBRI sound chip found on Sparcs.
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 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
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 *
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 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
 *
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 * Based entirely upon drivers/sbus/audio/dbri.c which is:
 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
 *
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 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
 * on Sun SPARCStation 10, 20, LX and Voyager models.
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 *
 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
 *   data time multiplexer with ISDN support (aka T7259)
 *   Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
 *   CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
 *   Documentation:
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 *   - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
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 *     Sparc Technology Business (courtesy of Sun Support)
 *   - Data sheet of the T7903, a newer but very similar ISA bus equivalent
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 *     available from the Lucent (formerly AT&T microelectronics) home
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 *     page.
 *   - http://www.freesoft.org/Linux/DBRI/
 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
 *   Interfaces: CHI, Audio In & Out, 2 bits parallel
 *   Documentation: from the Crystal Semiconductor home page.
 *
 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
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 * memory and a serial device (long pipes, no. 0-15) or between two serial
 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
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 * device (short pipes).
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 * A timeslot defines the bit-offset and no. of bits read from a serial device.
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 * The timeslots are linked to 6 circular lists, one for each direction for
 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
 * (the second one is a monitor/tee pipe, valid only for serial input).
 *
 * The mmcodec is connected via the CHI bus and needs the data & some
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 * parameters (volume, output selection) time multiplexed in 8 byte
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 * chunks. It also has a control mode, which serves for audio format setting.
 *
 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
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 * the same CHI bus, so I thought perhaps it is possible to use the on-board
 * & the speakerbox codec simultaneously, giving 2 (not very independent :-)
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 * audio devices. But the SUN HW group decided against it, at least on my
 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
 * connected.
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 *
 * I've tried to stick to the following function naming conventions:
 * snd_*	ALSA stuff
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 * cs4215_*	CS4215 codec specific stuff
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 * dbri_*	DBRI high-level stuff
 * other	DBRI low-level stuff
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 */

#include <linux/interrupt.h>
#include <linux/delay.h>
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#include <linux/irq.h>
#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/gfp.h>
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#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/info.h>
#include <sound/control.h>
#include <sound/initval.h>

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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/atomic.h>
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#include <linux/module.h>
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MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
MODULE_DESCRIPTION("Sun DBRI");
MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");

static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
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/* Enable this card */
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static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
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module_param_array(index, int, NULL, 0444);
MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
module_param_array(id, charp, NULL, 0444);
MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");

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#undef DBRI_DEBUG
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#define D_INT	(1<<0)
#define D_GEN	(1<<1)
#define D_CMD	(1<<2)
#define D_MM	(1<<3)
#define D_USR	(1<<4)
#define D_DESC	(1<<5)

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static int dbri_debug;
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module_param(dbri_debug, int, 0644);
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MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");

#ifdef DBRI_DEBUG
static char *cmds[] = {
	"WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
	"SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
};

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#define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x)
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#else
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#define dprintk(a, x...) do { } while (0)
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#endif				/* DBRI_DEBUG */

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#define DBRI_CMD(cmd, intr, value) ((cmd << 28) |	\
				    (intr << 27) |	\
				    value)

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/***************************************************************************
	CS4215 specific definitions and structures
****************************************************************************/

struct cs4215 {
	__u8 data[4];		/* Data mode: Time slots 5-8 */
	__u8 ctrl[4];		/* Ctrl mode: Time slots 1-4 */
	__u8 onboard;
	__u8 offset;		/* Bit offset from frame sync to time slot 1 */
	volatile __u32 status;
	volatile __u32 version;
	__u8 precision;		/* In bits, either 8 or 16 */
	__u8 channels;		/* 1 or 2 */
};

/*
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 * Control mode first
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 */

/* Time Slot 1, Status register */
#define CS4215_CLB	(1<<2)	/* Control Latch Bit */
#define CS4215_OLB	(1<<3)	/* 1: line: 2.0V, speaker 4V */
				/* 0: line: 2.8V, speaker 8V */
#define CS4215_MLB	(1<<4)	/* 1: Microphone: 20dB gain disabled */
#define CS4215_RSRVD_1  (1<<5)

/* Time Slot 2, Data Format Register */
#define CS4215_DFR_LINEAR16	0
#define CS4215_DFR_ULAW		1
#define CS4215_DFR_ALAW		2
#define CS4215_DFR_LINEAR8	3
#define CS4215_DFR_STEREO	(1<<2)
static struct {
	unsigned short freq;
	unsigned char xtal;
	unsigned char csval;
} CS4215_FREQ[] = {
	{  8000, (1 << 4), (0 << 3) },
	{ 16000, (1 << 4), (1 << 3) },
	{ 27429, (1 << 4), (2 << 3) },	/* Actually 24428.57 */
	{ 32000, (1 << 4), (3 << 3) },
     /* {    NA, (1 << 4), (4 << 3) }, */
     /* {    NA, (1 << 4), (5 << 3) }, */
	{ 48000, (1 << 4), (6 << 3) },
	{  9600, (1 << 4), (7 << 3) },
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	{  5512, (2 << 4), (0 << 3) },	/* Actually 5512.5 */
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	{ 11025, (2 << 4), (1 << 3) },
	{ 18900, (2 << 4), (2 << 3) },
	{ 22050, (2 << 4), (3 << 3) },
	{ 37800, (2 << 4), (4 << 3) },
	{ 44100, (2 << 4), (5 << 3) },
	{ 33075, (2 << 4), (6 << 3) },
	{  6615, (2 << 4), (7 << 3) },
	{ 0, 0, 0}
};

#define CS4215_HPF	(1<<7)	/* High Pass Filter, 1: Enabled */

#define CS4215_12_MASK	0xfcbf	/* Mask off reserved bits in slot 1 & 2 */

/* Time Slot 3, Serial Port Control register */
#define CS4215_XEN	(1<<0)	/* 0: Enable serial output */
#define CS4215_XCLK	(1<<1)	/* 1: Master mode: Generate SCLK */
#define CS4215_BSEL_64	(0<<2)	/* Bitrate: 64 bits per frame */
#define CS4215_BSEL_128	(1<<2)
#define CS4215_BSEL_256	(2<<2)
#define CS4215_MCK_MAST (0<<4)	/* Master clock */
#define CS4215_MCK_XTL1 (1<<4)	/* 24.576 MHz clock source */
#define CS4215_MCK_XTL2 (2<<4)	/* 16.9344 MHz clock source */
#define CS4215_MCK_CLK1 (3<<4)	/* Clockin, 256 x Fs */
#define CS4215_MCK_CLK2 (4<<4)	/* Clockin, see DFR */

/* Time Slot 4, Test Register */
#define CS4215_DAD	(1<<0)	/* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
#define CS4215_ENL	(1<<1)	/* Enable Loopback Testing */

/* Time Slot 5, Parallel Port Register */
/* Read only here and the same as the in data mode */

/* Time Slot 6, Reserved  */

/* Time Slot 7, Version Register  */
#define CS4215_VERSION_MASK 0xf	/* Known versions 0/C, 1/D, 2/E */

/* Time Slot 8, Reserved  */

/*
 * Data mode
 */
/* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data  */

/* Time Slot 5, Output Setting  */
#define CS4215_LO(v)	v	/* Left Output Attenuation 0x3f: -94.5 dB */
#define CS4215_LE	(1<<6)	/* Line Out Enable */
#define CS4215_HE	(1<<7)	/* Headphone Enable */

/* Time Slot 6, Output Setting  */
#define CS4215_RO(v)	v	/* Right Output Attenuation 0x3f: -94.5 dB */
#define CS4215_SE	(1<<6)	/* Speaker Enable */
#define CS4215_ADI	(1<<7)	/* A/D Data Invalid: Busy in calibration */

/* Time Slot 7, Input Setting */
#define CS4215_LG(v)	v	/* Left Gain Setting 0xf: 22.5 dB */
#define CS4215_IS	(1<<4)	/* Input Select: 1=Microphone, 0=Line */
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#define CS4215_OVR	(1<<5)	/* 1: Over range condition occurred */
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#define CS4215_PIO0	(1<<6)	/* Parallel I/O 0 */
#define CS4215_PIO1	(1<<7)

/* Time Slot 8, Input Setting */
#define CS4215_RG(v)	v	/* Right Gain Setting 0xf: 22.5 dB */
#define CS4215_MA(v)	(v<<4)	/* Monitor Path Attenuation 0xf: mute */

/***************************************************************************
		DBRI specific definitions and structures
****************************************************************************/

/* DBRI main registers */
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#define REG0	0x00		/* Status and Control */
#define REG1	0x04		/* Mode and Interrupt */
#define REG2	0x08		/* Parallel IO */
#define REG3	0x0c		/* Test */
#define REG8	0x20		/* Command Queue Pointer */
#define REG9	0x24		/* Interrupt Queue Pointer */
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#define DBRI_NO_CMDS	64
#define DBRI_INT_BLK	64
#define DBRI_NO_DESCS	64
#define DBRI_NO_PIPES	32
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#define DBRI_MAX_PIPE	(DBRI_NO_PIPES - 1)
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#define DBRI_REC	0
#define DBRI_PLAY	1
#define DBRI_NO_STREAMS	2

/* One transmit/receive descriptor */
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/* When ba != 0 descriptor is used */
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struct dbri_mem {
	volatile __u32 word1;
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	__u32 ba;	/* Transmit/Receive Buffer Address */
	__u32 nda;	/* Next Descriptor Address */
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	volatile __u32 word4;
};

/* This structure is in a DMA region where it can accessed by both
 * the CPU and the DBRI
 */
struct dbri_dma {
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	s32 cmd[DBRI_NO_CMDS];			/* Place for commands */
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	volatile s32 intr[DBRI_INT_BLK];	/* Interrupt field  */
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	struct dbri_mem desc[DBRI_NO_DESCS];	/* Xmit/receive descriptors */
};

#define dbri_dma_off(member, elem)	\
	((u32)(unsigned long)		\
	 (&(((struct dbri_dma *)0)->member[elem])))

enum in_or_out { PIPEinput, PIPEoutput };

struct dbri_pipe {
	u32 sdp;		/* SDP command word */
	int nextpipe;		/* Next pipe in linked list */
	int length;		/* Length of timeslot (bits) */
	int first_desc;		/* Index of first descriptor */
	int desc;		/* Index of active descriptor */
	volatile __u32 *recv_fixed_ptr;	/* Ptr to receive fixed data */
};

/* Per stream (playback or record) information */
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struct dbri_streaminfo {
	struct snd_pcm_substream *substream;
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	u32 dvma_buffer;	/* Device view of ALSA DMA buffer */
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	int size;		/* Size of DMA buffer             */
	size_t offset;		/* offset in user buffer          */
	int pipe;		/* Data pipe used                 */
	int left_gain;		/* mixer elements                 */
	int right_gain;
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};
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/* This structure holds the information for both chips (DBRI & CS4215) */
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struct snd_dbri {
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	int regs_size, irq;	/* Needed for unload */
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	struct platform_device *op;	/* OF device info */
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	spinlock_t lock;

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	struct dbri_dma *dma;	/* Pointer to our DMA block */
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	u32 dma_dvma;		/* DBRI visible DMA address */

	void __iomem *regs;	/* dbri HW regs */
	int dbri_irqp;		/* intr queue pointer */

	struct dbri_pipe pipes[DBRI_NO_PIPES];	/* DBRI's 32 data pipes */
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	int next_desc[DBRI_NO_DESCS];		/* Index of next desc, or -1 */
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	spinlock_t cmdlock;	/* Protects cmd queue accesses */
	s32 *cmdptr;		/* Pointer to the last queued cmd */
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	int chi_bpf;

	struct cs4215 mm;	/* mmcodec special info */
				/* per stream (playback/record) info */
	struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
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};
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#define DBRI_MAX_VOLUME		63	/* Output volume */
#define DBRI_MAX_GAIN		15	/* Input gain */

/* DBRI Reg0 - Status Control Register - defines. (Page 17) */
#define D_P		(1<<15)	/* Program command & queue pointer valid */
#define D_G		(1<<14)	/* Allow 4-Word SBus Burst */
#define D_S		(1<<13)	/* Allow 16-Word SBus Burst */
#define D_E		(1<<12)	/* Allow 8-Word SBus Burst */
#define D_X		(1<<7)	/* Sanity Timer Disable */
#define D_T		(1<<6)	/* Permit activation of the TE interface */
#define D_N		(1<<5)	/* Permit activation of the NT interface */
#define D_C		(1<<4)	/* Permit activation of the CHI interface */
#define D_F		(1<<3)	/* Force Sanity Timer Time-Out */
#define D_D		(1<<2)	/* Disable Master Mode */
#define D_H		(1<<1)	/* Halt for Analysis */
#define D_R		(1<<0)	/* Soft Reset */

/* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
#define D_LITTLE_END	(1<<8)	/* Byte Order */
#define D_BIG_END	(0<<8)	/* Byte Order */
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#define D_MRR		(1<<4)	/* Multiple Error Ack on SBus (read only) */
#define D_MLE		(1<<3)	/* Multiple Late Error on SBus (read only) */
#define D_LBG		(1<<2)	/* Lost Bus Grant on SBus (read only) */
#define D_MBE		(1<<1)	/* Burst Error on SBus (read only) */
#define D_IR		(1<<0)	/* Interrupt Indicator (read only) */
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/* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
#define D_ENPIO3	(1<<7)	/* Enable Pin 3 */
#define D_ENPIO2	(1<<6)	/* Enable Pin 2 */
#define D_ENPIO1	(1<<5)	/* Enable Pin 1 */
#define D_ENPIO0	(1<<4)	/* Enable Pin 0 */
#define D_ENPIO		(0xf0)	/* Enable all the pins */
#define D_PIO3		(1<<3)	/* Pin 3: 1: Data mode, 0: Ctrl mode */
#define D_PIO2		(1<<2)	/* Pin 2: 1: Onboard PDN */
#define D_PIO1		(1<<1)	/* Pin 1: 0: Reset */
#define D_PIO0		(1<<0)	/* Pin 0: 1: Speakerbox PDN */

/* DBRI Commands (Page 20) */
#define D_WAIT		0x0	/* Stop execution */
#define D_PAUSE		0x1	/* Flush long pipes */
#define D_JUMP		0x2	/* New command queue */
#define D_IIQ		0x3	/* Initialize Interrupt Queue */
#define D_REX		0x4	/* Report command execution via interrupt */
#define D_SDP		0x5	/* Setup Data Pipe */
#define D_CDP		0x6	/* Continue Data Pipe (reread NULL Pointer) */
#define D_DTS		0x7	/* Define Time Slot */
#define D_SSP		0x8	/* Set short Data Pipe */
#define D_CHI		0x9	/* Set CHI Global Mode */
#define D_NT		0xa	/* NT Command */
#define D_TE		0xb	/* TE Command */
#define D_CDEC		0xc	/* Codec setup */
#define D_TEST		0xd	/* No comment */
#define D_CDM		0xe	/* CHI Data mode command */

/* Special bits for some commands */
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#define D_PIPE(v)      ((v)<<0)	/* Pipe No.: 0-15 long, 16-21 short */
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/* Setup Data Pipe */
/* IRM */
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#define D_SDP_2SAME	(1<<18)	/* Report 2nd time in a row value received */
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#define D_SDP_CHANGE	(2<<18)	/* Report any changes */
#define D_SDP_EVERY	(3<<18)	/* Report any changes */
#define D_SDP_EOL	(1<<17)	/* EOL interrupt enable */
#define D_SDP_IDLE	(1<<16)	/* HDLC idle interrupt enable */

/* Pipe data MODE */
#define D_SDP_MEM	(0<<13)	/* To/from memory */
#define D_SDP_HDLC	(2<<13)
#define D_SDP_HDLC_D	(3<<13)	/* D Channel (prio control) */
#define D_SDP_SER	(4<<13)	/* Serial to serial */
#define D_SDP_FIXED	(6<<13)	/* Short only */
#define D_SDP_MODE(v)	((v)&(7<<13))

#define D_SDP_TO_SER	(1<<12)	/* Direction */
#define D_SDP_FROM_SER	(0<<12)	/* Direction */
#define D_SDP_MSB	(1<<11)	/* Bit order within Byte */
#define D_SDP_LSB	(0<<11)	/* Bit order within Byte */
#define D_SDP_P		(1<<10)	/* Pointer Valid */
#define D_SDP_A		(1<<8)	/* Abort */
#define D_SDP_C		(1<<7)	/* Clear */

/* Define Time Slot */
#define D_DTS_VI	(1<<17)	/* Valid Input Time-Slot Descriptor */
#define D_DTS_VO	(1<<16)	/* Valid Output Time-Slot Descriptor */
#define D_DTS_INS	(1<<15)	/* Insert Time Slot */
#define D_DTS_DEL	(0<<15)	/* Delete Time Slot */
#define D_DTS_PRVIN(v) ((v)<<10)	/* Previous In Pipe */
#define D_DTS_PRVOUT(v)        ((v)<<5)	/* Previous Out Pipe */

/* Time Slot defines */
#define D_TS_LEN(v)	((v)<<24)	/* Number of bits in this time slot */
#define D_TS_CYCLE(v)	((v)<<14)	/* Bit Count at start of TS */
#define D_TS_DI		(1<<13)	/* Data Invert */
#define D_TS_1CHANNEL	(0<<10)	/* Single Channel / Normal mode */
#define D_TS_MONITOR	(2<<10)	/* Monitor pipe */
#define D_TS_NONCONTIG	(3<<10)	/* Non contiguous mode */
#define D_TS_ANCHOR	(7<<10)	/* Starting short pipes */
#define D_TS_MON(v)    ((v)<<5)	/* Monitor Pipe */
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#define D_TS_NEXT(v)   ((v)<<0)	/* Pipe no.: 0-15 long, 16-21 short */
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/* Concentration Highway Interface Modes */
#define D_CHI_CHICM(v)	((v)<<16)	/* Clock mode */
#define D_CHI_IR	(1<<15)	/* Immediate Interrupt Report */
#define D_CHI_EN	(1<<14)	/* CHIL Interrupt enabled */
#define D_CHI_OD	(1<<13)	/* Open Drain Enable */
#define D_CHI_FE	(1<<12)	/* Sample CHIFS on Rising Frame Edge */
#define D_CHI_FD	(1<<11)	/* Frame Drive */
#define D_CHI_BPF(v)	((v)<<0)	/* Bits per Frame */

/* NT: These are here for completeness */
#define D_NT_FBIT	(1<<17)	/* Frame Bit */
#define D_NT_NBF	(1<<16)	/* Number of bad frames to loose framing */
#define D_NT_IRM_IMM	(1<<15)	/* Interrupt Report & Mask: Immediate */
#define D_NT_IRM_EN	(1<<14)	/* Interrupt Report & Mask: Enable */
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#define D_NT_ISNT	(1<<13)	/* Configure interface as NT */
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#define D_NT_FT		(1<<12)	/* Fixed Timing */
#define D_NT_EZ		(1<<11)	/* Echo Channel is Zeros */
#define D_NT_IFA	(1<<10)	/* Inhibit Final Activation */
#define D_NT_ACT	(1<<9)	/* Activate Interface */
#define D_NT_MFE	(1<<8)	/* Multiframe Enable */
#define D_NT_RLB(v)	((v)<<5)	/* Remote Loopback */
#define D_NT_LLB(v)	((v)<<2)	/* Local Loopback */
#define D_NT_FACT	(1<<1)	/* Force Activation */
#define D_NT_ABV	(1<<0)	/* Activate Bipolar Violation */

/* Codec Setup */
#define D_CDEC_CK(v)	((v)<<24)	/* Clock Select */
#define D_CDEC_FED(v)	((v)<<12)	/* FSCOD Falling Edge Delay */
#define D_CDEC_RED(v)	((v)<<0)	/* FSCOD Rising Edge Delay */

/* Test */
#define D_TEST_RAM(v)	((v)<<16)	/* RAM Pointer */
#define D_TEST_SIZE(v)	((v)<<11)	/* */
#define D_TEST_ROMONOFF	0x5	/* Toggle ROM opcode monitor on/off */
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#define D_TEST_PROC	0x6	/* Microprocessor test */
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#define D_TEST_SER	0x7	/* Serial-Controller test */
#define D_TEST_RAMREAD	0x8	/* Copy from Ram to system memory */
#define D_TEST_RAMWRITE	0x9	/* Copy into Ram from system memory */
#define D_TEST_RAMBIST	0xa	/* RAM Built-In Self Test */
#define D_TEST_MCBIST	0xb	/* Microcontroller Built-In Self Test */
#define D_TEST_DUMP	0xe	/* ROM Dump */

/* CHI Data Mode */
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#define D_CDM_THI	(1 << 8)	/* Transmit Data on CHIDR Pin */
#define D_CDM_RHI	(1 << 7)	/* Receive Data on CHIDX Pin */
#define D_CDM_RCE	(1 << 6)	/* Receive on Rising Edge of CHICK */
#define D_CDM_XCE	(1 << 2) /* Transmit Data on Rising Edge of CHICK */
#define D_CDM_XEN	(1 << 1)	/* Transmit Highway Enable */
#define D_CDM_REN	(1 << 0)	/* Receive Highway Enable */
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/* The Interrupts */
#define D_INTR_BRDY	1	/* Buffer Ready for processing */
#define D_INTR_MINT	2	/* Marked Interrupt in RD/TD */
#define D_INTR_IBEG	3	/* Flag to idle transition detected (HDLC) */
#define D_INTR_IEND	4	/* Idle to flag transition detected (HDLC) */
#define D_INTR_EOL	5	/* End of List */
#define D_INTR_CMDI	6	/* Command has bean read */
#define D_INTR_XCMP	8	/* Transmission of frame complete */
#define D_INTR_SBRI	9	/* BRI status change info */
#define D_INTR_FXDT	10	/* Fixed data change */
#define D_INTR_CHIL	11	/* CHI lost frame sync (channel 36 only) */
#define D_INTR_COLL	11	/* Unrecoverable D-Channel collision */
#define D_INTR_DBYT	12	/* Dropped by frame slip */
#define D_INTR_RBYT	13	/* Repeated by frame slip */
#define D_INTR_LINT	14	/* Lost Interrupt */
#define D_INTR_UNDR	15	/* DMA underrun */

#define D_INTR_TE	32
#define D_INTR_NT	34
#define D_INTR_CHI	36
#define D_INTR_CMD	38

496 497 498
#define D_INTR_GETCHAN(v)	(((v) >> 24) & 0x3f)
#define D_INTR_GETCODE(v)	(((v) >> 20) & 0xf)
#define D_INTR_GETCMD(v)	(((v) >> 16) & 0xf)
499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535
#define D_INTR_GETVAL(v)	((v) & 0xffff)
#define D_INTR_GETRVAL(v)	((v) & 0xfffff)

#define D_P_0		0	/* TE receive anchor */
#define D_P_1		1	/* TE transmit anchor */
#define D_P_2		2	/* NT transmit anchor */
#define D_P_3		3	/* NT receive anchor */
#define D_P_4		4	/* CHI send data */
#define D_P_5		5	/* CHI receive data */
#define D_P_6		6	/* */
#define D_P_7		7	/* */
#define D_P_8		8	/* */
#define D_P_9		9	/* */
#define D_P_10		10	/* */
#define D_P_11		11	/* */
#define D_P_12		12	/* */
#define D_P_13		13	/* */
#define D_P_14		14	/* */
#define D_P_15		15	/* */
#define D_P_16		16	/* CHI anchor pipe */
#define D_P_17		17	/* CHI send */
#define D_P_18		18	/* CHI receive */
#define D_P_19		19	/* CHI receive */
#define D_P_20		20	/* CHI receive */
#define D_P_21		21	/* */
#define D_P_22		22	/* */
#define D_P_23		23	/* */
#define D_P_24		24	/* */
#define D_P_25		25	/* */
#define D_P_26		26	/* */
#define D_P_27		27	/* */
#define D_P_28		28	/* */
#define D_P_29		29	/* */
#define D_P_30		30	/* */
#define D_P_31		31	/* */

/* Transmit descriptor defines */
536 537 538 539 540 541 542 543 544 545 546 547
#define DBRI_TD_F	(1 << 31)	/* End of Frame */
#define DBRI_TD_D	(1 << 30)	/* Do not append CRC */
#define DBRI_TD_CNT(v)	((v) << 16) /* Number of valid bytes in the buffer */
#define DBRI_TD_B	(1 << 15)	/* Final interrupt */
#define DBRI_TD_M	(1 << 14)	/* Marker interrupt */
#define DBRI_TD_I	(1 << 13)	/* Transmit Idle Characters */
#define DBRI_TD_FCNT(v)	(v)		/* Flag Count */
#define DBRI_TD_UNR	(1 << 3) /* Underrun: transmitter is out of data */
#define DBRI_TD_ABT	(1 << 2)	/* Abort: frame aborted */
#define DBRI_TD_TBC	(1 << 0)	/* Transmit buffer Complete */
#define DBRI_TD_STATUS(v)       ((v) & 0xff)	/* Transmit status */
			/* Maximum buffer size per TD: almost 8KB */
548
#define DBRI_TD_MAXCNT	((1 << 13) - 4)
549 550

/* Receive descriptor defines */
551 552 553 554 555 556 557 558 559 560 561
#define DBRI_RD_F	(1 << 31)	/* End of Frame */
#define DBRI_RD_C	(1 << 30)	/* Completed buffer */
#define DBRI_RD_B	(1 << 15)	/* Final interrupt */
#define DBRI_RD_M	(1 << 14)	/* Marker interrupt */
#define DBRI_RD_BCNT(v)	(v)		/* Buffer size */
#define DBRI_RD_CRC	(1 << 7)	/* 0: CRC is correct */
#define DBRI_RD_BBC	(1 << 6)	/* 1: Bad Byte received */
#define DBRI_RD_ABT	(1 << 5)	/* Abort: frame aborted */
#define DBRI_RD_OVRN	(1 << 3)	/* Overrun: data lost */
#define DBRI_RD_STATUS(v)      ((v) & 0xff)	/* Receive status */
#define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff)	/* Valid bytes in the buffer */
562 563 564 565

/* stream_info[] access */
/* Translate the ALSA direction into the array index */
#define DBRI_STREAMNO(substream)				\
566
		(substream->stream ==				\
567
		 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)
568 569

/* Return a pointer to dbri_streaminfo */
570 571
#define DBRI_STREAM(dbri, substream)	\
		&dbri->stream_info[DBRI_STREAMNO(substream)]
572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594

/*
 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
 * So we have to reverse the bits. Note: not all bit lengths are supported
 */
static __u32 reverse_bytes(__u32 b, int len)
{
	switch (len) {
	case 32:
		b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
	case 16:
		b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
	case 8:
		b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
	case 4:
		b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
	case 2:
		b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
	case 1:
	case 0:
		break;
	default:
		printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
595
	}
596 597 598 599 600 601 602 603 604 605 606

	return b;
}

/*
****************************************************************************
************** DBRI initialization and command synchronization *************
****************************************************************************

Commands are sent to the DBRI by building a list of them in memory,
then writing the address of the first list item to DBRI register 8.
607 608
The list is terminated with a WAIT command, which generates a
CPU interrupt to signal completion.
609 610

Since the DBRI can run in parallel with the CPU, several means of
611 612
synchronization present themselves. The method implemented here uses
the dbri_cmdwait() to wait for execution of batch of sent commands.
613

614
A circular command buffer is used here. A new command is being added
615
while another can be executed. The scheme works by adding two WAIT commands
616 617
after each sent batch of commands. When the next batch is prepared it is
added after the WAIT commands then the WAITs are replaced with single JUMP
618 619
command to the new batch. The the DBRI is forced to reread the last WAIT
command (replaced by the JUMP by then). If the DBRI is still executing
620
previous commands the request to reread the WAIT command is ignored.
621 622

Every time a routine wants to write commands to the DBRI, it must
623 624 625
first call dbri_cmdlock() and get pointer to a free space in
dbri->dma->cmd buffer. After this, the commands can be written to
the buffer, and dbri_cmdsend() is called with the final pointer value
626
to send them to the DBRI.
627 628 629

*/

630
#define MAXLOOPS 20
631 632 633 634
/*
 * Wait for the current command string to execute
 */
static void dbri_cmdwait(struct snd_dbri *dbri)
635
{
636
	int maxloops = MAXLOOPS;
637
	unsigned long flags;
638 639

	/* Delay if previous commands are still being processed */
640 641 642
	spin_lock_irqsave(&dbri->lock, flags);
	while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
		spin_unlock_irqrestore(&dbri->lock, flags);
643
		msleep_interruptible(1);
644 645 646
		spin_lock_irqsave(&dbri->lock, flags);
	}
	spin_unlock_irqrestore(&dbri->lock, flags);
647

648
	if (maxloops == 0)
649
		printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
650
	else
651 652
		dprintk(D_CMD, "Chip completed command buffer (%d)\n",
			MAXLOOPS - maxloops - 1);
653 654
}
/*
655
 * Lock the command queue and return pointer to space for len cmd words
656 657
 * It locks the cmdlock spinlock.
 */
658
static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
659 660 661 662 663 664 665 666 667 668
{
	/* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
	len += 2;
	spin_lock(&dbri->cmdlock);
	if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
		return dbri->cmdptr + 2;
	else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma)
		return dbri->dma->cmd;
	else
		printk(KERN_ERR "DBRI: no space for commands.");
669

A
Al Viro 已提交
670
	return NULL;
671 672
}

673
/*
674
 * Send prepared cmd string. It works by writing a JUMP cmd into
675
 * the last WAIT cmd and force DBRI to reread the cmd.
676
 * The JUMP cmd points to the new cmd string.
677
 * It also releases the cmdlock spinlock.
678
 *
679
 * Lock must be held before calling this.
680
 */
681
static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
682
{
683 684
	s32 tmp, addr;
	static int wait_id = 0;
685

686 687 688 689
	wait_id++;
	wait_id &= 0xffff;	/* restrict it to a 16 bit counter. */
	*(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
	*(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
690

691 692 693 694
	/* Replace the last command with JUMP */
	addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32);
	*(dbri->cmdptr+1) = addr;
	*(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
695

696
#ifdef DBRI_DEBUG
697 698 699
	if (cmd > dbri->cmdptr) {
		s32 *ptr;

700
		for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
701 702
			dprintk(D_CMD, "cmd: %lx:%08x\n",
				(unsigned long)ptr, *ptr);
703 704 705
	} else {
		s32 *ptr = dbri->cmdptr;

706
		dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
707
		ptr++;
708
		dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
709 710 711
		for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
			dprintk(D_CMD, "cmd: %lx:%08x\n",
				(unsigned long)ptr, *ptr);
712 713
	}
#endif
714

715 716 717 718
	/* Reread the last command */
	tmp = sbus_readl(dbri->regs + REG0);
	tmp |= D_P;
	sbus_writel(tmp, dbri->regs + REG0);
719

720 721
	dbri->cmdptr = cmd;
	spin_unlock(&dbri->cmdlock);
722 723 724
}

/* Lock must be held when calling this */
725
static void dbri_reset(struct snd_dbri *dbri)
726 727
{
	int i;
728
	u32 tmp;
729 730 731 732 733 734 735 736 737

	dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
		sbus_readl(dbri->regs + REG0),
		sbus_readl(dbri->regs + REG2),
		sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));

	sbus_writel(D_R, dbri->regs + REG0);	/* Soft Reset */
	for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
		udelay(10);
738 739 740 741 742 743 744

	/* A brute approach - DBRI falls back to working burst size by itself
	 * On SS20 D_S does not work, so do not try so high. */
	tmp = sbus_readl(dbri->regs + REG0);
	tmp |= D_G | D_E;
	tmp &= ~D_S;
	sbus_writel(tmp, dbri->regs + REG0);
745 746 747
}

/* Lock must not be held before calling this */
748
static void dbri_initialize(struct snd_dbri *dbri)
749
{
750
	s32 *cmd;
751
	u32 dma_addr;
752 753 754 755 756 757 758 759 760 761 762
	unsigned long flags;
	int n;

	spin_lock_irqsave(&dbri->lock, flags);

	dbri_reset(dbri);

	/* Initialize pipes */
	for (n = 0; n < DBRI_NO_PIPES; n++)
		dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;

763
	spin_lock_init(&dbri->cmdlock);
764
	/*
765
	 * Initialize the interrupt ring buffer.
766 767
	 */
	dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
768 769 770 771 772
	dbri->dma->intr[0] = dma_addr;
	dbri->dbri_irqp = 1;
	/*
	 * Set up the interrupt queue
	 */
773 774
	spin_lock(&dbri->cmdlock);
	cmd = dbri->cmdptr = dbri->dma->cmd;
775 776
	*(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
	*(cmd++) = dma_addr;
777 778 779 780 781 782 783
	*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
	dbri->cmdptr = cmd;
	*(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
	*(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
	dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0);
	sbus_writel(dma_addr, dbri->regs + REG8);
	spin_unlock(&dbri->cmdlock);
784 785

	spin_unlock_irqrestore(&dbri->lock, flags);
786
	dbri_cmdwait(dbri);
787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802
}

/*
****************************************************************************
************************** DBRI data pipe management ***********************
****************************************************************************

While DBRI control functions use the command and interrupt buffers, the
main data path takes the form of data pipes, which can be short (command
and interrupt driven), or long (attached to DMA buffers).  These functions
provide a rudimentary means of setting up and managing the DBRI's pipes,
but the calling functions have to make sure they respect the pipes' linked
list ordering, among other things.  The transmit and receive functions
here interface closely with the transmit and receive interrupt code.

*/
803
static inline int pipe_active(struct snd_dbri *dbri, int pipe)
804 805 806 807 808 809 810 811 812
{
	return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
}

/* reset_pipe(dbri, pipe)
 *
 * Called on an in-use pipe to clear anything being transmitted or received
 * Lock must be held before calling this.
 */
813
static void reset_pipe(struct snd_dbri *dbri, int pipe)
814 815 816
{
	int sdp;
	int desc;
817
	s32 *cmd;
818

819
	if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
820 821
		printk(KERN_ERR "DBRI: reset_pipe called with "
			"illegal pipe number\n");
822 823 824 825 826
		return;
	}

	sdp = dbri->pipes[pipe].sdp;
	if (sdp == 0) {
827 828
		printk(KERN_ERR "DBRI: reset_pipe called "
			"on uninitialized pipe\n");
829 830 831
		return;
	}

832
	cmd = dbri_cmdlock(dbri, 3);
833 834
	*(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
	*(cmd++) = 0;
835 836
	*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
	dbri_cmdsend(dbri, cmd, 3);
837 838

	desc = dbri->pipes[pipe].first_desc;
839
	if (desc >= 0)
840
		do {
841 842
			dbri->dma->desc[desc].ba = 0;
			dbri->dma->desc[desc].nda = 0;
843 844
			desc = dbri->next_desc[desc];
		} while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
845 846 847 848 849

	dbri->pipes[pipe].desc = -1;
	dbri->pipes[pipe].first_desc = -1;
}

850 851 852
/*
 * Lock must be held before calling this.
 */
853
static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
854
{
855
	if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
856 857
		printk(KERN_ERR "DBRI: setup_pipe called "
			"with illegal pipe number\n");
858 859 860 861
		return;
	}

	if ((sdp & 0xf800) != sdp) {
862 863
		printk(KERN_ERR "DBRI: setup_pipe called "
			"with strange SDP value\n");
864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880
		/* sdp &= 0xf800; */
	}

	/* If this is a fixed receive pipe, arrange for an interrupt
	 * every time its data changes
	 */
	if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
		sdp |= D_SDP_CHANGE;

	sdp |= D_PIPE(pipe);
	dbri->pipes[pipe].sdp = sdp;
	dbri->pipes[pipe].desc = -1;
	dbri->pipes[pipe].first_desc = -1;

	reset_pipe(dbri, pipe);
}

881 882 883
/*
 * Lock must be held before calling this.
 */
884
static void link_time_slot(struct snd_dbri *dbri, int pipe,
885
			   int prevpipe, int nextpipe,
886 887
			   int length, int cycle)
{
888
	s32 *cmd;
889 890
	int val;

891
	if (pipe < 0 || pipe > DBRI_MAX_PIPE
892 893
			|| prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
			|| nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
894
		printk(KERN_ERR
895
		    "DBRI: link_time_slot called with illegal pipe number\n");
896 897 898
		return;
	}

899
	if (dbri->pipes[pipe].sdp == 0
900 901
			|| dbri->pipes[prevpipe].sdp == 0
			|| dbri->pipes[nextpipe].sdp == 0) {
902 903
		printk(KERN_ERR "DBRI: link_time_slot called "
			"on uninitialized pipe\n");
904 905 906
		return;
	}

907
	dbri->pipes[prevpipe].nextpipe = pipe;
908 909 910
	dbri->pipes[pipe].nextpipe = nextpipe;
	dbri->pipes[pipe].length = length;

911
	cmd = dbri_cmdlock(dbri, 4);
912

913 914 915 916 917 918 919 920 921 922
	if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
		/* Deal with CHI special case:
		 * "If transmission on edges 0 or 1 is desired, then cycle n
		 *  (where n = # of bit times per frame...) must be used."
		 *                  - DBRI data sheet, page 11
		 */
		if (prevpipe == 16 && cycle == 0)
			cycle = dbri->chi_bpf;

		val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
923
		*(cmd++) = DBRI_CMD(D_DTS, 0, val);
924
		*(cmd++) = 0;
925 926 927
		*(cmd++) =
		    D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
	} else {
928
		val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
929 930 931
		*(cmd++) = DBRI_CMD(D_DTS, 0, val);
		*(cmd++) =
		    D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
932
		*(cmd++) = 0;
933
	}
934
	*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
935

936
	dbri_cmdsend(dbri, cmd, 4);
937 938
}

939 940 941 942
#if 0
/*
 * Lock must be held before calling this.
 */
943
static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
944 945 946
			     enum in_or_out direction, int prevpipe,
			     int nextpipe)
{
947
	s32 *cmd;
948 949
	int val;

950
	if (pipe < 0 || pipe > DBRI_MAX_PIPE
951 952
			|| prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
			|| nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
953
		printk(KERN_ERR
954
		    "DBRI: unlink_time_slot called with illegal pipe number\n");
955 956 957
		return;
	}

958
	cmd = dbri_cmdlock(dbri, 4);
959 960 961 962 963 964 965 966 967 968 969 970

	if (direction == PIPEinput) {
		val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
		*(cmd++) = DBRI_CMD(D_DTS, 0, val);
		*(cmd++) = D_TS_NEXT(nextpipe);
		*(cmd++) = 0;
	} else {
		val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
		*(cmd++) = DBRI_CMD(D_DTS, 0, val);
		*(cmd++) = 0;
		*(cmd++) = D_TS_NEXT(nextpipe);
	}
971
	*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
972

973
	dbri_cmdsend(dbri, cmd, 4);
974
}
975
#endif
976 977 978 979 980 981 982 983 984 985 986 987 988

/* xmit_fixed() / recv_fixed()
 *
 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
 * expected to change much, and which we don't need to buffer.
 * The DBRI only interrupts us when the data changes (receive pipes),
 * or only changes the data when this function is called (transmit pipes).
 * Only short pipes (numbers 16-31) can be used in fixed data mode.
 *
 * These function operate on a 32-bit field, no matter how large
 * the actual time slot is.  The interrupt handler takes care of bit
 * ordering and alignment.  An 8-bit time slot will always end up
 * in the low-order 8 bits, filled either MSB-first or LSB-first,
989 990 991
 * depending on the settings passed to setup_pipe().
 *
 * Lock must not be held before calling it.
992
 */
993
static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
994
{
995
	s32 *cmd;
996
	unsigned long flags;
997

998
	if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
999
		printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
1000 1001 1002 1003
		return;
	}

	if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
1004 1005
		printk(KERN_ERR "DBRI: xmit_fixed: "
			"Uninitialized pipe %d\n", pipe);
1006 1007 1008 1009
		return;
	}

	if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1010
		printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
1011 1012 1013 1014
		return;
	}

	if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1015 1016
		printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n",
			pipe);
1017 1018 1019 1020 1021 1022 1023 1024
		return;
	}

	/* DBRI short pipes always transmit LSB first */

	if (dbri->pipes[pipe].sdp & D_SDP_MSB)
		data = reverse_bytes(data, dbri->pipes[pipe].length);

1025
	cmd = dbri_cmdlock(dbri, 3);
1026 1027 1028

	*(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
	*(cmd++) = data;
1029
	*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1030

1031
	spin_lock_irqsave(&dbri->lock, flags);
1032
	dbri_cmdsend(dbri, cmd, 3);
1033
	spin_unlock_irqrestore(&dbri->lock, flags);
1034
	dbri_cmdwait(dbri);
1035

1036 1037
}

1038
static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
1039
{
1040
	if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1041 1042
		printk(KERN_ERR "DBRI: recv_fixed called with "
			"illegal pipe number\n");
1043 1044 1045 1046
		return;
	}

	if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1047 1048
		printk(KERN_ERR "DBRI: recv_fixed called on "
			"non-fixed pipe %d\n", pipe);
1049 1050 1051 1052
		return;
	}

	if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1053 1054
		printk(KERN_ERR "DBRI: recv_fixed called on "
			"transmit pipe %d\n", pipe);
1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071
		return;
	}

	dbri->pipes[pipe].recv_fixed_ptr = ptr;
}

/* setup_descs()
 *
 * Setup transmit/receive data on a "long" pipe - i.e, one associated
 * with a DMA buffer.
 *
 * Only pipe numbers 0-15 can be used in this mode.
 *
 * This function takes a stream number pointing to a data buffer,
 * and work by building chains of descriptors which identify the
 * data buffers.  Buffers too large for a single descriptor will
 * be spread across multiple descriptors.
1072 1073
 *
 * All descriptors create a ring buffer.
1074 1075
 *
 * Lock must be held before calling this.
1076
 */
1077
static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
1078
{
1079
	struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1080
	__u32 dvma_buffer;
1081
	int desc;
1082 1083 1084 1085 1086
	int len;
	int first_desc = -1;
	int last_desc = -1;

	if (info->pipe < 0 || info->pipe > 15) {
1087
		printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1088 1089 1090 1091
		return -2;
	}

	if (dbri->pipes[info->pipe].sdp == 0) {
1092
		printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1093 1094 1095 1096 1097 1098 1099 1100 1101
		       info->pipe);
		return -2;
	}

	dvma_buffer = info->dvma_buffer;
	len = info->size;

	if (streamno == DBRI_PLAY) {
		if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1102 1103
			printk(KERN_ERR "DBRI: setup_descs: "
				"Called on receive pipe %d\n", info->pipe);
1104 1105 1106 1107
			return -2;
		}
	} else {
		if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1108
			printk(KERN_ERR
1109
			    "DBRI: setup_descs: Called on transmit pipe %d\n",
1110 1111 1112
			     info->pipe);
			return -2;
		}
1113 1114 1115
		/* Should be able to queue multiple buffers
		 * to receive on a pipe
		 */
1116
		if (pipe_active(dbri, info->pipe)) {
1117 1118
			printk(KERN_ERR "DBRI: recv_on_pipe: "
				"Called on active pipe %d\n", info->pipe);
1119 1120 1121 1122 1123 1124 1125
			return -2;
		}

		/* Make sure buffer size is multiple of four */
		len &= ~3;
	}

1126 1127
	/* Free descriptors if pipe has any */
	desc = dbri->pipes[info->pipe].first_desc;
1128
	if (desc >= 0)
1129
		do {
1130 1131
			dbri->dma->desc[desc].ba = 0;
			dbri->dma->desc[desc].nda = 0;
1132
			desc = dbri->next_desc[desc];
1133 1134
		} while (desc != -1 &&
			 desc != dbri->pipes[info->pipe].first_desc);
1135 1136 1137 1138 1139

	dbri->pipes[info->pipe].desc = -1;
	dbri->pipes[info->pipe].first_desc = -1;

	desc = 0;
1140 1141 1142 1143
	while (len > 0) {
		int mylen;

		for (; desc < DBRI_NO_DESCS; desc++) {
1144
			if (!dbri->dma->desc[desc].ba)
1145 1146
				break;
		}
1147

1148
		if (desc == DBRI_NO_DESCS) {
1149
			printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1150 1151 1152
			return -1;
		}

1153 1154 1155
		if (len > DBRI_TD_MAXCNT)
			mylen = DBRI_TD_MAXCNT;	/* 8KB - 4 */
		else
1156
			mylen = len;
1157 1158

		if (mylen > period)
1159 1160
			mylen = period;

1161
		dbri->next_desc[desc] = -1;
1162 1163 1164 1165 1166 1167
		dbri->dma->desc[desc].ba = dvma_buffer;
		dbri->dma->desc[desc].nda = 0;

		if (streamno == DBRI_PLAY) {
			dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
			dbri->dma->desc[desc].word4 = 0;
1168
			dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
1169 1170 1171 1172 1173 1174
		} else {
			dbri->dma->desc[desc].word1 = 0;
			dbri->dma->desc[desc].word4 =
			    DBRI_RD_B | DBRI_RD_BCNT(mylen);
		}

1175
		if (first_desc == -1)
1176
			first_desc = desc;
1177
		else {
1178
			dbri->next_desc[last_desc] = desc;
1179 1180 1181 1182 1183 1184 1185 1186 1187 1188
			dbri->dma->desc[last_desc].nda =
			    dbri->dma_dvma + dbri_dma_off(desc, desc);
		}

		last_desc = desc;
		dvma_buffer += mylen;
		len -= mylen;
	}

	if (first_desc == -1 || last_desc == -1) {
1189 1190
		printk(KERN_ERR "DBRI: setup_descs: "
			" Not enough descriptors available\n");
1191 1192 1193
		return -1;
	}

1194 1195 1196
	dbri->dma->desc[last_desc].nda =
	    dbri->dma_dvma + dbri_dma_off(desc, first_desc);
	dbri->next_desc[last_desc] = first_desc;
1197 1198 1199
	dbri->pipes[info->pipe].first_desc = first_desc;
	dbri->pipes[info->pipe].desc = first_desc;

1200
#ifdef DBRI_DEBUG
1201
	for (desc = first_desc; desc != -1;) {
1202 1203 1204 1205 1206
		dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
			desc,
			dbri->dma->desc[desc].word1,
			dbri->dma->desc[desc].ba,
			dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1207
			desc = dbri->next_desc[desc];
1208
			if (desc == first_desc)
1209
				break;
1210
	}
1211
#endif
1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227
	return 0;
}

/*
****************************************************************************
************************** DBRI - CHI interface ****************************
****************************************************************************

The CHI is a four-wire (clock, frame sync, data in, data out) time-division
multiplexed serial interface which the DBRI can operate in either master
(give clock/frame sync) or slave (take clock/frame sync) mode.

*/

enum master_or_slave { CHImaster, CHIslave };

1228 1229 1230
/*
 * Lock must not be held before calling it.
 */
1231 1232
static void reset_chi(struct snd_dbri *dbri,
		      enum master_or_slave master_or_slave,
1233 1234
		      int bits_per_frame)
{
1235
	s32 *cmd;
1236 1237
	int val;

1238
	/* Set CHI Anchor: Pipe 16 */
1239

1240
	cmd = dbri_cmdlock(dbri, 4);
1241
	val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1242 1243 1244 1245 1246 1247
		| D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
	*(cmd++) = DBRI_CMD(D_DTS, 0, val);
	*(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
	*(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
	*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
	dbri_cmdsend(dbri, cmd, 4);
1248

1249 1250
	dbri->pipes[16].sdp = 1;
	dbri->pipes[16].nextpipe = 16;
1251

1252
	cmd = dbri_cmdlock(dbri, 4);
1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264

	if (master_or_slave == CHIslave) {
		/* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
		 *
		 * CHICM  = 0 (slave mode, 8 kHz frame rate)
		 * IR     = give immediate CHI status interrupt
		 * EN     = give CHI status interrupt upon change
		 */
		*(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
	} else {
		/* Setup DBRI for CHI Master - generate clock, FS
		 *
1265 1266 1267
		 * BPF				=  bits per 8 kHz frame
		 * 12.288 MHz / CHICM_divisor	= clock rate
		 * FD = 1 - drive CHIFS on rising edge of CHICK
1268 1269 1270 1271 1272
		 */
		int clockrate = bits_per_frame * 8;
		int divisor = 12288 / clockrate;

		if (divisor > 255 || divisor * clockrate != 12288)
1273 1274
			printk(KERN_ERR "DBRI: illegal bits_per_frame "
				"in setup_chi\n");
1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291

		*(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
				    | D_CHI_BPF(bits_per_frame));
	}

	dbri->chi_bpf = bits_per_frame;

	/* CHI Data Mode
	 *
	 * RCE   =  0 - receive on falling edge of CHICK
	 * XCE   =  1 - transmit on rising edge of CHICK
	 * XEN   =  1 - enable transmitter
	 * REN   =  1 - enable receiver
	 */

	*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
	*(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1292
	*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1293

1294
	dbri_cmdsend(dbri, cmd, 4);
1295 1296 1297 1298 1299 1300 1301 1302 1303 1304
}

/*
****************************************************************************
*********************** CS4215 audio codec management **********************
****************************************************************************

In the standard SPARC audio configuration, the CS4215 codec is attached
to the DBRI via the CHI interface and few of the DBRI's PIO pins.

1305 1306
 * Lock must not be held before calling it.

1307
*/
1308
static void cs4215_setup_pipes(struct snd_dbri *dbri)
1309
{
1310 1311 1312
	unsigned long flags;

	spin_lock_irqsave(&dbri->lock, flags);
1313 1314 1315 1316 1317 1318 1319 1320 1321 1322
	/*
	 * Data mode:
	 * Pipe  4: Send timeslots 1-4 (audio data)
	 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
	 * Pipe  6: Receive timeslots 1-4 (audio data)
	 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
	 *          interrupt, and the rest of the data (slot 5 and 8) is
	 *          not relevant for us (only for doublechecking).
	 *
	 * Control mode:
1323
	 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1324
	 * Pipe 18: Receive timeslot 1 (clb).
1325
	 * Pipe 19: Receive timeslot 7 (version).
1326 1327 1328 1329 1330 1331 1332 1333 1334 1335
	 */

	setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
	setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
	setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
	setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);

	setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
	setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
	setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1336
	spin_unlock_irqrestore(&dbri->lock, flags);
1337 1338

	dbri_cmdwait(dbri);
1339 1340
}

1341
static int cs4215_init_data(struct cs4215 *mm)
1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369
{
	/*
	 * No action, memory resetting only.
	 *
	 * Data Time Slot 5-8
	 * Speaker,Line and Headphone enable. Gain set to the half.
	 * Input is mike.
	 */
	mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
	mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
	mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
	mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);

	/*
	 * Control Time Slot 1-4
	 * 0: Default I/O voltage scale
	 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
	 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
	 * 3: Tests disabled
	 */
	mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
	mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
	mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
	mm->ctrl[3] = 0;

	mm->status = 0;
	mm->version = 0xff;
	mm->precision = 8;	/* For ULAW */
1370
	mm->channels = 1;
1371 1372 1373 1374

	return 0;
}

1375
static void cs4215_setdata(struct snd_dbri *dbri, int muted)
1376 1377 1378 1379 1380 1381 1382 1383
{
	if (muted) {
		dbri->mm.data[0] |= 63;
		dbri->mm.data[1] |= 63;
		dbri->mm.data[2] &= ~15;
		dbri->mm.data[3] &= ~15;
	} else {
		/* Start by setting the playback attenuation. */
1384
		struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1385 1386
		int left_gain = info->left_gain & 0x3f;
		int right_gain = info->right_gain & 0x3f;
1387 1388 1389 1390 1391 1392 1393 1394

		dbri->mm.data[0] &= ~0x3f;	/* Reset the volume bits */
		dbri->mm.data[1] &= ~0x3f;
		dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
		dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);

		/* Now set the recording gain. */
		info = &dbri->stream_info[DBRI_REC];
1395 1396
		left_gain = info->left_gain & 0xf;
		right_gain = info->right_gain & 0xf;
1397 1398 1399 1400 1401 1402 1403 1404 1405 1406
		dbri->mm.data[2] |= CS4215_LG(left_gain);
		dbri->mm.data[3] |= CS4215_RG(right_gain);
	}

	xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
}

/*
 * Set the CS4215 to data mode.
 */
1407
static void cs4215_open(struct snd_dbri *dbri)
1408 1409 1410
{
	int data_width;
	u32 tmp;
1411
	unsigned long flags;
1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435

	dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
		dbri->mm.channels, dbri->mm.precision);

	/* Temporarily mute outputs, and wait 1/8000 sec (125 us)
	 * to make sure this takes.  This avoids clicking noises.
	 */

	cs4215_setdata(dbri, 1);
	udelay(125);

	/*
	 * Data mode:
	 * Pipe  4: Send timeslots 1-4 (audio data)
	 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
	 * Pipe  6: Receive timeslots 1-4 (audio data)
	 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
	 *          interrupt, and the rest of the data (slot 5 and 8) is
	 *          not relevant for us (only for doublechecking).
	 *
	 * Just like in control mode, the time slots are all offset by eight
	 * bits.  The CS4215, it seems, observes TSIN (the delayed signal)
	 * even if it's the CHI master.  Don't ask me...
	 */
1436
	spin_lock_irqsave(&dbri->lock, flags);
1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454
	tmp = sbus_readl(dbri->regs + REG0);
	tmp &= ~(D_C);		/* Disable CHI */
	sbus_writel(tmp, dbri->regs + REG0);

	/* Switch CS4215 to data mode - set PIO3 to 1 */
	sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
		    (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);

	reset_chi(dbri, CHIslave, 128);

	/* Note: this next doesn't work for 8-bit stereo, because the two
	 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
	 * (See CS4215 datasheet Fig 15)
	 *
	 * DBRI non-contiguous mode would be required to make this work.
	 */
	data_width = dbri->mm.channels * dbri->mm.precision;

1455 1456 1457 1458
	link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
	link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
	link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
	link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1459 1460 1461 1462 1463

	/* FIXME: enable CHI after _setdata? */
	tmp = sbus_readl(dbri->regs + REG0);
	tmp |= D_C;		/* Enable CHI */
	sbus_writel(tmp, dbri->regs + REG0);
1464
	spin_unlock_irqrestore(&dbri->lock, flags);
1465 1466 1467 1468 1469 1470 1471

	cs4215_setdata(dbri, 0);
}

/*
 * Send the control information (i.e. audio format)
 */
1472
static int cs4215_setctrl(struct snd_dbri *dbri)
1473 1474 1475
{
	int i, val;
	u32 tmp;
1476
	unsigned long flags;
1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512

	/* FIXME - let the CPU do something useful during these delays */

	/* Temporarily mute outputs, and wait 1/8000 sec (125 us)
	 * to make sure this takes.  This avoids clicking noises.
	 */
	cs4215_setdata(dbri, 1);
	udelay(125);

	/*
	 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
	 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
	 */
	val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
	sbus_writel(val, dbri->regs + REG2);
	dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
	udelay(34);

	/* In Control mode, the CS4215 is a slave device, so the DBRI must
	 * operate as CHI master, supplying clocking and frame synchronization.
	 *
	 * In Data mode, however, the CS4215 must be CHI master to insure
	 * that its data stream is synchronous with its codec.
	 *
	 * The upshot of all this?  We start by putting the DBRI into master
	 * mode, program the CS4215 in Control mode, then switch the CS4215
	 * into Data mode and put the DBRI into slave mode.  Various timing
	 * requirements must be observed along the way.
	 *
	 * Oh, and one more thing, on a SPARCStation 20 (and maybe
	 * others?), the addressing of the CS4215's time slots is
	 * offset by eight bits, so we add eight to all the "cycle"
	 * values in the Define Time Slot (DTS) commands.  This is
	 * done in hardware by a TI 248 that delays the DBRI->4215
	 * frame sync signal by eight clock cycles.  Anybody know why?
	 */
1513
	spin_lock_irqsave(&dbri->lock, flags);
1514 1515 1516 1517 1518 1519 1520 1521
	tmp = sbus_readl(dbri->regs + REG0);
	tmp &= ~D_C;		/* Disable CHI */
	sbus_writel(tmp, dbri->regs + REG0);

	reset_chi(dbri, CHImaster, 128);

	/*
	 * Control mode:
1522
	 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1523
	 * Pipe 18: Receive timeslot 1 (clb).
1524
	 * Pipe 19: Receive timeslot 7 (version).
1525 1526
	 */

1527 1528 1529
	link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
	link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
	link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1530
	spin_unlock_irqrestore(&dbri->lock, flags);
1531 1532 1533 1534 1535

	/* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
	dbri->mm.ctrl[0] &= ~CS4215_CLB;
	xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);

1536
	spin_lock_irqsave(&dbri->lock, flags);
1537 1538 1539
	tmp = sbus_readl(dbri->regs + REG0);
	tmp |= D_C;		/* Enable CHI */
	sbus_writel(tmp, dbri->regs + REG0);
1540
	spin_unlock_irqrestore(&dbri->lock, flags);
1541

1542
	for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1543
		msleep_interruptible(1);
1544

1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575
	if (i == 0) {
		dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
			dbri->mm.status);
		return -1;
	}

	/* Disable changes to our copy of the version number, as we are about
	 * to leave control mode.
	 */
	recv_fixed(dbri, 19, NULL);

	/* Terminate CS4215 control mode - data sheet says
	 * "Set CLB=1 and send two more frames of valid control info"
	 */
	dbri->mm.ctrl[0] |= CS4215_CLB;
	xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);

	/* Two frames of control info @ 8kHz frame rate = 250 us delay */
	udelay(250);

	cs4215_setdata(dbri, 0);

	return 0;
}

/*
 * Setup the codec with the sampling rate, audio format and number of
 * channels.
 * As part of the process we resend the settings for the data
 * timeslots as well.
 */
1576
static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619
			  snd_pcm_format_t format, unsigned int channels)
{
	int freq_idx;
	int ret = 0;

	/* Lookup index for this rate */
	for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
		if (CS4215_FREQ[freq_idx].freq == rate)
			break;
	}
	if (CS4215_FREQ[freq_idx].freq != rate) {
		printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
		return -1;
	}

	switch (format) {
	case SNDRV_PCM_FORMAT_MU_LAW:
		dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
		dbri->mm.precision = 8;
		break;
	case SNDRV_PCM_FORMAT_A_LAW:
		dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
		dbri->mm.precision = 8;
		break;
	case SNDRV_PCM_FORMAT_U8:
		dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
		dbri->mm.precision = 8;
		break;
	case SNDRV_PCM_FORMAT_S16_BE:
		dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
		dbri->mm.precision = 16;
		break;
	default:
		printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
		return -1;
	}

	/* Add rate parameters */
	dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
	dbri->mm.ctrl[2] = CS4215_XCLK |
	    CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;

	dbri->mm.channels = channels;
1620
	if (channels == 2)
1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632
		dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;

	ret = cs4215_setctrl(dbri);
	if (ret == 0)
		cs4215_open(dbri);	/* set codec to data mode */

	return ret;
}

/*
 *
 */
1633
static int cs4215_init(struct snd_dbri *dbri)
1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687
{
	u32 reg2 = sbus_readl(dbri->regs + REG2);
	dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);

	/* Look for the cs4215 chips */
	if (reg2 & D_PIO2) {
		dprintk(D_MM, "Onboard CS4215 detected\n");
		dbri->mm.onboard = 1;
	}
	if (reg2 & D_PIO0) {
		dprintk(D_MM, "Speakerbox detected\n");
		dbri->mm.onboard = 0;

		if (reg2 & D_PIO2) {
			printk(KERN_INFO "DBRI: Using speakerbox / "
			       "ignoring onboard mmcodec.\n");
			sbus_writel(D_ENPIO2, dbri->regs + REG2);
		}
	}

	if (!(reg2 & (D_PIO0 | D_PIO2))) {
		printk(KERN_ERR "DBRI: no mmcodec found.\n");
		return -EIO;
	}

	cs4215_setup_pipes(dbri);
	cs4215_init_data(&dbri->mm);

	/* Enable capture of the status & version timeslots. */
	recv_fixed(dbri, 18, &dbri->mm.status);
	recv_fixed(dbri, 19, &dbri->mm.version);

	dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
	if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
		dprintk(D_MM, "CS4215 failed probe at offset %d\n",
			dbri->mm.offset);
		return -EIO;
	}
	dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);

	return 0;
}

/*
****************************************************************************
*************************** DBRI interrupt handler *************************
****************************************************************************

The DBRI communicates with the CPU mainly via a circular interrupt
buffer.  When an interrupt is signaled, the CPU walks through the
buffer and calls dbri_process_one_interrupt() for each interrupt word.
Complicated interrupts are handled by dedicated functions (which
appear first in this file).  Any pending interrupts can be serviced by
calling dbri_process_interrupt_buffer(), which works even if the CPU's
1688
interrupts are disabled.
1689 1690 1691 1692 1693

*/

/* xmit_descs()
 *
1694
 * Starts transmitting the current TD's for recording/playing.
1695 1696
 * For playback, ALSA has filled the DMA memory with new data (we hope).
 */
1697
static void xmit_descs(struct snd_dbri *dbri)
1698
{
1699
	struct dbri_streaminfo *info;
1700
	s32 *cmd;
1701 1702 1703 1704 1705 1706 1707 1708 1709
	unsigned long flags;
	int first_td;

	if (dbri == NULL)
		return;		/* Disabled */

	info = &dbri->stream_info[DBRI_REC];
	spin_lock_irqsave(&dbri->lock, flags);

1710
	if (info->pipe >= 0) {
1711 1712 1713 1714 1715
		first_td = dbri->pipes[info->pipe].first_desc;

		dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);

		/* Stream could be closed by the time we run. */
1716 1717 1718 1719 1720
		if (first_td >= 0) {
			cmd = dbri_cmdlock(dbri, 2);
			*(cmd++) = DBRI_CMD(D_SDP, 0,
					    dbri->pipes[info->pipe].sdp
					    | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1721 1722
			*(cmd++) = dbri->dma_dvma +
				   dbri_dma_off(desc, first_td);
1723
			dbri_cmdsend(dbri, cmd, 2);
1724

1725 1726 1727
			/* Reset our admin of the pipe. */
			dbri->pipes[info->pipe].desc = first_td;
		}
1728 1729 1730 1731
	}

	info = &dbri->stream_info[DBRI_PLAY];

1732
	if (info->pipe >= 0) {
1733 1734 1735 1736 1737
		first_td = dbri->pipes[info->pipe].first_desc;

		dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);

		/* Stream could be closed by the time we run. */
1738 1739 1740 1741 1742
		if (first_td >= 0) {
			cmd = dbri_cmdlock(dbri, 2);
			*(cmd++) = DBRI_CMD(D_SDP, 0,
					    dbri->pipes[info->pipe].sdp
					    | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1743 1744
			*(cmd++) = dbri->dma_dvma +
				   dbri_dma_off(desc, first_td);
1745
			dbri_cmdsend(dbri, cmd, 2);
1746

1747
			/* Reset our admin of the pipe. */
1748 1749
			dbri->pipes[info->pipe].desc = first_td;
		}
1750
	}
1751

1752 1753 1754 1755 1756 1757 1758 1759
	spin_unlock_irqrestore(&dbri->lock, flags);
}

/* transmission_complete_intr()
 *
 * Called by main interrupt handler when DBRI signals transmission complete
 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
 *
1760 1761
 * Walks through the pipe's list of transmit buffer descriptors and marks
 * them as available. Stops when the first descriptor is found without
1762
 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1763
 *
1764 1765 1766
 * The DMA buffers are not released. They form a ring buffer and
 * they are filled by ALSA while others are transmitted by DMA.
 *
1767 1768
 */

1769
static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
1770
{
1771 1772
	struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
	int td = dbri->pipes[pipe].desc;
1773 1774 1775 1776 1777 1778 1779 1780 1781
	int status;

	while (td >= 0) {
		if (td >= DBRI_NO_DESCS) {
			printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
			return;
		}

		status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1782
		if (!(status & DBRI_TD_TBC))
1783 1784 1785 1786 1787
			break;

		dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);

		dbri->dma->desc[td].word4 = 0;	/* Reset it for next time. */
1788
		info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1789

1790
		td = dbri->next_desc[td];
1791 1792 1793 1794
		dbri->pipes[pipe].desc = td;
	}

	/* Notify ALSA */
1795 1796 1797
	spin_unlock(&dbri->lock);
	snd_pcm_period_elapsed(info->substream);
	spin_lock(&dbri->lock);
1798 1799
}

1800
static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
1801
{
1802
	struct dbri_streaminfo *info;
1803 1804 1805 1806 1807 1808 1809 1810
	int rd = dbri->pipes[pipe].desc;
	s32 status;

	if (rd < 0 || rd >= DBRI_NO_DESCS) {
		printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
		return;
	}

1811
	dbri->pipes[pipe].desc = dbri->next_desc[rd];
1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823
	status = dbri->dma->desc[rd].word1;
	dbri->dma->desc[rd].word1 = 0;	/* Reset it for next time. */

	info = &dbri->stream_info[DBRI_REC];
	info->offset += DBRI_RD_CNT(status);

	/* FIXME: Check status */

	dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
		rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));

	/* Notify ALSA */
1824 1825 1826
	spin_unlock(&dbri->lock);
	snd_pcm_period_elapsed(info->substream);
	spin_lock(&dbri->lock);
1827 1828
}

1829
static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847
{
	int val = D_INTR_GETVAL(x);
	int channel = D_INTR_GETCHAN(x);
	int command = D_INTR_GETCMD(x);
	int code = D_INTR_GETCODE(x);
#ifdef DBRI_DEBUG
	int rval = D_INTR_GETRVAL(x);
#endif

	if (channel == D_INTR_CMD) {
		dprintk(D_CMD, "INTR: Command: %-5s  Value:%d\n",
			cmds[command], val);
	} else {
		dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
			channel, code, rval);
	}

	switch (code) {
1848 1849 1850 1851
	case D_INTR_CMDI:
		if (command != D_WAIT)
			printk(KERN_ERR "DBRI: Command read interrupt\n");
		break;
1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863
	case D_INTR_BRDY:
		reception_complete_intr(dbri, channel);
		break;
	case D_INTR_XCMP:
	case D_INTR_MINT:
		transmission_complete_intr(dbri, channel);
		break;
	case D_INTR_UNDR:
		/* UNDR - Transmission underrun
		 * resend SDP command with clear pipe bit (C) set
		 */
		{
1864 1865 1866 1867
	/* FIXME: do something useful in case of underrun */
			printk(KERN_ERR "DBRI: Underrun error\n");
#if 0
			s32 *cmd;
1868 1869 1870 1871 1872 1873 1874 1875 1876 1877
			int pipe = channel;
			int td = dbri->pipes[pipe].desc;

			dbri->dma->desc[td].word4 = 0;
			cmd = dbri_cmdlock(dbri, NoGetLock);
			*(cmd++) = DBRI_CMD(D_SDP, 0,
					    dbri->pipes[pipe].sdp
					    | D_SDP_P | D_SDP_C | D_SDP_2SAME);
			*(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
			dbri_cmdsend(dbri, cmd);
1878
#endif
1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898
		}
		break;
	case D_INTR_FXDT:
		/* FXDT - Fixed data change */
		if (dbri->pipes[channel].sdp & D_SDP_MSB)
			val = reverse_bytes(val, dbri->pipes[channel].length);

		if (dbri->pipes[channel].recv_fixed_ptr)
			*(dbri->pipes[channel].recv_fixed_ptr) = val;
		break;
	default:
		if (channel != D_INTR_CMD)
			printk(KERN_WARNING
			       "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
	}
}

/* dbri_process_interrupt_buffer advances through the DBRI's interrupt
 * buffer until it finds a zero word (indicating nothing more to do
 * right now).  Non-zero words require processing and are handed off
1899
 * to dbri_process_one_interrupt AFTER advancing the pointer.
1900
 */
1901
static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
1902 1903 1904 1905 1906 1907
{
	s32 x;

	while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
		dbri->dma->intr[dbri->dbri_irqp] = 0;
		dbri->dbri_irqp++;
1908
		if (dbri->dbri_irqp == DBRI_INT_BLK)
1909 1910 1911 1912 1913 1914
			dbri->dbri_irqp = 1;

		dbri_process_one_interrupt(dbri, x);
	}
}

1915
static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
1916
{
1917
	struct snd_dbri *dbri = dev_id;
1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953
	static int errcnt = 0;
	int x;

	if (dbri == NULL)
		return IRQ_NONE;
	spin_lock(&dbri->lock);

	/*
	 * Read it, so the interrupt goes away.
	 */
	x = sbus_readl(dbri->regs + REG1);

	if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
		u32 tmp;

		if (x & D_MRR)
			printk(KERN_ERR
			       "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
			       x);
		if (x & D_MLE)
			printk(KERN_ERR
			       "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
			       x);
		if (x & D_LBG)
			printk(KERN_ERR
			       "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
		if (x & D_MBE)
			printk(KERN_ERR
			       "DBRI: Burst Error on SBus reg1=0x%x\n", x);

		/* Some of these SBus errors cause the chip's SBus circuitry
		 * to be disabled, so just re-enable and try to keep going.
		 *
		 * The only one I've seen is MRR, which will be triggered
		 * if you let a transmit pipe underrun, then try to CDP it.
		 *
1954
		 * If these things persist, we reset the chip.
1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975
		 */
		if ((++errcnt) % 10 == 0) {
			dprintk(D_INT, "Interrupt errors exceeded.\n");
			dbri_reset(dbri);
		} else {
			tmp = sbus_readl(dbri->regs + REG0);
			tmp &= ~(D_D);
			sbus_writel(tmp, dbri->regs + REG0);
		}
	}

	dbri_process_interrupt_buffer(dbri);

	spin_unlock(&dbri->lock);

	return IRQ_HANDLED;
}

/****************************************************************************
		PCM Interface
****************************************************************************/
1976
static struct snd_pcm_hardware snd_dbri_pcm_hw = {
1977 1978 1979
	.info		= SNDRV_PCM_INFO_MMAP |
			  SNDRV_PCM_INFO_INTERLEAVED |
			  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1980 1981
			  SNDRV_PCM_INFO_MMAP_VALID |
			  SNDRV_PCM_INFO_BATCH,
1982 1983 1984 1985 1986
	.formats	= SNDRV_PCM_FMTBIT_MU_LAW |
			  SNDRV_PCM_FMTBIT_A_LAW |
			  SNDRV_PCM_FMTBIT_U8 |
			  SNDRV_PCM_FMTBIT_S16_BE,
	.rates		= SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
1987
	.rate_min		= 5512,
1988 1989 1990
	.rate_max		= 48000,
	.channels_min		= 1,
	.channels_max		= 2,
1991
	.buffer_bytes_max	= 64 * 1024,
1992 1993 1994 1995 1996 1997
	.period_bytes_min	= 1,
	.period_bytes_max	= DBRI_TD_MAXCNT,
	.periods_min		= 1,
	.periods_max		= 1024,
};

1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023
static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
			      struct snd_pcm_hw_rule *rule)
{
	struct snd_interval *c = hw_param_interval(params,
				SNDRV_PCM_HW_PARAM_CHANNELS);
	struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
	struct snd_mask fmt;

	snd_mask_any(&fmt);
	if (c->min > 1) {
		fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
		return snd_mask_refine(f, &fmt);
	}
	return 0;
}

static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
				struct snd_pcm_hw_rule *rule)
{
	struct snd_interval *c = hw_param_interval(params,
				SNDRV_PCM_HW_PARAM_CHANNELS);
	struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
	struct snd_interval ch;

	snd_interval_any(&ch);
	if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
2024 2025
		ch.min = 1;
		ch.max = 1;
2026 2027 2028 2029 2030 2031
		ch.integer = 1;
		return snd_interval_refine(c, &ch);
	}
	return 0;
}

2032
static int snd_dbri_open(struct snd_pcm_substream *substream)
2033
{
2034 2035 2036
	struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048
	unsigned long flags;

	dprintk(D_USR, "open audio output.\n");
	runtime->hw = snd_dbri_pcm_hw;

	spin_lock_irqsave(&dbri->lock, flags);
	info->substream = substream;
	info->offset = 0;
	info->dvma_buffer = 0;
	info->pipe = -1;
	spin_unlock_irqrestore(&dbri->lock, flags);

2049
	snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
A
Al Viro 已提交
2050
			    snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
2051
			    -1);
2052 2053
	snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
			    snd_hw_rule_channels, NULL,
2054 2055
			    SNDRV_PCM_HW_PARAM_CHANNELS,
			    -1);
2056

2057 2058 2059 2060 2061
	cs4215_open(dbri);

	return 0;
}

2062
static int snd_dbri_close(struct snd_pcm_substream *substream)
2063
{
2064 2065
	struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
	struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2066 2067 2068 2069 2070 2071 2072 2073

	dprintk(D_USR, "close audio output.\n");
	info->substream = NULL;
	info->offset = 0;

	return 0;
}

2074 2075
static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
			      struct snd_pcm_hw_params *hw_params)
2076
{
2077 2078 2079
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
	struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091
	int direction;
	int ret;

	/* set sampling rate, audio format and number of channels */
	ret = cs4215_prepare(dbri, params_rate(hw_params),
			     params_format(hw_params),
			     params_channels(hw_params));
	if (ret != 0)
		return ret;

	if ((ret = snd_pcm_lib_malloc_pages(substream,
				params_buffer_bytes(hw_params))) < 0) {
2092
		printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2093 2094 2095 2096 2097 2098 2099
		return ret;
	}

	/* hw_params can get called multiple times. Only map the DMA once.
	 */
	if (info->dvma_buffer == 0) {
		if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2100
			direction = DMA_TO_DEVICE;
2101
		else
2102
			direction = DMA_FROM_DEVICE;
2103

2104
		info->dvma_buffer =
2105
			dma_map_single(&dbri->op->dev,
2106 2107 2108
				       runtime->dma_area,
				       params_buffer_bytes(hw_params),
				       direction);
2109 2110 2111 2112 2113 2114 2115 2116
	}

	direction = params_buffer_bytes(hw_params);
	dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
		direction, info->dvma_buffer);
	return 0;
}

2117
static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2118
{
2119 2120
	struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
	struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2121
	int direction;
2122

2123 2124 2125 2126 2127 2128
	dprintk(D_USR, "hw_free.\n");

	/* hw_free can get called multiple times. Only unmap the DMA once.
	 */
	if (info->dvma_buffer) {
		if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2129
			direction = DMA_TO_DEVICE;
2130
		else
2131
			direction = DMA_FROM_DEVICE;
2132

2133
		dma_unmap_single(&dbri->op->dev, info->dvma_buffer,
2134
				 substream->runtime->buffer_size, direction);
2135 2136
		info->dvma_buffer = 0;
	}
2137 2138 2139 2140
	if (info->pipe != -1) {
		reset_pipe(dbri, info->pipe);
		info->pipe = -1;
	}
2141 2142 2143 2144

	return snd_pcm_lib_free_pages(substream);
}

2145
static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2146
{
2147 2148
	struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
	struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2149 2150 2151 2152 2153
	int ret;

	info->size = snd_pcm_lib_buffer_bytes(substream);
	if (DBRI_STREAMNO(substream) == DBRI_PLAY)
		info->pipe = 4;	/* Send pipe */
2154
	else
2155 2156 2157
		info->pipe = 6;	/* Receive pipe */

	spin_lock_irq(&dbri->lock);
2158
	info->offset = 0;
2159

2160
	/* Setup the all the transmit/receive descriptors to cover the
2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171
	 * whole DMA buffer.
	 */
	ret = setup_descs(dbri, DBRI_STREAMNO(substream),
			  snd_pcm_lib_period_bytes(substream));

	spin_unlock_irq(&dbri->lock);

	dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
	return ret;
}

2172
static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2173
{
2174 2175
	struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
	struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2176 2177 2178 2179 2180 2181
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		dprintk(D_USR, "start audio, period is %d bytes\n",
			(int)snd_pcm_lib_period_bytes(substream));
2182 2183
		/* Re-submit the TDs. */
		xmit_descs(dbri);
2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195
		break;
	case SNDRV_PCM_TRIGGER_STOP:
		dprintk(D_USR, "stop audio.\n");
		reset_pipe(dbri, info->pipe);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

2196
static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2197
{
2198 2199
	struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
	struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2200 2201 2202 2203
	snd_pcm_uframes_t ret;

	ret = bytes_to_frames(substream->runtime, info->offset)
		% substream->runtime->buffer_size;
2204 2205
	dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
		ret, substream->runtime->buffer_size);
2206 2207 2208
	return ret;
}

2209
static struct snd_pcm_ops snd_dbri_ops = {
2210 2211 2212 2213 2214 2215 2216 2217 2218 2219
	.open = snd_dbri_open,
	.close = snd_dbri_close,
	.ioctl = snd_pcm_lib_ioctl,
	.hw_params = snd_dbri_hw_params,
	.hw_free = snd_dbri_hw_free,
	.prepare = snd_dbri_prepare,
	.trigger = snd_dbri_trigger,
	.pointer = snd_dbri_pointer,
};

2220
static int snd_dbri_pcm(struct snd_card *card)
2221
{
2222
	struct snd_pcm *pcm;
2223 2224
	int err;

2225
	if ((err = snd_pcm_new(card,
2226 2227 2228 2229 2230 2231 2232 2233 2234
			       /* ID */		    "sun_dbri",
			       /* device */	    0,
			       /* playback count */ 1,
			       /* capture count */  1, &pcm)) < 0)
		return err;

	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);

2235
	pcm->private_data = card->private_data;
2236
	pcm->info_flags = 0;
2237
	strcpy(pcm->name, card->shortname);
2238 2239 2240 2241

	if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
			SNDRV_DMA_TYPE_CONTINUOUS,
			snd_dma_continuous_data(GFP_KERNEL),
2242
			64 * 1024, 64 * 1024)) < 0)
2243 2244 2245 2246 2247 2248 2249 2250 2251
		return err;

	return 0;
}

/*****************************************************************************
			Mixer interface
*****************************************************************************/

2252 2253
static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
				  struct snd_ctl_elem_info *uinfo)
2254 2255 2256 2257
{
	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
	uinfo->count = 2;
	uinfo->value.integer.min = 0;
2258
	if (kcontrol->private_value == DBRI_PLAY)
2259
		uinfo->value.integer.max = DBRI_MAX_VOLUME;
2260
	else
2261 2262 2263 2264
		uinfo->value.integer.max = DBRI_MAX_GAIN;
	return 0;
}

2265 2266
static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
				 struct snd_ctl_elem_value *ucontrol)
2267
{
2268 2269
	struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
	struct dbri_streaminfo *info;
2270 2271 2272

	if (snd_BUG_ON(!dbri))
		return -EINVAL;
2273 2274 2275 2276 2277 2278 2279
	info = &dbri->stream_info[kcontrol->private_value];

	ucontrol->value.integer.value[0] = info->left_gain;
	ucontrol->value.integer.value[1] = info->right_gain;
	return 0;
}

2280 2281
static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
				 struct snd_ctl_elem_value *ucontrol)
2282
{
2283
	struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2284 2285
	struct dbri_streaminfo *info =
				&dbri->stream_info[kcontrol->private_value];
2286
	unsigned int vol[2];
2287 2288
	int changed = 0;

2289 2290 2291 2292 2293 2294 2295 2296 2297 2298
	vol[0] = ucontrol->value.integer.value[0];
	vol[1] = ucontrol->value.integer.value[1];
	if (kcontrol->private_value == DBRI_PLAY) {
		if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME)
			return -EINVAL;
	} else {
		if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN)
			return -EINVAL;
	}

2299 2300
	if (info->left_gain != vol[0]) {
		info->left_gain = vol[0];
2301 2302
		changed = 1;
	}
2303 2304
	if (info->right_gain != vol[1]) {
		info->right_gain = vol[1];
2305 2306
		changed = 1;
	}
2307
	if (changed) {
2308 2309 2310 2311 2312 2313 2314 2315 2316 2317
		/* First mute outputs, and wait 1/8000 sec (125 us)
		 * to make sure this takes.  This avoids clicking noises.
		 */
		cs4215_setdata(dbri, 1);
		udelay(125);
		cs4215_setdata(dbri, 0);
	}
	return changed;
}

2318 2319
static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
				  struct snd_ctl_elem_info *uinfo)
2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330
{
	int mask = (kcontrol->private_value >> 16) & 0xff;

	uinfo->type = (mask == 1) ?
	    SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
	uinfo->count = 1;
	uinfo->value.integer.min = 0;
	uinfo->value.integer.max = mask;
	return 0;
}

2331 2332
static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
				 struct snd_ctl_elem_value *ucontrol)
2333
{
2334
	struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2335 2336 2337 2338
	int elem = kcontrol->private_value & 0xff;
	int shift = (kcontrol->private_value >> 8) & 0xff;
	int mask = (kcontrol->private_value >> 16) & 0xff;
	int invert = (kcontrol->private_value >> 24) & 1;
2339 2340 2341

	if (snd_BUG_ON(!dbri))
		return -EINVAL;
2342

2343
	if (elem < 4)
2344 2345
		ucontrol->value.integer.value[0] =
		    (dbri->mm.data[elem] >> shift) & mask;
2346
	else
2347 2348 2349
		ucontrol->value.integer.value[0] =
		    (dbri->mm.ctrl[elem - 4] >> shift) & mask;

2350
	if (invert == 1)
2351 2352 2353 2354 2355
		ucontrol->value.integer.value[0] =
		    mask - ucontrol->value.integer.value[0];
	return 0;
}

2356 2357
static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
				 struct snd_ctl_elem_value *ucontrol)
2358
{
2359
	struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2360 2361 2362 2363 2364 2365
	int elem = kcontrol->private_value & 0xff;
	int shift = (kcontrol->private_value >> 8) & 0xff;
	int mask = (kcontrol->private_value >> 16) & 0xff;
	int invert = (kcontrol->private_value >> 24) & 1;
	int changed = 0;
	unsigned short val;
2366 2367 2368

	if (snd_BUG_ON(!dbri))
		return -EINVAL;
2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404

	val = (ucontrol->value.integer.value[0] & mask);
	if (invert == 1)
		val = mask - val;
	val <<= shift;

	if (elem < 4) {
		dbri->mm.data[elem] = (dbri->mm.data[elem] &
				       ~(mask << shift)) | val;
		changed = (val != dbri->mm.data[elem]);
	} else {
		dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
					   ~(mask << shift)) | val;
		changed = (val != dbri->mm.ctrl[elem - 4]);
	}

	dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
		"mixer-value=%ld, mm-value=0x%x\n",
		mask, changed, ucontrol->value.integer.value[0],
		dbri->mm.data[elem & 3]);

	if (changed) {
		/* First mute outputs, and wait 1/8000 sec (125 us)
		 * to make sure this takes.  This avoids clicking noises.
		 */
		cs4215_setdata(dbri, 1);
		udelay(125);
		cs4215_setdata(dbri, 0);
	}
	return changed;
}

/* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
   timeslots. Shift is the bit offset in the timeslot, mask defines the
   number of bits. invert is a boolean for use with attenuation.
 */
2405 2406 2407 2408 2409 2410
#define CS4215_SINGLE(xname, entry, shift, mask, invert)	\
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),		\
  .info = snd_cs4215_info_single,				\
  .get = snd_cs4215_get_single, .put = snd_cs4215_put_single,	\
  .private_value = (entry) | ((shift) << 8) | ((mask) << 16) |	\
			((invert) << 24) },
2411

2412
static struct snd_kcontrol_new dbri_controls[] = {
2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438
	{
	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
	 .name  = "Playback Volume",
	 .info  = snd_cs4215_info_volume,
	 .get   = snd_cs4215_get_volume,
	 .put   = snd_cs4215_put_volume,
	 .private_value = DBRI_PLAY,
	 },
	CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
	CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
	CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
	{
	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
	 .name  = "Capture Volume",
	 .info  = snd_cs4215_info_volume,
	 .get   = snd_cs4215_get_volume,
	 .put   = snd_cs4215_put_volume,
	 .private_value = DBRI_REC,
	 },
	/* FIXME: mic/line switch */
	CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
	CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
	CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
	CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
};

2439
static int snd_dbri_mixer(struct snd_card *card)
2440 2441
{
	int idx, err;
2442
	struct snd_dbri *dbri;
2443

2444 2445
	if (snd_BUG_ON(!card || !card->private_data))
		return -EINVAL;
2446
	dbri = card->private_data;
2447 2448 2449

	strcpy(card->mixername, card->shortname);

2450
	for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
2451 2452 2453
		err = snd_ctl_add(card,
				snd_ctl_new1(&dbri_controls[idx], dbri));
		if (err < 0)
2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467
			return err;
	}

	for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
		dbri->stream_info[idx].left_gain = 0;
		dbri->stream_info[idx].right_gain = 0;
	}

	return 0;
}

/****************************************************************************
			/proc interface
****************************************************************************/
2468 2469
static void dbri_regs_read(struct snd_info_entry *entry,
			   struct snd_info_buffer *buffer)
2470
{
2471
	struct snd_dbri *dbri = entry->private_data;
2472 2473 2474 2475 2476 2477 2478 2479

	snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
	snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
	snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
	snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
}

#ifdef DBRI_DEBUG
2480
static void dbri_debug_read(struct snd_info_entry *entry,
2481
			    struct snd_info_buffer *buffer)
2482
{
2483
	struct snd_dbri *dbri = entry->private_data;
2484 2485 2486 2487 2488 2489 2490 2491
	int pipe;
	snd_iprintf(buffer, "debug=%d\n", dbri_debug);

	for (pipe = 0; pipe < 32; pipe++) {
		if (pipe_active(dbri, pipe)) {
			struct dbri_pipe *pptr = &dbri->pipes[pipe];
			snd_iprintf(buffer,
				    "Pipe %d: %s SDP=0x%x desc=%d, "
2492
				    "len=%d next %d\n",
2493
				    pipe,
2494 2495
				   (pptr->sdp & D_SDP_TO_SER) ? "output" :
								 "input",
2496
				    pptr->sdp, pptr->desc,
2497
				    pptr->length, pptr->nextpipe);
2498 2499 2500 2501 2502
		}
	}
}
#endif

2503
static void snd_dbri_proc(struct snd_card *card)
2504
{
2505
	struct snd_dbri *dbri = card->private_data;
2506
	struct snd_info_entry *entry;
2507

2508
	if (!snd_card_proc_new(card, "regs", &entry))
2509
		snd_info_set_text_ops(entry, dbri, dbri_regs_read);
2510 2511

#ifdef DBRI_DEBUG
2512
	if (!snd_card_proc_new(card, "debug", &entry)) {
2513
		snd_info_set_text_ops(entry, dbri, dbri_debug_read);
2514 2515
		entry->mode = S_IFREG | S_IRUGO;	/* Readable only. */
	}
2516 2517 2518 2519 2520 2521 2522 2523
#endif
}

/*
****************************************************************************
**************************** Initialization ********************************
****************************************************************************
*/
2524
static void snd_dbri_free(struct snd_dbri *dbri);
2525

2526 2527 2528
static int snd_dbri_create(struct snd_card *card,
			   struct platform_device *op,
			   int irq, int dev)
2529
{
2530
	struct snd_dbri *dbri = card->private_data;
2531 2532 2533
	int err;

	spin_lock_init(&dbri->lock);
2534
	dbri->op = op;
2535
	dbri->irq = irq;
2536

2537 2538
	dbri->dma = dma_zalloc_coherent(&op->dev, sizeof(struct dbri_dma),
					&dbri->dma_dvma, GFP_ATOMIC);
2539 2540
	if (!dbri->dma)
		return -ENOMEM;
2541 2542 2543 2544 2545

	dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
		dbri->dma, dbri->dma_dvma);

	/* Map the registers into memory. */
2546 2547 2548
	dbri->regs_size = resource_size(&op->resource[0]);
	dbri->regs = of_ioremap(&op->resource[0], 0,
				dbri->regs_size, "DBRI Registers");
2549 2550
	if (!dbri->regs) {
		printk(KERN_ERR "DBRI: could not allocate registers\n");
2551
		dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2552
				  (void *)dbri->dma, dbri->dma_dvma);
2553 2554 2555
		return -EIO;
	}

2556
	err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2557 2558 2559
			  "DBRI audio", dbri);
	if (err) {
		printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2560 2561
		of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size);
		dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2562
				  (void *)dbri->dma, dbri->dma_dvma);
2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576
		return err;
	}

	/* Do low level initialization of the DBRI and CS4215 chips */
	dbri_initialize(dbri);
	err = cs4215_init(dbri);
	if (err) {
		snd_dbri_free(dbri);
		return err;
	}

	return 0;
}

2577
static void snd_dbri_free(struct snd_dbri *dbri)
2578 2579 2580 2581 2582 2583 2584 2585
{
	dprintk(D_GEN, "snd_dbri_free\n");
	dbri_reset(dbri);

	if (dbri->irq)
		free_irq(dbri->irq, dbri);

	if (dbri->regs)
2586
		of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size);
2587 2588

	if (dbri->dma)
2589
		dma_free_coherent(&dbri->op->dev,
2590 2591
				  sizeof(struct dbri_dma),
				  (void *)dbri->dma, dbri->dma_dvma);
2592 2593
}

2594
static int dbri_probe(struct platform_device *op)
2595
{
2596
	struct snd_dbri *dbri;
2597
	struct resource *rp;
2598
	struct snd_card *card;
2599
	static int dev = 0;
2600
	int irq;
2601 2602 2603 2604 2605 2606 2607 2608 2609
	int err;

	if (dev >= SNDRV_CARDS)
		return -ENODEV;
	if (!enable[dev]) {
		dev++;
		return -ENOENT;
	}

2610
	irq = op->archdata.irqs[0];
2611 2612
	if (irq <= 0) {
		printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev);
2613 2614
		return -ENODEV;
	}
2615

2616 2617
	err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE,
			   sizeof(struct snd_dbri), &card);
2618 2619
	if (err < 0)
		return err;
2620 2621 2622

	strcpy(card->driver, "DBRI");
	strcpy(card->shortname, "Sun DBRI");
2623
	rp = &op->resource[0];
2624
	sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2625
		card->shortname,
2626
		rp->flags & 0xffL, (unsigned long long)rp->start, irq);
2627

2628
	err = snd_dbri_create(card, op, irq, dev);
2629
	if (err < 0) {
2630 2631 2632 2633
		snd_card_free(card);
		return err;
	}

2634
	dbri = card->private_data;
2635
	err = snd_dbri_pcm(card);
2636
	if (err < 0)
2637
		goto _err;
2638

2639
	err = snd_dbri_mixer(card);
2640
	if (err < 0)
2641
		goto _err;
2642 2643

	/* /proc file handling */
2644
	snd_dbri_proc(card);
2645
	dev_set_drvdata(&op->dev, card);
2646

2647 2648
	err = snd_card_register(card);
	if (err < 0)
2649
		goto _err;
2650 2651 2652

	printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
	       dev, dbri->regs,
2653
	       dbri->irq, op->dev.of_node->name[9], dbri->mm.version);
2654 2655 2656
	dev++;

	return 0;
2657

2658
_err:
2659 2660 2661
	snd_dbri_free(dbri);
	snd_card_free(card);
	return err;
2662 2663
}

2664
static int dbri_remove(struct platform_device *op)
2665
{
2666
	struct snd_card *card = dev_get_drvdata(&op->dev);
2667

2668 2669
	snd_dbri_free(card->private_data);
	snd_card_free(card);
2670

2671
	return 0;
2672 2673
}

2674
static const struct of_device_id dbri_match[] = {
2675 2676 2677 2678 2679 2680 2681 2682
	{
		.name = "SUNW,DBRIe",
	},
	{
		.name = "SUNW,DBRIf",
	},
	{},
};
2683

2684
MODULE_DEVICE_TABLE(of, dbri_match);
2685

2686
static struct platform_driver dbri_sbus_driver = {
2687 2688 2689 2690
	.driver = {
		.name = "dbri",
		.of_match_table = dbri_match,
	},
2691
	.probe		= dbri_probe,
2692
	.remove		= dbri_remove,
2693 2694
};

2695
module_platform_driver(dbri_sbus_driver);
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