i915_gem.c 131.7 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#include <linux/slab.h>
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#include <linux/swap.h>
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#include <linux/pci.h>
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#include <linux/intel-gtt.h>
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static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
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static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
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static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
					     int write);
static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
						     uint64_t offset,
						     uint64_t size);
static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
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static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
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static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
					   unsigned alignment);
static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
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static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
				struct drm_i915_gem_pwrite *args,
				struct drm_file *file_priv);
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static void i915_gem_free_object_tail(struct drm_gem_object *obj);
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static LIST_HEAD(shrink_list);
static DEFINE_SPINLOCK(shrink_list_lock);

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static inline bool
i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
{
	return obj_priv->gtt_space &&
		!obj_priv->active &&
		obj_priv->pin_count == 0;
}

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int i915_gem_do_init(struct drm_device *dev, unsigned long start,
		     unsigned long end)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;

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	if (start >= end ||
	    (start & (PAGE_SIZE - 1)) != 0 ||
	    (end & (PAGE_SIZE - 1)) != 0) {
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		return -EINVAL;
	}

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	drm_mm_init(&dev_priv->mm.gtt_space, start,
		    end - start);
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	dev->gtt_total = (uint32_t) (end - start);

	return 0;
}
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int
i915_gem_init_ioctl(struct drm_device *dev, void *data,
		    struct drm_file *file_priv)
{
	struct drm_i915_gem_init *args = data;
	int ret;

	mutex_lock(&dev->struct_mutex);
	ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
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	mutex_unlock(&dev->struct_mutex);

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	return ret;
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}

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int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv)
{
	struct drm_i915_gem_get_aperture *args = data;

	if (!(dev->driver->driver_features & DRIVER_GEM))
		return -ENODEV;

	args->aper_size = dev->gtt_total;
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	args->aper_available_size = (args->aper_size -
				     atomic_read(&dev->pin_memory));
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	return 0;
}

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/**
 * Creates a new mm object and returns a handle to it.
 */
int
i915_gem_create_ioctl(struct drm_device *dev, void *data,
		      struct drm_file *file_priv)
{
	struct drm_i915_gem_create *args = data;
	struct drm_gem_object *obj;
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	int ret;
	u32 handle;
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	args->size = roundup(args->size, PAGE_SIZE);

	/* Allocate the new object */
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	obj = i915_gem_alloc_object(dev, args->size);
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	if (obj == NULL)
		return -ENOMEM;

	ret = drm_gem_handle_create(file_priv, obj, &handle);
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	if (ret) {
		drm_gem_object_unreference_unlocked(obj);
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		return ret;
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	}
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	/* Sink the floating reference from kref_init(handlecount) */
	drm_gem_object_handle_unreference_unlocked(obj);
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	args->handle = handle;
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	return 0;
}

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static inline int
fast_shmem_read(struct page **pages,
		loff_t page_base, int page_offset,
		char __user *data,
		int length)
{
	char __iomem *vaddr;
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	int unwritten;
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	vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
	if (vaddr == NULL)
		return -ENOMEM;
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	unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
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	kunmap_atomic(vaddr, KM_USER0);

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	if (unwritten)
		return -EFAULT;

	return 0;
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}

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static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
{
	drm_i915_private_t *dev_priv = obj->dev->dev_private;
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	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
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	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
		obj_priv->tiling_mode != I915_TILING_NONE;
}

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static inline void
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slow_shmem_copy(struct page *dst_page,
		int dst_offset,
		struct page *src_page,
		int src_offset,
		int length)
{
	char *dst_vaddr, *src_vaddr;

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	dst_vaddr = kmap(dst_page);
	src_vaddr = kmap(src_page);
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	memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);

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	kunmap(src_page);
	kunmap(dst_page);
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}

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static inline void
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slow_shmem_bit17_copy(struct page *gpu_page,
		      int gpu_offset,
		      struct page *cpu_page,
		      int cpu_offset,
		      int length,
		      int is_read)
{
	char *gpu_vaddr, *cpu_vaddr;

	/* Use the unswizzled path if this page isn't affected. */
	if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
		if (is_read)
			return slow_shmem_copy(cpu_page, cpu_offset,
					       gpu_page, gpu_offset, length);
		else
			return slow_shmem_copy(gpu_page, gpu_offset,
					       cpu_page, cpu_offset, length);
	}

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	gpu_vaddr = kmap(gpu_page);
	cpu_vaddr = kmap(cpu_page);
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	/* Copy the data, XORing A6 with A17 (1). The user already knows he's
	 * XORing with the other bits (A9 for Y, A9 and A10 for X)
	 */
	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;

		if (is_read) {
			memcpy(cpu_vaddr + cpu_offset,
			       gpu_vaddr + swizzled_gpu_offset,
			       this_length);
		} else {
			memcpy(gpu_vaddr + swizzled_gpu_offset,
			       cpu_vaddr + cpu_offset,
			       this_length);
		}
		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}

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	kunmap(cpu_page);
	kunmap(gpu_page);
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}

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/**
 * This is the fast shmem pread path, which attempts to copy_from_user directly
 * from the backing pages of the object to the user's address space.  On a
 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 */
static int
i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
			  struct drm_i915_gem_pread *args,
			  struct drm_file *file_priv)
{
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	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
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	ssize_t remain;
	loff_t offset, page_base;
	char __user *user_data;
	int page_offset, page_length;
	int ret;

	user_data = (char __user *) (uintptr_t) args->data_ptr;
	remain = args->size;

	mutex_lock(&dev->struct_mutex);

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	ret = i915_gem_object_get_pages(obj, 0);
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	if (ret != 0)
		goto fail_unlock;

	ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
							args->size);
	if (ret != 0)
		goto fail_put_pages;

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	obj_priv = to_intel_bo(obj);
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	offset = args->offset;

	while (remain > 0) {
		/* Operation in this page
		 *
		 * page_base = page offset within aperture
		 * page_offset = offset within page
		 * page_length = bytes to copy for this page
		 */
		page_base = (offset & ~(PAGE_SIZE-1));
		page_offset = offset & (PAGE_SIZE-1);
		page_length = remain;
		if ((page_offset + remain) > PAGE_SIZE)
			page_length = PAGE_SIZE - page_offset;

		ret = fast_shmem_read(obj_priv->pages,
				      page_base, page_offset,
				      user_data, page_length);
		if (ret)
			goto fail_put_pages;

		remain -= page_length;
		user_data += page_length;
		offset += page_length;
	}

fail_put_pages:
	i915_gem_object_put_pages(obj);
fail_unlock:
	mutex_unlock(&dev->struct_mutex);

	return ret;
}

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static int
i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
{
	int ret;

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	ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
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	/* If we've insufficient memory to map in the pages, attempt
	 * to make some space by throwing out some old buffers.
	 */
	if (ret == -ENOMEM) {
		struct drm_device *dev = obj->dev;

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		ret = i915_gem_evict_something(dev, obj->size,
					       i915_gem_get_gtt_alignment(obj));
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		if (ret)
			return ret;

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		ret = i915_gem_object_get_pages(obj, 0);
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	}

	return ret;
}

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/**
 * This is the fallback shmem pread path, which allocates temporary storage
 * in kernel space to copy_to_user into outside of the struct_mutex, so we
 * can copy out of the object's backing pages while holding the struct mutex
 * and not take page faults.
 */
static int
i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
			  struct drm_i915_gem_pread *args,
			  struct drm_file *file_priv)
{
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	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
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	struct mm_struct *mm = current->mm;
	struct page **user_pages;
	ssize_t remain;
	loff_t offset, pinned_pages, i;
	loff_t first_data_page, last_data_page, num_pages;
	int shmem_page_index, shmem_page_offset;
	int data_page_index,  data_page_offset;
	int page_length;
	int ret;
	uint64_t data_ptr = args->data_ptr;
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	int do_bit17_swizzling;
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	remain = args->size;

	/* Pin the user pages containing the data.  We can't fault while
	 * holding the struct mutex, yet we want to hold it while
	 * dereferencing the user data.
	 */
	first_data_page = data_ptr / PAGE_SIZE;
	last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
	num_pages = last_data_page - first_data_page + 1;

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	user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
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	if (user_pages == NULL)
		return -ENOMEM;

	down_read(&mm->mmap_sem);
	pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
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				      num_pages, 1, 0, user_pages, NULL);
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	up_read(&mm->mmap_sem);
	if (pinned_pages < num_pages) {
		ret = -EFAULT;
		goto fail_put_user_pages;
	}

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	do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);

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	mutex_lock(&dev->struct_mutex);

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	ret = i915_gem_object_get_pages_or_evict(obj);
	if (ret)
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		goto fail_unlock;

	ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
							args->size);
	if (ret != 0)
		goto fail_put_pages;

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	obj_priv = to_intel_bo(obj);
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	offset = args->offset;

	while (remain > 0) {
		/* Operation in this page
		 *
		 * shmem_page_index = page number within shmem file
		 * shmem_page_offset = offset within page in shmem file
		 * data_page_index = page number in get_user_pages return
		 * data_page_offset = offset with data_page_index page.
		 * page_length = bytes to copy for this page
		 */
		shmem_page_index = offset / PAGE_SIZE;
		shmem_page_offset = offset & ~PAGE_MASK;
		data_page_index = data_ptr / PAGE_SIZE - first_data_page;
		data_page_offset = data_ptr & ~PAGE_MASK;

		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;
		if ((data_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - data_page_offset;

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		if (do_bit17_swizzling) {
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			slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
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					      shmem_page_offset,
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					      user_pages[data_page_index],
					      data_page_offset,
					      page_length,
					      1);
		} else {
			slow_shmem_copy(user_pages[data_page_index],
					data_page_offset,
					obj_priv->pages[shmem_page_index],
					shmem_page_offset,
					page_length);
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		}
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		remain -= page_length;
		data_ptr += page_length;
		offset += page_length;
	}

fail_put_pages:
	i915_gem_object_put_pages(obj);
fail_unlock:
	mutex_unlock(&dev->struct_mutex);
fail_put_user_pages:
	for (i = 0; i < pinned_pages; i++) {
		SetPageDirty(user_pages[i]);
		page_cache_release(user_pages[i]);
	}
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	drm_free_large(user_pages);
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	return ret;
}

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/**
 * Reads data from the object referenced by handle.
 *
 * On error, the contents of *data are undefined.
 */
int
i915_gem_pread_ioctl(struct drm_device *dev, void *data,
		     struct drm_file *file_priv)
{
	struct drm_i915_gem_pread *args = data;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;
	int ret;

	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	if (obj == NULL)
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		return -ENOENT;
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	obj_priv = to_intel_bo(obj);
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	/* Bounds check source.
	 *
	 * XXX: This could use review for overflow issues...
	 */
	if (args->offset > obj->size || args->size > obj->size ||
	    args->offset + args->size > obj->size) {
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		drm_gem_object_unreference_unlocked(obj);
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		return -EINVAL;
	}

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	if (i915_gem_object_needs_bit17_swizzle(obj)) {
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		ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
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	} else {
		ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
		if (ret != 0)
			ret = i915_gem_shmem_pread_slow(dev, obj, args,
							file_priv);
	}
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	drm_gem_object_unreference_unlocked(obj);
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	return ret;
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}

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/* This is the fast write path which cannot handle
 * page faults in the source data
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 */
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static inline int
fast_user_write(struct io_mapping *mapping,
		loff_t page_base, int page_offset,
		char __user *user_data,
		int length)
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{
	char *vaddr_atomic;
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	unsigned long unwritten;
510

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	vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
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	unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
						      user_data, length);
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	io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
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	if (unwritten)
		return -EFAULT;
	return 0;
}

/* Here's the write path which can sleep for
 * page faults
 */

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static inline void
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slow_kernel_write(struct io_mapping *mapping,
		  loff_t gtt_base, int gtt_offset,
		  struct page *user_page, int user_offset,
		  int length)
529
{
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	char __iomem *dst_vaddr;
	char *src_vaddr;
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	dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
	src_vaddr = kmap(user_page);

	memcpy_toio(dst_vaddr + gtt_offset,
		    src_vaddr + user_offset,
		    length);

	kunmap(user_page);
	io_mapping_unmap(dst_vaddr);
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}

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static inline int
fast_shmem_write(struct page **pages,
		 loff_t page_base, int page_offset,
		 char __user *data,
		 int length)
{
	char __iomem *vaddr;
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	unsigned long unwritten;
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	vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
	if (vaddr == NULL)
		return -ENOMEM;
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	unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
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	kunmap_atomic(vaddr, KM_USER0);

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	if (unwritten)
		return -EFAULT;
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	return 0;
}

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/**
 * This is the fast pwrite path, where we copy the data directly from the
 * user into the GTT, uncached.
 */
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static int
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i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
			 struct drm_i915_gem_pwrite *args,
			 struct drm_file *file_priv)
572
{
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	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
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	drm_i915_private_t *dev_priv = dev->dev_private;
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	ssize_t remain;
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	loff_t offset, page_base;
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	char __user *user_data;
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	int page_offset, page_length;
	int ret;
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	user_data = (char __user *) (uintptr_t) args->data_ptr;
	remain = args->size;
	if (!access_ok(VERIFY_READ, user_data, remain))
		return -EFAULT;


	mutex_lock(&dev->struct_mutex);
	ret = i915_gem_object_pin(obj, 0);
	if (ret) {
		mutex_unlock(&dev->struct_mutex);
		return ret;
	}
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	ret = i915_gem_object_set_to_gtt_domain(obj, 1);
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	if (ret)
		goto fail;

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	obj_priv = to_intel_bo(obj);
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	offset = obj_priv->gtt_offset + args->offset;

	while (remain > 0) {
		/* Operation in this page
		 *
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		 * page_base = page offset within aperture
		 * page_offset = offset within page
		 * page_length = bytes to copy for this page
606
		 */
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		page_base = (offset & ~(PAGE_SIZE-1));
		page_offset = offset & (PAGE_SIZE-1);
		page_length = remain;
		if ((page_offset + remain) > PAGE_SIZE)
			page_length = PAGE_SIZE - page_offset;

		ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
				       page_offset, user_data, page_length);

		/* If we get a fault while copying data, then (presumably) our
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		 * source page isn't available.  Return the error and we'll
		 * retry in the slow path.
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		 */
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		if (ret)
			goto fail;
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		remain -= page_length;
		user_data += page_length;
		offset += page_length;
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	}

fail:
	i915_gem_object_unpin(obj);
	mutex_unlock(&dev->struct_mutex);

	return ret;
}

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/**
 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 * the memory and maps it using kmap_atomic for copying.
 *
 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 */
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static int
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i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
			 struct drm_i915_gem_pwrite *args,
			 struct drm_file *file_priv)
646
{
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	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
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	drm_i915_private_t *dev_priv = dev->dev_private;
	ssize_t remain;
	loff_t gtt_page_base, offset;
	loff_t first_data_page, last_data_page, num_pages;
	loff_t pinned_pages, i;
	struct page **user_pages;
	struct mm_struct *mm = current->mm;
	int gtt_page_offset, data_page_offset, data_page_index, page_length;
656
	int ret;
657 658 659 660 661 662 663 664 665 666 667 668
	uint64_t data_ptr = args->data_ptr;

	remain = args->size;

	/* Pin the user pages containing the data.  We can't fault while
	 * holding the struct mutex, and all of the pwrite implementations
	 * want to hold it while dereferencing the user data.
	 */
	first_data_page = data_ptr / PAGE_SIZE;
	last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
	num_pages = last_data_page - first_data_page + 1;

669
	user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
670 671 672 673 674 675 676 677 678 679 680
	if (user_pages == NULL)
		return -ENOMEM;

	down_read(&mm->mmap_sem);
	pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
				      num_pages, 0, 0, user_pages, NULL);
	up_read(&mm->mmap_sem);
	if (pinned_pages < num_pages) {
		ret = -EFAULT;
		goto out_unpin_pages;
	}
681 682

	mutex_lock(&dev->struct_mutex);
683 684 685 686 687 688 689 690
	ret = i915_gem_object_pin(obj, 0);
	if (ret)
		goto out_unlock;

	ret = i915_gem_object_set_to_gtt_domain(obj, 1);
	if (ret)
		goto out_unpin_object;

691
	obj_priv = to_intel_bo(obj);
692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713
	offset = obj_priv->gtt_offset + args->offset;

	while (remain > 0) {
		/* Operation in this page
		 *
		 * gtt_page_base = page offset within aperture
		 * gtt_page_offset = offset within page in aperture
		 * data_page_index = page number in get_user_pages return
		 * data_page_offset = offset with data_page_index page.
		 * page_length = bytes to copy for this page
		 */
		gtt_page_base = offset & PAGE_MASK;
		gtt_page_offset = offset & ~PAGE_MASK;
		data_page_index = data_ptr / PAGE_SIZE - first_data_page;
		data_page_offset = data_ptr & ~PAGE_MASK;

		page_length = remain;
		if ((gtt_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - gtt_page_offset;
		if ((data_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - data_page_offset;

714 715 716 717 718
		slow_kernel_write(dev_priv->mm.gtt_mapping,
				  gtt_page_base, gtt_page_offset,
				  user_pages[data_page_index],
				  data_page_offset,
				  page_length);
719 720 721 722 723 724 725 726 727 728 729 730 731

		remain -= page_length;
		offset += page_length;
		data_ptr += page_length;
	}

out_unpin_object:
	i915_gem_object_unpin(obj);
out_unlock:
	mutex_unlock(&dev->struct_mutex);
out_unpin_pages:
	for (i = 0; i < pinned_pages; i++)
		page_cache_release(user_pages[i]);
732
	drm_free_large(user_pages);
733 734 735 736

	return ret;
}

737 738 739 740
/**
 * This is the fast shmem pwrite path, which attempts to directly
 * copy_from_user into the kmapped pages backing the object.
 */
741
static int
742 743 744
i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
			   struct drm_i915_gem_pwrite *args,
			   struct drm_file *file_priv)
745
{
746
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
747 748 749 750
	ssize_t remain;
	loff_t offset, page_base;
	char __user *user_data;
	int page_offset, page_length;
751
	int ret;
752 753 754

	user_data = (char __user *) (uintptr_t) args->data_ptr;
	remain = args->size;
755 756 757

	mutex_lock(&dev->struct_mutex);

758
	ret = i915_gem_object_get_pages(obj, 0);
759 760
	if (ret != 0)
		goto fail_unlock;
761

762
	ret = i915_gem_object_set_to_cpu_domain(obj, 1);
763 764 765
	if (ret != 0)
		goto fail_put_pages;

766
	obj_priv = to_intel_bo(obj);
767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813
	offset = args->offset;
	obj_priv->dirty = 1;

	while (remain > 0) {
		/* Operation in this page
		 *
		 * page_base = page offset within aperture
		 * page_offset = offset within page
		 * page_length = bytes to copy for this page
		 */
		page_base = (offset & ~(PAGE_SIZE-1));
		page_offset = offset & (PAGE_SIZE-1);
		page_length = remain;
		if ((page_offset + remain) > PAGE_SIZE)
			page_length = PAGE_SIZE - page_offset;

		ret = fast_shmem_write(obj_priv->pages,
				       page_base, page_offset,
				       user_data, page_length);
		if (ret)
			goto fail_put_pages;

		remain -= page_length;
		user_data += page_length;
		offset += page_length;
	}

fail_put_pages:
	i915_gem_object_put_pages(obj);
fail_unlock:
	mutex_unlock(&dev->struct_mutex);

	return ret;
}

/**
 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 * the memory and maps it using kmap_atomic for copying.
 *
 * This avoids taking mmap_sem for faulting on the user's address while the
 * struct_mutex is held.
 */
static int
i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
			   struct drm_i915_gem_pwrite *args,
			   struct drm_file *file_priv)
{
814
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
815 816 817 818 819 820 821 822 823 824
	struct mm_struct *mm = current->mm;
	struct page **user_pages;
	ssize_t remain;
	loff_t offset, pinned_pages, i;
	loff_t first_data_page, last_data_page, num_pages;
	int shmem_page_index, shmem_page_offset;
	int data_page_index,  data_page_offset;
	int page_length;
	int ret;
	uint64_t data_ptr = args->data_ptr;
825
	int do_bit17_swizzling;
826 827 828 829 830 831 832 833 834 835 836

	remain = args->size;

	/* Pin the user pages containing the data.  We can't fault while
	 * holding the struct mutex, and all of the pwrite implementations
	 * want to hold it while dereferencing the user data.
	 */
	first_data_page = data_ptr / PAGE_SIZE;
	last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
	num_pages = last_data_page - first_data_page + 1;

837
	user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
838 839 840 841 842 843 844 845 846 847
	if (user_pages == NULL)
		return -ENOMEM;

	down_read(&mm->mmap_sem);
	pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
				      num_pages, 0, 0, user_pages, NULL);
	up_read(&mm->mmap_sem);
	if (pinned_pages < num_pages) {
		ret = -EFAULT;
		goto fail_put_user_pages;
848 849
	}

850 851
	do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);

852 853
	mutex_lock(&dev->struct_mutex);

854 855
	ret = i915_gem_object_get_pages_or_evict(obj);
	if (ret)
856 857 858 859 860 861
		goto fail_unlock;

	ret = i915_gem_object_set_to_cpu_domain(obj, 1);
	if (ret != 0)
		goto fail_put_pages;

862
	obj_priv = to_intel_bo(obj);
863
	offset = args->offset;
864
	obj_priv->dirty = 1;
865

866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885
	while (remain > 0) {
		/* Operation in this page
		 *
		 * shmem_page_index = page number within shmem file
		 * shmem_page_offset = offset within page in shmem file
		 * data_page_index = page number in get_user_pages return
		 * data_page_offset = offset with data_page_index page.
		 * page_length = bytes to copy for this page
		 */
		shmem_page_index = offset / PAGE_SIZE;
		shmem_page_offset = offset & ~PAGE_MASK;
		data_page_index = data_ptr / PAGE_SIZE - first_data_page;
		data_page_offset = data_ptr & ~PAGE_MASK;

		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;
		if ((data_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - data_page_offset;

886
		if (do_bit17_swizzling) {
887
			slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
888 889 890
					      shmem_page_offset,
					      user_pages[data_page_index],
					      data_page_offset,
891 892 893 894 895 896 897 898
					      page_length,
					      0);
		} else {
			slow_shmem_copy(obj_priv->pages[shmem_page_index],
					shmem_page_offset,
					user_pages[data_page_index],
					data_page_offset,
					page_length);
899
		}
900 901 902 903

		remain -= page_length;
		data_ptr += page_length;
		offset += page_length;
904 905
	}

906 907 908
fail_put_pages:
	i915_gem_object_put_pages(obj);
fail_unlock:
909
	mutex_unlock(&dev->struct_mutex);
910 911 912
fail_put_user_pages:
	for (i = 0; i < pinned_pages; i++)
		page_cache_release(user_pages[i]);
913
	drm_free_large(user_pages);
914

915
	return ret;
916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933
}

/**
 * Writes data to the object referenced by handle.
 *
 * On error, the contents of the buffer that were to be modified are undefined.
 */
int
i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
		      struct drm_file *file_priv)
{
	struct drm_i915_gem_pwrite *args = data;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;
	int ret = 0;

	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	if (obj == NULL)
934
		return -ENOENT;
935
	obj_priv = to_intel_bo(obj);
936 937 938 939 940 941 942

	/* Bounds check destination.
	 *
	 * XXX: This could use review for overflow issues...
	 */
	if (args->offset > obj->size || args->size > obj->size ||
	    args->offset + args->size > obj->size) {
943
		drm_gem_object_unreference_unlocked(obj);
944 945 946 947 948 949 950 951 952
		return -EINVAL;
	}

	/* We can only do the GTT pwrite on untiled buffers, as otherwise
	 * it would end up going through the fenced access, and we'll get
	 * different detiling behavior between reading and writing.
	 * pread/pwrite currently are reading and writing from the CPU
	 * perspective, requiring manual detiling by the client.
	 */
953 954 955
	if (obj_priv->phys_obj)
		ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
	else if (obj_priv->tiling_mode == I915_TILING_NONE &&
956 957
		 dev->gtt_total != 0 &&
		 obj->write_domain != I915_GEM_DOMAIN_CPU) {
958 959 960 961 962
		ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
		if (ret == -EFAULT) {
			ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
						       file_priv);
		}
963 964
	} else if (i915_gem_object_needs_bit17_swizzle(obj)) {
		ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
965 966 967 968 969 970 971
	} else {
		ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
		if (ret == -EFAULT) {
			ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
							 file_priv);
		}
	}
972 973 974 975 976 977

#if WATCH_PWRITE
	if (ret)
		DRM_INFO("pwrite failed %d\n", ret);
#endif

978
	drm_gem_object_unreference_unlocked(obj);
979 980 981 982 983

	return ret;
}

/**
984 985
 * Called when user space prepares to use an object with the CPU, either
 * through the mmap ioctl's mapping or a GTT mapping.
986 987 988 989 990
 */
int
i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv)
{
991
	struct drm_i915_private *dev_priv = dev->dev_private;
992 993
	struct drm_i915_gem_set_domain *args = data;
	struct drm_gem_object *obj;
994
	struct drm_i915_gem_object *obj_priv;
995 996
	uint32_t read_domains = args->read_domains;
	uint32_t write_domain = args->write_domain;
997 998 999 1000 1001
	int ret;

	if (!(dev->driver->driver_features & DRIVER_GEM))
		return -ENODEV;

1002
	/* Only handle setting domains to types used by the CPU. */
1003
	if (write_domain & I915_GEM_GPU_DOMAINS)
1004 1005
		return -EINVAL;

1006
	if (read_domains & I915_GEM_GPU_DOMAINS)
1007 1008 1009 1010 1011 1012 1013 1014
		return -EINVAL;

	/* Having something in the write domain implies it's in the read
	 * domain, and only that read domain.  Enforce that in the request.
	 */
	if (write_domain != 0 && read_domains != write_domain)
		return -EINVAL;

1015 1016
	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	if (obj == NULL)
1017
		return -ENOENT;
1018
	obj_priv = to_intel_bo(obj);
1019 1020

	mutex_lock(&dev->struct_mutex);
1021 1022 1023

	intel_mark_busy(dev, obj);

1024
#if WATCH_BUF
1025
	DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1026
		 obj, obj->size, read_domains, write_domain);
1027
#endif
1028 1029
	if (read_domains & I915_GEM_DOMAIN_GTT) {
		ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1030

1031 1032 1033 1034
		/* Update the LRU on the fence for the CPU access that's
		 * about to occur.
		 */
		if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1035 1036 1037
			struct drm_i915_fence_reg *reg =
				&dev_priv->fence_regs[obj_priv->fence_reg];
			list_move_tail(&reg->lru_list,
1038 1039 1040
				       &dev_priv->mm.fence_list);
		}

1041 1042 1043 1044 1045 1046
		/* Silently promote "you're not bound, there was nothing to do"
		 * to success, since the client was just asking us to
		 * make sure everything was done.
		 */
		if (ret == -EINVAL)
			ret = 0;
1047
	} else {
1048
		ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1049 1050
	}

1051 1052 1053 1054 1055
	
	/* Maintain LRU order of "inactive" objects */
	if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
		list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);

1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079
	drm_gem_object_unreference(obj);
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

/**
 * Called when user space has done writes to this buffer
 */
int
i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
		      struct drm_file *file_priv)
{
	struct drm_i915_gem_sw_finish *args = data;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;
	int ret = 0;

	if (!(dev->driver->driver_features & DRIVER_GEM))
		return -ENODEV;

	mutex_lock(&dev->struct_mutex);
	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	if (obj == NULL) {
		mutex_unlock(&dev->struct_mutex);
1080
		return -ENOENT;
1081 1082 1083
	}

#if WATCH_BUF
1084
	DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1085 1086
		 __func__, args->handle, obj, obj->size);
#endif
1087
	obj_priv = to_intel_bo(obj);
1088 1089

	/* Pinned buffers may be scanout, so flush the cache */
1090 1091 1092
	if (obj_priv->pin_count)
		i915_gem_object_flush_cpu_write_domain(obj);

1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118
	drm_gem_object_unreference(obj);
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

/**
 * Maps the contents of an object, returning the address it is mapped
 * into.
 *
 * While the mapping holds a reference on the contents of the object, it doesn't
 * imply a ref on the object itself.
 */
int
i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
		   struct drm_file *file_priv)
{
	struct drm_i915_gem_mmap *args = data;
	struct drm_gem_object *obj;
	loff_t offset;
	unsigned long addr;

	if (!(dev->driver->driver_features & DRIVER_GEM))
		return -ENODEV;

	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	if (obj == NULL)
1119
		return -ENOENT;
1120 1121 1122 1123 1124 1125 1126 1127

	offset = args->offset;

	down_write(&current->mm->mmap_sem);
	addr = do_mmap(obj->filp, 0, args->size,
		       PROT_READ | PROT_WRITE, MAP_SHARED,
		       args->offset);
	up_write(&current->mm->mmap_sem);
1128
	drm_gem_object_unreference_unlocked(obj);
1129 1130 1131 1132 1133 1134 1135 1136
	if (IS_ERR((void *)addr))
		return addr;

	args->addr_ptr = (uint64_t) addr;

	return 0;
}

1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156
/**
 * i915_gem_fault - fault a page into the GTT
 * vma: VMA in question
 * vmf: fault info
 *
 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
 * from userspace.  The fault handler takes care of binding the object to
 * the GTT (if needed), allocating and programming a fence register (again,
 * only if needed based on whether the old reg is still valid or the object
 * is tiled) and inserting a new PTE into the faulting process.
 *
 * Note that the faulting process may involve evicting existing objects
 * from the GTT and/or fence registers to make room.  So performance may
 * suffer if the GTT working set is large or there are few fence registers
 * left.
 */
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
{
	struct drm_gem_object *obj = vma->vm_private_data;
	struct drm_device *dev = obj->dev;
1157
	drm_i915_private_t *dev_priv = dev->dev_private;
1158
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1159 1160 1161
	pgoff_t page_offset;
	unsigned long pfn;
	int ret = 0;
1162
	bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1163 1164 1165 1166 1167 1168 1169 1170

	/* We don't use vmf->pgoff since that has the fake offset */
	page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
		PAGE_SHIFT;

	/* Now bind it into the GTT if needed */
	mutex_lock(&dev->struct_mutex);
	if (!obj_priv->gtt_space) {
1171
		ret = i915_gem_object_bind_to_gtt(obj, 0);
1172 1173
		if (ret)
			goto unlock;
1174 1175

		ret = i915_gem_object_set_to_gtt_domain(obj, write);
1176 1177
		if (ret)
			goto unlock;
1178 1179 1180
	}

	/* Need a new fence register? */
1181
	if (obj_priv->tiling_mode != I915_TILING_NONE) {
1182
		ret = i915_gem_object_get_fence_reg(obj);
1183 1184
		if (ret)
			goto unlock;
1185
	}
1186

1187 1188 1189
	if (i915_gem_object_is_inactive(obj_priv))
		list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);

1190 1191 1192 1193 1194
	pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
		page_offset;

	/* Finally, remap it using the new GTT offset */
	ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1195
unlock:
1196 1197 1198
	mutex_unlock(&dev->struct_mutex);

	switch (ret) {
1199 1200 1201
	case 0:
	case -ERESTARTSYS:
		return VM_FAULT_NOPAGE;
1202 1203 1204 1205
	case -ENOMEM:
	case -EAGAIN:
		return VM_FAULT_OOM;
	default:
1206
		return VM_FAULT_SIGBUS;
1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225
	}
}

/**
 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
 * @obj: obj in question
 *
 * GEM memory mapping works by handing back to userspace a fake mmap offset
 * it can use in a subsequent mmap(2) call.  The DRM core code then looks
 * up the object based on the offset and sets up the various memory mapping
 * structures.
 *
 * This routine allocates and attaches a fake offset for @obj.
 */
static int
i915_gem_create_mmap_offset(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
	struct drm_gem_mm *mm = dev->mm_private;
1226
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1227
	struct drm_map_list *list;
1228
	struct drm_local_map *map;
1229 1230 1231 1232
	int ret = 0;

	/* Set the object up for mmap'ing */
	list = &obj->map_list;
1233
	list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260
	if (!list->map)
		return -ENOMEM;

	map = list->map;
	map->type = _DRM_GEM;
	map->size = obj->size;
	map->handle = obj;

	/* Get a DRM GEM mmap offset allocated... */
	list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
						    obj->size / PAGE_SIZE, 0, 0);
	if (!list->file_offset_node) {
		DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
		ret = -ENOMEM;
		goto out_free_list;
	}

	list->file_offset_node = drm_mm_get_block(list->file_offset_node,
						  obj->size / PAGE_SIZE, 0);
	if (!list->file_offset_node) {
		ret = -ENOMEM;
		goto out_free_list;
	}

	list->hash.key = list->file_offset_node->start;
	if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
		DRM_ERROR("failed to add to map hash\n");
1261
		ret = -ENOMEM;
1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273
		goto out_free_mm;
	}

	/* By now we should be all set, any drm_mmap request on the offset
	 * below will get to our mmap & fault handler */
	obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;

	return 0;

out_free_mm:
	drm_mm_put_block(list->file_offset_node);
out_free_list:
1274
	kfree(list->map);
1275 1276 1277 1278

	return ret;
}

1279 1280 1281 1282
/**
 * i915_gem_release_mmap - remove physical page mappings
 * @obj: obj in question
 *
1283
 * Preserve the reservation of the mmapping with the DRM core code, but
1284 1285 1286 1287 1288 1289 1290 1291 1292
 * relinquish ownership of the pages back to the system.
 *
 * It is vital that we remove the page mapping if we have mapped a tiled
 * object through the GTT and then lose the fence register due to
 * resource pressure. Similarly if the object has been moved out of the
 * aperture, than pages mapped into userspace must be revoked. Removing the
 * mapping will then trigger a page fault on the next user access, allowing
 * fixup by i915_gem_fault().
 */
1293
void
1294 1295 1296
i915_gem_release_mmap(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
1297
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1298 1299 1300 1301 1302 1303

	if (dev->dev_mapping)
		unmap_mapping_range(dev->dev_mapping,
				    obj_priv->mmap_offset, obj->size, 1);
}

1304 1305 1306 1307
static void
i915_gem_free_mmap_offset(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
1308
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320
	struct drm_gem_mm *mm = dev->mm_private;
	struct drm_map_list *list;

	list = &obj->map_list;
	drm_ht_remove_item(&mm->offset_hash, &list->hash);

	if (list->file_offset_node) {
		drm_mm_put_block(list->file_offset_node);
		list->file_offset_node = NULL;
	}

	if (list->map) {
1321
		kfree(list->map);
1322 1323 1324 1325 1326 1327
		list->map = NULL;
	}

	obj_priv->mmap_offset = 0;
}

1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338
/**
 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
 * @obj: object to check
 *
 * Return the required GTT alignment for an object, taking into account
 * potential fence register mapping if needed.
 */
static uint32_t
i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
1339
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392
	int start, i;

	/*
	 * Minimum alignment is 4k (GTT page size), but might be greater
	 * if a fence register is needed for the object.
	 */
	if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
		return 4096;

	/*
	 * Previous chips need to be aligned to the size of the smallest
	 * fence register that can contain the object.
	 */
	if (IS_I9XX(dev))
		start = 1024*1024;
	else
		start = 512*1024;

	for (i = start; i < obj->size; i <<= 1)
		;

	return i;
}

/**
 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
 * @dev: DRM device
 * @data: GTT mapping ioctl data
 * @file_priv: GEM object info
 *
 * Simply returns the fake offset to userspace so it can mmap it.
 * The mmap call will end up in drm_gem_mmap(), which will set things
 * up so we can get faults in the handler above.
 *
 * The fault handler will take care of binding the object into the GTT
 * (since it may have been evicted to make room for something), allocating
 * a fence register, and mapping the appropriate aperture address into
 * userspace.
 */
int
i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
	struct drm_i915_gem_mmap_gtt *args = data;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;
	int ret;

	if (!(dev->driver->driver_features & DRIVER_GEM))
		return -ENODEV;

	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	if (obj == NULL)
1393
		return -ENOENT;
1394 1395 1396

	mutex_lock(&dev->struct_mutex);

1397
	obj_priv = to_intel_bo(obj);
1398

1399 1400 1401 1402 1403 1404 1405 1406
	if (obj_priv->madv != I915_MADV_WILLNEED) {
		DRM_ERROR("Attempting to mmap a purgeable buffer\n");
		drm_gem_object_unreference(obj);
		mutex_unlock(&dev->struct_mutex);
		return -EINVAL;
	}


1407 1408
	if (!obj_priv->mmap_offset) {
		ret = i915_gem_create_mmap_offset(obj);
1409 1410 1411
		if (ret) {
			drm_gem_object_unreference(obj);
			mutex_unlock(&dev->struct_mutex);
1412
			return ret;
1413
		}
1414 1415 1416 1417 1418 1419 1420 1421 1422
	}

	args->offset = obj_priv->mmap_offset;

	/*
	 * Pull it into the GTT so that we have a page list (makes the
	 * initial fault faster and any subsequent flushing possible).
	 */
	if (!obj_priv->agp_mem) {
1423
		ret = i915_gem_object_bind_to_gtt(obj, 0);
1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436
		if (ret) {
			drm_gem_object_unreference(obj);
			mutex_unlock(&dev->struct_mutex);
			return ret;
		}
	}

	drm_gem_object_unreference(obj);
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

1437
void
1438
i915_gem_object_put_pages(struct drm_gem_object *obj)
1439
{
1440
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1441 1442 1443
	int page_count = obj->size / PAGE_SIZE;
	int i;

1444
	BUG_ON(obj_priv->pages_refcount == 0);
C
Chris Wilson 已提交
1445
	BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1446

1447 1448
	if (--obj_priv->pages_refcount != 0)
		return;
1449

1450 1451 1452
	if (obj_priv->tiling_mode != I915_TILING_NONE)
		i915_gem_object_save_bit_17_swizzle(obj);

1453
	if (obj_priv->madv == I915_MADV_DONTNEED)
1454
		obj_priv->dirty = 0;
1455 1456 1457 1458 1459 1460

	for (i = 0; i < page_count; i++) {
		if (obj_priv->dirty)
			set_page_dirty(obj_priv->pages[i]);

		if (obj_priv->madv == I915_MADV_WILLNEED)
1461
			mark_page_accessed(obj_priv->pages[i]);
1462 1463 1464

		page_cache_release(obj_priv->pages[i]);
	}
1465 1466
	obj_priv->dirty = 0;

1467
	drm_free_large(obj_priv->pages);
1468
	obj_priv->pages = NULL;
1469 1470 1471
}

static void
1472 1473
i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
			       struct intel_ring_buffer *ring)
1474 1475 1476
{
	struct drm_device *dev = obj->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
1477
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1478 1479
	BUG_ON(ring == NULL);
	obj_priv->ring = ring;
1480 1481 1482 1483 1484 1485 1486

	/* Add a reference if we're newly entering the active list. */
	if (!obj_priv->active) {
		drm_gem_object_reference(obj);
		obj_priv->active = 1;
	}
	/* Move from whatever list we were on to the tail of execution. */
1487
	spin_lock(&dev_priv->mm.active_list_lock);
1488
	list_move_tail(&obj_priv->list, &ring->active_list);
1489
	spin_unlock(&dev_priv->mm.active_list_lock);
1490
	obj_priv->last_rendering_seqno = seqno;
1491 1492
}

1493 1494 1495 1496 1497
static void
i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
1498
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1499 1500 1501 1502 1503

	BUG_ON(!obj_priv->active);
	list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
	obj_priv->last_rendering_seqno = 0;
}
1504

1505 1506 1507 1508
/* Immediately discard the backing storage */
static void
i915_gem_object_truncate(struct drm_gem_object *obj)
{
1509
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
C
Chris Wilson 已提交
1510
	struct inode *inode;
1511

1512 1513 1514 1515 1516 1517
	/* Our goal here is to return as much of the memory as
	 * is possible back to the system as we are called from OOM.
	 * To do this we must instruct the shmfs to drop all of its
	 * backing pages, *now*. Here we mirror the actions taken
	 * when by shmem_delete_inode() to release the backing store.
	 */
C
Chris Wilson 已提交
1518
	inode = obj->filp->f_path.dentry->d_inode;
1519 1520 1521
	truncate_inode_pages(inode->i_mapping, 0);
	if (inode->i_op->truncate_range)
		inode->i_op->truncate_range(inode, 0, (loff_t)-1);
C
Chris Wilson 已提交
1522 1523

	obj_priv->madv = __I915_MADV_PURGED;
1524 1525 1526 1527 1528 1529 1530 1531
}

static inline int
i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
{
	return obj_priv->madv == I915_MADV_DONTNEED;
}

1532 1533 1534 1535 1536
static void
i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
1537
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1538 1539 1540 1541 1542 1543 1544

	i915_verify_inactive(dev, __FILE__, __LINE__);
	if (obj_priv->pin_count != 0)
		list_del_init(&obj_priv->list);
	else
		list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);

1545 1546
	BUG_ON(!list_empty(&obj_priv->gpu_write_list));

1547
	obj_priv->last_rendering_seqno = 0;
1548
	obj_priv->ring = NULL;
1549 1550 1551 1552 1553 1554 1555
	if (obj_priv->active) {
		obj_priv->active = 0;
		drm_gem_object_unreference(obj);
	}
	i915_verify_inactive(dev, __FILE__, __LINE__);
}

1556 1557
static void
i915_gem_process_flushing_list(struct drm_device *dev,
1558 1559
			       uint32_t flush_domains, uint32_t seqno,
			       struct intel_ring_buffer *ring)
1560 1561 1562 1563 1564 1565 1566
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj_priv, *next;

	list_for_each_entry_safe(obj_priv, next,
				 &dev_priv->mm.gpu_write_list,
				 gpu_write_list) {
1567
		struct drm_gem_object *obj = &obj_priv->base;
1568 1569

		if ((obj->write_domain & flush_domains) ==
1570 1571
		    obj->write_domain &&
		    obj_priv->ring->ring_flag == ring->ring_flag) {
1572 1573 1574 1575
			uint32_t old_write_domain = obj->write_domain;

			obj->write_domain = 0;
			list_del_init(&obj_priv->gpu_write_list);
1576
			i915_gem_object_move_to_active(obj, seqno, ring);
1577 1578

			/* update the fence lru list */
1579 1580 1581 1582
			if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
				struct drm_i915_fence_reg *reg =
					&dev_priv->fence_regs[obj_priv->fence_reg];
				list_move_tail(&reg->lru_list,
1583
						&dev_priv->mm.fence_list);
1584
			}
1585 1586 1587 1588 1589 1590 1591

			trace_i915_gem_object_change_domain(obj,
							    obj->read_domains,
							    old_write_domain);
		}
	}
}
1592

1593
uint32_t
1594
i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1595
		 uint32_t flush_domains, struct intel_ring_buffer *ring)
1596 1597
{
	drm_i915_private_t *dev_priv = dev->dev_private;
1598
	struct drm_i915_file_private *i915_file_priv = NULL;
1599 1600 1601 1602
	struct drm_i915_gem_request *request;
	uint32_t seqno;
	int was_empty;

1603 1604 1605
	if (file_priv != NULL)
		i915_file_priv = file_priv->driver_priv;

1606
	request = kzalloc(sizeof(*request), GFP_KERNEL);
1607 1608 1609
	if (request == NULL)
		return 0;

1610
	seqno = ring->add_request(dev, ring, file_priv, flush_domains);
1611 1612

	request->seqno = seqno;
1613
	request->ring = ring;
1614
	request->emitted_jiffies = jiffies;
1615 1616 1617
	was_empty = list_empty(&ring->request_list);
	list_add_tail(&request->list, &ring->request_list);

1618 1619 1620 1621 1622 1623
	if (i915_file_priv) {
		list_add_tail(&request->client_list,
			      &i915_file_priv->mm.request_list);
	} else {
		INIT_LIST_HEAD(&request->client_list);
	}
1624

1625 1626 1627
	/* Associate any objects on the flushing list matching the write
	 * domain we're flushing with our flush.
	 */
1628
	if (flush_domains != 0) 
1629
		i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
1630

B
Ben Gamari 已提交
1631 1632 1633 1634 1635
	if (!dev_priv->mm.suspended) {
		mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
		if (was_empty)
			queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
	}
1636 1637 1638 1639 1640 1641 1642 1643 1644
	return seqno;
}

/**
 * Command execution barrier
 *
 * Ensures that all commands in the ring are finished
 * before signalling the CPU
 */
1645
static uint32_t
1646
i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1647 1648 1649 1650 1651 1652
{
	uint32_t flush_domains = 0;

	/* The sampler always gets flushed on i965 (sigh) */
	if (IS_I965G(dev))
		flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1653 1654 1655

	ring->flush(dev, ring,
			I915_GEM_DOMAIN_COMMAND, flush_domains);
1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668
	return flush_domains;
}

/**
 * Moves buffers associated only with the given active seqno from the active
 * to inactive list, potentially freeing them.
 */
static void
i915_gem_retire_request(struct drm_device *dev,
			struct drm_i915_gem_request *request)
{
	drm_i915_private_t *dev_priv = dev->dev_private;

C
Chris Wilson 已提交
1669 1670
	trace_i915_gem_request_retire(dev, request->seqno);

1671 1672 1673
	/* Move any buffers on the active list that are no longer referenced
	 * by the ringbuffer to the flushing/inactive lists as appropriate.
	 */
1674
	spin_lock(&dev_priv->mm.active_list_lock);
1675
	while (!list_empty(&request->ring->active_list)) {
1676 1677 1678
		struct drm_gem_object *obj;
		struct drm_i915_gem_object *obj_priv;

1679
		obj_priv = list_first_entry(&request->ring->active_list,
1680 1681
					    struct drm_i915_gem_object,
					    list);
1682
		obj = &obj_priv->base;
1683 1684 1685 1686 1687 1688

		/* If the seqno being retired doesn't match the oldest in the
		 * list, then the oldest in the list must still be newer than
		 * this seqno.
		 */
		if (obj_priv->last_rendering_seqno != request->seqno)
1689
			goto out;
1690

1691 1692 1693 1694 1695
#if WATCH_LRU
		DRM_INFO("%s: retire %d moves to inactive list %p\n",
			 __func__, request->seqno, obj);
#endif

1696 1697
		if (obj->write_domain != 0)
			i915_gem_object_move_to_flushing(obj);
1698 1699 1700 1701 1702 1703 1704 1705
		else {
			/* Take a reference on the object so it won't be
			 * freed while the spinlock is held.  The list
			 * protection for this spinlock is safe when breaking
			 * the lock like this since the next thing we do
			 * is just get the head of the list again.
			 */
			drm_gem_object_reference(obj);
1706
			i915_gem_object_move_to_inactive(obj);
1707 1708 1709 1710
			spin_unlock(&dev_priv->mm.active_list_lock);
			drm_gem_object_unreference(obj);
			spin_lock(&dev_priv->mm.active_list_lock);
		}
1711
	}
1712 1713
out:
	spin_unlock(&dev_priv->mm.active_list_lock);
1714 1715 1716 1717 1718
}

/**
 * Returns true if seq1 is later than seq2.
 */
1719
bool
1720 1721 1722 1723 1724 1725
i915_seqno_passed(uint32_t seq1, uint32_t seq2)
{
	return (int32_t)(seq1 - seq2) >= 0;
}

uint32_t
1726
i915_get_gem_seqno(struct drm_device *dev,
1727
		   struct intel_ring_buffer *ring)
1728
{
1729
	return ring->get_gem_seqno(dev, ring);
1730 1731 1732 1733 1734
}

/**
 * This function clears the request list as sequence numbers are passed.
 */
1735 1736 1737
static void
i915_gem_retire_requests_ring(struct drm_device *dev,
			      struct intel_ring_buffer *ring)
1738 1739 1740 1741
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	uint32_t seqno;

1742
	if (!ring->status_page.page_addr
1743
			|| list_empty(&ring->request_list))
1744 1745
		return;

1746
	seqno = i915_get_gem_seqno(dev, ring);
1747

1748
	while (!list_empty(&ring->request_list)) {
1749 1750 1751
		struct drm_i915_gem_request *request;
		uint32_t retiring_seqno;

1752
		request = list_first_entry(&ring->request_list,
1753 1754 1755 1756 1757
					   struct drm_i915_gem_request,
					   list);
		retiring_seqno = request->seqno;

		if (i915_seqno_passed(seqno, retiring_seqno) ||
1758
		    atomic_read(&dev_priv->mm.wedged)) {
1759 1760 1761
			i915_gem_retire_request(dev, request);

			list_del(&request->list);
1762
			list_del(&request->client_list);
1763
			kfree(request);
1764 1765 1766
		} else
			break;
	}
1767 1768 1769

	if (unlikely (dev_priv->trace_irq_seqno &&
		      i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1770 1771

		ring->user_irq_put(dev, ring);
1772 1773
		dev_priv->trace_irq_seqno = 0;
	}
1774 1775
}

1776 1777 1778 1779 1780
void
i915_gem_retire_requests(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;

1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794
	if (!list_empty(&dev_priv->mm.deferred_free_list)) {
	    struct drm_i915_gem_object *obj_priv, *tmp;

	    /* We must be careful that during unbind() we do not
	     * accidentally infinitely recurse into retire requests.
	     * Currently:
	     *   retire -> free -> unbind -> wait -> retire_ring
	     */
	    list_for_each_entry_safe(obj_priv, tmp,
				     &dev_priv->mm.deferred_free_list,
				     list)
		    i915_gem_free_object_tail(&obj_priv->base);
	}

1795 1796 1797 1798 1799
	i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
	if (HAS_BSD(dev))
		i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
}

1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810
void
i915_gem_retire_work_handler(struct work_struct *work)
{
	drm_i915_private_t *dev_priv;
	struct drm_device *dev;

	dev_priv = container_of(work, drm_i915_private_t,
				mm.retire_work.work);
	dev = dev_priv->dev;

	mutex_lock(&dev->struct_mutex);
1811
	i915_gem_retire_requests(dev);
1812

1813
	if (!dev_priv->mm.suspended &&
1814 1815 1816
		(!list_empty(&dev_priv->render_ring.request_list) ||
			(HAS_BSD(dev) &&
			 !list_empty(&dev_priv->bsd_ring.request_list))))
1817
		queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1818 1819 1820
	mutex_unlock(&dev->struct_mutex);
}

1821
int
1822 1823
i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
		int interruptible, struct intel_ring_buffer *ring)
1824 1825
{
	drm_i915_private_t *dev_priv = dev->dev_private;
1826
	u32 ier;
1827 1828 1829 1830
	int ret = 0;

	BUG_ON(seqno == 0);

1831
	if (atomic_read(&dev_priv->mm.wedged))
1832 1833
		return -EIO;

1834
	if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
1835
		if (HAS_PCH_SPLIT(dev))
1836 1837 1838
			ier = I915_READ(DEIER) | I915_READ(GTIER);
		else
			ier = I915_READ(IER);
1839 1840 1841 1842 1843 1844 1845
		if (!ier) {
			DRM_ERROR("something (likely vbetool) disabled "
				  "interrupts, re-enabling\n");
			i915_driver_irq_preinstall(dev);
			i915_driver_irq_postinstall(dev);
		}

C
Chris Wilson 已提交
1846 1847
		trace_i915_gem_request_wait_begin(dev, seqno);

1848
		ring->waiting_gem_seqno = seqno;
1849
		ring->user_irq_get(dev, ring);
1850
		if (interruptible)
1851 1852 1853 1854
			ret = wait_event_interruptible(ring->irq_queue,
				i915_seqno_passed(
					ring->get_gem_seqno(dev, ring), seqno)
				|| atomic_read(&dev_priv->mm.wedged));
1855
		else
1856 1857 1858 1859
			wait_event(ring->irq_queue,
				i915_seqno_passed(
					ring->get_gem_seqno(dev, ring), seqno)
				|| atomic_read(&dev_priv->mm.wedged));
1860

1861
		ring->user_irq_put(dev, ring);
1862
		ring->waiting_gem_seqno = 0;
C
Chris Wilson 已提交
1863 1864

		trace_i915_gem_request_wait_end(dev, seqno);
1865
	}
1866
	if (atomic_read(&dev_priv->mm.wedged))
1867 1868 1869 1870
		ret = -EIO;

	if (ret && ret != -ERESTARTSYS)
		DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1871
			  __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
1872 1873 1874 1875 1876 1877 1878

	/* Directly dispatch request retiring.  While we have the work queue
	 * to handle this, the waiter on a request often wants an associated
	 * buffer to have made it to the inactive list, and we would need
	 * a separate wait queue to handle that.
	 */
	if (ret == 0)
1879
		i915_gem_retire_requests_ring(dev, ring);
1880 1881 1882 1883

	return ret;
}

1884 1885 1886 1887 1888
/**
 * Waits for a sequence number to be signaled, and cleans up the
 * request and object lists appropriately for that event.
 */
static int
1889 1890
i915_wait_request(struct drm_device *dev, uint32_t seqno,
		struct intel_ring_buffer *ring)
1891
{
1892
	return i915_do_wait_request(dev, seqno, 1, ring);
1893 1894
}

1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905
static void
i915_gem_flush(struct drm_device *dev,
	       uint32_t invalidate_domains,
	       uint32_t flush_domains)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	if (flush_domains & I915_GEM_DOMAIN_CPU)
		drm_agp_chipset_flush(dev);
	dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
			invalidate_domains,
			flush_domains);
1906 1907 1908 1909 1910

	if (HAS_BSD(dev))
		dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
				invalidate_domains,
				flush_domains);
1911 1912
}

1913 1914 1915 1916 1917 1918 1919 1920
/**
 * Ensures that all rendering to the object has completed and the object is
 * safe to unbind from the GTT or access from the CPU.
 */
static int
i915_gem_object_wait_rendering(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
1921
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1922 1923
	int ret;

1924 1925
	/* This function only exists to support waiting for existing rendering,
	 * not for emitting required flushes.
1926
	 */
1927
	BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1928 1929 1930 1931 1932 1933 1934 1935 1936

	/* If there is rendering queued on the buffer being evicted, wait for
	 * it.
	 */
	if (obj_priv->active) {
#if WATCH_BUF
		DRM_INFO("%s: object %p wait for seqno %08x\n",
			  __func__, obj, obj_priv->last_rendering_seqno);
#endif
1937 1938
		ret = i915_wait_request(dev,
				obj_priv->last_rendering_seqno, obj_priv->ring);
1939 1940 1941 1942 1943 1944 1945 1946 1947 1948
		if (ret != 0)
			return ret;
	}

	return 0;
}

/**
 * Unbinds an object from the GTT aperture.
 */
1949
int
1950 1951 1952
i915_gem_object_unbind(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
1953
	drm_i915_private_t *dev_priv = dev->dev_private;
1954
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968
	int ret = 0;

#if WATCH_BUF
	DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
	DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
#endif
	if (obj_priv->gtt_space == NULL)
		return 0;

	if (obj_priv->pin_count != 0) {
		DRM_ERROR("Attempting to unbind pinned buffer\n");
		return -EINVAL;
	}

1969 1970 1971
	/* blow away mappings if mapped through GTT */
	i915_gem_release_mmap(obj);

1972 1973 1974 1975 1976 1977
	/* Move the object to the CPU domain to ensure that
	 * any possible CPU writes while it's not in the GTT
	 * are flushed when we go to remap it. This will
	 * also ensure that all pending GPU writes are finished
	 * before we unbind.
	 */
1978
	ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1979
	if (ret == -ERESTARTSYS)
1980
		return ret;
1981 1982 1983 1984
	/* Continue on if we fail due to EIO, the GPU is hung so we
	 * should be safe and we need to cleanup or else we might
	 * cause memory corruption through use-after-free.
	 */
1985

1986 1987 1988 1989
	/* release the fence reg _after_ flushing */
	if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
		i915_gem_clear_fence_reg(obj);

1990 1991 1992 1993 1994 1995
	if (obj_priv->agp_mem != NULL) {
		drm_unbind_agp(obj_priv->agp_mem);
		drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
		obj_priv->agp_mem = NULL;
	}

1996
	i915_gem_object_put_pages(obj);
1997
	BUG_ON(obj_priv->pages_refcount);
1998 1999 2000 2001 2002 2003 2004 2005 2006 2007

	if (obj_priv->gtt_space) {
		atomic_dec(&dev->gtt_count);
		atomic_sub(obj->size, &dev->gtt_memory);

		drm_mm_put_block(obj_priv->gtt_space);
		obj_priv->gtt_space = NULL;
	}

	/* Remove ourselves from the LRU list if present. */
2008
	spin_lock(&dev_priv->mm.active_list_lock);
2009 2010
	if (!list_empty(&obj_priv->list))
		list_del_init(&obj_priv->list);
2011
	spin_unlock(&dev_priv->mm.active_list_lock);
2012

2013 2014 2015
	if (i915_gem_object_is_purgeable(obj_priv))
		i915_gem_object_truncate(obj);

C
Chris Wilson 已提交
2016 2017
	trace_i915_gem_object_unbind(obj);

2018
	return ret;
2019 2020
}

2021
int
2022 2023 2024 2025
i915_gpu_idle(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	bool lists_empty;
2026
	uint32_t seqno1, seqno2;
2027
	int ret;
2028 2029

	spin_lock(&dev_priv->mm.active_list_lock);
2030 2031 2032 2033
	lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
		       list_empty(&dev_priv->render_ring.active_list) &&
		       (!HAS_BSD(dev) ||
			list_empty(&dev_priv->bsd_ring.active_list)));
2034 2035 2036 2037 2038 2039 2040
	spin_unlock(&dev_priv->mm.active_list_lock);

	if (lists_empty)
		return 0;

	/* Flush everything onto the inactive list. */
	i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2041
	seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2042
			&dev_priv->render_ring);
2043
	if (seqno1 == 0)
2044
		return -ENOMEM;
2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057
	ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);

	if (HAS_BSD(dev)) {
		seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
				&dev_priv->bsd_ring);
		if (seqno2 == 0)
			return -ENOMEM;

		ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
		if (ret)
			return ret;
	}

2058

2059
	return ret;
2060 2061
}

2062
int
2063 2064
i915_gem_object_get_pages(struct drm_gem_object *obj,
			  gfp_t gfpmask)
2065
{
2066
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2067 2068 2069 2070 2071
	int page_count, i;
	struct address_space *mapping;
	struct inode *inode;
	struct page *page;

2072 2073 2074
	BUG_ON(obj_priv->pages_refcount
			== DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);

2075
	if (obj_priv->pages_refcount++ != 0)
2076 2077 2078 2079 2080 2081
		return 0;

	/* Get the list of pages out of our struct file.  They'll be pinned
	 * at this point until we release them.
	 */
	page_count = obj->size / PAGE_SIZE;
2082
	BUG_ON(obj_priv->pages != NULL);
2083
	obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2084 2085
	if (obj_priv->pages == NULL) {
		obj_priv->pages_refcount--;
2086 2087 2088 2089 2090 2091
		return -ENOMEM;
	}

	inode = obj->filp->f_path.dentry->d_inode;
	mapping = inode->i_mapping;
	for (i = 0; i < page_count; i++) {
2092
		page = read_cache_page_gfp(mapping, i,
2093
					   GFP_HIGHUSER |
2094
					   __GFP_COLD |
2095
					   __GFP_RECLAIMABLE |
2096
					   gfpmask);
2097 2098 2099
		if (IS_ERR(page))
			goto err_pages;

2100
		obj_priv->pages[i] = page;
2101
	}
2102 2103 2104 2105

	if (obj_priv->tiling_mode != I915_TILING_NONE)
		i915_gem_object_do_bit_17_swizzle(obj);

2106
	return 0;
2107 2108 2109 2110 2111 2112 2113 2114 2115

err_pages:
	while (i--)
		page_cache_release(obj_priv->pages[i]);

	drm_free_large(obj_priv->pages);
	obj_priv->pages = NULL;
	obj_priv->pages_refcount--;
	return PTR_ERR(page);
2116 2117
}

2118 2119 2120 2121 2122
static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
{
	struct drm_gem_object *obj = reg->obj;
	struct drm_device *dev = obj->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
2123
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139
	int regnum = obj_priv->fence_reg;
	uint64_t val;

	val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
		    0xfffff000) << 32;
	val |= obj_priv->gtt_offset & 0xfffff000;
	val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
		SANDYBRIDGE_FENCE_PITCH_SHIFT;

	if (obj_priv->tiling_mode == I915_TILING_Y)
		val |= 1 << I965_FENCE_TILING_Y_SHIFT;
	val |= I965_FENCE_REG_VALID;

	I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
}

2140 2141 2142 2143 2144
static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
{
	struct drm_gem_object *obj = reg->obj;
	struct drm_device *dev = obj->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
2145
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164
	int regnum = obj_priv->fence_reg;
	uint64_t val;

	val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
		    0xfffff000) << 32;
	val |= obj_priv->gtt_offset & 0xfffff000;
	val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
	if (obj_priv->tiling_mode == I915_TILING_Y)
		val |= 1 << I965_FENCE_TILING_Y_SHIFT;
	val |= I965_FENCE_REG_VALID;

	I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
}

static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
{
	struct drm_gem_object *obj = reg->obj;
	struct drm_device *dev = obj->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
2165
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2166
	int regnum = obj_priv->fence_reg;
2167
	int tile_width;
2168
	uint32_t fence_reg, val;
2169 2170 2171 2172
	uint32_t pitch_val;

	if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
	    (obj_priv->gtt_offset & (obj->size - 1))) {
2173
		WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2174
		     __func__, obj_priv->gtt_offset, obj->size);
2175 2176 2177
		return;
	}

2178 2179 2180
	if (obj_priv->tiling_mode == I915_TILING_Y &&
	    HAS_128_BYTE_Y_TILING(dev))
		tile_width = 128;
2181
	else
2182 2183 2184 2185 2186
		tile_width = 512;

	/* Note: pitch better be a power of two tile widths */
	pitch_val = obj_priv->stride / tile_width;
	pitch_val = ffs(pitch_val) - 1;
2187

2188 2189 2190 2191 2192 2193
	if (obj_priv->tiling_mode == I915_TILING_Y &&
	    HAS_128_BYTE_Y_TILING(dev))
		WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
	else
		WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);

2194 2195 2196 2197 2198 2199 2200
	val = obj_priv->gtt_offset;
	if (obj_priv->tiling_mode == I915_TILING_Y)
		val |= 1 << I830_FENCE_TILING_Y_SHIFT;
	val |= I915_FENCE_SIZE_BITS(obj->size);
	val |= pitch_val << I830_FENCE_PITCH_SHIFT;
	val |= I830_FENCE_REG_VALID;

2201 2202 2203 2204 2205
	if (regnum < 8)
		fence_reg = FENCE_REG_830_0 + (regnum * 4);
	else
		fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
	I915_WRITE(fence_reg, val);
2206 2207 2208 2209 2210 2211 2212
}

static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
{
	struct drm_gem_object *obj = reg->obj;
	struct drm_device *dev = obj->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
2213
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2214 2215 2216
	int regnum = obj_priv->fence_reg;
	uint32_t val;
	uint32_t pitch_val;
2217
	uint32_t fence_size_bits;
2218

2219
	if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2220
	    (obj_priv->gtt_offset & (obj->size - 1))) {
2221
		WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2222
		     __func__, obj_priv->gtt_offset);
2223 2224 2225
		return;
	}

2226 2227 2228 2229
	pitch_val = obj_priv->stride / 128;
	pitch_val = ffs(pitch_val) - 1;
	WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);

2230 2231 2232
	val = obj_priv->gtt_offset;
	if (obj_priv->tiling_mode == I915_TILING_Y)
		val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2233 2234 2235
	fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
	WARN_ON(fence_size_bits & ~0x00000f00);
	val |= fence_size_bits;
2236 2237 2238 2239 2240 2241
	val |= pitch_val << I830_FENCE_PITCH_SHIFT;
	val |= I830_FENCE_REG_VALID;

	I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
}

2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256
static int i915_find_fence_reg(struct drm_device *dev)
{
	struct drm_i915_fence_reg *reg = NULL;
	struct drm_i915_gem_object *obj_priv = NULL;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_gem_object *obj = NULL;
	int i, avail, ret;

	/* First try to find a free reg */
	avail = 0;
	for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
		reg = &dev_priv->fence_regs[i];
		if (!reg->obj)
			return i;

2257
		obj_priv = to_intel_bo(reg->obj);
2258 2259 2260 2261 2262 2263 2264 2265 2266
		if (!obj_priv->pin_count)
		    avail++;
	}

	if (avail == 0)
		return -ENOSPC;

	/* None available, try to steal one or wait for a user to finish */
	i = I915_FENCE_REG_NONE;
2267 2268 2269 2270
	list_for_each_entry(reg, &dev_priv->mm.fence_list,
			    lru_list) {
		obj = reg->obj;
		obj_priv = to_intel_bo(obj);
2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294

		if (obj_priv->pin_count)
			continue;

		/* found one! */
		i = obj_priv->fence_reg;
		break;
	}

	BUG_ON(i == I915_FENCE_REG_NONE);

	/* We only have a reference on obj from the active list. put_fence_reg
	 * might drop that one, causing a use-after-free in it. So hold a
	 * private reference to obj like the other callers of put_fence_reg
	 * (set_tiling ioctl) do. */
	drm_gem_object_reference(obj);
	ret = i915_gem_object_put_fence_reg(obj);
	drm_gem_object_unreference(obj);
	if (ret != 0)
		return ret;

	return i;
}

2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307
/**
 * i915_gem_object_get_fence_reg - set up a fence reg for an object
 * @obj: object to map through a fence reg
 *
 * When mapping objects through the GTT, userspace wants to be able to write
 * to them without having to worry about swizzling if the object is tiled.
 *
 * This function walks the fence regs looking for a free one for @obj,
 * stealing one if it can't find any.
 *
 * It then sets up the reg based on the object's properties: address, pitch
 * and tiling format.
 */
2308 2309
int
i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2310 2311
{
	struct drm_device *dev = obj->dev;
J
Jesse Barnes 已提交
2312
	struct drm_i915_private *dev_priv = dev->dev_private;
2313
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2314
	struct drm_i915_fence_reg *reg = NULL;
2315
	int ret;
2316

2317 2318
	/* Just update our place in the LRU if our fence is getting used. */
	if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2319 2320
		reg = &dev_priv->fence_regs[obj_priv->fence_reg];
		list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2321 2322 2323
		return 0;
	}

2324 2325 2326 2327 2328
	switch (obj_priv->tiling_mode) {
	case I915_TILING_NONE:
		WARN(1, "allocating a fence for non-tiled object?\n");
		break;
	case I915_TILING_X:
2329 2330 2331 2332 2333
		if (!obj_priv->stride)
			return -EINVAL;
		WARN((obj_priv->stride & (512 - 1)),
		     "object 0x%08x is X tiled but has non-512B pitch\n",
		     obj_priv->gtt_offset);
2334 2335
		break;
	case I915_TILING_Y:
2336 2337 2338 2339 2340
		if (!obj_priv->stride)
			return -EINVAL;
		WARN((obj_priv->stride & (128 - 1)),
		     "object 0x%08x is Y tiled but has non-128B pitch\n",
		     obj_priv->gtt_offset);
2341 2342 2343
		break;
	}

2344 2345 2346
	ret = i915_find_fence_reg(dev);
	if (ret < 0)
		return ret;
2347

2348 2349
	obj_priv->fence_reg = ret;
	reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2350
	list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2351

2352 2353
	reg->obj = obj;

2354 2355
	switch (INTEL_INFO(dev)->gen) {
	case 6:
2356
		sandybridge_write_fence_reg(reg);
2357 2358 2359
		break;
	case 5:
	case 4:
2360
		i965_write_fence_reg(reg);
2361 2362
		break;
	case 3:
2363
		i915_write_fence_reg(reg);
2364 2365
		break;
	case 2:
2366
		i830_write_fence_reg(reg);
2367 2368
		break;
	}
2369

2370 2371
	trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
			obj_priv->tiling_mode);
C
Chris Wilson 已提交
2372

2373
	return 0;
2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386
}

/**
 * i915_gem_clear_fence_reg - clear out fence register info
 * @obj: object to clear
 *
 * Zeroes out the fence register itself and clears out the associated
 * data structures in dev_priv and obj_priv.
 */
static void
i915_gem_clear_fence_reg(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
J
Jesse Barnes 已提交
2387
	drm_i915_private_t *dev_priv = dev->dev_private;
2388
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2389 2390
	struct drm_i915_fence_reg *reg =
		&dev_priv->fence_regs[obj_priv->fence_reg];
2391
	uint32_t fence_reg;
2392

2393 2394
	switch (INTEL_INFO(dev)->gen) {
	case 6:
2395 2396
		I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
			     (obj_priv->fence_reg * 8), 0);
2397 2398 2399
		break;
	case 5:
	case 4:
2400
		I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2401 2402 2403 2404
		break;
	case 3:
		if (obj_priv->fence_reg > 8)
			fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2405
		else
2406 2407
	case 2:
			fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2408 2409

		I915_WRITE(fence_reg, 0);
2410
		break;
2411
	}
2412

2413
	reg->obj = NULL;
2414
	obj_priv->fence_reg = I915_FENCE_REG_NONE;
2415
	list_del_init(&reg->lru_list);
2416 2417
}

2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429
/**
 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
 * to the buffer to finish, and then resets the fence register.
 * @obj: tiled object holding a fence register.
 *
 * Zeroes out the fence register itself and clears out the associated
 * data structures in dev_priv and obj_priv.
 */
int
i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
2430
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2431 2432 2433 2434

	if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
		return 0;

2435 2436 2437 2438 2439 2440
	/* If we've changed tiling, GTT-mappings of the object
	 * need to re-fault to ensure that the correct fence register
	 * setup is in place.
	 */
	i915_gem_release_mmap(obj);

2441 2442 2443 2444 2445 2446 2447
	/* On the i915, GPU access to tiled buffers is via a fence,
	 * therefore we must wait for any outstanding access to complete
	 * before clearing the fence.
	 */
	if (!IS_I965G(dev)) {
		int ret;

2448 2449 2450 2451
		ret = i915_gem_object_flush_gpu_write_domain(obj);
		if (ret != 0)
			return ret;

2452 2453 2454 2455 2456
		ret = i915_gem_object_wait_rendering(obj);
		if (ret != 0)
			return ret;
	}

2457
	i915_gem_object_flush_gtt_write_domain(obj);
2458 2459 2460 2461 2462
	i915_gem_clear_fence_reg (obj);

	return 0;
}

2463 2464 2465 2466 2467 2468 2469 2470
/**
 * Finds free space in the GTT aperture and binds the object there.
 */
static int
i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
{
	struct drm_device *dev = obj->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
2471
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2472
	struct drm_mm_node *free_space;
2473
	gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2474
	int ret;
2475

C
Chris Wilson 已提交
2476
	if (obj_priv->madv != I915_MADV_WILLNEED) {
2477 2478 2479 2480
		DRM_ERROR("Attempting to bind a purgeable object\n");
		return -EINVAL;
	}

2481
	if (alignment == 0)
2482
		alignment = i915_gem_get_gtt_alignment(obj);
2483
	if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2484 2485 2486 2487
		DRM_ERROR("Invalid object alignment requested %u\n", alignment);
		return -EINVAL;
	}

2488 2489 2490 2491 2492 2493 2494 2495
	/* If the object is bigger than the entire aperture, reject it early
	 * before evicting everything in a vain attempt to find space.
	 */
	if (obj->size > dev->gtt_total) {
		DRM_ERROR("Attempting to bind an object larger than the aperture\n");
		return -E2BIG;
	}

2496 2497 2498 2499 2500 2501
 search_free:
	free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
					obj->size, alignment, 0);
	if (free_space != NULL) {
		obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
						       alignment);
D
Daniel Vetter 已提交
2502
		if (obj_priv->gtt_space != NULL)
2503 2504 2505 2506 2507 2508 2509 2510 2511
			obj_priv->gtt_offset = obj_priv->gtt_space->start;
	}
	if (obj_priv->gtt_space == NULL) {
		/* If the gtt is empty and we're still having trouble
		 * fitting our object in, we're out of memory.
		 */
#if WATCH_LRU
		DRM_INFO("%s: GTT full, evicting something\n", __func__);
#endif
2512
		ret = i915_gem_evict_something(dev, obj->size, alignment);
2513
		if (ret)
2514
			return ret;
2515

2516 2517 2518 2519
		goto search_free;
	}

#if WATCH_BUF
2520
	DRM_INFO("Binding object of size %zd at 0x%08x\n",
2521 2522
		 obj->size, obj_priv->gtt_offset);
#endif
2523
	ret = i915_gem_object_get_pages(obj, gfpmask);
2524 2525 2526
	if (ret) {
		drm_mm_put_block(obj_priv->gtt_space);
		obj_priv->gtt_space = NULL;
2527 2528 2529

		if (ret == -ENOMEM) {
			/* first try to clear up some space from the GTT */
2530 2531
			ret = i915_gem_evict_something(dev, obj->size,
						       alignment);
2532 2533
			if (ret) {
				/* now try to shrink everyone else */
2534 2535 2536
				if (gfpmask) {
					gfpmask = 0;
					goto search_free;
2537 2538 2539 2540 2541 2542 2543 2544
				}

				return ret;
			}

			goto search_free;
		}

2545 2546 2547 2548 2549 2550 2551
		return ret;
	}

	/* Create an AGP memory structure pointing at our pages, and bind it
	 * into the GTT.
	 */
	obj_priv->agp_mem = drm_agp_bind_pages(dev,
2552
					       obj_priv->pages,
2553
					       obj->size >> PAGE_SHIFT,
2554 2555
					       obj_priv->gtt_offset,
					       obj_priv->agp_type);
2556
	if (obj_priv->agp_mem == NULL) {
2557
		i915_gem_object_put_pages(obj);
2558 2559
		drm_mm_put_block(obj_priv->gtt_space);
		obj_priv->gtt_space = NULL;
2560

2561
		ret = i915_gem_evict_something(dev, obj->size, alignment);
2562
		if (ret)
2563 2564 2565
			return ret;

		goto search_free;
2566 2567 2568 2569
	}
	atomic_inc(&dev->gtt_count);
	atomic_add(obj->size, &dev->gtt_memory);

2570 2571 2572
	/* keep track of bounds object by adding it to the inactive list */
	list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);

2573 2574 2575 2576
	/* Assert that the object is not currently in any GPU domain. As it
	 * wasn't in the GTT, there shouldn't be any way it could have been in
	 * a GPU cache
	 */
2577 2578
	BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
	BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2579

C
Chris Wilson 已提交
2580 2581
	trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);

2582 2583 2584 2585 2586 2587
	return 0;
}

void
i915_gem_clflush_object(struct drm_gem_object *obj)
{
2588
	struct drm_i915_gem_object	*obj_priv = to_intel_bo(obj);
2589 2590 2591 2592 2593

	/* If we don't have a page list set up, then we're not pinned
	 * to GPU, and we can ignore the cache flush because it'll happen
	 * again at bind time.
	 */
2594
	if (obj_priv->pages == NULL)
2595 2596
		return;

C
Chris Wilson 已提交
2597
	trace_i915_gem_object_clflush(obj);
2598

2599
	drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2600 2601
}

2602
/** Flushes any GPU write domain for the object if it's dirty. */
2603
static int
2604 2605 2606
i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
C
Chris Wilson 已提交
2607
	uint32_t old_write_domain;
2608
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2609 2610

	if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2611
		return 0;
2612 2613

	/* Queue the GPU write cache flushing we need. */
C
Chris Wilson 已提交
2614
	old_write_domain = obj->write_domain;
2615
	i915_gem_flush(dev, 0, obj->write_domain);
2616 2617
	if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
		return -ENOMEM;
C
Chris Wilson 已提交
2618 2619 2620 2621

	trace_i915_gem_object_change_domain(obj,
					    obj->read_domains,
					    old_write_domain);
2622
	return 0;
2623 2624 2625 2626 2627 2628
}

/** Flushes the GTT write domain for the object if it's dirty. */
static void
i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
{
C
Chris Wilson 已提交
2629 2630
	uint32_t old_write_domain;

2631 2632 2633 2634 2635 2636 2637
	if (obj->write_domain != I915_GEM_DOMAIN_GTT)
		return;

	/* No actual flushing is required for the GTT write domain.   Writes
	 * to it immediately go to main memory as far as we know, so there's
	 * no chipset flush.  It also doesn't land in render cache.
	 */
C
Chris Wilson 已提交
2638
	old_write_domain = obj->write_domain;
2639
	obj->write_domain = 0;
C
Chris Wilson 已提交
2640 2641 2642 2643

	trace_i915_gem_object_change_domain(obj,
					    obj->read_domains,
					    old_write_domain);
2644 2645 2646 2647 2648 2649 2650
}

/** Flushes the CPU write domain for the object if it's dirty. */
static void
i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
C
Chris Wilson 已提交
2651
	uint32_t old_write_domain;
2652 2653 2654 2655 2656 2657

	if (obj->write_domain != I915_GEM_DOMAIN_CPU)
		return;

	i915_gem_clflush_object(obj);
	drm_agp_chipset_flush(dev);
C
Chris Wilson 已提交
2658
	old_write_domain = obj->write_domain;
2659
	obj->write_domain = 0;
C
Chris Wilson 已提交
2660 2661 2662 2663

	trace_i915_gem_object_change_domain(obj,
					    obj->read_domains,
					    old_write_domain);
2664 2665
}

2666
int
2667 2668
i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
{
2669 2670
	int ret = 0;

2671 2672 2673 2674 2675 2676 2677 2678
	switch (obj->write_domain) {
	case I915_GEM_DOMAIN_GTT:
		i915_gem_object_flush_gtt_write_domain(obj);
		break;
	case I915_GEM_DOMAIN_CPU:
		i915_gem_object_flush_cpu_write_domain(obj);
		break;
	default:
2679
		ret = i915_gem_object_flush_gpu_write_domain(obj);
2680 2681
		break;
	}
2682 2683

	return ret;
2684 2685
}

2686 2687 2688 2689 2690 2691
/**
 * Moves a single object to the GTT read, and possibly write domain.
 *
 * This function returns when the move is complete, including waiting on
 * flushes to occur.
 */
J
Jesse Barnes 已提交
2692
int
2693 2694
i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
{
2695
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
C
Chris Wilson 已提交
2696
	uint32_t old_write_domain, old_read_domains;
2697
	int ret;
2698

2699 2700 2701 2702
	/* Not valid to be called on unbound objects. */
	if (obj_priv->gtt_space == NULL)
		return -EINVAL;

2703 2704 2705 2706
	ret = i915_gem_object_flush_gpu_write_domain(obj);
	if (ret != 0)
		return ret;

2707 2708 2709 2710 2711
	/* Wait on any GPU rendering and flushing to occur. */
	ret = i915_gem_object_wait_rendering(obj);
	if (ret != 0)
		return ret;

C
Chris Wilson 已提交
2712 2713 2714
	old_write_domain = obj->write_domain;
	old_read_domains = obj->read_domains;

2715 2716
	/* If we're writing through the GTT domain, then CPU and GPU caches
	 * will need to be invalidated at next use.
2717
	 */
2718 2719
	if (write)
		obj->read_domains &= I915_GEM_DOMAIN_GTT;
2720

2721
	i915_gem_object_flush_cpu_write_domain(obj);
2722

2723 2724 2725 2726 2727 2728 2729 2730
	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
	BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
	obj->read_domains |= I915_GEM_DOMAIN_GTT;
	if (write) {
		obj->write_domain = I915_GEM_DOMAIN_GTT;
		obj_priv->dirty = 1;
2731 2732
	}

C
Chris Wilson 已提交
2733 2734 2735 2736
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);

2737 2738 2739
	return 0;
}

2740 2741 2742 2743 2744 2745 2746 2747
/*
 * Prepare buffer for display plane. Use uninterruptible for possible flush
 * wait, as in modesetting process we're not supposed to be interrupted.
 */
int
i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
2748
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2749 2750 2751 2752 2753 2754 2755
	uint32_t old_write_domain, old_read_domains;
	int ret;

	/* Not valid to be called on unbound objects. */
	if (obj_priv->gtt_space == NULL)
		return -EINVAL;

2756 2757 2758
	ret = i915_gem_object_flush_gpu_write_domain(obj);
	if (ret)
		return ret;
2759 2760 2761 2762 2763 2764 2765

	/* Wait on any GPU rendering and flushing to occur. */
	if (obj_priv->active) {
#if WATCH_BUF
		DRM_INFO("%s: object %p wait for seqno %08x\n",
			  __func__, obj, obj_priv->last_rendering_seqno);
#endif
2766 2767 2768 2769
		ret = i915_do_wait_request(dev,
				obj_priv->last_rendering_seqno,
				0,
				obj_priv->ring);
2770 2771 2772 2773
		if (ret != 0)
			return ret;
	}

2774 2775
	i915_gem_object_flush_cpu_write_domain(obj);

2776 2777 2778 2779 2780 2781 2782
	old_write_domain = obj->write_domain;
	old_read_domains = obj->read_domains;

	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
	BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2783
	obj->read_domains = I915_GEM_DOMAIN_GTT;
2784 2785 2786 2787 2788 2789 2790 2791 2792 2793
	obj->write_domain = I915_GEM_DOMAIN_GTT;
	obj_priv->dirty = 1;

	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);

	return 0;
}

2794 2795 2796 2797 2798 2799 2800 2801 2802
/**
 * Moves a single object to the CPU read, and possibly write domain.
 *
 * This function returns when the move is complete, including waiting on
 * flushes to occur.
 */
static int
i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
{
C
Chris Wilson 已提交
2803
	uint32_t old_write_domain, old_read_domains;
2804 2805
	int ret;

2806 2807 2808 2809
	ret = i915_gem_object_flush_gpu_write_domain(obj);
	if (ret)
		return ret;

2810
	/* Wait on any GPU rendering and flushing to occur. */
2811 2812 2813
	ret = i915_gem_object_wait_rendering(obj);
	if (ret != 0)
		return ret;
2814

2815
	i915_gem_object_flush_gtt_write_domain(obj);
2816

2817 2818
	/* If we have a partially-valid cache of the object in the CPU,
	 * finish invalidating it and free the per-page flags.
2819
	 */
2820
	i915_gem_object_set_to_full_cpu_read_domain(obj);
2821

C
Chris Wilson 已提交
2822 2823 2824
	old_write_domain = obj->write_domain;
	old_read_domains = obj->read_domains;

2825 2826
	/* Flush the CPU cache if it's still invalid. */
	if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2827 2828
		i915_gem_clflush_object(obj);

2829
		obj->read_domains |= I915_GEM_DOMAIN_CPU;
2830 2831 2832 2833 2834
	}

	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
2835 2836 2837 2838 2839 2840 2841 2842 2843
	BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);

	/* If we're writing through the CPU, then the GPU read domains will
	 * need to be invalidated at next use.
	 */
	if (write) {
		obj->read_domains &= I915_GEM_DOMAIN_CPU;
		obj->write_domain = I915_GEM_DOMAIN_CPU;
	}
2844

C
Chris Wilson 已提交
2845 2846 2847 2848
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);

2849 2850 2851
	return 0;
}

2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962
/*
 * Set the next domain for the specified object. This
 * may not actually perform the necessary flushing/invaliding though,
 * as that may want to be batched with other set_domain operations
 *
 * This is (we hope) the only really tricky part of gem. The goal
 * is fairly simple -- track which caches hold bits of the object
 * and make sure they remain coherent. A few concrete examples may
 * help to explain how it works. For shorthand, we use the notation
 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
 * a pair of read and write domain masks.
 *
 * Case 1: the batch buffer
 *
 *	1. Allocated
 *	2. Written by CPU
 *	3. Mapped to GTT
 *	4. Read by GPU
 *	5. Unmapped from GTT
 *	6. Freed
 *
 *	Let's take these a step at a time
 *
 *	1. Allocated
 *		Pages allocated from the kernel may still have
 *		cache contents, so we set them to (CPU, CPU) always.
 *	2. Written by CPU (using pwrite)
 *		The pwrite function calls set_domain (CPU, CPU) and
 *		this function does nothing (as nothing changes)
 *	3. Mapped by GTT
 *		This function asserts that the object is not
 *		currently in any GPU-based read or write domains
 *	4. Read by GPU
 *		i915_gem_execbuffer calls set_domain (COMMAND, 0).
 *		As write_domain is zero, this function adds in the
 *		current read domains (CPU+COMMAND, 0).
 *		flush_domains is set to CPU.
 *		invalidate_domains is set to COMMAND
 *		clflush is run to get data out of the CPU caches
 *		then i915_dev_set_domain calls i915_gem_flush to
 *		emit an MI_FLUSH and drm_agp_chipset_flush
 *	5. Unmapped from GTT
 *		i915_gem_object_unbind calls set_domain (CPU, CPU)
 *		flush_domains and invalidate_domains end up both zero
 *		so no flushing/invalidating happens
 *	6. Freed
 *		yay, done
 *
 * Case 2: The shared render buffer
 *
 *	1. Allocated
 *	2. Mapped to GTT
 *	3. Read/written by GPU
 *	4. set_domain to (CPU,CPU)
 *	5. Read/written by CPU
 *	6. Read/written by GPU
 *
 *	1. Allocated
 *		Same as last example, (CPU, CPU)
 *	2. Mapped to GTT
 *		Nothing changes (assertions find that it is not in the GPU)
 *	3. Read/written by GPU
 *		execbuffer calls set_domain (RENDER, RENDER)
 *		flush_domains gets CPU
 *		invalidate_domains gets GPU
 *		clflush (obj)
 *		MI_FLUSH and drm_agp_chipset_flush
 *	4. set_domain (CPU, CPU)
 *		flush_domains gets GPU
 *		invalidate_domains gets CPU
 *		wait_rendering (obj) to make sure all drawing is complete.
 *		This will include an MI_FLUSH to get the data from GPU
 *		to memory
 *		clflush (obj) to invalidate the CPU cache
 *		Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
 *	5. Read/written by CPU
 *		cache lines are loaded and dirtied
 *	6. Read written by GPU
 *		Same as last GPU access
 *
 * Case 3: The constant buffer
 *
 *	1. Allocated
 *	2. Written by CPU
 *	3. Read by GPU
 *	4. Updated (written) by CPU again
 *	5. Read by GPU
 *
 *	1. Allocated
 *		(CPU, CPU)
 *	2. Written by CPU
 *		(CPU, CPU)
 *	3. Read by GPU
 *		(CPU+RENDER, 0)
 *		flush_domains = CPU
 *		invalidate_domains = RENDER
 *		clflush (obj)
 *		MI_FLUSH
 *		drm_agp_chipset_flush
 *	4. Updated (written) by CPU again
 *		(CPU, CPU)
 *		flush_domains = 0 (no previous write domain)
 *		invalidate_domains = 0 (no new read domains)
 *	5. Read by GPU
 *		(CPU+RENDER, 0)
 *		flush_domains = CPU
 *		invalidate_domains = RENDER
 *		clflush (obj)
 *		MI_FLUSH
 *		drm_agp_chipset_flush
 */
2963
static void
2964
i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2965 2966
{
	struct drm_device		*dev = obj->dev;
2967
	drm_i915_private_t		*dev_priv = dev->dev_private;
2968
	struct drm_i915_gem_object	*obj_priv = to_intel_bo(obj);
2969 2970
	uint32_t			invalidate_domains = 0;
	uint32_t			flush_domains = 0;
C
Chris Wilson 已提交
2971
	uint32_t			old_read_domains;
2972

2973 2974
	BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
	BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2975

2976 2977
	intel_mark_busy(dev, obj);

2978 2979 2980
#if WATCH_BUF
	DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
		 __func__, obj,
2981 2982
		 obj->read_domains, obj->pending_read_domains,
		 obj->write_domain, obj->pending_write_domain);
2983 2984 2985 2986 2987
#endif
	/*
	 * If the object isn't moving to a new write domain,
	 * let the object stay in multiple read domains
	 */
2988 2989
	if (obj->pending_write_domain == 0)
		obj->pending_read_domains |= obj->read_domains;
2990 2991 2992 2993 2994 2995 2996 2997 2998
	else
		obj_priv->dirty = 1;

	/*
	 * Flush the current write domain if
	 * the new read domains don't match. Invalidate
	 * any read domains which differ from the old
	 * write domain
	 */
2999 3000
	if (obj->write_domain &&
	    obj->write_domain != obj->pending_read_domains) {
3001
		flush_domains |= obj->write_domain;
3002 3003
		invalidate_domains |=
			obj->pending_read_domains & ~obj->write_domain;
3004 3005 3006 3007 3008
	}
	/*
	 * Invalidate any read caches which may have
	 * stale data. That is, any new read domains.
	 */
3009
	invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3010 3011 3012 3013 3014 3015 3016 3017
	if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
#if WATCH_BUF
		DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
			 __func__, flush_domains, invalidate_domains);
#endif
		i915_gem_clflush_object(obj);
	}

C
Chris Wilson 已提交
3018 3019
	old_read_domains = obj->read_domains;

3020 3021 3022 3023 3024 3025 3026 3027
	/* The actual obj->write_domain will be updated with
	 * pending_write_domain after we emit the accumulated flush for all
	 * of our domain changes in execbuffers (which clears objects'
	 * write_domains).  So if we have a current write domain that we
	 * aren't changing, set pending_write_domain to that.
	 */
	if (flush_domains == 0 && obj->pending_write_domain == 0)
		obj->pending_write_domain = obj->write_domain;
3028
	obj->read_domains = obj->pending_read_domains;
3029

3030 3031 3032 3033 3034 3035 3036
	if (flush_domains & I915_GEM_GPU_DOMAINS) {
		if (obj_priv->ring == &dev_priv->render_ring)
			dev_priv->flush_rings |= FLUSH_RENDER_RING;
		else if (obj_priv->ring == &dev_priv->bsd_ring)
			dev_priv->flush_rings |= FLUSH_BSD_RING;
	}

3037 3038 3039 3040 3041 3042 3043 3044
	dev->invalidate_domains |= invalidate_domains;
	dev->flush_domains |= flush_domains;
#if WATCH_BUF
	DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
		 __func__,
		 obj->read_domains, obj->write_domain,
		 dev->invalidate_domains, dev->flush_domains);
#endif
C
Chris Wilson 已提交
3045 3046 3047 3048

	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    obj->write_domain);
3049 3050 3051
}

/**
3052
 * Moves the object from a partially CPU read to a full one.
3053
 *
3054 3055
 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3056
 */
3057 3058
static void
i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3059
{
3060
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3061

3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072
	if (!obj_priv->page_cpu_valid)
		return;

	/* If we're partially in the CPU read domain, finish moving it in.
	 */
	if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
		int i;

		for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
			if (obj_priv->page_cpu_valid[i])
				continue;
3073
			drm_clflush_pages(obj_priv->pages + i, 1);
3074 3075 3076 3077 3078 3079
		}
	}

	/* Free the page_cpu_valid mappings which are now stale, whether
	 * or not we've got I915_GEM_DOMAIN_CPU.
	 */
3080
	kfree(obj_priv->page_cpu_valid);
3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099
	obj_priv->page_cpu_valid = NULL;
}

/**
 * Set the CPU read domain on a range of the object.
 *
 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
 * not entirely valid.  The page_cpu_valid member of the object flags which
 * pages have been flushed, and will be respected by
 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
 * of the whole object.
 *
 * This function returns when the move is complete, including waiting on
 * flushes to occur.
 */
static int
i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
					  uint64_t offset, uint64_t size)
{
3100
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
C
Chris Wilson 已提交
3101
	uint32_t old_read_domains;
3102
	int i, ret;
3103

3104 3105
	if (offset == 0 && size == obj->size)
		return i915_gem_object_set_to_cpu_domain(obj, 0);
3106

3107 3108 3109 3110
	ret = i915_gem_object_flush_gpu_write_domain(obj);
	if (ret)
		return ret;

3111
	/* Wait on any GPU rendering and flushing to occur. */
3112
	ret = i915_gem_object_wait_rendering(obj);
3113
	if (ret != 0)
3114
		return ret;
3115 3116 3117 3118 3119 3120
	i915_gem_object_flush_gtt_write_domain(obj);

	/* If we're already fully in the CPU read domain, we're done. */
	if (obj_priv->page_cpu_valid == NULL &&
	    (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
		return 0;
3121

3122 3123 3124
	/* Otherwise, create/clear the per-page CPU read domain flag if we're
	 * newly adding I915_GEM_DOMAIN_CPU
	 */
3125
	if (obj_priv->page_cpu_valid == NULL) {
3126 3127
		obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
						   GFP_KERNEL);
3128 3129 3130 3131
		if (obj_priv->page_cpu_valid == NULL)
			return -ENOMEM;
	} else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
		memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3132 3133 3134 3135

	/* Flush the cache on any pages that are still invalid from the CPU's
	 * perspective.
	 */
3136 3137
	for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
	     i++) {
3138 3139 3140
		if (obj_priv->page_cpu_valid[i])
			continue;

3141
		drm_clflush_pages(obj_priv->pages + i, 1);
3142 3143 3144 3145

		obj_priv->page_cpu_valid[i] = 1;
	}

3146 3147 3148 3149 3150
	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
	BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);

C
Chris Wilson 已提交
3151
	old_read_domains = obj->read_domains;
3152 3153
	obj->read_domains |= I915_GEM_DOMAIN_CPU;

C
Chris Wilson 已提交
3154 3155 3156 3157
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    obj->write_domain);

3158 3159 3160 3161 3162 3163 3164 3165 3166
	return 0;
}

/**
 * Pin an object to the GTT and evaluate the relocations landing in it.
 */
static int
i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
				 struct drm_file *file_priv,
J
Jesse Barnes 已提交
3167
				 struct drm_i915_gem_exec_object2 *entry,
3168
				 struct drm_i915_gem_relocation_entry *relocs)
3169 3170
{
	struct drm_device *dev = obj->dev;
3171
	drm_i915_private_t *dev_priv = dev->dev_private;
3172
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3173
	int i, ret;
3174
	void __iomem *reloc_page;
J
Jesse Barnes 已提交
3175 3176 3177 3178 3179 3180
	bool need_fence;

	need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
	             obj_priv->tiling_mode != I915_TILING_NONE;

	/* Check fence reg constraints and rebind if necessary */
3181 3182 3183 3184 3185 3186 3187
	if (need_fence &&
	    !i915_gem_object_fence_offset_ok(obj,
					     obj_priv->tiling_mode)) {
		ret = i915_gem_object_unbind(obj);
		if (ret)
			return ret;
	}
3188 3189 3190 3191 3192 3193

	/* Choose the GTT offset for our buffer and put it there. */
	ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
	if (ret)
		return ret;

J
Jesse Barnes 已提交
3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205
	/*
	 * Pre-965 chips need a fence register set up in order to
	 * properly handle blits to/from tiled surfaces.
	 */
	if (need_fence) {
		ret = i915_gem_object_get_fence_reg(obj);
		if (ret != 0) {
			i915_gem_object_unpin(obj);
			return ret;
		}
	}

3206 3207 3208 3209 3210 3211
	entry->offset = obj_priv->gtt_offset;

	/* Apply the relocations, using the GTT aperture to avoid cache
	 * flushing requirements.
	 */
	for (i = 0; i < entry->relocation_count; i++) {
3212
		struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3213 3214
		struct drm_gem_object *target_obj;
		struct drm_i915_gem_object *target_obj_priv;
3215 3216
		uint32_t reloc_val, reloc_offset;
		uint32_t __iomem *reloc_entry;
3217 3218

		target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3219
						   reloc->target_handle);
3220 3221
		if (target_obj == NULL) {
			i915_gem_object_unpin(obj);
3222
			return -ENOENT;
3223
		}
3224
		target_obj_priv = to_intel_bo(target_obj);
3225

3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240
#if WATCH_RELOC
		DRM_INFO("%s: obj %p offset %08x target %d "
			 "read %08x write %08x gtt %08x "
			 "presumed %08x delta %08x\n",
			 __func__,
			 obj,
			 (int) reloc->offset,
			 (int) reloc->target_handle,
			 (int) reloc->read_domains,
			 (int) reloc->write_domain,
			 (int) target_obj_priv->gtt_offset,
			 (int) reloc->presumed_offset,
			 reloc->delta);
#endif

3241 3242 3243 3244 3245
		/* The target buffer should have appeared before us in the
		 * exec_object list, so it should have a GTT space bound by now.
		 */
		if (target_obj_priv->gtt_space == NULL) {
			DRM_ERROR("No GTT space found for object %d\n",
3246
				  reloc->target_handle);
3247 3248 3249 3250 3251
			drm_gem_object_unreference(target_obj);
			i915_gem_object_unpin(obj);
			return -EINVAL;
		}

3252
		/* Validate that the target is in a valid r/w GPU domain */
3253 3254 3255 3256 3257 3258 3259 3260 3261 3262
		if (reloc->write_domain & (reloc->write_domain - 1)) {
			DRM_ERROR("reloc with multiple write domains: "
				  "obj %p target %d offset %d "
				  "read %08x write %08x",
				  obj, reloc->target_handle,
				  (int) reloc->offset,
				  reloc->read_domains,
				  reloc->write_domain);
			return -EINVAL;
		}
3263 3264
		if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
		    reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3265 3266 3267
			DRM_ERROR("reloc with read/write CPU domains: "
				  "obj %p target %d offset %d "
				  "read %08x write %08x",
3268 3269 3270 3271
				  obj, reloc->target_handle,
				  (int) reloc->offset,
				  reloc->read_domains,
				  reloc->write_domain);
3272 3273
			drm_gem_object_unreference(target_obj);
			i915_gem_object_unpin(obj);
3274 3275
			return -EINVAL;
		}
3276 3277
		if (reloc->write_domain && target_obj->pending_write_domain &&
		    reloc->write_domain != target_obj->pending_write_domain) {
3278 3279 3280
			DRM_ERROR("Write domain conflict: "
				  "obj %p target %d offset %d "
				  "new %08x old %08x\n",
3281 3282 3283
				  obj, reloc->target_handle,
				  (int) reloc->offset,
				  reloc->write_domain,
3284 3285 3286 3287 3288 3289
				  target_obj->pending_write_domain);
			drm_gem_object_unreference(target_obj);
			i915_gem_object_unpin(obj);
			return -EINVAL;
		}

3290 3291
		target_obj->pending_read_domains |= reloc->read_domains;
		target_obj->pending_write_domain |= reloc->write_domain;
3292 3293 3294 3295

		/* If the relocation already has the right value in it, no
		 * more work needs to be done.
		 */
3296
		if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3297 3298 3299 3300
			drm_gem_object_unreference(target_obj);
			continue;
		}

3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331
		/* Check that the relocation address is valid... */
		if (reloc->offset > obj->size - 4) {
			DRM_ERROR("Relocation beyond object bounds: "
				  "obj %p target %d offset %d size %d.\n",
				  obj, reloc->target_handle,
				  (int) reloc->offset, (int) obj->size);
			drm_gem_object_unreference(target_obj);
			i915_gem_object_unpin(obj);
			return -EINVAL;
		}
		if (reloc->offset & 3) {
			DRM_ERROR("Relocation not 4-byte aligned: "
				  "obj %p target %d offset %d.\n",
				  obj, reloc->target_handle,
				  (int) reloc->offset);
			drm_gem_object_unreference(target_obj);
			i915_gem_object_unpin(obj);
			return -EINVAL;
		}

		/* and points to somewhere within the target object. */
		if (reloc->delta >= target_obj->size) {
			DRM_ERROR("Relocation beyond target object bounds: "
				  "obj %p target %d delta %d size %d.\n",
				  obj, reloc->target_handle,
				  (int) reloc->delta, (int) target_obj->size);
			drm_gem_object_unreference(target_obj);
			i915_gem_object_unpin(obj);
			return -EINVAL;
		}

3332 3333 3334 3335 3336
		ret = i915_gem_object_set_to_gtt_domain(obj, 1);
		if (ret != 0) {
			drm_gem_object_unreference(target_obj);
			i915_gem_object_unpin(obj);
			return -EINVAL;
3337 3338 3339 3340 3341
		}

		/* Map the page containing the relocation we're going to
		 * perform.
		 */
3342
		reloc_offset = obj_priv->gtt_offset + reloc->offset;
3343 3344
		reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
						      (reloc_offset &
3345 3346
						       ~(PAGE_SIZE - 1)),
						      KM_USER0);
3347
		reloc_entry = (uint32_t __iomem *)(reloc_page +
3348
						   (reloc_offset & (PAGE_SIZE - 1)));
3349
		reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3350 3351 3352

#if WATCH_BUF
		DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3353
			  obj, (unsigned int) reloc->offset,
3354 3355 3356
			  readl(reloc_entry), reloc_val);
#endif
		writel(reloc_val, reloc_entry);
3357
		io_mapping_unmap_atomic(reloc_page, KM_USER0);
3358

3359 3360
		/* The updated presumed offset for this entry will be
		 * copied back out to the user.
3361
		 */
3362
		reloc->presumed_offset = target_obj_priv->gtt_offset;
3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376

		drm_gem_object_unreference(target_obj);
	}

#if WATCH_BUF
	if (0)
		i915_gem_dump_object(obj, 128, __func__, ~0);
#endif
	return 0;
}

/* Throttle our rendering by waiting until the ring has completed our requests
 * emitted over 20 msec ago.
 *
3377 3378 3379 3380
 * Note that if we were to use the current jiffies each time around the loop,
 * we wouldn't escape the function with any frames outstanding if the time to
 * render a frame was over 20ms.
 *
3381 3382 3383 3384 3385 3386 3387 3388
 * This should get us reasonable parallelism between CPU and GPU but also
 * relatively low latency when blocking on a particular request to finish.
 */
static int
i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
{
	struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
	int ret = 0;
3389
	unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3390 3391

	mutex_lock(&dev->struct_mutex);
3392 3393 3394 3395 3396 3397 3398 3399 3400 3401
	while (!list_empty(&i915_file_priv->mm.request_list)) {
		struct drm_i915_gem_request *request;

		request = list_first_entry(&i915_file_priv->mm.request_list,
					   struct drm_i915_gem_request,
					   client_list);

		if (time_after_eq(request->emitted_jiffies, recent_enough))
			break;

3402
		ret = i915_wait_request(dev, request->seqno, request->ring);
3403 3404 3405
		if (ret != 0)
			break;
	}
3406
	mutex_unlock(&dev->struct_mutex);
3407

3408 3409 3410
	return ret;
}

3411
static int
J
Jesse Barnes 已提交
3412
i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425
			      uint32_t buffer_count,
			      struct drm_i915_gem_relocation_entry **relocs)
{
	uint32_t reloc_count = 0, reloc_index = 0, i;
	int ret;

	*relocs = NULL;
	for (i = 0; i < buffer_count; i++) {
		if (reloc_count + exec_list[i].relocation_count < reloc_count)
			return -EINVAL;
		reloc_count += exec_list[i].relocation_count;
	}

3426
	*relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
J
Jesse Barnes 已提交
3427 3428
	if (*relocs == NULL) {
		DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3429
		return -ENOMEM;
J
Jesse Barnes 已提交
3430
	}
3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441

	for (i = 0; i < buffer_count; i++) {
		struct drm_i915_gem_relocation_entry __user *user_relocs;

		user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;

		ret = copy_from_user(&(*relocs)[reloc_index],
				     user_relocs,
				     exec_list[i].relocation_count *
				     sizeof(**relocs));
		if (ret != 0) {
3442
			drm_free_large(*relocs);
3443
			*relocs = NULL;
3444
			return -EFAULT;
3445 3446 3447 3448 3449
		}

		reloc_index += exec_list[i].relocation_count;
	}

3450
	return 0;
3451 3452 3453
}

static int
J
Jesse Barnes 已提交
3454
i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3455 3456 3457 3458
			    uint32_t buffer_count,
			    struct drm_i915_gem_relocation_entry *relocs)
{
	uint32_t reloc_count = 0, i;
3459
	int ret = 0;
3460

3461 3462 3463
	if (relocs == NULL)
	    return 0;

3464 3465
	for (i = 0; i < buffer_count; i++) {
		struct drm_i915_gem_relocation_entry __user *user_relocs;
3466
		int unwritten;
3467 3468 3469

		user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;

3470 3471 3472 3473 3474 3475 3476 3477
		unwritten = copy_to_user(user_relocs,
					 &relocs[reloc_count],
					 exec_list[i].relocation_count *
					 sizeof(*relocs));

		if (unwritten) {
			ret = -EFAULT;
			goto err;
3478 3479 3480 3481 3482
		}

		reloc_count += exec_list[i].relocation_count;
	}

3483
err:
3484
	drm_free_large(relocs);
3485 3486 3487 3488

	return ret;
}

3489
static int
J
Jesse Barnes 已提交
3490
i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506
			   uint64_t exec_offset)
{
	uint32_t exec_start, exec_len;

	exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
	exec_len = (uint32_t) exec->batch_len;

	if ((exec_start | exec_len) & 0x7)
		return -EINVAL;

	if (!exec_start)
		return -EINVAL;

	return 0;
}

3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520
static int
i915_gem_wait_for_pending_flip(struct drm_device *dev,
			       struct drm_gem_object **object_list,
			       int count)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj_priv;
	DEFINE_WAIT(wait);
	int i, ret = 0;

	for (;;) {
		prepare_to_wait(&dev_priv->pending_flip_queue,
				&wait, TASK_INTERRUPTIBLE);
		for (i = 0; i < count; i++) {
3521
			obj_priv = to_intel_bo(object_list[i]);
3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541
			if (atomic_read(&obj_priv->pending_flip) > 0)
				break;
		}
		if (i == count)
			break;

		if (!signal_pending(current)) {
			mutex_unlock(&dev->struct_mutex);
			schedule();
			mutex_lock(&dev->struct_mutex);
			continue;
		}
		ret = -ERESTARTSYS;
		break;
	}
	finish_wait(&dev_priv->pending_flip_queue, &wait);

	return ret;
}

3542

3543
int
J
Jesse Barnes 已提交
3544 3545 3546 3547
i915_gem_do_execbuffer(struct drm_device *dev, void *data,
		       struct drm_file *file_priv,
		       struct drm_i915_gem_execbuffer2 *args,
		       struct drm_i915_gem_exec_object2 *exec_list)
3548 3549 3550 3551
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_gem_object **object_list = NULL;
	struct drm_gem_object *batch_obj;
3552
	struct drm_i915_gem_object *obj_priv;
3553
	struct drm_clip_rect *cliprects = NULL;
3554
	struct drm_i915_gem_relocation_entry *relocs = NULL;
J
Jesse Barnes 已提交
3555
	int ret = 0, ret2, i, pinned = 0;
3556
	uint64_t exec_offset;
3557
	uint32_t seqno, flush_domains, reloc_index;
3558
	int pin_tries, flips;
3559

3560 3561
	struct intel_ring_buffer *ring = NULL;

3562 3563 3564 3565
#if WATCH_EXEC
	DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
		  (int) args->buffers_ptr, args->buffer_count, args->batch_len);
#endif
3566 3567 3568 3569 3570 3571 3572 3573 3574 3575
	if (args->flags & I915_EXEC_BSD) {
		if (!HAS_BSD(dev)) {
			DRM_ERROR("execbuf with wrong flag\n");
			return -EINVAL;
		}
		ring = &dev_priv->bsd_ring;
	} else {
		ring = &dev_priv->render_ring;
	}

3576 3577 3578 3579
	if (args->buffer_count < 1) {
		DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
		return -EINVAL;
	}
3580
	object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
J
Jesse Barnes 已提交
3581 3582
	if (object_list == NULL) {
		DRM_ERROR("Failed to allocate object list for %d buffers\n",
3583 3584 3585 3586 3587
			  args->buffer_count);
		ret = -ENOMEM;
		goto pre_mutex_err;
	}

3588
	if (args->num_cliprects != 0) {
3589 3590
		cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
				    GFP_KERNEL);
3591 3592
		if (cliprects == NULL) {
			ret = -ENOMEM;
3593
			goto pre_mutex_err;
3594
		}
3595 3596 3597 3598 3599 3600 3601 3602

		ret = copy_from_user(cliprects,
				     (struct drm_clip_rect __user *)
				     (uintptr_t) args->cliprects_ptr,
				     sizeof(*cliprects) * args->num_cliprects);
		if (ret != 0) {
			DRM_ERROR("copy %d cliprects failed: %d\n",
				  args->num_cliprects, ret);
3603
			ret = -EFAULT;
3604 3605 3606 3607
			goto pre_mutex_err;
		}
	}

3608 3609 3610 3611 3612
	ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
					    &relocs);
	if (ret != 0)
		goto pre_mutex_err;

3613 3614 3615 3616
	mutex_lock(&dev->struct_mutex);

	i915_verify_inactive(dev, __FILE__, __LINE__);

3617
	if (atomic_read(&dev_priv->mm.wedged)) {
3618
		mutex_unlock(&dev->struct_mutex);
3619 3620
		ret = -EIO;
		goto pre_mutex_err;
3621 3622 3623 3624
	}

	if (dev_priv->mm.suspended) {
		mutex_unlock(&dev->struct_mutex);
3625 3626
		ret = -EBUSY;
		goto pre_mutex_err;
3627 3628
	}

3629
	/* Look up object handles */
3630
	flips = 0;
3631 3632 3633 3634 3635 3636
	for (i = 0; i < args->buffer_count; i++) {
		object_list[i] = drm_gem_object_lookup(dev, file_priv,
						       exec_list[i].handle);
		if (object_list[i] == NULL) {
			DRM_ERROR("Invalid object handle %d at index %d\n",
				   exec_list[i].handle, i);
3637 3638
			/* prevent error path from reading uninitialized data */
			args->buffer_count = i + 1;
3639
			ret = -ENOENT;
3640 3641
			goto err;
		}
3642

3643
		obj_priv = to_intel_bo(object_list[i]);
3644 3645 3646
		if (obj_priv->in_execbuffer) {
			DRM_ERROR("Object %p appears more than once in object list\n",
				   object_list[i]);
3647 3648
			/* prevent error path from reading uninitialized data */
			args->buffer_count = i + 1;
3649
			ret = -EINVAL;
3650 3651 3652
			goto err;
		}
		obj_priv->in_execbuffer = true;
3653 3654 3655 3656 3657 3658 3659 3660
		flips += atomic_read(&obj_priv->pending_flip);
	}

	if (flips > 0) {
		ret = i915_gem_wait_for_pending_flip(dev, object_list,
						     args->buffer_count);
		if (ret)
			goto err;
3661
	}
3662

3663 3664 3665
	/* Pin and relocate */
	for (pin_tries = 0; ; pin_tries++) {
		ret = 0;
3666 3667
		reloc_index = 0;

3668 3669 3670 3671 3672
		for (i = 0; i < args->buffer_count; i++) {
			object_list[i]->pending_read_domains = 0;
			object_list[i]->pending_write_domain = 0;
			ret = i915_gem_object_pin_and_relocate(object_list[i],
							       file_priv,
3673 3674
							       &exec_list[i],
							       &relocs[reloc_index]);
3675 3676 3677
			if (ret)
				break;
			pinned = i + 1;
3678
			reloc_index += exec_list[i].relocation_count;
3679 3680 3681 3682 3683 3684
		}
		/* success */
		if (ret == 0)
			break;

		/* error other than GTT full, or we've already tried again */
C
Chris Wilson 已提交
3685
		if (ret != -ENOSPC || pin_tries >= 1) {
3686 3687
			if (ret != -ERESTARTSYS) {
				unsigned long long total_size = 0;
3688 3689
				int num_fences = 0;
				for (i = 0; i < args->buffer_count; i++) {
3690
					obj_priv = to_intel_bo(object_list[i]);
3691

3692
					total_size += object_list[i]->size;
3693 3694 3695 3696 3697
					num_fences +=
						exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
						obj_priv->tiling_mode != I915_TILING_NONE;
				}
				DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3698
					  pinned+1, args->buffer_count,
3699 3700
					  total_size, num_fences,
					  ret);
3701 3702 3703 3704 3705 3706 3707 3708 3709 3710
				DRM_ERROR("%d objects [%d pinned], "
					  "%d object bytes [%d pinned], "
					  "%d/%d gtt bytes\n",
					  atomic_read(&dev->object_count),
					  atomic_read(&dev->pin_count),
					  atomic_read(&dev->object_memory),
					  atomic_read(&dev->pin_memory),
					  atomic_read(&dev->gtt_memory),
					  dev->gtt_total);
			}
3711 3712
			goto err;
		}
3713 3714 3715 3716

		/* unpin all of our buffers */
		for (i = 0; i < pinned; i++)
			i915_gem_object_unpin(object_list[i]);
3717
		pinned = 0;
3718 3719 3720

		/* evict everyone we can from the aperture */
		ret = i915_gem_evict_everything(dev);
3721
		if (ret && ret != -ENOSPC)
3722
			goto err;
3723 3724 3725 3726
	}

	/* Set the pending read domains for the batch buffer to COMMAND */
	batch_obj = object_list[args->buffer_count-1];
3727 3728 3729 3730 3731 3732
	if (batch_obj->pending_write_domain) {
		DRM_ERROR("Attempting to use self-modifying batch buffer\n");
		ret = -EINVAL;
		goto err;
	}
	batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3733

3734 3735 3736 3737 3738 3739 3740 3741
	/* Sanity check the batch buffer, prior to moving objects */
	exec_offset = exec_list[args->buffer_count - 1].offset;
	ret = i915_gem_check_execbuffer (args, exec_offset);
	if (ret != 0) {
		DRM_ERROR("execbuf with invalid offset/length\n");
		goto err;
	}

3742 3743
	i915_verify_inactive(dev, __FILE__, __LINE__);

3744 3745 3746 3747 3748 3749
	/* Zero the global flush/invalidate flags. These
	 * will be modified as new domains are computed
	 * for each object
	 */
	dev->invalidate_domains = 0;
	dev->flush_domains = 0;
3750
	dev_priv->flush_rings = 0;
3751

3752 3753 3754
	for (i = 0; i < args->buffer_count; i++) {
		struct drm_gem_object *obj = object_list[i];

3755
		/* Compute new gpu domains and update invalidate/flush */
3756
		i915_gem_object_set_to_gpu_domain(obj);
3757 3758 3759 3760
	}

	i915_verify_inactive(dev, __FILE__, __LINE__);

3761 3762 3763 3764 3765 3766 3767 3768 3769 3770
	if (dev->invalidate_domains | dev->flush_domains) {
#if WATCH_EXEC
		DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
			  __func__,
			 dev->invalidate_domains,
			 dev->flush_domains);
#endif
		i915_gem_flush(dev,
			       dev->invalidate_domains,
			       dev->flush_domains);
3771
		if (dev_priv->flush_rings & FLUSH_RENDER_RING)
3772
			(void)i915_add_request(dev, file_priv,
3773 3774 3775 3776 3777 3778
					       dev->flush_domains,
					       &dev_priv->render_ring);
		if (dev_priv->flush_rings & FLUSH_BSD_RING)
			(void)i915_add_request(dev, file_priv,
					       dev->flush_domains,
					       &dev_priv->bsd_ring);
3779
	}
3780

3781 3782
	for (i = 0; i < args->buffer_count; i++) {
		struct drm_gem_object *obj = object_list[i];
3783
		struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
C
Chris Wilson 已提交
3784
		uint32_t old_write_domain = obj->write_domain;
3785 3786

		obj->write_domain = obj->pending_write_domain;
3787 3788 3789 3790 3791 3792
		if (obj->write_domain)
			list_move_tail(&obj_priv->gpu_write_list,
				       &dev_priv->mm.gpu_write_list);
		else
			list_del_init(&obj_priv->gpu_write_list);

C
Chris Wilson 已提交
3793 3794 3795
		trace_i915_gem_object_change_domain(obj,
						    obj->read_domains,
						    old_write_domain);
3796 3797
	}

3798 3799 3800 3801 3802 3803 3804 3805 3806 3807
	i915_verify_inactive(dev, __FILE__, __LINE__);

#if WATCH_COHERENCY
	for (i = 0; i < args->buffer_count; i++) {
		i915_gem_object_check_coherency(object_list[i],
						exec_list[i].handle);
	}
#endif

#if WATCH_EXEC
3808
	i915_gem_dump_object(batch_obj,
3809 3810 3811 3812 3813 3814
			      args->batch_len,
			      __func__,
			      ~0);
#endif

	/* Exec the batchbuffer */
3815 3816
	ret = ring->dispatch_gem_execbuffer(dev, ring, args,
			cliprects, exec_offset);
3817 3818 3819 3820 3821 3822 3823 3824 3825
	if (ret) {
		DRM_ERROR("dispatch failed %d\n", ret);
		goto err;
	}

	/*
	 * Ensure that the commands in the batch buffer are
	 * finished before the interrupt fires
	 */
3826
	flush_domains = i915_retire_commands(dev, ring);
3827 3828 3829 3830 3831 3832 3833 3834 3835 3836

	i915_verify_inactive(dev, __FILE__, __LINE__);

	/*
	 * Get a seqno representing the execution of the current buffer,
	 * which we can wait on.  We would like to mitigate these interrupts,
	 * likely by only creating seqnos occasionally (so that we have
	 * *some* interrupts representing completion of buffers that we can
	 * wait on when trying to clear up gtt space).
	 */
3837
	seqno = i915_add_request(dev, file_priv, flush_domains, ring);
3838 3839 3840
	BUG_ON(seqno == 0);
	for (i = 0; i < args->buffer_count; i++) {
		struct drm_gem_object *obj = object_list[i];
3841
		obj_priv = to_intel_bo(obj);
3842

3843
		i915_gem_object_move_to_active(obj, seqno, ring);
3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854
#if WATCH_LRU
		DRM_INFO("%s: move to exec list %p\n", __func__, obj);
#endif
	}
#if WATCH_LRU
	i915_dump_lru(dev, __func__);
#endif

	i915_verify_inactive(dev, __FILE__, __LINE__);

err:
3855 3856 3857
	for (i = 0; i < pinned; i++)
		i915_gem_object_unpin(object_list[i]);

3858 3859
	for (i = 0; i < args->buffer_count; i++) {
		if (object_list[i]) {
3860
			obj_priv = to_intel_bo(object_list[i]);
3861 3862
			obj_priv->in_execbuffer = false;
		}
3863
		drm_gem_object_unreference(object_list[i]);
3864
	}
3865 3866 3867

	mutex_unlock(&dev->struct_mutex);

3868
pre_mutex_err:
3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882
	/* Copy the updated relocations out regardless of current error
	 * state.  Failure to update the relocs would mean that the next
	 * time userland calls execbuf, it would do so with presumed offset
	 * state that didn't match the actual object state.
	 */
	ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
					   relocs);
	if (ret2 != 0) {
		DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);

		if (ret == 0)
			ret = ret2;
	}

3883
	drm_free_large(object_list);
3884
	kfree(cliprects);
3885 3886 3887 3888

	return ret;
}

J
Jesse Barnes 已提交
3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954
/*
 * Legacy execbuffer just creates an exec2 list from the original exec object
 * list array and passes it to the real function.
 */
int
i915_gem_execbuffer(struct drm_device *dev, void *data,
		    struct drm_file *file_priv)
{
	struct drm_i915_gem_execbuffer *args = data;
	struct drm_i915_gem_execbuffer2 exec2;
	struct drm_i915_gem_exec_object *exec_list = NULL;
	struct drm_i915_gem_exec_object2 *exec2_list = NULL;
	int ret, i;

#if WATCH_EXEC
	DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
		  (int) args->buffers_ptr, args->buffer_count, args->batch_len);
#endif

	if (args->buffer_count < 1) {
		DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
		return -EINVAL;
	}

	/* Copy in the exec list from userland */
	exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
	exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
	if (exec_list == NULL || exec2_list == NULL) {
		DRM_ERROR("Failed to allocate exec list for %d buffers\n",
			  args->buffer_count);
		drm_free_large(exec_list);
		drm_free_large(exec2_list);
		return -ENOMEM;
	}
	ret = copy_from_user(exec_list,
			     (struct drm_i915_relocation_entry __user *)
			     (uintptr_t) args->buffers_ptr,
			     sizeof(*exec_list) * args->buffer_count);
	if (ret != 0) {
		DRM_ERROR("copy %d exec entries failed %d\n",
			  args->buffer_count, ret);
		drm_free_large(exec_list);
		drm_free_large(exec2_list);
		return -EFAULT;
	}

	for (i = 0; i < args->buffer_count; i++) {
		exec2_list[i].handle = exec_list[i].handle;
		exec2_list[i].relocation_count = exec_list[i].relocation_count;
		exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
		exec2_list[i].alignment = exec_list[i].alignment;
		exec2_list[i].offset = exec_list[i].offset;
		if (!IS_I965G(dev))
			exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
		else
			exec2_list[i].flags = 0;
	}

	exec2.buffers_ptr = args->buffers_ptr;
	exec2.buffer_count = args->buffer_count;
	exec2.batch_start_offset = args->batch_start_offset;
	exec2.batch_len = args->batch_len;
	exec2.DR1 = args->DR1;
	exec2.DR4 = args->DR4;
	exec2.num_cliprects = args->num_cliprects;
	exec2.cliprects_ptr = args->cliprects_ptr;
3955
	exec2.flags = I915_EXEC_RENDER;
J
Jesse Barnes 已提交
3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033

	ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
	if (!ret) {
		/* Copy the new buffer offsets back to the user's exec list. */
		for (i = 0; i < args->buffer_count; i++)
			exec_list[i].offset = exec2_list[i].offset;
		/* ... and back out to userspace */
		ret = copy_to_user((struct drm_i915_relocation_entry __user *)
				   (uintptr_t) args->buffers_ptr,
				   exec_list,
				   sizeof(*exec_list) * args->buffer_count);
		if (ret) {
			ret = -EFAULT;
			DRM_ERROR("failed to copy %d exec entries "
				  "back to user (%d)\n",
				  args->buffer_count, ret);
		}
	}

	drm_free_large(exec_list);
	drm_free_large(exec2_list);
	return ret;
}

int
i915_gem_execbuffer2(struct drm_device *dev, void *data,
		     struct drm_file *file_priv)
{
	struct drm_i915_gem_execbuffer2 *args = data;
	struct drm_i915_gem_exec_object2 *exec2_list = NULL;
	int ret;

#if WATCH_EXEC
	DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
		  (int) args->buffers_ptr, args->buffer_count, args->batch_len);
#endif

	if (args->buffer_count < 1) {
		DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
		return -EINVAL;
	}

	exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
	if (exec2_list == NULL) {
		DRM_ERROR("Failed to allocate exec list for %d buffers\n",
			  args->buffer_count);
		return -ENOMEM;
	}
	ret = copy_from_user(exec2_list,
			     (struct drm_i915_relocation_entry __user *)
			     (uintptr_t) args->buffers_ptr,
			     sizeof(*exec2_list) * args->buffer_count);
	if (ret != 0) {
		DRM_ERROR("copy %d exec entries failed %d\n",
			  args->buffer_count, ret);
		drm_free_large(exec2_list);
		return -EFAULT;
	}

	ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
	if (!ret) {
		/* Copy the new buffer offsets back to the user's exec list. */
		ret = copy_to_user((struct drm_i915_relocation_entry __user *)
				   (uintptr_t) args->buffers_ptr,
				   exec2_list,
				   sizeof(*exec2_list) * args->buffer_count);
		if (ret) {
			ret = -EFAULT;
			DRM_ERROR("failed to copy %d exec entries "
				  "back to user (%d)\n",
				  args->buffer_count, ret);
		}
	}

	drm_free_large(exec2_list);
	return ret;
}

4034 4035 4036 4037
int
i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
{
	struct drm_device *dev = obj->dev;
4038
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4039 4040
	int ret;

4041 4042
	BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);

4043
	i915_verify_inactive(dev, __FILE__, __LINE__);
4044 4045 4046 4047 4048

	if (obj_priv->gtt_space != NULL) {
		if (alignment == 0)
			alignment = i915_gem_get_gtt_alignment(obj);
		if (obj_priv->gtt_offset & (alignment - 1)) {
4049 4050 4051 4052
			WARN(obj_priv->pin_count,
			     "bo is already pinned with incorrect alignment:"
			     " offset=%x, req.alignment=%x\n",
			     obj_priv->gtt_offset, alignment);
4053 4054 4055 4056 4057 4058
			ret = i915_gem_object_unbind(obj);
			if (ret)
				return ret;
		}
	}

4059 4060
	if (obj_priv->gtt_space == NULL) {
		ret = i915_gem_object_bind_to_gtt(obj, alignment);
4061
		if (ret)
4062
			return ret;
4063
	}
J
Jesse Barnes 已提交
4064

4065 4066 4067 4068 4069 4070 4071 4072 4073
	obj_priv->pin_count++;

	/* If the object is not active and not pending a flush,
	 * remove it from the inactive list
	 */
	if (obj_priv->pin_count == 1) {
		atomic_inc(&dev->pin_count);
		atomic_add(obj->size, &dev->pin_memory);
		if (!obj_priv->active &&
4074
		    (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086
			list_del_init(&obj_priv->list);
	}
	i915_verify_inactive(dev, __FILE__, __LINE__);

	return 0;
}

void
i915_gem_object_unpin(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
4087
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099

	i915_verify_inactive(dev, __FILE__, __LINE__);
	obj_priv->pin_count--;
	BUG_ON(obj_priv->pin_count < 0);
	BUG_ON(obj_priv->gtt_space == NULL);

	/* If the object is no longer pinned, and is
	 * neither active nor being flushed, then stick it on
	 * the inactive list
	 */
	if (obj_priv->pin_count == 0) {
		if (!obj_priv->active &&
4100
		    (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124
			list_move_tail(&obj_priv->list,
				       &dev_priv->mm.inactive_list);
		atomic_dec(&dev->pin_count);
		atomic_sub(obj->size, &dev->pin_memory);
	}
	i915_verify_inactive(dev, __FILE__, __LINE__);
}

int
i915_gem_pin_ioctl(struct drm_device *dev, void *data,
		   struct drm_file *file_priv)
{
	struct drm_i915_gem_pin *args = data;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;
	int ret;

	mutex_lock(&dev->struct_mutex);

	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	if (obj == NULL) {
		DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
			  args->handle);
		mutex_unlock(&dev->struct_mutex);
4125
		return -ENOENT;
4126
	}
4127
	obj_priv = to_intel_bo(obj);
4128

C
Chris Wilson 已提交
4129 4130
	if (obj_priv->madv != I915_MADV_WILLNEED) {
		DRM_ERROR("Attempting to pin a purgeable buffer\n");
4131 4132 4133 4134 4135
		drm_gem_object_unreference(obj);
		mutex_unlock(&dev->struct_mutex);
		return -EINVAL;
	}

J
Jesse Barnes 已提交
4136 4137 4138
	if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
		DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
			  args->handle);
4139
		drm_gem_object_unreference(obj);
4140
		mutex_unlock(&dev->struct_mutex);
J
Jesse Barnes 已提交
4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152
		return -EINVAL;
	}

	obj_priv->user_pin_count++;
	obj_priv->pin_filp = file_priv;
	if (obj_priv->user_pin_count == 1) {
		ret = i915_gem_object_pin(obj, args->alignment);
		if (ret != 0) {
			drm_gem_object_unreference(obj);
			mutex_unlock(&dev->struct_mutex);
			return ret;
		}
4153 4154 4155 4156 4157
	}

	/* XXX - flush the CPU caches for pinned objects
	 * as the X server doesn't manage domains yet
	 */
4158
	i915_gem_object_flush_cpu_write_domain(obj);
4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171
	args->offset = obj_priv->gtt_offset;
	drm_gem_object_unreference(obj);
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

int
i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
		     struct drm_file *file_priv)
{
	struct drm_i915_gem_pin *args = data;
	struct drm_gem_object *obj;
J
Jesse Barnes 已提交
4172
	struct drm_i915_gem_object *obj_priv;
4173 4174 4175 4176 4177 4178 4179 4180

	mutex_lock(&dev->struct_mutex);

	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	if (obj == NULL) {
		DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
			  args->handle);
		mutex_unlock(&dev->struct_mutex);
4181
		return -ENOENT;
4182 4183
	}

4184
	obj_priv = to_intel_bo(obj);
J
Jesse Barnes 已提交
4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196
	if (obj_priv->pin_filp != file_priv) {
		DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
			  args->handle);
		drm_gem_object_unreference(obj);
		mutex_unlock(&dev->struct_mutex);
		return -EINVAL;
	}
	obj_priv->user_pin_count--;
	if (obj_priv->user_pin_count == 0) {
		obj_priv->pin_filp = NULL;
		i915_gem_object_unpin(obj);
	}
4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214

	drm_gem_object_unreference(obj);
	mutex_unlock(&dev->struct_mutex);
	return 0;
}

int
i915_gem_busy_ioctl(struct drm_device *dev, void *data,
		    struct drm_file *file_priv)
{
	struct drm_i915_gem_busy *args = data;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;

	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	if (obj == NULL) {
		DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
			  args->handle);
4215
		return -ENOENT;
4216 4217
	}

4218
	mutex_lock(&dev->struct_mutex);
4219

4220 4221 4222 4223
	/* Count all active objects as busy, even if they are currently not used
	 * by the gpu. Users of this interface expect objects to eventually
	 * become non-busy without any further actions, therefore emit any
	 * necessary flushes here.
4224
	 */
4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246
	obj_priv = to_intel_bo(obj);
	args->busy = obj_priv->active;
	if (args->busy) {
		/* Unconditionally flush objects, even when the gpu still uses this
		 * object. Userspace calling this function indicates that it wants to
		 * use this buffer rather sooner than later, so issuing the required
		 * flush earlier is beneficial.
		 */
		if (obj->write_domain) {
			i915_gem_flush(dev, 0, obj->write_domain);
			(void)i915_add_request(dev, file_priv, obj->write_domain, obj_priv->ring);
		}

		/* Update the active list for the hardware's current position.
		 * Otherwise this only updates on a delayed timer or when irqs
		 * are actually unmasked, and our working set ends up being
		 * larger than required.
		 */
		i915_gem_retire_requests_ring(dev, obj_priv->ring);

		args->busy = obj_priv->active;
	}
4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259

	drm_gem_object_unreference(obj);
	mutex_unlock(&dev->struct_mutex);
	return 0;
}

int
i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
    return i915_gem_ring_throttle(dev, file_priv);
}

4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279
int
i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
	struct drm_i915_gem_madvise *args = data;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;

	switch (args->madv) {
	case I915_MADV_DONTNEED:
	case I915_MADV_WILLNEED:
	    break;
	default:
	    return -EINVAL;
	}

	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	if (obj == NULL) {
		DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
			  args->handle);
4280
		return -ENOENT;
4281 4282 4283
	}

	mutex_lock(&dev->struct_mutex);
4284
	obj_priv = to_intel_bo(obj);
4285 4286 4287 4288 4289 4290 4291 4292 4293

	if (obj_priv->pin_count) {
		drm_gem_object_unreference(obj);
		mutex_unlock(&dev->struct_mutex);

		DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
		return -EINVAL;
	}

C
Chris Wilson 已提交
4294 4295
	if (obj_priv->madv != __I915_MADV_PURGED)
		obj_priv->madv = args->madv;
4296

4297 4298 4299 4300 4301
	/* if the object is no longer bound, discard its backing storage */
	if (i915_gem_object_is_purgeable(obj_priv) &&
	    obj_priv->gtt_space == NULL)
		i915_gem_object_truncate(obj);

C
Chris Wilson 已提交
4302 4303
	args->retained = obj_priv->madv != __I915_MADV_PURGED;

4304 4305 4306 4307 4308 4309
	drm_gem_object_unreference(obj);
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

4310 4311 4312
struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
					      size_t size)
{
4313
	struct drm_i915_gem_object *obj;
4314

4315 4316 4317
	obj = kzalloc(sizeof(*obj), GFP_KERNEL);
	if (obj == NULL)
		return NULL;
4318

4319 4320 4321 4322
	if (drm_gem_object_init(dev, &obj->base, size) != 0) {
		kfree(obj);
		return NULL;
	}
4323

4324 4325
	obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4326

4327
	obj->agp_type = AGP_USER_MEMORY;
4328
	obj->base.driver_private = NULL;
4329 4330 4331 4332
	obj->fence_reg = I915_FENCE_REG_NONE;
	INIT_LIST_HEAD(&obj->list);
	INIT_LIST_HEAD(&obj->gpu_write_list);
	obj->madv = I915_MADV_WILLNEED;
4333

4334 4335 4336 4337 4338 4339 4340 4341
	trace_i915_gem_object_create(&obj->base);

	return &obj->base;
}

int i915_gem_init_object(struct drm_gem_object *obj)
{
	BUG();
4342

4343 4344 4345
	return 0;
}

4346
static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4347
{
4348
	struct drm_device *dev = obj->dev;
4349
	drm_i915_private_t *dev_priv = dev->dev_private;
4350
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4351
	int ret;
4352

4353 4354 4355 4356 4357 4358
	ret = i915_gem_object_unbind(obj);
	if (ret == -ERESTARTSYS) {
		list_move(&obj_priv->list,
			  &dev_priv->mm.deferred_free_list);
		return;
	}
4359

4360 4361
	if (obj_priv->mmap_offset)
		i915_gem_free_mmap_offset(obj);
4362

4363 4364
	drm_gem_object_release(obj);

4365
	kfree(obj_priv->page_cpu_valid);
4366
	kfree(obj_priv->bit_17);
4367
	kfree(obj_priv);
4368 4369
}

4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385
void i915_gem_free_object(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);

	trace_i915_gem_object_destroy(obj);

	while (obj_priv->pin_count > 0)
		i915_gem_object_unpin(obj);

	if (obj_priv->phys_obj)
		i915_gem_detach_phys_object(dev, obj);

	i915_gem_free_object_tail(obj);
}

4386 4387 4388 4389 4390
int
i915_gem_idle(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int ret;
4391

4392
	mutex_lock(&dev->struct_mutex);
C
Chris Wilson 已提交
4393

4394
	if (dev_priv->mm.suspended ||
4395 4396 4397
			(dev_priv->render_ring.gem_object == NULL) ||
			(HAS_BSD(dev) &&
			 dev_priv->bsd_ring.gem_object == NULL)) {
4398 4399
		mutex_unlock(&dev->struct_mutex);
		return 0;
4400 4401
	}

4402
	ret = i915_gpu_idle(dev);
4403 4404
	if (ret) {
		mutex_unlock(&dev->struct_mutex);
4405
		return ret;
4406
	}
4407

4408 4409
	/* Under UMS, be paranoid and evict. */
	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4410
		ret = i915_gem_evict_inactive(dev);
4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424
		if (ret) {
			mutex_unlock(&dev->struct_mutex);
			return ret;
		}
	}

	/* Hack!  Don't let anybody do execbuf while we don't control the chip.
	 * We need to replace this with a semaphore, or something.
	 * And not confound mm.suspended!
	 */
	dev_priv->mm.suspended = 1;
	del_timer(&dev_priv->hangcheck_timer);

	i915_kernel_lost_context(dev);
4425
	i915_gem_cleanup_ringbuffer(dev);
4426

4427 4428
	mutex_unlock(&dev->struct_mutex);

4429 4430 4431
	/* Cancel the retire work handler, which should be idle now. */
	cancel_delayed_work_sync(&dev_priv->mm.retire_work);

4432 4433 4434
	return 0;
}

4435 4436 4437 4438
/*
 * 965+ support PIPE_CONTROL commands, which provide finer grained control
 * over cache flushing.
 */
4439
static int
4440 4441 4442 4443 4444 4445 4446
i915_gem_init_pipe_control(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;
	int ret;

4447
	obj = i915_gem_alloc_object(dev, 4096);
4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477
	if (obj == NULL) {
		DRM_ERROR("Failed to allocate seqno page\n");
		ret = -ENOMEM;
		goto err;
	}
	obj_priv = to_intel_bo(obj);
	obj_priv->agp_type = AGP_USER_CACHED_MEMORY;

	ret = i915_gem_object_pin(obj, 4096);
	if (ret)
		goto err_unref;

	dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
	dev_priv->seqno_page =  kmap(obj_priv->pages[0]);
	if (dev_priv->seqno_page == NULL)
		goto err_unpin;

	dev_priv->seqno_obj = obj;
	memset(dev_priv->seqno_page, 0, PAGE_SIZE);

	return 0;

err_unpin:
	i915_gem_object_unpin(obj);
err_unref:
	drm_gem_object_unreference(obj);
err:
	return ret;
}

4478 4479

static void
4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493
i915_gem_cleanup_pipe_control(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;

	obj = dev_priv->seqno_obj;
	obj_priv = to_intel_bo(obj);
	kunmap(obj_priv->pages[0]);
	i915_gem_object_unpin(obj);
	drm_gem_object_unreference(obj);
	dev_priv->seqno_obj = NULL;

	dev_priv->seqno_page = NULL;
4494 4495
}

4496 4497 4498 4499 4500
int
i915_gem_init_ringbuffer(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int ret;
4501

4502
	dev_priv->render_ring = render_ring;
4503

4504 4505 4506 4507 4508 4509
	if (!I915_NEED_GFX_HWS(dev)) {
		dev_priv->render_ring.status_page.page_addr
			= dev_priv->status_page_dmah->vaddr;
		memset(dev_priv->render_ring.status_page.page_addr,
				0, PAGE_SIZE);
	}
4510

4511 4512 4513 4514 4515
	if (HAS_PIPE_CONTROL(dev)) {
		ret = i915_gem_init_pipe_control(dev);
		if (ret)
			return ret;
	}
4516

4517
	ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4518 4519 4520 4521
	if (ret)
		goto cleanup_pipe_control;

	if (HAS_BSD(dev)) {
4522 4523
		dev_priv->bsd_ring = bsd_ring;
		ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4524 4525
		if (ret)
			goto cleanup_render_ring;
4526
	}
4527

4528 4529
	dev_priv->next_seqno = 1;

4530 4531 4532 4533 4534 4535 4536
	return 0;

cleanup_render_ring:
	intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
cleanup_pipe_control:
	if (HAS_PIPE_CONTROL(dev))
		i915_gem_cleanup_pipe_control(dev);
4537 4538 4539 4540 4541 4542 4543 4544 4545
	return ret;
}

void
i915_gem_cleanup_ringbuffer(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;

	intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4546 4547
	if (HAS_BSD(dev))
		intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4548 4549 4550 4551
	if (HAS_PIPE_CONTROL(dev))
		i915_gem_cleanup_pipe_control(dev);
}

4552 4553 4554 4555 4556 4557 4558
int
i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int ret;

J
Jesse Barnes 已提交
4559 4560 4561
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return 0;

4562
	if (atomic_read(&dev_priv->mm.wedged)) {
4563
		DRM_ERROR("Reenabling wedged hardware, good luck\n");
4564
		atomic_set(&dev_priv->mm.wedged, 0);
4565 4566 4567
	}

	mutex_lock(&dev->struct_mutex);
4568 4569 4570
	dev_priv->mm.suspended = 0;

	ret = i915_gem_init_ringbuffer(dev);
4571 4572
	if (ret != 0) {
		mutex_unlock(&dev->struct_mutex);
4573
		return ret;
4574
	}
4575

4576
	spin_lock(&dev_priv->mm.active_list_lock);
4577
	BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4578
	BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4579 4580
	spin_unlock(&dev_priv->mm.active_list_lock);

4581 4582
	BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
	BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4583
	BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4584
	BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4585
	mutex_unlock(&dev->struct_mutex);
4586

4587 4588 4589
	ret = drm_irq_install(dev);
	if (ret)
		goto cleanup_ringbuffer;
4590

4591
	return 0;
4592 4593 4594 4595 4596 4597 4598 4599

cleanup_ringbuffer:
	mutex_lock(&dev->struct_mutex);
	i915_gem_cleanup_ringbuffer(dev);
	dev_priv->mm.suspended = 1;
	mutex_unlock(&dev->struct_mutex);

	return ret;
4600 4601 4602 4603 4604 4605
}

int
i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
J
Jesse Barnes 已提交
4606 4607 4608
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return 0;

4609
	drm_irq_uninstall(dev);
4610
	return i915_gem_idle(dev);
4611 4612 4613 4614 4615 4616 4617
}

void
i915_gem_lastclose(struct drm_device *dev)
{
	int ret;

4618 4619 4620
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return;

4621 4622 4623
	ret = i915_gem_idle(dev);
	if (ret)
		DRM_ERROR("failed to idle hardware: %d\n", ret);
4624 4625 4626 4627 4628
}

void
i915_gem_load(struct drm_device *dev)
{
4629
	int i;
4630 4631
	drm_i915_private_t *dev_priv = dev->dev_private;

4632
	spin_lock_init(&dev_priv->mm.active_list_lock);
4633
	INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4634
	INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4635
	INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4636
	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4637
	INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4638 4639
	INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
	INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4640 4641 4642 4643
	if (HAS_BSD(dev)) {
		INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
		INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
	}
4644 4645
	for (i = 0; i < 16; i++)
		INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4646 4647
	INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
			  i915_gem_retire_work_handler);
4648 4649 4650 4651
	spin_lock(&shrink_list_lock);
	list_add(&dev_priv->mm.shrink_list, &shrink_list);
	spin_unlock(&shrink_list_lock);

4652 4653 4654 4655 4656 4657 4658 4659 4660 4661
	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
	if (IS_GEN3(dev)) {
		u32 tmp = I915_READ(MI_ARB_STATE);
		if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
			/* arb state is a masked write, so set bit + bit in mask */
			tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
			I915_WRITE(MI_ARB_STATE, tmp);
		}
	}

4662
	/* Old X drivers will take 0-2 for front, back, depth buffers */
4663 4664
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		dev_priv->fence_reg_start = 3;
4665

4666
	if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4667 4668 4669 4670
		dev_priv->num_fence_regs = 16;
	else
		dev_priv->num_fence_regs = 8;

4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681
	/* Initialize fence registers to zero */
	if (IS_I965G(dev)) {
		for (i = 0; i < 16; i++)
			I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
	} else {
		for (i = 0; i < 8; i++)
			I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
			for (i = 0; i < 8; i++)
				I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
	}
4682
	i915_gem_detect_bit_6_swizzle(dev);
4683
	init_waitqueue_head(&dev_priv->pending_flip_queue);
4684
}
4685 4686 4687 4688 4689 4690

/*
 * Create a physically contiguous memory object for this object
 * e.g. for cursor + overlay regs
 */
int i915_gem_init_phys_object(struct drm_device *dev,
4691
			      int id, int size, int align)
4692 4693 4694 4695 4696 4697 4698 4699
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_phys_object *phys_obj;
	int ret;

	if (dev_priv->mm.phys_objs[id - 1] || !size)
		return 0;

4700
	phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4701 4702 4703 4704 4705
	if (!phys_obj)
		return -ENOMEM;

	phys_obj->id = id;

4706
	phys_obj->handle = drm_pci_alloc(dev, size, align);
4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718
	if (!phys_obj->handle) {
		ret = -ENOMEM;
		goto kfree_obj;
	}
#ifdef CONFIG_X86
	set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
#endif

	dev_priv->mm.phys_objs[id - 1] = phys_obj;

	return 0;
kfree_obj:
4719
	kfree(phys_obj);
4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747
	return ret;
}

void i915_gem_free_phys_object(struct drm_device *dev, int id)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_phys_object *phys_obj;

	if (!dev_priv->mm.phys_objs[id - 1])
		return;

	phys_obj = dev_priv->mm.phys_objs[id - 1];
	if (phys_obj->cur_obj) {
		i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
	}

#ifdef CONFIG_X86
	set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
#endif
	drm_pci_free(dev, phys_obj->handle);
	kfree(phys_obj);
	dev_priv->mm.phys_objs[id - 1] = NULL;
}

void i915_gem_free_all_phys_object(struct drm_device *dev)
{
	int i;

4748
	for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759
		i915_gem_free_phys_object(dev, i);
}

void i915_gem_detach_phys_object(struct drm_device *dev,
				 struct drm_gem_object *obj)
{
	struct drm_i915_gem_object *obj_priv;
	int i;
	int ret;
	int page_count;

4760
	obj_priv = to_intel_bo(obj);
4761 4762 4763
	if (!obj_priv->phys_obj)
		return;

4764
	ret = i915_gem_object_get_pages(obj, 0);
4765 4766 4767 4768 4769 4770
	if (ret)
		goto out;

	page_count = obj->size / PAGE_SIZE;

	for (i = 0; i < page_count; i++) {
4771
		char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4772 4773 4774 4775 4776
		char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);

		memcpy(dst, src, PAGE_SIZE);
		kunmap_atomic(dst, KM_USER0);
	}
4777
	drm_clflush_pages(obj_priv->pages, page_count);
4778
	drm_agp_chipset_flush(dev);
4779 4780

	i915_gem_object_put_pages(obj);
4781 4782 4783 4784 4785 4786 4787
out:
	obj_priv->phys_obj->cur_obj = NULL;
	obj_priv->phys_obj = NULL;
}

int
i915_gem_attach_phys_object(struct drm_device *dev,
4788 4789 4790
			    struct drm_gem_object *obj,
			    int id,
			    int align)
4791 4792 4793 4794 4795 4796 4797 4798 4799 4800
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj_priv;
	int ret = 0;
	int page_count;
	int i;

	if (id > I915_MAX_PHYS_OBJECT)
		return -EINVAL;

4801
	obj_priv = to_intel_bo(obj);
4802 4803 4804 4805 4806 4807 4808 4809 4810 4811

	if (obj_priv->phys_obj) {
		if (obj_priv->phys_obj->id == id)
			return 0;
		i915_gem_detach_phys_object(dev, obj);
	}

	/* create a new object */
	if (!dev_priv->mm.phys_objs[id - 1]) {
		ret = i915_gem_init_phys_object(dev, id,
4812
						obj->size, align);
4813
		if (ret) {
4814
			DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4815 4816 4817 4818 4819 4820 4821 4822
			goto out;
		}
	}

	/* bind to the object */
	obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
	obj_priv->phys_obj->cur_obj = obj;

4823
	ret = i915_gem_object_get_pages(obj, 0);
4824 4825 4826 4827 4828 4829 4830 4831
	if (ret) {
		DRM_ERROR("failed to get page list\n");
		goto out;
	}

	page_count = obj->size / PAGE_SIZE;

	for (i = 0; i < page_count; i++) {
4832
		char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4833 4834 4835 4836 4837 4838
		char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);

		memcpy(dst, src, PAGE_SIZE);
		kunmap_atomic(src, KM_USER0);
	}

4839 4840
	i915_gem_object_put_pages(obj);

4841 4842 4843 4844 4845 4846 4847 4848 4849 4850
	return 0;
out:
	return ret;
}

static int
i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
		     struct drm_i915_gem_pwrite *args,
		     struct drm_file *file_priv)
{
4851
	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4852 4853 4854 4855 4856 4857 4858
	void *obj_addr;
	int ret;
	char __user *user_data;

	user_data = (char __user *) (uintptr_t) args->data_ptr;
	obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;

4859
	DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4860 4861 4862 4863 4864 4865 4866
	ret = copy_from_user(obj_addr, user_data, args->size);
	if (ret)
		return -EFAULT;

	drm_agp_chipset_flush(dev);
	return 0;
}
4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880

void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
{
	struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;

	/* Clean up our request list when the client is going away, so that
	 * later retire_requests won't dereference our soon-to-be-gone
	 * file_priv.
	 */
	mutex_lock(&dev->struct_mutex);
	while (!list_empty(&i915_file_priv->mm.request_list))
		list_del_init(i915_file_priv->mm.request_list.next);
	mutex_unlock(&dev->struct_mutex);
}
4881

4882 4883 4884 4885 4886 4887 4888 4889
static int
i915_gpu_is_active(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int lists_empty;

	spin_lock(&dev_priv->mm.active_list_lock);
	lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4890
		      list_empty(&dev_priv->render_ring.active_list);
4891 4892
	if (HAS_BSD(dev))
		lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
4893 4894 4895 4896 4897
	spin_unlock(&dev_priv->mm.active_list_lock);

	return !lists_empty;
}

4898
static int
4899
i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926
{
	drm_i915_private_t *dev_priv, *next_dev;
	struct drm_i915_gem_object *obj_priv, *next_obj;
	int cnt = 0;
	int would_deadlock = 1;

	/* "fast-path" to count number of available objects */
	if (nr_to_scan == 0) {
		spin_lock(&shrink_list_lock);
		list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
			struct drm_device *dev = dev_priv->dev;

			if (mutex_trylock(&dev->struct_mutex)) {
				list_for_each_entry(obj_priv,
						    &dev_priv->mm.inactive_list,
						    list)
					cnt++;
				mutex_unlock(&dev->struct_mutex);
			}
		}
		spin_unlock(&shrink_list_lock);

		return (cnt / 100) * sysctl_vfs_cache_pressure;
	}

	spin_lock(&shrink_list_lock);

4927
rescan:
4928 4929 4930 4931 4932 4933 4934 4935 4936
	/* first scan for clean buffers */
	list_for_each_entry_safe(dev_priv, next_dev,
				 &shrink_list, mm.shrink_list) {
		struct drm_device *dev = dev_priv->dev;

		if (! mutex_trylock(&dev->struct_mutex))
			continue;

		spin_unlock(&shrink_list_lock);
4937
		i915_gem_retire_requests(dev);
4938 4939 4940 4941 4942

		list_for_each_entry_safe(obj_priv, next_obj,
					 &dev_priv->mm.inactive_list,
					 list) {
			if (i915_gem_object_is_purgeable(obj_priv)) {
4943
				i915_gem_object_unbind(&obj_priv->base);
4944 4945 4946 4947 4948 4949 4950 4951
				if (--nr_to_scan <= 0)
					break;
			}
		}

		spin_lock(&shrink_list_lock);
		mutex_unlock(&dev->struct_mutex);

4952 4953
		would_deadlock = 0;

4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971
		if (nr_to_scan <= 0)
			break;
	}

	/* second pass, evict/count anything still on the inactive list */
	list_for_each_entry_safe(dev_priv, next_dev,
				 &shrink_list, mm.shrink_list) {
		struct drm_device *dev = dev_priv->dev;

		if (! mutex_trylock(&dev->struct_mutex))
			continue;

		spin_unlock(&shrink_list_lock);

		list_for_each_entry_safe(obj_priv, next_obj,
					 &dev_priv->mm.inactive_list,
					 list) {
			if (nr_to_scan > 0) {
4972
				i915_gem_object_unbind(&obj_priv->base);
4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983
				nr_to_scan--;
			} else
				cnt++;
		}

		spin_lock(&shrink_list_lock);
		mutex_unlock(&dev->struct_mutex);

		would_deadlock = 0;
	}

4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013
	if (nr_to_scan) {
		int active = 0;

		/*
		 * We are desperate for pages, so as a last resort, wait
		 * for the GPU to finish and discard whatever we can.
		 * This has a dramatic impact to reduce the number of
		 * OOM-killer events whilst running the GPU aggressively.
		 */
		list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
			struct drm_device *dev = dev_priv->dev;

			if (!mutex_trylock(&dev->struct_mutex))
				continue;

			spin_unlock(&shrink_list_lock);

			if (i915_gpu_is_active(dev)) {
				i915_gpu_idle(dev);
				active++;
			}

			spin_lock(&shrink_list_lock);
			mutex_unlock(&dev->struct_mutex);
		}

		if (active)
			goto rescan;
	}

5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039
	spin_unlock(&shrink_list_lock);

	if (would_deadlock)
		return -1;
	else if (cnt > 0)
		return (cnt / 100) * sysctl_vfs_cache_pressure;
	else
		return 0;
}

static struct shrinker shrinker = {
	.shrink = i915_gem_shrink,
	.seeks = DEFAULT_SEEKS,
};

__init void
i915_gem_shrinker_init(void)
{
    register_shrinker(&shrinker);
}

__exit void
i915_gem_shrinker_exit(void)
{
    unregister_shrinker(&shrinker);
}