mac.c 46.8 KB
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/*******************************************************************************

  Intel PRO/1000 Linux driver
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  Copyright(c) 1999 - 2012 Intel Corporation.
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  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#include "e1000.h"

/**
 *  e1000e_get_bus_info_pcie - Get PCIe bus information
 *  @hw: pointer to the HW structure
 *
 *  Determines and stores the system bus information for a particular
 *  network interface.  The following bus information is determined and stored:
 *  bus speed, bus width, type (PCIe), and PCIe function.
 **/
s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
{
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	struct e1000_mac_info *mac = &hw->mac;
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	struct e1000_bus_info *bus = &hw->bus;
	struct e1000_adapter *adapter = hw->adapter;
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	u16 pcie_link_status, cap_offset;
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	cap_offset = adapter->pdev->pcie_cap;
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	if (!cap_offset) {
		bus->width = e1000_bus_width_unknown;
	} else {
		pci_read_config_word(adapter->pdev,
				     cap_offset + PCIE_LINK_STATUS,
				     &pcie_link_status);
		bus->width = (enum e1000_bus_width)((pcie_link_status &
						     PCIE_LINK_WIDTH_MASK) >>
						    PCIE_LINK_WIDTH_SHIFT);
	}

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	mac->ops.set_lan_id(hw);
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	return 0;
}

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/**
 *  e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
 *
 *  @hw: pointer to the HW structure
 *
 *  Determines the LAN function id by reading memory-mapped registers
 *  and swaps the port value if requested.
 **/
void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
{
	struct e1000_bus_info *bus = &hw->bus;
	u32 reg;

	/*
	 * The status register reports the correct function number
	 * for the device regardless of function swap state.
	 */
	reg = er32(STATUS);
	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
}

/**
 *  e1000_set_lan_id_single_port - Set LAN id for a single port device
 *  @hw: pointer to the HW structure
 *
 *  Sets the LAN function id to zero for a single port device.
 **/
void e1000_set_lan_id_single_port(struct e1000_hw *hw)
{
	struct e1000_bus_info *bus = &hw->bus;

	bus->func = 0;
}

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/**
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 *  e1000_clear_vfta_generic - Clear VLAN filter table
 *  @hw: pointer to the HW structure
 *
 *  Clears the register array which contains the VLAN filter table by
 *  setting all the values to 0.
 **/
void e1000_clear_vfta_generic(struct e1000_hw *hw)
{
	u32 offset;

	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
		e1e_flush();
	}
}

/**
 *  e1000_write_vfta_generic - Write value to VLAN filter table
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 *  @hw: pointer to the HW structure
 *  @offset: register offset in VLAN filter table
 *  @value: register value written to VLAN filter table
 *
 *  Writes value at the given offset in the register array which stores
 *  the VLAN filter table.
 **/
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void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
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{
	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
	e1e_flush();
}

/**
 *  e1000e_init_rx_addrs - Initialize receive address's
 *  @hw: pointer to the HW structure
 *  @rar_count: receive address registers
 *
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 *  Setup the receive address registers by setting the base receive address
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 *  register to the devices MAC address and clearing all the other receive
 *  address registers to 0.
 **/
void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
{
	u32 i;
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	u8 mac_addr[ETH_ALEN] = { 0 };
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	/* Setup the receive address */
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	e_dbg("Programming MAC Address into RAR[0]\n");
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	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
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	/* Zero out the other (rar_entry_count - 1) receive addresses */
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	e_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
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	for (i = 1; i < rar_count; i++)
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		hw->mac.ops.rar_set(hw, mac_addr, i);
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}

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/**
 *  e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
 *  @hw: pointer to the HW structure
 *
 *  Checks the nvm for an alternate MAC address.  An alternate MAC address
 *  can be setup by pre-boot software and must be treated like a permanent
 *  address and must override the actual permanent MAC address. If an
 *  alternate MAC address is found it is programmed into RAR0, replacing
 *  the permanent address that was installed into RAR0 by the Si on reset.
 *  This function will return SUCCESS unless it encounters an error while
 *  reading the EEPROM.
 **/
s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
{
	u32 i;
	s32 ret_val = 0;
	u16 offset, nvm_alt_mac_addr_offset, nvm_data;
	u8 alt_mac_addr[ETH_ALEN];

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	ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);
	if (ret_val)
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		return ret_val;
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	/* not supported on 82573 */
	if (hw->mac.type == e1000_82573)
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		return 0;
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	ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
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				 &nvm_alt_mac_addr_offset);
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	if (ret_val) {
		e_dbg("NVM Read Error\n");
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		return ret_val;
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	}

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	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
	    (nvm_alt_mac_addr_offset == 0x0000))
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		/* There is no Alternate MAC Address */
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		return 0;
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	if (hw->bus.func == E1000_FUNC_1)
		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
	for (i = 0; i < ETH_ALEN; i += 2) {
		offset = nvm_alt_mac_addr_offset + (i >> 1);
		ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
		if (ret_val) {
			e_dbg("NVM Read Error\n");
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			return ret_val;
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		}

		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
	}

	/* if multicast bit is set, the alternate address will not be used */
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	if (is_multicast_ether_addr(alt_mac_addr)) {
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		e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
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		return 0;
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	}

	/*
	 * We have a valid alternate MAC address, and we want to treat it the
	 * same as the normal permanent MAC address stored by the HW into the
	 * RAR. Do this by mapping this address into RAR0.
	 */
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	hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
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	return 0;
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}

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/**
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 *  e1000e_rar_set_generic - Set receive address register
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 *  @hw: pointer to the HW structure
 *  @addr: pointer to the receive address
 *  @index: receive address array register
 *
 *  Sets the receive address array register at index to the address passed
 *  in by addr.
 **/
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void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
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{
	u32 rar_low, rar_high;

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	/*
	 * HW expects these in little endian so we reverse the byte order
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	 * from network order (big endian) to little endian
	 */
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	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
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	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
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	/* If MAC address zero, no need to set the AV bit */
	if (rar_low || rar_high)
		rar_high |= E1000_RAH_AV;
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	/*
	 * Some bridges will combine consecutive 32-bit writes into
	 * a single burst write, which will malfunction on some parts.
	 * The flushes avoid this.
	 */
	ew32(RAL(index), rar_low);
	e1e_flush();
	ew32(RAH(index), rar_high);
	e1e_flush();
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}

/**
 *  e1000_hash_mc_addr - Generate a multicast hash value
 *  @hw: pointer to the HW structure
 *  @mc_addr: pointer to a multicast address
 *
 *  Generates a multicast address hash value which is used to determine
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 *  the multicast filter table array address and new table value.
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 **/
static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
{
	u32 hash_value, hash_mask;
	u8 bit_shift = 0;

	/* Register count multiplied by bits per register */
	hash_mask = (hw->mac.mta_reg_count * 32) - 1;

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	/*
	 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
	 * where 0xFF would still fall within the hash mask.
	 */
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	while (hash_mask >> bit_shift != 0xFF)
		bit_shift++;

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	/*
	 * The portion of the address that is used for the hash table
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	 * is determined by the mc_filter_type setting.
	 * The algorithm is such that there is a total of 8 bits of shifting.
	 * The bit_shift for a mc_filter_type of 0 represents the number of
	 * left-shifts where the MSB of mc_addr[5] would still fall within
	 * the hash_mask.  Case 0 does this exactly.  Since there are a total
	 * of 8 bits of shifting, then mc_addr[4] will shift right the
	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the
	 * cases are a variation of this algorithm...essentially raising the
	 * number of bits to shift mc_addr[5] left, while still keeping the
	 * 8-bit shifting total.
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	 *
	 * For example, given the following Destination MAC Address and an
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	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
	 * we can see that the bit_shift for case 0 is 4.  These are the hash
	 * values resulting from each mc_filter_type...
	 * [0] [1] [2] [3] [4] [5]
	 * 01  AA  00  12  34  56
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	 * LSB           MSB
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	 *
	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
	 */
	switch (hw->mac.mc_filter_type) {
	default:
	case 0:
		break;
	case 1:
		bit_shift += 1;
		break;
	case 2:
		bit_shift += 2;
		break;
	case 3:
		bit_shift += 4;
		break;
	}

	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
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				   (((u16)mc_addr[5]) << bit_shift)));
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	return hash_value;
}

/**
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 *  e1000e_update_mc_addr_list_generic - Update Multicast addresses
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 *  @hw: pointer to the HW structure
 *  @mc_addr_list: array of multicast addresses to program
 *  @mc_addr_count: number of multicast addresses to program
 *
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 *  Updates entire Multicast Table Array.
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 *  The caller must have a packed mc_addr_list of multicast addresses.
 **/
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void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
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					u8 *mc_addr_list, u32 mc_addr_count)
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{
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	u32 hash_value, hash_bit, hash_reg;
	int i;
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	/* clear mta_shadow */
	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
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	/* update mta_shadow from mc_addr_list */
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	for (i = 0; (u32)i < mc_addr_count; i++) {
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		hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
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		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
		hash_bit = hash_value & 0x1F;

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		hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
		mc_addr_list += (ETH_ALEN);
	}
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	/* replace the entire MTA table */
	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
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	e1e_flush();
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}

/**
 *  e1000e_clear_hw_cntrs_base - Clear base hardware counters
 *  @hw: pointer to the HW structure
 *
 *  Clears the base hardware counters by reading the counter registers.
 **/
void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
{
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	er32(CRCERRS);
	er32(SYMERRS);
	er32(MPC);
	er32(SCC);
	er32(ECOL);
	er32(MCC);
	er32(LATECOL);
	er32(COLC);
	er32(DC);
	er32(SEC);
	er32(RLEC);
	er32(XONRXC);
	er32(XONTXC);
	er32(XOFFRXC);
	er32(XOFFTXC);
	er32(FCRUC);
	er32(GPRC);
	er32(BPRC);
	er32(MPRC);
	er32(GPTC);
	er32(GORCL);
	er32(GORCH);
	er32(GOTCL);
	er32(GOTCH);
	er32(RNBC);
	er32(RUC);
	er32(RFC);
	er32(ROC);
	er32(RJC);
	er32(TORL);
	er32(TORH);
	er32(TOTL);
	er32(TOTH);
	er32(TPR);
	er32(TPT);
	er32(MPTC);
	er32(BPTC);
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}

/**
 *  e1000e_check_for_copper_link - Check for link (Copper)
 *  @hw: pointer to the HW structure
 *
 *  Checks to see of the link status of the hardware has changed.  If a
 *  change in link status has been detected, then we read the PHY registers
 *  to get the current speed/duplex if link exists.
 **/
s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
{
	struct e1000_mac_info *mac = &hw->mac;
	s32 ret_val;
	bool link;

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	/*
	 * We only want to go out to the PHY registers to see if Auto-Neg
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	 * has completed and/or if our link status has changed.  The
	 * get_link_status flag is set upon receiving a Link Status
	 * Change or Rx Sequence Error interrupt.
	 */
	if (!mac->get_link_status)
		return 0;

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	/*
	 * First we want to see if the MII Status Register reports
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	 * link.  If so, then we want to get the current speed/duplex
	 * of the PHY.
	 */
	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
	if (ret_val)
		return ret_val;

	if (!link)
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		return 0;	/* No link detected */
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	mac->get_link_status = false;
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	/*
	 * Check if there was DownShift, must be checked
	 * immediately after link-up
	 */
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	e1000e_check_downshift(hw);

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	/*
	 * If we are forcing speed/duplex, then we simply return since
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	 * we have already determined whether we have link or not.
	 */
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	if (!mac->autoneg)
		return -E1000_ERR_CONFIG;
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	/*
	 * Auto-Neg is enabled.  Auto Speed Detection takes care
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	 * of MAC speed/duplex configuration.  So we only need to
	 * configure Collision Distance in the MAC.
	 */
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	mac->ops.config_collision_dist(hw);
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	/*
	 * Configure Flow Control now that Auto-Neg has completed.
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	 * First, we need to restore the desired flow control
	 * settings because we may have had to re-autoneg with a
	 * different link partner.
	 */
	ret_val = e1000e_config_fc_after_link_up(hw);
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	if (ret_val)
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		e_dbg("Error configuring flow control\n");
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	return ret_val;
}

/**
 *  e1000e_check_for_fiber_link - Check for link (Fiber)
 *  @hw: pointer to the HW structure
 *
 *  Checks for link up on the hardware.  If link is not up and we have
 *  a signal, then we need to force link up.
 **/
s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
{
	struct e1000_mac_info *mac = &hw->mac;
	u32 rxcw;
	u32 ctrl;
	u32 status;
	s32 ret_val;

	ctrl = er32(CTRL);
	status = er32(STATUS);
	rxcw = er32(RXCW);

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	/*
	 * If we don't have link (auto-negotiation failed or link partner
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	 * cannot auto-negotiate), the cable is plugged in (we have signal),
	 * and our link partner is not trying to auto-negotiate with us (we
	 * are receiving idles or data), we need to force link up. We also
	 * need to give auto-negotiation time to complete, in case the cable
	 * was just plugged in. The autoneg_failed flag does this.
	 */
	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
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	if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
	    !(rxcw & E1000_RXCW_C)) {
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		if (!mac->autoneg_failed) {
			mac->autoneg_failed = true;
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			return 0;
		}
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		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
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		/* Disable auto-negotiation in the TXCW register */
		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));

		/* Force link-up and also force full-duplex. */
		ctrl = er32(CTRL);
		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
		ew32(CTRL, ctrl);

		/* Configure Flow Control after forcing link up. */
		ret_val = e1000e_config_fc_after_link_up(hw);
		if (ret_val) {
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			e_dbg("Error configuring flow control\n");
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			return ret_val;
		}
	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
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		/*
		 * If we are forcing link and we are receiving /C/ ordered
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		 * sets, re-enable auto-negotiation in the TXCW register
		 * and disable forced link in the Device Control register
		 * in an attempt to auto-negotiate with our link partner.
		 */
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		e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
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		ew32(TXCW, mac->txcw);
		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));

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		mac->serdes_has_link = true;
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	}

	return 0;
}

/**
 *  e1000e_check_for_serdes_link - Check for link (Serdes)
 *  @hw: pointer to the HW structure
 *
 *  Checks for link up on the hardware.  If link is not up and we have
 *  a signal, then we need to force link up.
 **/
s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
{
	struct e1000_mac_info *mac = &hw->mac;
	u32 rxcw;
	u32 ctrl;
	u32 status;
	s32 ret_val;

	ctrl = er32(CTRL);
	status = er32(STATUS);
	rxcw = er32(RXCW);

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	/*
	 * If we don't have link (auto-negotiation failed or link partner
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	 * cannot auto-negotiate), and our link partner is not trying to
	 * auto-negotiate with us (we are receiving idles or data),
	 * we need to force link up. We also need to give auto-negotiation
	 * time to complete.
	 */
	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
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	if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
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		if (!mac->autoneg_failed) {
			mac->autoneg_failed = true;
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			return 0;
		}
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		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
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		/* Disable auto-negotiation in the TXCW register */
		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));

		/* Force link-up and also force full-duplex. */
		ctrl = er32(CTRL);
		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
		ew32(CTRL, ctrl);

		/* Configure Flow Control after forcing link up. */
		ret_val = e1000e_config_fc_after_link_up(hw);
		if (ret_val) {
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			e_dbg("Error configuring flow control\n");
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			return ret_val;
		}
	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
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		/*
		 * If we are forcing link and we are receiving /C/ ordered
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		 * sets, re-enable auto-negotiation in the TXCW register
		 * and disable forced link in the Device Control register
		 * in an attempt to auto-negotiate with our link partner.
		 */
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		e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
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		ew32(TXCW, mac->txcw);
		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));

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		mac->serdes_has_link = true;
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	} else if (!(E1000_TXCW_ANE & er32(TXCW))) {
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		/*
		 * If we force link for non-auto-negotiation switch, check
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		 * link status based on MAC synchronization for internal
		 * serdes media type.
		 */
		/* SYNCH bit and IV bit are sticky. */
		udelay(10);
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		rxcw = er32(RXCW);
		if (rxcw & E1000_RXCW_SYNCH) {
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			if (!(rxcw & E1000_RXCW_IV)) {
620
				mac->serdes_has_link = true;
621
				e_dbg("SERDES: Link up - forced.\n");
622 623
			}
		} else {
624
			mac->serdes_has_link = false;
625
			e_dbg("SERDES: Link down - force failed.\n");
626 627 628 629 630
		}
	}

	if (E1000_TXCW_ANE & er32(TXCW)) {
		status = er32(STATUS);
631
		if (status & E1000_STATUS_LU) {
632
			/* SYNCH bit and IV bit are sticky, so reread rxcw. */
633 634 635 636 637
			udelay(10);
			rxcw = er32(RXCW);
			if (rxcw & E1000_RXCW_SYNCH) {
				if (!(rxcw & E1000_RXCW_IV)) {
					mac->serdes_has_link = true;
638
					e_dbg("SERDES: Link up - autoneg completed successfully.\n");
639 640
				} else {
					mac->serdes_has_link = false;
641
					e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n");
642 643 644
				}
			} else {
				mac->serdes_has_link = false;
645
				e_dbg("SERDES: Link down - no sync.\n");
646 647 648
			}
		} else {
			mac->serdes_has_link = false;
649
			e_dbg("SERDES: Link down - autoneg failed\n");
650
		}
651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667
	}

	return 0;
}

/**
 *  e1000_set_default_fc_generic - Set flow control default values
 *  @hw: pointer to the HW structure
 *
 *  Read the EEPROM for the default values for flow control and store the
 *  values.
 **/
static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
{
	s32 ret_val;
	u16 nvm_data;

668 669
	/*
	 * Read and store word 0x0F of the EEPROM. This word contains bits
670 671 672 673 674 675 676 677 678 679
	 * that determine the hardware's default PAUSE (flow control) mode,
	 * a bit that determines whether the HW defaults to enabling or
	 * disabling auto-negotiation, and the direction of the
	 * SW defined pins. If there is no SW over-ride of the flow
	 * control setting, then the variable hw->fc will
	 * be initialized based on a value in the EEPROM.
	 */
	ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);

	if (ret_val) {
680
		e_dbg("NVM Read Error\n");
681 682 683
		return ret_val;
	}

B
Bruce Allan 已提交
684
	if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
685
		hw->fc.requested_mode = e1000_fc_none;
686
	else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR)
687
		hw->fc.requested_mode = e1000_fc_tx_pause;
688
	else
689
		hw->fc.requested_mode = e1000_fc_full;
690 691 692 693 694

	return 0;
}

/**
695
 *  e1000e_setup_link_generic - Setup flow control and link settings
696 697 698 699 700 701 702 703
 *  @hw: pointer to the HW structure
 *
 *  Determines which flow control settings to use, then configures flow
 *  control.  Calls the appropriate media-specific link configuration
 *  function.  Assuming the adapter has a valid link partner, a valid link
 *  should be established.  Assumes the hardware has previously been reset
 *  and the transmitter and receiver are not enabled.
 **/
704
s32 e1000e_setup_link_generic(struct e1000_hw *hw)
705 706 707
{
	s32 ret_val;

708 709
	/*
	 * In the case of the phy reset being blocked, we already have a link.
710 711
	 * We do not need to set it up again.
	 */
712
	if (hw->phy.ops.check_reset_block(hw))
713 714
		return 0;

715
	/*
716 717
	 * If requested flow control is set to default, set flow control
	 * based on the EEPROM flow control settings.
718
	 */
719
	if (hw->fc.requested_mode == e1000_fc_default) {
720 721 722 723
		ret_val = e1000_set_default_fc_generic(hw);
		if (ret_val)
			return ret_val;
	}
724

725
	/*
726 727
	 * Save off the requested flow control mode for use later.  Depending
	 * on the link partner's capabilities, we may or may not use this mode.
728
	 */
729
	hw->fc.current_mode = hw->fc.requested_mode;
730

731
	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
732 733

	/* Call the necessary media_type subroutine to configure the link. */
734
	ret_val = hw->mac.ops.setup_physical_interface(hw);
735 736 737
	if (ret_val)
		return ret_val;

738 739
	/*
	 * Initialize the flow control address, type, and PAUSE timer
740 741 742 743
	 * registers to their default values.  This is done even if flow
	 * control is disabled, because it does not hurt anything to
	 * initialize these registers.
	 */
744
	e_dbg("Initializing the Flow Control address, type and timer regs\n");
745 746 747 748
	ew32(FCT, FLOW_CONTROL_TYPE);
	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);

749
	ew32(FCTTV, hw->fc.pause_time);
750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765

	return e1000e_set_fc_watermarks(hw);
}

/**
 *  e1000_commit_fc_settings_generic - Configure flow control
 *  @hw: pointer to the HW structure
 *
 *  Write the flow control settings to the Transmit Config Word Register (TXCW)
 *  base on the flow control settings in e1000_mac_info.
 **/
static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
{
	struct e1000_mac_info *mac = &hw->mac;
	u32 txcw;

766 767
	/*
	 * Check for a software override of the flow control settings, and
768 769 770 771 772 773 774 775 776 777
	 * setup the device accordingly.  If auto-negotiation is enabled, then
	 * software will have to set the "PAUSE" bits to the correct value in
	 * the Transmit Config Word Register (TXCW) and re-start auto-
	 * negotiation.  However, if auto-negotiation is disabled, then
	 * software will have to manually configure the two flow control enable
	 * bits in the CTRL register.
	 *
	 * The possible values of the "fc" parameter are:
	 *      0:  Flow control is completely disabled
	 *      1:  Rx flow control is enabled (we can receive pause frames,
778
	 *          but not send pause frames).
779
	 *      2:  Tx flow control is enabled (we can send pause frames but we
780
	 *          do not support receiving pause frames).
781
	 *      3:  Both Rx and Tx flow control (symmetric) are enabled.
782
	 */
783
	switch (hw->fc.current_mode) {
784 785 786 787 788
	case e1000_fc_none:
		/* Flow control completely disabled by a software over-ride. */
		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
		break;
	case e1000_fc_rx_pause:
789 790
		/*
		 * Rx Flow control is enabled and Tx Flow control is disabled
791
		 * by a software over-ride. Since there really isn't a way to
792 793
		 * advertise that we are capable of Rx Pause ONLY, we will
		 * advertise that we support both symmetric and asymmetric Rx
794 795 796 797 798 799
		 * PAUSE.  Later, we will disable the adapter's ability to send
		 * PAUSE frames.
		 */
		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
		break;
	case e1000_fc_tx_pause:
800 801
		/*
		 * Tx Flow control is enabled, and Rx Flow control is disabled,
802 803 804 805 806
		 * by a software over-ride.
		 */
		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
		break;
	case e1000_fc_full:
807 808
		/*
		 * Flow control (both Rx and Tx) is enabled by a software
809 810 811 812 813
		 * over-ride.
		 */
		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
		break;
	default:
814
		e_dbg("Flow control param set incorrectly\n");
815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837
		return -E1000_ERR_CONFIG;
		break;
	}

	ew32(TXCW, txcw);
	mac->txcw = txcw;

	return 0;
}

/**
 *  e1000_poll_fiber_serdes_link_generic - Poll for link up
 *  @hw: pointer to the HW structure
 *
 *  Polls for link up by reading the status register, if link fails to come
 *  up with auto-negotiation, then the link is forced if a signal is detected.
 **/
static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
{
	struct e1000_mac_info *mac = &hw->mac;
	u32 i, status;
	s32 ret_val;

838 839
	/*
	 * If we have a signal (the cable is plugged in, or assumed true for
840 841 842 843 844 845
	 * serdes media) then poll for a "Link-Up" indication in the Device
	 * Status Register.  Time-out if a link isn't seen in 500 milliseconds
	 * seconds (Auto-negotiation should complete in less than 500
	 * milliseconds even if the other end is doing it in SW).
	 */
	for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
846
		usleep_range(10000, 20000);
847 848 849 850 851
		status = er32(STATUS);
		if (status & E1000_STATUS_LU)
			break;
	}
	if (i == FIBER_LINK_UP_LIMIT) {
852
		e_dbg("Never got a valid link from auto-neg!!!\n");
853
		mac->autoneg_failed = true;
854 855
		/*
		 * AutoNeg failed to achieve a link, so we'll call
856 857 858 859 860 861
		 * mac->check_for_link. This routine will force the
		 * link up if we detect a signal. This will allow us to
		 * communicate with non-autonegotiating link partners.
		 */
		ret_val = mac->ops.check_for_link(hw);
		if (ret_val) {
862
			e_dbg("Error while checking for link\n");
863 864
			return ret_val;
		}
865
		mac->autoneg_failed = false;
866
	} else {
867
		mac->autoneg_failed = false;
868
		e_dbg("Valid Link Found\n");
869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890
	}

	return 0;
}

/**
 *  e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
 *  @hw: pointer to the HW structure
 *
 *  Configures collision distance and flow control for fiber and serdes
 *  links.  Upon successful setup, poll for link.
 **/
s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
{
	u32 ctrl;
	s32 ret_val;

	ctrl = er32(CTRL);

	/* Take the link out of reset */
	ctrl &= ~E1000_CTRL_LRST;

891
	hw->mac.ops.config_collision_dist(hw);
892 893 894 895 896

	ret_val = e1000_commit_fc_settings_generic(hw);
	if (ret_val)
		return ret_val;

897 898
	/*
	 * Since auto-negotiation is enabled, take the link out of reset (the
899 900 901 902 903
	 * link will be in reset, because we previously reset the chip). This
	 * will restart auto-negotiation.  If auto-negotiation is successful
	 * then the link-up status bit will be set and the flow control enable
	 * bits (RFCE and TFCE) will be set according to their negotiated value.
	 */
904
	e_dbg("Auto-negotiation enabled\n");
905 906 907

	ew32(CTRL, ctrl);
	e1e_flush();
908
	usleep_range(1000, 2000);
909

910 911
	/*
	 * For these adapters, the SW definable pin 1 is set when the optics
912 913 914
	 * detect a signal.  If we have a signal, then poll for a "Link-Up"
	 * indication.
	 */
915
	if (hw->phy.media_type == e1000_media_type_internal_serdes ||
916 917 918
	    (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
		ret_val = e1000_poll_fiber_serdes_link_generic(hw);
	} else {
919
		e_dbg("No signal detected\n");
920 921
	}

922
	return ret_val;
923 924 925
}

/**
926
 *  e1000e_config_collision_dist_generic - Configure collision distance
927 928 929
 *  @hw: pointer to the HW structure
 *
 *  Configures the collision distance to the default value and is used
930
 *  during link setup.
931
 **/
932
void e1000e_config_collision_dist_generic(struct e1000_hw *hw)
933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950
{
	u32 tctl;

	tctl = er32(TCTL);

	tctl &= ~E1000_TCTL_COLD;
	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;

	ew32(TCTL, tctl);
	e1e_flush();
}

/**
 *  e1000e_set_fc_watermarks - Set flow control high/low watermarks
 *  @hw: pointer to the HW structure
 *
 *  Sets the flow control high/low threshold (watermark) registers.  If
 *  flow control XON frame transmission is enabled, then set XON frame
951
 *  transmission as well.
952 953 954 955 956
 **/
s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
{
	u32 fcrtl = 0, fcrth = 0;

957 958
	/*
	 * Set the flow control receive threshold registers.  Normally,
959 960 961 962 963
	 * these registers will be set to a default threshold that may be
	 * adjusted later by the driver's runtime code.  However, if the
	 * ability to transmit pause frames is not enabled, then these
	 * registers will be set to 0.
	 */
964
	if (hw->fc.current_mode & e1000_fc_tx_pause) {
965 966
		/*
		 * We need to set up the Receive Threshold high and low water
967 968 969
		 * marks as well as (optionally) enabling the transmission of
		 * XON frames.
		 */
970
		fcrtl = hw->fc.low_water;
971 972 973
		if (hw->fc.send_xon)
			fcrtl |= E1000_FCRTL_XONE;

974
		fcrth = hw->fc.high_water;
975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997
	}
	ew32(FCRTL, fcrtl);
	ew32(FCRTH, fcrth);

	return 0;
}

/**
 *  e1000e_force_mac_fc - Force the MAC's flow control settings
 *  @hw: pointer to the HW structure
 *
 *  Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the
 *  device control register to reflect the adapter settings.  TFCE and RFCE
 *  need to be explicitly set by software when a copper PHY is used because
 *  autonegotiation is managed by the PHY rather than the MAC.  Software must
 *  also configure these bits when link is forced on a fiber connection.
 **/
s32 e1000e_force_mac_fc(struct e1000_hw *hw)
{
	u32 ctrl;

	ctrl = er32(CTRL);

998 999
	/*
	 * Because we didn't get link via the internal auto-negotiation
1000 1001 1002 1003 1004
	 * mechanism (we either forced link or we got link via PHY
	 * auto-neg), we have to manually enable/disable transmit an
	 * receive flow control.
	 *
	 * The "Case" statement below enables/disable flow control
1005
	 * according to the "hw->fc.current_mode" parameter.
1006 1007 1008 1009
	 *
	 * The possible values of the "fc" parameter are:
	 *      0:  Flow control is completely disabled
	 *      1:  Rx flow control is enabled (we can receive pause
1010
	 *          frames but not send pause frames).
1011
	 *      2:  Tx flow control is enabled (we can send pause frames
1012
	 *          frames but we do not receive pause frames).
1013
	 *      3:  Both Rx and Tx flow control (symmetric) is enabled.
1014 1015
	 *  other:  No other values should be possible at this point.
	 */
1016
	e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1017

1018
	switch (hw->fc.current_mode) {
1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033
	case e1000_fc_none:
		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
		break;
	case e1000_fc_rx_pause:
		ctrl &= (~E1000_CTRL_TFCE);
		ctrl |= E1000_CTRL_RFCE;
		break;
	case e1000_fc_tx_pause:
		ctrl &= (~E1000_CTRL_RFCE);
		ctrl |= E1000_CTRL_TFCE;
		break;
	case e1000_fc_full:
		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
		break;
	default:
1034
		e_dbg("Flow control param set incorrectly\n");
1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059
		return -E1000_ERR_CONFIG;
	}

	ew32(CTRL, ctrl);

	return 0;
}

/**
 *  e1000e_config_fc_after_link_up - Configures flow control after link
 *  @hw: pointer to the HW structure
 *
 *  Checks the status of auto-negotiation after link up to ensure that the
 *  speed and duplex were not forced.  If the link needed to be forced, then
 *  flow control needs to be forced also.  If auto-negotiation is enabled
 *  and did not fail, then we configure flow control based on our link
 *  partner.
 **/
s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
{
	struct e1000_mac_info *mac = &hw->mac;
	s32 ret_val = 0;
	u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
	u16 speed, duplex;

1060 1061
	/*
	 * Check for the case where we have fiber media and auto-neg failed
1062 1063 1064 1065
	 * so we had to force link.  In this case, we need to force the
	 * configuration of the MAC to match the "fc" parameter.
	 */
	if (mac->autoneg_failed) {
1066 1067
		if (hw->phy.media_type == e1000_media_type_fiber ||
		    hw->phy.media_type == e1000_media_type_internal_serdes)
1068 1069
			ret_val = e1000e_force_mac_fc(hw);
	} else {
1070
		if (hw->phy.media_type == e1000_media_type_copper)
1071 1072 1073 1074
			ret_val = e1000e_force_mac_fc(hw);
	}

	if (ret_val) {
1075
		e_dbg("Error forcing flow control settings\n");
1076 1077 1078
		return ret_val;
	}

1079 1080
	/*
	 * Check for the case where we have copper media and auto-neg is
1081 1082 1083 1084
	 * enabled.  In this case, we need to check and see if Auto-Neg
	 * has completed, and if so, how the PHY and link partner has
	 * flow control configured.
	 */
1085
	if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1086 1087
		/*
		 * Read the MII Status Register and check to see if AutoNeg
1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098
		 * has completed.  We read this twice because this reg has
		 * some "sticky" (latched) bits.
		 */
		ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
		if (ret_val)
			return ret_val;
		ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
		if (ret_val)
			return ret_val;

		if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1099
			e_dbg("Copper PHY and Auto Neg has not completed.\n");
1100 1101 1102
			return ret_val;
		}

1103 1104
		/*
		 * The AutoNeg process has completed, so we now need to
1105 1106 1107 1108 1109 1110 1111 1112
		 * read both the Auto Negotiation Advertisement
		 * Register (Address 4) and the Auto_Negotiation Base
		 * Page Ability Register (Address 5) to determine how
		 * flow control was negotiated.
		 */
		ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
		if (ret_val)
			return ret_val;
1113 1114
		ret_val =
		    e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1115 1116 1117
		if (ret_val)
			return ret_val;

1118 1119
		/*
		 * Two bits in the Auto Negotiation Advertisement Register
1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139
		 * (Address 4) and two bits in the Auto Negotiation Base
		 * Page Ability Register (Address 5) determine flow control
		 * for both the PHY and the link partner.  The following
		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
		 * 1999, describes these PAUSE resolution bits and how flow
		 * control is determined based upon these settings.
		 * NOTE:  DC = Don't Care
		 *
		 *   LOCAL DEVICE  |   LINK PARTNER
		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
		 *-------|---------|-------|---------|--------------------
		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
		 *   0   |    1    |   0   |   DC    | e1000_fc_none
		 *   0   |    1    |   1   |    0    | e1000_fc_none
		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
		 *   1   |    0    |   0   |   DC    | e1000_fc_none
		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
		 *   1   |    1    |   0   |    0    | e1000_fc_none
		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
		 *
1140
		 * Are both PAUSE bits set to 1?  If so, this implies
1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153
		 * Symmetric Flow Control is enabled at both ends.  The
		 * ASM_DIR bits are irrelevant per the spec.
		 *
		 * For Symmetric Flow Control:
		 *
		 *   LOCAL DEVICE  |   LINK PARTNER
		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
		 *-------|---------|-------|---------|--------------------
		 *   1   |   DC    |   1   |   DC    | E1000_fc_full
		 *
		 */
		if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
		    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1154 1155
			/*
			 * Now we need to check if the user selected Rx ONLY
1156
			 * of pause frames.  In this case, we had to advertise
1157
			 * FULL flow control because we could not advertise Rx
1158
			 * ONLY. Hence, we must now check to see if we need to
B
Bruce Allan 已提交
1159
			 * turn OFF the TRANSMISSION of PAUSE frames.
1160
			 */
1161 1162
			if (hw->fc.requested_mode == e1000_fc_full) {
				hw->fc.current_mode = e1000_fc_full;
1163
				e_dbg("Flow Control = FULL.\n");
1164
			} else {
1165
				hw->fc.current_mode = e1000_fc_rx_pause;
1166
				e_dbg("Flow Control = Rx PAUSE frames only.\n");
1167 1168
			}
		}
1169 1170
		/*
		 * For receiving PAUSE frames ONLY.
1171 1172 1173 1174 1175 1176 1177
		 *
		 *   LOCAL DEVICE  |   LINK PARTNER
		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
		 *-------|---------|-------|---------|--------------------
		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
		 */
		else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1178 1179 1180
			 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
			 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
			 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1181
			hw->fc.current_mode = e1000_fc_tx_pause;
1182
			e_dbg("Flow Control = Tx PAUSE frames only.\n");
1183
		}
1184 1185
		/*
		 * For transmitting PAUSE frames ONLY.
1186 1187 1188 1189 1190 1191 1192 1193 1194 1195
		 *
		 *   LOCAL DEVICE  |   LINK PARTNER
		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
		 *-------|---------|-------|---------|--------------------
		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
		 */
		else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
			 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
			 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
			 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1196
			hw->fc.current_mode = e1000_fc_rx_pause;
1197
			e_dbg("Flow Control = Rx PAUSE frames only.\n");
1198 1199 1200 1201 1202
		} else {
			/*
			 * Per the IEEE spec, at this point flow control
			 * should be disabled.
			 */
1203
			hw->fc.current_mode = e1000_fc_none;
1204
			e_dbg("Flow Control = NONE.\n");
1205 1206
		}

1207 1208
		/*
		 * Now we need to do one last check...  If we auto-
1209 1210 1211 1212 1213
		 * negotiated to HALF DUPLEX, flow control should not be
		 * enabled per IEEE 802.3 spec.
		 */
		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
		if (ret_val) {
1214
			e_dbg("Error getting link speed and duplex\n");
1215 1216 1217 1218
			return ret_val;
		}

		if (duplex == HALF_DUPLEX)
1219
			hw->fc.current_mode = e1000_fc_none;
1220

1221 1222
		/*
		 * Now we call a subroutine to actually force the MAC
1223 1224 1225 1226
		 * controller to use the correct flow control settings.
		 */
		ret_val = e1000e_force_mac_fc(hw);
		if (ret_val) {
1227
			e_dbg("Error forcing flow control settings\n");
1228 1229 1230 1231 1232 1233 1234 1235
			return ret_val;
		}
	}

	return 0;
}

/**
1236
 *  e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1237 1238 1239 1240 1241 1242 1243
 *  @hw: pointer to the HW structure
 *  @speed: stores the current speed
 *  @duplex: stores the current duplex
 *
 *  Read the status register for the current speed/duplex and store the current
 *  speed and duplex for copper connections.
 **/
1244 1245
s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
				       u16 *duplex)
1246 1247 1248 1249
{
	u32 status;

	status = er32(STATUS);
J
Joe Perches 已提交
1250
	if (status & E1000_STATUS_SPEED_1000)
1251
		*speed = SPEED_1000;
J
Joe Perches 已提交
1252
	else if (status & E1000_STATUS_SPEED_100)
1253
		*speed = SPEED_100;
J
Joe Perches 已提交
1254
	else
1255 1256
		*speed = SPEED_10;

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Joe Perches 已提交
1257
	if (status & E1000_STATUS_FD)
1258
		*duplex = FULL_DUPLEX;
J
Joe Perches 已提交
1259
	else
1260
		*duplex = HALF_DUPLEX;
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Joe Perches 已提交
1261 1262 1263 1264

	e_dbg("%u Mbps, %s Duplex\n",
	      *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10,
	      *duplex == FULL_DUPLEX ? "Full" : "Half");
1265 1266 1267 1268 1269

	return 0;
}

/**
1270
 *  e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1271 1272 1273 1274 1275 1276 1277
 *  @hw: pointer to the HW structure
 *  @speed: stores the current speed
 *  @duplex: stores the current duplex
 *
 *  Sets the speed and duplex to gigabit full duplex (the only possible option)
 *  for fiber/serdes links.
 **/
1278 1279
s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed,
					     u16 *duplex)
1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309
{
	*speed = SPEED_1000;
	*duplex = FULL_DUPLEX;

	return 0;
}

/**
 *  e1000e_get_hw_semaphore - Acquire hardware semaphore
 *  @hw: pointer to the HW structure
 *
 *  Acquire the HW semaphore to access the PHY or NVM
 **/
s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
{
	u32 swsm;
	s32 timeout = hw->nvm.word_size + 1;
	s32 i = 0;

	/* Get the SW semaphore */
	while (i < timeout) {
		swsm = er32(SWSM);
		if (!(swsm & E1000_SWSM_SMBI))
			break;

		udelay(50);
		i++;
	}

	if (i == timeout) {
1310
		e_dbg("Driver can't access device - SMBI bit is set.\n");
1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328
		return -E1000_ERR_NVM;
	}

	/* Get the FW semaphore. */
	for (i = 0; i < timeout; i++) {
		swsm = er32(SWSM);
		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);

		/* Semaphore acquired if bit latched */
		if (er32(SWSM) & E1000_SWSM_SWESMBI)
			break;

		udelay(50);
	}

	if (i == timeout) {
		/* Release semaphores */
		e1000e_put_hw_semaphore(hw);
1329
		e_dbg("Driver can't access the NVM\n");
1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363
		return -E1000_ERR_NVM;
	}

	return 0;
}

/**
 *  e1000e_put_hw_semaphore - Release hardware semaphore
 *  @hw: pointer to the HW structure
 *
 *  Release hardware semaphore used to access the PHY or NVM
 **/
void e1000e_put_hw_semaphore(struct e1000_hw *hw)
{
	u32 swsm;

	swsm = er32(SWSM);
	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
	ew32(SWSM, swsm);
}

/**
 *  e1000e_get_auto_rd_done - Check for auto read completion
 *  @hw: pointer to the HW structure
 *
 *  Check EEPROM for Auto Read done bit.
 **/
s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
{
	s32 i = 0;

	while (i < AUTO_READ_DONE_TIMEOUT) {
		if (er32(EECD) & E1000_EECD_AUTO_RD)
			break;
1364
		usleep_range(1000, 2000);
1365 1366 1367 1368
		i++;
	}

	if (i == AUTO_READ_DONE_TIMEOUT) {
1369
		e_dbg("Auto read by HW from NVM has not completed.\n");
1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389
		return -E1000_ERR_RESET;
	}

	return 0;
}

/**
 *  e1000e_valid_led_default - Verify a valid default LED config
 *  @hw: pointer to the HW structure
 *  @data: pointer to the NVM (EEPROM)
 *
 *  Read the EEPROM for the current default LED configuration.  If the
 *  LED configuration is not valid, set to a valid LED configuration.
 **/
s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
{
	s32 ret_val;

	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
	if (ret_val) {
1390
		e_dbg("NVM Read Error\n");
1391 1392 1393 1394 1395 1396 1397 1398 1399 1400
		return ret_val;
	}

	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
		*data = ID_LED_DEFAULT;

	return 0;
}

/**
1401
 *  e1000e_id_led_init_generic -
1402 1403 1404
 *  @hw: pointer to the HW structure
 *
 **/
1405
s32 e1000e_id_led_init_generic(struct e1000_hw *hw)
1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463
{
	struct e1000_mac_info *mac = &hw->mac;
	s32 ret_val;
	const u32 ledctl_mask = 0x000000FF;
	const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
	const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
	u16 data, i, temp;
	const u16 led_mask = 0x0F;

	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
	if (ret_val)
		return ret_val;

	mac->ledctl_default = er32(LEDCTL);
	mac->ledctl_mode1 = mac->ledctl_default;
	mac->ledctl_mode2 = mac->ledctl_default;

	for (i = 0; i < 4; i++) {
		temp = (data >> (i << 2)) & led_mask;
		switch (temp) {
		case ID_LED_ON1_DEF2:
		case ID_LED_ON1_ON2:
		case ID_LED_ON1_OFF2:
			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
			mac->ledctl_mode1 |= ledctl_on << (i << 3);
			break;
		case ID_LED_OFF1_DEF2:
		case ID_LED_OFF1_ON2:
		case ID_LED_OFF1_OFF2:
			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
			mac->ledctl_mode1 |= ledctl_off << (i << 3);
			break;
		default:
			/* Do nothing */
			break;
		}
		switch (temp) {
		case ID_LED_DEF1_ON2:
		case ID_LED_ON1_ON2:
		case ID_LED_OFF1_ON2:
			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
			mac->ledctl_mode2 |= ledctl_on << (i << 3);
			break;
		case ID_LED_DEF1_OFF2:
		case ID_LED_ON1_OFF2:
		case ID_LED_OFF1_OFF2:
			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
			mac->ledctl_mode2 |= ledctl_off << (i << 3);
			break;
		default:
			/* Do nothing */
			break;
		}
	}

	return 0;
}

1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474
/**
 *  e1000e_setup_led_generic - Configures SW controllable LED
 *  @hw: pointer to the HW structure
 *
 *  This prepares the SW controllable LED for use and saves the current state
 *  of the LED so it can be later restored.
 **/
s32 e1000e_setup_led_generic(struct e1000_hw *hw)
{
	u32 ledctl;

B
Bruce Allan 已提交
1475
	if (hw->mac.ops.setup_led != e1000e_setup_led_generic)
1476 1477 1478 1479 1480 1481
		return -E1000_ERR_CONFIG;

	if (hw->phy.media_type == e1000_media_type_fiber) {
		ledctl = er32(LEDCTL);
		hw->mac.ledctl_default = ledctl;
		/* Turn off LED0 */
1482 1483
		ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
			    E1000_LEDCTL_LED0_MODE_MASK);
1484
		ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1485
			   E1000_LEDCTL_LED0_MODE_SHIFT);
1486 1487 1488 1489 1490 1491 1492 1493
		ew32(LEDCTL, ledctl);
	} else if (hw->phy.media_type == e1000_media_type_copper) {
		ew32(LEDCTL, hw->mac.ledctl_mode1);
	}

	return 0;
}

1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507
/**
 *  e1000e_cleanup_led_generic - Set LED config to default operation
 *  @hw: pointer to the HW structure
 *
 *  Remove the current LED configuration and set the LED configuration
 *  to the default value, saved from the EEPROM.
 **/
s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
{
	ew32(LEDCTL, hw->mac.ledctl_default);
	return 0;
}

/**
1508
 *  e1000e_blink_led_generic - Blink LED
1509 1510
 *  @hw: pointer to the HW structure
 *
1511
 *  Blink the LEDs which are set to be on.
1512
 **/
1513
s32 e1000e_blink_led_generic(struct e1000_hw *hw)
1514 1515 1516 1517
{
	u32 ledctl_blink = 0;
	u32 i;

1518
	if (hw->phy.media_type == e1000_media_type_fiber) {
1519 1520
		/* always blink LED0 for PCI-E fiber */
		ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1521
		    (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1522
	} else {
1523 1524 1525 1526
		/*
		 * set the blink bit for each LED that's "on" (0x0E)
		 * in ledctl_mode2
		 */
1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549
		ledctl_blink = hw->mac.ledctl_mode2;
		for (i = 0; i < 4; i++)
			if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
			    E1000_LEDCTL_MODE_LED_ON)
				ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
						 (i * 8));
	}

	ew32(LEDCTL, ledctl_blink);

	return 0;
}

/**
 *  e1000e_led_on_generic - Turn LED on
 *  @hw: pointer to the HW structure
 *
 *  Turn LED on.
 **/
s32 e1000e_led_on_generic(struct e1000_hw *hw)
{
	u32 ctrl;

1550
	switch (hw->phy.media_type) {
1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576
	case e1000_media_type_fiber:
		ctrl = er32(CTRL);
		ctrl &= ~E1000_CTRL_SWDPIN0;
		ctrl |= E1000_CTRL_SWDPIO0;
		ew32(CTRL, ctrl);
		break;
	case e1000_media_type_copper:
		ew32(LEDCTL, hw->mac.ledctl_mode2);
		break;
	default:
		break;
	}

	return 0;
}

/**
 *  e1000e_led_off_generic - Turn LED off
 *  @hw: pointer to the HW structure
 *
 *  Turn LED off.
 **/
s32 e1000e_led_off_generic(struct e1000_hw *hw)
{
	u32 ctrl;

1577
	switch (hw->phy.media_type) {
1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617
	case e1000_media_type_fiber:
		ctrl = er32(CTRL);
		ctrl |= E1000_CTRL_SWDPIN0;
		ctrl |= E1000_CTRL_SWDPIO0;
		ew32(CTRL, ctrl);
		break;
	case e1000_media_type_copper:
		ew32(LEDCTL, hw->mac.ledctl_mode1);
		break;
	default:
		break;
	}

	return 0;
}

/**
 *  e1000e_set_pcie_no_snoop - Set PCI-express capabilities
 *  @hw: pointer to the HW structure
 *  @no_snoop: bitmap of snoop events
 *
 *  Set the PCI-express register to snoop for events enabled in 'no_snoop'.
 **/
void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
{
	u32 gcr;

	if (no_snoop) {
		gcr = er32(GCR);
		gcr &= ~(PCIE_NO_SNOOP_ALL);
		gcr |= no_snoop;
		ew32(GCR, gcr);
	}
}

/**
 *  e1000e_disable_pcie_master - Disables PCI-express master access
 *  @hw: pointer to the HW structure
 *
 *  Returns 0 if successful, else returns -10
1618
 *  (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633
 *  the master requests to be disabled.
 *
 *  Disables PCI-Express master access and verifies there are no pending
 *  requests.
 **/
s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
{
	u32 ctrl;
	s32 timeout = MASTER_DISABLE_TIMEOUT;

	ctrl = er32(CTRL);
	ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
	ew32(CTRL, ctrl);

	while (timeout) {
1634
		if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
1635 1636 1637 1638 1639 1640
			break;
		udelay(100);
		timeout--;
	}

	if (!timeout) {
1641
		e_dbg("Master requests are pending.\n");
1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657
		return -E1000_ERR_MASTER_REQUESTS_PENDING;
	}

	return 0;
}

/**
 *  e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
 *  @hw: pointer to the HW structure
 *
 *  Reset the Adaptive Interframe Spacing throttle to default values.
 **/
void e1000e_reset_adaptive(struct e1000_hw *hw)
{
	struct e1000_mac_info *mac = &hw->mac;

1658 1659
	if (!mac->adaptive_ifs) {
		e_dbg("Not in Adaptive IFS mode!\n");
1660
		return;
1661 1662
	}

1663 1664 1665 1666 1667 1668
	mac->current_ifs_val = 0;
	mac->ifs_min_val = IFS_MIN;
	mac->ifs_max_val = IFS_MAX;
	mac->ifs_step_size = IFS_STEP;
	mac->ifs_ratio = IFS_RATIO;

1669
	mac->in_ifs_mode = false;
1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683
	ew32(AIT, 0);
}

/**
 *  e1000e_update_adaptive - Update Adaptive Interframe Spacing
 *  @hw: pointer to the HW structure
 *
 *  Update the Adaptive Interframe Spacing Throttle value based on the
 *  time between transmitted packets and time between collisions.
 **/
void e1000e_update_adaptive(struct e1000_hw *hw)
{
	struct e1000_mac_info *mac = &hw->mac;

1684 1685
	if (!mac->adaptive_ifs) {
		e_dbg("Not in Adaptive IFS mode!\n");
1686
		return;
1687 1688
	}

1689 1690
	if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
		if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1691
			mac->in_ifs_mode = true;
1692 1693 1694 1695 1696
			if (mac->current_ifs_val < mac->ifs_max_val) {
				if (!mac->current_ifs_val)
					mac->current_ifs_val = mac->ifs_min_val;
				else
					mac->current_ifs_val +=
1697
					    mac->ifs_step_size;
1698
				ew32(AIT, mac->current_ifs_val);
1699 1700 1701 1702 1703 1704
			}
		}
	} else {
		if (mac->in_ifs_mode &&
		    (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
			mac->current_ifs_val = 0;
1705
			mac->in_ifs_mode = false;
1706 1707 1708 1709
			ew32(AIT, 0);
		}
	}
}