hns_roce_device.h 34.5 KB
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/*
 * Copyright (c) 2016 Hisilicon Limited.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef _HNS_ROCE_DEVICE_H
#define _HNS_ROCE_DEVICE_H

#include <rdma/ib_verbs.h>

#define DRV_NAME "hns_roce"

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#define PCI_REVISION_ID_HIP08			0x21
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#define PCI_REVISION_ID_HIP09			0x30
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#define HNS_ROCE_HW_VER1	('h' << 24 | 'i' << 16 | '0' << 8 | '6')

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#define HNS_ROCE_MAX_MSG_LEN			0x80000000

#define HNS_ROCE_IB_MIN_SQ_STRIDE		6

#define HNS_ROCE_BA_SIZE			(32 * 4096)

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#define BA_BYTE_LEN				8

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/* Hardware specification only for v1 engine */
#define HNS_ROCE_MIN_CQE_NUM			0x40
#define HNS_ROCE_MIN_WQE_NUM			0x20

/* Hardware specification only for v1 engine */
#define HNS_ROCE_MAX_INNER_MTPT_NUM		0x7
#define HNS_ROCE_MAX_MTPT_PBL_NUM		0x100000

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#define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS	20
#define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT	\
	(5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
#define HNS_ROCE_CQE_WCMD_EMPTY_BIT		0x2
#define HNS_ROCE_MIN_CQE_CNT			16

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#define HNS_ROCE_MAX_IRQ_NUM			128
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#define HNS_ROCE_SGE_IN_WQE			2
#define HNS_ROCE_SGE_SHIFT			4

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#define EQ_ENABLE				1
#define EQ_DISABLE				0
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#define HNS_ROCE_CEQ				0
#define HNS_ROCE_AEQ				1

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#define HNS_ROCE_CEQE_SIZE 0x4
#define HNS_ROCE_AEQE_SIZE 0x10

#define HNS_ROCE_V3_EQE_SIZE 0x40
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#define HNS_ROCE_V2_CQE_SIZE 32
#define HNS_ROCE_V3_CQE_SIZE 64

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#define HNS_ROCE_V2_QPC_SZ 256
#define HNS_ROCE_V3_QPC_SZ 512

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#define HNS_ROCE_MAX_PORTS			6
#define HNS_ROCE_GID_SIZE			16
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#define HNS_ROCE_SGE_SIZE			16
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#define HNS_ROCE_HOP_NUM_0			0xff

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#define BITMAP_NO_RR				0
#define BITMAP_RR				1

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#define MR_TYPE_MR				0x00
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#define MR_TYPE_FRMR				0x01
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#define MR_TYPE_DMA				0x03

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#define HNS_ROCE_FRMR_MAX_PA			512

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#define PKEY_ID					0xffff
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#define GUID_LEN				8
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#define NODE_DESC_SIZE				64
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#define DB_REG_OFFSET				0x1000
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/* Configure to HW for PAGE_SIZE larger than 4KB */
#define PG_SHIFT_OFFSET				(PAGE_SHIFT - 12)

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#define PAGES_SHIFT_8				8
#define PAGES_SHIFT_16				16
#define PAGES_SHIFT_24				24
#define PAGES_SHIFT_32				32

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#define HNS_ROCE_IDX_QUE_ENTRY_SZ		4
#define SRQ_DB_REG				0x230

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/* The chip implementation of the consumer index is calculated
 * according to twice the actual EQ depth
 */
#define EQ_DEPTH_COEFF				2

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enum {
	SERV_TYPE_RC,
	SERV_TYPE_UC,
	SERV_TYPE_RD,
	SERV_TYPE_UD,
};

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enum {
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	HNS_ROCE_QP_CAP_RQ_RECORD_DB = BIT(0),
	HNS_ROCE_QP_CAP_SQ_RECORD_DB = BIT(1),
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};

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enum hns_roce_cq_flags {
	HNS_ROCE_CQ_FLAG_RECORD_DB = BIT(0),
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};

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enum hns_roce_qp_state {
	HNS_ROCE_QP_STATE_RST,
	HNS_ROCE_QP_STATE_INIT,
	HNS_ROCE_QP_STATE_RTR,
	HNS_ROCE_QP_STATE_RTS,
	HNS_ROCE_QP_STATE_SQD,
	HNS_ROCE_QP_STATE_ERR,
	HNS_ROCE_QP_NUM_STATE,
};

enum hns_roce_event {
	HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
	HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
	HNS_ROCE_EVENT_TYPE_COMM_EST                  = 0x03,
	HNS_ROCE_EVENT_TYPE_SQ_DRAINED                = 0x04,
	HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR            = 0x05,
	HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR    = 0x06,
	HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR     = 0x07,
	HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH           = 0x08,
	HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH        = 0x09,
	HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR           = 0x0a,
	HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR           = 0x0b,
	HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW               = 0x0c,
	HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID             = 0x0d,
	HNS_ROCE_EVENT_TYPE_PORT_CHANGE               = 0x0f,
	/* 0x10 and 0x11 is unused in currently application case */
	HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,
	HNS_ROCE_EVENT_TYPE_MB                        = 0x13,
	HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW              = 0x14,
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	HNS_ROCE_EVENT_TYPE_FLR			      = 0x15,
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};

/* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
enum {
	HNS_ROCE_LWQCE_QPC_ERROR		= 1,
	HNS_ROCE_LWQCE_MTU_ERROR		= 2,
	HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR	= 3,
	HNS_ROCE_LWQCE_WQE_ADDR_ERROR		= 4,
	HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR	= 5,
	HNS_ROCE_LWQCE_SL_ERROR			= 6,
	HNS_ROCE_LWQCE_PORT_ERROR		= 7,
};

/* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
enum {
	HNS_ROCE_LAVWQE_R_KEY_VIOLATION		= 1,
	HNS_ROCE_LAVWQE_LENGTH_ERROR		= 2,
	HNS_ROCE_LAVWQE_VA_ERROR		= 3,
	HNS_ROCE_LAVWQE_PD_ERROR		= 4,
	HNS_ROCE_LAVWQE_RW_ACC_ERROR		= 5,
	HNS_ROCE_LAVWQE_KEY_STATE_ERROR		= 6,
	HNS_ROCE_LAVWQE_MR_OPERATION_ERROR	= 7,
};

/* DOORBELL overflow subtype */
enum {
	HNS_ROCE_DB_SUBTYPE_SDB_OVF		= 1,
	HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF		= 2,
	HNS_ROCE_DB_SUBTYPE_ODB_OVF		= 3,
	HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF		= 4,
	HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP		= 5,
	HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP		= 6,
};

enum {
	/* RQ&SRQ related operations */
	HNS_ROCE_OPCODE_SEND_DATA_RECEIVE	= 0x06,
	HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE	= 0x07,
};

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#define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12

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enum {
	HNS_ROCE_CAP_FLAG_REREG_MR		= BIT(0),
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	HNS_ROCE_CAP_FLAG_ROCE_V1_V2		= BIT(1),
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	HNS_ROCE_CAP_FLAG_RQ_INLINE		= BIT(2),
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	HNS_ROCE_CAP_FLAG_RECORD_DB		= BIT(3),
	HNS_ROCE_CAP_FLAG_SQ_RECORD_DB		= BIT(4),
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	HNS_ROCE_CAP_FLAG_SRQ			= BIT(5),
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	HNS_ROCE_CAP_FLAG_MW			= BIT(7),
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	HNS_ROCE_CAP_FLAG_FRMR                  = BIT(8),
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	HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL		= BIT(9),
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	HNS_ROCE_CAP_FLAG_ATOMIC		= BIT(10),
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};

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#define HNS_ROCE_DB_TYPE_COUNT			2
#define HNS_ROCE_DB_UNIT_SIZE			4

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enum {
	HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
};

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enum hns_roce_reset_stage {
	HNS_ROCE_STATE_NON_RST,
	HNS_ROCE_STATE_RST_BEF_DOWN,
	HNS_ROCE_STATE_RST_DOWN,
	HNS_ROCE_STATE_RST_UNINIT,
	HNS_ROCE_STATE_RST_INIT,
	HNS_ROCE_STATE_RST_INITED,
};

enum hns_roce_instance_state {
	HNS_ROCE_STATE_NON_INIT,
	HNS_ROCE_STATE_INIT,
	HNS_ROCE_STATE_INITED,
	HNS_ROCE_STATE_UNINIT,
};

enum {
	HNS_ROCE_RST_DIRECT_RETURN		= 0,
};

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enum {
	CMD_RST_PRC_OTHERS,
	CMD_RST_PRC_SUCCESS,
	CMD_RST_PRC_EBUSY,
};

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#define HNS_ROCE_CMD_SUCCESS			1

#define HNS_ROCE_PORT_DOWN			0
#define HNS_ROCE_PORT_UP			1

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/* The minimum page size is 4K for hardware */
#define HNS_HW_PAGE_SHIFT			12
#define HNS_HW_PAGE_SIZE			(1 << HNS_HW_PAGE_SHIFT)
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/* The minimum page count for hardware access page directly. */
#define HNS_HW_DIRECT_PAGE_COUNT 2

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struct hns_roce_uar {
	u64		pfn;
	unsigned long	index;
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	unsigned long	logic_idx;
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};

struct hns_roce_ucontext {
	struct ib_ucontext	ibucontext;
	struct hns_roce_uar	uar;
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	struct list_head	page_list;
	struct mutex		page_mutex;
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};

struct hns_roce_pd {
	struct ib_pd		ibpd;
	unsigned long		pdn;
};

struct hns_roce_bitmap {
	/* Bitmap Traversal last a bit which is 1 */
	unsigned long		last;
	unsigned long		top;
	unsigned long		max;
	unsigned long		reserved_top;
	unsigned long		mask;
	spinlock_t		lock;
	unsigned long		*table;
};

/* For Hardware Entry Memory */
struct hns_roce_hem_table {
	/* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
	u32		type;
	/* HEM array elment num */
	unsigned long	num_hem;
	/* HEM entry record obj total num */
	unsigned long	num_obj;
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	/* Single obj size */
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	unsigned long	obj_size;
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	unsigned long	table_chunk_size;
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	int		lowmem;
	struct mutex	mutex;
	struct hns_roce_hem **hem;
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	u64		**bt_l1;
	dma_addr_t	*bt_l1_dma_addr;
	u64		**bt_l0;
	dma_addr_t	*bt_l0_dma_addr;
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};

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struct hns_roce_buf_region {
	int offset; /* page offset */
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	u32 count; /* page count */
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	int hopnum; /* addressing hop num */
};

#define HNS_ROCE_MAX_BT_REGION	3
#define HNS_ROCE_MAX_BT_LEVEL	3
struct hns_roce_hem_list {
	struct list_head root_bt;
	/* link all bt dma mem by hop config */
	struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
	struct list_head btm_bt; /* link all bottom bt in @mid_bt */
	dma_addr_t root_ba; /* pointer to the root ba table */
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};

struct hns_roce_buf_attr {
	struct {
		size_t	size;  /* region size */
		int	hopnum; /* multi-hop addressing hop num */
	} region[HNS_ROCE_MAX_BT_REGION];
	int region_count; /* valid region count */
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	unsigned int page_shift;  /* buffer page shift */
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	bool fixed_page; /* decide page shift is fixed-size or maximum size */
	int user_access; /* umem access flag */
	bool mtt_only; /* only alloc buffer-required MTT memory */
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};

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struct hns_roce_hem_cfg {
	dma_addr_t	root_ba; /* root BA table's address */
	bool		is_direct; /* addressing without BA table */
	unsigned int	ba_pg_shift; /* BA table page shift */
	unsigned int	buf_pg_shift; /* buffer page shift */
	unsigned int	buf_pg_count;  /* buffer page count */
	struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
	int		region_count;
};

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/* memory translate region */
struct hns_roce_mtr {
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	struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
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	struct ib_umem		*umem; /* user space buffer */
	struct hns_roce_buf	*kmem; /* kernel space buffer */
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	struct hns_roce_hem_cfg  hem_cfg; /* config for hardware addressing */
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};

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struct hns_roce_mw {
	struct ib_mw		ibmw;
	u32			pdn;
	u32			rkey;
	int			enabled; /* MW's active status */
	u32			pbl_hop_num;
	u32			pbl_ba_pg_sz;
	u32			pbl_buf_pg_sz;
};

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/* Only support 4K page size for mr register */
#define MR_SIZE_4K 0

struct hns_roce_mr {
	struct ib_mr		ibmr;
	u64			iova; /* MR's virtual orignal addr */
	u64			size; /* Address range of MR */
	u32			key; /* Key of MR */
	u32			pd;   /* PD num of MR */
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	u32			access;	/* Access permission of MR */
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	int			enabled; /* MR's active status */
	int			type;	/* MR's register type */
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	u32			pbl_hop_num;	/* multi-hop number */
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	struct hns_roce_mtr	pbl_mtr;
	u32			npages;
	dma_addr_t		*page_list;
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};

struct hns_roce_mr_table {
	struct hns_roce_bitmap		mtpt_bitmap;
	struct hns_roce_hem_table	mtpt_table;
};

struct hns_roce_wq {
	u64		*wrid;     /* Work request ID */
	spinlock_t	lock;
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	u32		wqe_cnt;  /* WQE num */
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	int		max_gs;
	int		offset;
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	int		wqe_shift;	/* WQE size */
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	u32		head;
	u32		tail;
	void __iomem	*db_reg_l;
};

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struct hns_roce_sge {
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	unsigned int	sge_cnt;	/* SGE num */
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	int		offset;
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	int		sge_shift;	/* SGE size */
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};

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struct hns_roce_buf_list {
	void		*buf;
	dma_addr_t	map;
};

struct hns_roce_buf {
	struct hns_roce_buf_list	direct;
	struct hns_roce_buf_list	*page_list;
	u32				npages;
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	u32				size;
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	unsigned int			page_shift;
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};

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struct hns_roce_db_pgdir {
	struct list_head	list;
	DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
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	DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
	unsigned long		*bits[HNS_ROCE_DB_TYPE_COUNT];
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	u32			*page;
	dma_addr_t		db_dma;
};

struct hns_roce_user_db_page {
	struct list_head	list;
	struct ib_umem		*umem;
	unsigned long		user_virt;
	refcount_t		refcount;
};

struct hns_roce_db {
	u32		*db_record;
	union {
		struct hns_roce_db_pgdir *pgdir;
		struct hns_roce_user_db_page *user_page;
	} u;
	dma_addr_t	dma;
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	void		*virt_addr;
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	int		index;
	int		order;
};

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struct hns_roce_cq {
	struct ib_cq			ib_cq;
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	struct hns_roce_mtr		mtr;
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	struct hns_roce_db		db;
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	u32				flags;
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	spinlock_t			lock;
	u32				cq_depth;
	u32				cons_index;
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	u32				*set_ci_db;
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	void __iomem			*cq_db_l;
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	u16				*tptr_addr;
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	int				arm_sn;
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	int				cqe_size;
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	unsigned long			cqn;
	u32				vector;
	atomic_t			refcount;
	struct completion		free;
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	struct list_head		sq_list; /* all qps on this send cq */
	struct list_head		rq_list; /* all qps on this recv cq */
	int				is_armed; /* cq is armed */
	struct list_head		node; /* all armed cqs are on a list */
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};

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struct hns_roce_idx_que {
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	struct hns_roce_mtr		mtr;
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	int				entry_shift;
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	unsigned long			*bitmap;
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};

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struct hns_roce_srq {
	struct ib_srq		ibsrq;
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	unsigned long		srqn;
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	u32			wqe_cnt;
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	int			max_gs;
	int			wqe_shift;
	void __iomem		*db_reg_l;

	atomic_t		refcount;
	struct completion	free;

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	struct hns_roce_mtr	buf_mtr;

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	u64		       *wrid;
	struct hns_roce_idx_que idx_que;
	spinlock_t		lock;
	int			head;
	int			tail;
	struct mutex		mutex;
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	void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
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};

struct hns_roce_uar_table {
	struct hns_roce_bitmap bitmap;
};

struct hns_roce_qp_table {
	struct hns_roce_bitmap		bitmap;
	struct hns_roce_hem_table	qp_table;
	struct hns_roce_hem_table	irrl_table;
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	struct hns_roce_hem_table	trrl_table;
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	struct hns_roce_hem_table	sccc_table;
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	struct mutex			scc_mutex;
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};

struct hns_roce_cq_table {
	struct hns_roce_bitmap		bitmap;
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	struct xarray			array;
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	struct hns_roce_hem_table	table;
};

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struct hns_roce_srq_table {
	struct hns_roce_bitmap		bitmap;
	struct xarray			xa;
	struct hns_roce_hem_table	table;
};

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struct hns_roce_raq_table {
	struct hns_roce_buf_list	*e_raq_buf;
};

struct hns_roce_av {
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	u8 port;
	u8 gid_index;
	u8 stat_rate;
	u8 hop_limit;
	u32 flowlabel;
	u16 udp_sport;
	u8 sl;
	u8 tclass;
	u8 dgid[HNS_ROCE_GID_SIZE];
	u8 mac[ETH_ALEN];
	u16 vlan_id;
	bool vlan_en;
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};

struct hns_roce_ah {
	struct ib_ah		ibah;
	struct hns_roce_av	av;
};

struct hns_roce_cmd_context {
	struct completion	done;
	int			result;
	int			next;
	u64			out_param;
	u16			token;
};

struct hns_roce_cmdq {
	struct dma_pool		*pool;
	struct mutex		hcr_mutex;
	struct semaphore	poll_sem;
	/*
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	 * Event mode: cmd register mutex protection,
	 * ensure to not exceed max_cmds and user use limit region
	 */
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	struct semaphore	event_sem;
	int			max_cmds;
	spinlock_t		context_lock;
	int			free_head;
	struct hns_roce_cmd_context *context;
	/*
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	 * Result of get integer part
	 * which max_comds compute according a power of 2
	 */
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	u16			token_mask;
	/*
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	 * Process whether use event mode, init default non-zero
	 * After the event queue of cmd event ready,
	 * can switch into event mode
	 * close device, switch into poll mode(non event mode)
	 */
590 591 592
	u8			use_events;
};

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Shaobo Xu 已提交
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struct hns_roce_cmd_mailbox {
	void		       *buf;
	dma_addr_t		dma;
};

598 599
struct hns_roce_dev;

600 601 602 603 604 605 606 607 608 609 610 611 612 613 614
struct hns_roce_rinl_sge {
	void			*addr;
	u32			len;
};

struct hns_roce_rinl_wqe {
	struct hns_roce_rinl_sge *sg_list;
	u32			 sge_cnt;
};

struct hns_roce_rinl_buf {
	struct hns_roce_rinl_wqe *wqe_list;
	u32			 wqe_cnt;
};

615 616 617 618
enum {
	HNS_ROCE_FLUSH_FLAG = 0,
};

619 620 621 622 623 624 625 626 627
struct hns_roce_work {
	struct hns_roce_dev *hr_dev;
	struct work_struct work;
	u32 qpn;
	u32 cqn;
	int event_type;
	int sub_type;
};

628 629 630
struct hns_roce_qp {
	struct ib_qp		ibqp;
	struct hns_roce_wq	rq;
631
	struct hns_roce_db	rdb;
632
	struct hns_roce_db	sdb;
633
	unsigned long		en_flags;
634
	u32			doorbell_qpn;
635
	u32			sq_signal_bits;
636 637
	struct hns_roce_wq	sq;

638 639
	struct hns_roce_mtr	mtr;

640 641 642
	u32			buff_size;
	struct mutex		mutex;
	u8			port;
643
	u8			phy_port;
644 645 646 647
	u8			sl;
	u8			resp_depth;
	u8			state;
	u32			access_flags;
648
	u32                     atomic_rd_en;
649
	u32			pkey_index;
650
	u32			qkey;
651 652
	void			(*event)(struct hns_roce_qp *qp,
					 enum hns_roce_event event_type);
653 654 655 656
	unsigned long		qpn;

	atomic_t		refcount;
	struct completion	free;
657 658 659

	struct hns_roce_sge	sge;
	u32			next_sge;
660 661
	enum ib_mtu		path_mtu;
	u32			max_inline_data;
662

663 664
	/* 0: flush needed, 1: unneeded */
	unsigned long		flush_flag;
665
	struct hns_roce_work	flush_work;
666
	struct hns_roce_rinl_buf rq_inl_buf;
667 668 669
	struct list_head	node;		/* all qps are on a list */
	struct list_head	rq_node;	/* all recv qps are on a list */
	struct list_head	sq_node;	/* all send qps are on a list */
670 671 672 673 674 675 676 677 678
};

struct hns_roce_ib_iboe {
	spinlock_t		lock;
	struct net_device      *netdevs[HNS_ROCE_MAX_PORTS];
	struct notifier_block	nb;
	u8			phy_port[HNS_ROCE_MAX_PORTS];
};

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Yixian Liu 已提交
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enum {
	HNS_ROCE_EQ_STAT_INVALID  = 0,
	HNS_ROCE_EQ_STAT_VALID    = 2,
};

struct hns_roce_ceqe {
685 686
	__le32	comp;
	__le32	rsv[15];
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};

struct hns_roce_aeqe {
690
	__le32 asyn;
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691 692
	union {
		struct {
693
			__le32 qp;
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			u32 rsv0;
			u32 rsv1;
		} qp_event;

698 699 700 701 702 703
		struct {
			__le32 srq;
			u32 rsv0;
			u32 rsv1;
		} srq_event;

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Yixian Liu 已提交
704
		struct {
705
			__le32 cq;
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Yixian Liu 已提交
706 707 708 709 710
			u32 rsv0;
			u32 rsv1;
		} cq_event;

		struct {
711
			__le32 ceqe;
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Yixian Liu 已提交
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			u32 rsv0;
			u32 rsv1;
		} ce_event;

		struct {
			__le64  out_param;
			__le16  token;
			u8	status;
			u8	rsv0;
		} __packed cmd;
	 } event;
723
	__le32 rsv[12];
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Yixian Liu 已提交
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};

726 727 728 729
struct hns_roce_eq {
	struct hns_roce_dev		*hr_dev;
	void __iomem			*doorbell;

730
	int				type_flag; /* Aeq:1 ceq:0 */
731 732 733 734 735 736 737 738
	int				eqn;
	u32				entries;
	int				log_entries;
	int				eqe_size;
	int				irq;
	int				log_page_size;
	int				cons_index;
	struct hns_roce_buf_list	*buf_list;
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Yixian Liu 已提交
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	int				over_ignore;
	int				coalesce;
	int				arm_st;
	int				hop_num;
743
	struct hns_roce_mtr		mtr;
744
	u16				eq_max_cnt;
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Yixian Liu 已提交
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	int				eq_period;
	int				shift;
747 748
	int				event_type;
	int				sub_type;
749 750 751 752
};

struct hns_roce_eq_table {
	struct hns_roce_eq	*eq;
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Yixian Liu 已提交
753
	void __iomem		**eqc_base; /* only for hw v1 */
754 755 756
};

struct hns_roce_caps {
757
	u64		fw_ver;
758 759 760 761 762 763
	u8		num_ports;
	int		gid_table_len[HNS_ROCE_MAX_PORTS];
	int		pkey_table_len[HNS_ROCE_MAX_PORTS];
	int		local_ca_ack_delay;
	int		num_uars;
	u32		phy_num_uars;
764 765 766
	u32		max_sq_sg;
	u32		max_sq_inline;
	u32		max_rq_sg;
767
	u32		max_extend_sg;
768
	int		num_qps;
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	int             reserved_qps;
770 771
	int		num_qpc_timer;
	int		num_cqc_timer;
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	int		num_srqs;
773
	u32		max_wqes;
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	u32		max_srq_wrs;
	u32		max_srq_sges;
776 777
	u32		max_sq_desc_sz;
	u32		max_rq_desc_sz;
778
	u32		max_srq_desc_sz;
779 780 781
	int		max_qp_init_rdma;
	int		max_qp_dest_rdma;
	int		num_cqs;
782 783
	u32		max_cqes;
	u32		min_cqes;
784
	u32		min_wqes;
785
	int		reserved_cqs;
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Lijun Ou 已提交
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	int		reserved_srqs;
787
	int		num_aeq_vectors;
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Yixian Liu 已提交
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	int		num_comp_vectors;
789 790 791
	int		num_other_vectors;
	int		num_mtpts;
	u32		num_mtt_segs;
792
	u32		num_cqe_segs;
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Lijun Ou 已提交
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	u32		num_srqwqe_segs;
	u32		num_idx_segs;
795 796 797 798 799
	int		reserved_mrws;
	int		reserved_uars;
	int		num_pds;
	int		reserved_pds;
	u32		mtt_entry_sz;
800
	u32		cqe_sz;
801 802 803
	u32		page_size_cap;
	u32		reserved_lkey;
	int		mtpt_entry_sz;
804
	int		qpc_sz;
805
	int		irrl_entry_sz;
806
	int		trrl_entry_sz;
807
	int		cqc_entry_sz;
808
	int		sccc_sz;
809 810
	int		qpc_timer_entry_sz;
	int		cqc_timer_entry_sz;
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Lijun Ou 已提交
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	int		srqc_entry_sz;
	int		idx_entry_sz;
813 814 815
	u32		pbl_ba_pg_sz;
	u32		pbl_buf_pg_sz;
	u32		pbl_hop_num;
816
	int		aeqe_depth;
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Yixian Liu 已提交
817
	int		ceqe_depth;
818 819
	u32		aeqe_size;
	u32		ceqe_size;
820
	enum ib_mtu	max_mtu;
821
	u32		qpc_bt_num;
822
	u32		qpc_timer_bt_num;
823 824
	u32		srqc_bt_num;
	u32		cqc_bt_num;
825
	u32		cqc_timer_bt_num;
826
	u32		mpt_bt_num;
827
	u32		sccc_bt_num;
828 829 830 831 832 833 834 835 836 837 838 839
	u32		qpc_ba_pg_sz;
	u32		qpc_buf_pg_sz;
	u32		qpc_hop_num;
	u32		srqc_ba_pg_sz;
	u32		srqc_buf_pg_sz;
	u32		srqc_hop_num;
	u32		cqc_ba_pg_sz;
	u32		cqc_buf_pg_sz;
	u32		cqc_hop_num;
	u32		mpt_ba_pg_sz;
	u32		mpt_buf_pg_sz;
	u32		mpt_hop_num;
840 841 842
	u32		mtt_ba_pg_sz;
	u32		mtt_buf_pg_sz;
	u32		mtt_hop_num;
843 844 845
	u32		wqe_sq_hop_num;
	u32		wqe_sge_hop_num;
	u32		wqe_rq_hop_num;
846 847 848
	u32		sccc_ba_pg_sz;
	u32		sccc_buf_pg_sz;
	u32		sccc_hop_num;
849 850 851 852 853 854
	u32		qpc_timer_ba_pg_sz;
	u32		qpc_timer_buf_pg_sz;
	u32		qpc_timer_hop_num;
	u32		cqc_timer_ba_pg_sz;
	u32		cqc_timer_buf_pg_sz;
	u32		cqc_timer_hop_num;
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Lang Cheng 已提交
855
	u32             cqe_ba_pg_sz;	/* page_size = 4K*(2^cqe_ba_pg_sz) */
856 857
	u32		cqe_buf_pg_sz;
	u32		cqe_hop_num;
858 859 860 861 862 863
	u32		srqwqe_ba_pg_sz;
	u32		srqwqe_buf_pg_sz;
	u32		srqwqe_hop_num;
	u32		idx_ba_pg_sz;
	u32		idx_buf_pg_sz;
	u32		idx_hop_num;
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Yixian Liu 已提交
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	u32		eqe_ba_pg_sz;
	u32		eqe_buf_pg_sz;
	u32		eqe_hop_num;
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oulijun 已提交
867 868
	u32		sl_num;
	u32		tsq_buf_pg_sz;
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869
	u32		tpq_buf_pg_sz;
870
	u32		chunk_sz;	/* chunk size in non multihop mode */
871
	u64		flags;
872 873 874 875 876 877
	u16		default_ceq_max_cnt;
	u16		default_ceq_period;
	u16		default_aeq_max_cnt;
	u16		default_aeq_period;
	u16		default_aeq_arm_st;
	u16		default_ceq_arm_st;
878 879
};

880 881 882 883 884
struct hns_roce_dfx_hw {
	int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
			      int *buffer);
};

885 886 887 888 889 890
enum hns_roce_device_state {
	HNS_ROCE_DEVICE_STATE_INITED,
	HNS_ROCE_DEVICE_STATE_RST_DOWN,
	HNS_ROCE_DEVICE_STATE_UNINIT,
};

891 892
struct hns_roce_hw {
	int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
893 894
	int (*cmq_init)(struct hns_roce_dev *hr_dev);
	void (*cmq_exit)(struct hns_roce_dev *hr_dev);
895
	int (*hw_profile)(struct hns_roce_dev *hr_dev);
896 897
	int (*hw_init)(struct hns_roce_dev *hr_dev);
	void (*hw_exit)(struct hns_roce_dev *hr_dev);
898 899 900 901
	int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
			 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
			 u16 token, int event);
	int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
902
	int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev);
903
	int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
904
		       const union ib_gid *gid, const struct ib_gid_attr *attr);
905
	int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
906 907
	void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
			enum ib_mtu mtu);
908 909
	int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
			  struct hns_roce_mr *mr, unsigned long mtpt_idx);
910 911 912 913
	int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
				struct hns_roce_mr *mr, int flags, u32 pdn,
				int mr_access_flags, u64 iova, u64 size,
				void *mb_buf);
914 915
	int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
			       struct hns_roce_mr *mr);
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Yixian Liu 已提交
916
	int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
917 918
	void (*write_cqc)(struct hns_roce_dev *hr_dev,
			  struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
919
			  dma_addr_t dma_handle);
920 921
	int (*set_hem)(struct hns_roce_dev *hr_dev,
		       struct hns_roce_hem_table *table, int obj, int step_idx);
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Wei Hu (Xavier) 已提交
922
	int (*clear_hem)(struct hns_roce_dev *hr_dev,
923 924
			 struct hns_roce_hem_table *table, int obj,
			 int step_idx);
925 926 927 928 929
	int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
			int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
	int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
			 int attr_mask, enum ib_qp_state cur_state,
			 enum ib_qp_state new_state);
930
	int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata);
931 932
	int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
			 struct hns_roce_qp *hr_qp);
933 934 935 936
	int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr,
			 const struct ib_send_wr **bad_wr);
	int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr,
			 const struct ib_recv_wr **bad_recv_wr);
937 938
	int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
	int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
939 940
	int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
			struct ib_udata *udata);
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Leon Romanovsky 已提交
941
	int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
942
	int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
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Yixian Liu 已提交
943 944
	int (*init_eq)(struct hns_roce_dev *hr_dev);
	void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
945 946 947 948 949 950 951 952 953 954 955
	void (*write_srqc)(struct hns_roce_dev *hr_dev,
			   struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn,
			   void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx,
			   dma_addr_t dma_handle_wqe,
			   dma_addr_t dma_handle_idx);
	int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
		       enum ib_srq_attr_mask srq_attr_mask,
		       struct ib_udata *udata);
	int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr);
	int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
			     const struct ib_recv_wr **bad_wr);
956 957
	const struct ib_device_ops *hns_roce_dev_ops;
	const struct ib_device_ops *hns_roce_dev_srq_ops;
958 959 960 961 962
};

struct hns_roce_dev {
	struct ib_device	ib_dev;
	struct platform_device  *pdev;
963 964
	struct pci_dev		*pci_dev;
	struct device		*dev;
965
	struct hns_roce_uar     priv_uar;
966
	const char		*irq_names[HNS_ROCE_MAX_IRQ_NUM];
967 968
	spinlock_t		sm_lock;
	spinlock_t		bt_cmd_lock;
969 970
	bool			active;
	bool			is_reset;
971
	bool			dis_db;
972
	unsigned long		reset_cnt;
973
	struct hns_roce_ib_iboe iboe;
974 975 976
	enum hns_roce_device_state state;
	struct list_head	qp_list; /* list of all qps on this dev */
	spinlock_t		qp_list_lock; /* protect qp_list */
977

978 979
	struct list_head        pgdir_list;
	struct mutex            pgdir_mutex;
980 981 982
	int			irq[HNS_ROCE_MAX_IRQ_NUM];
	u8 __iomem		*reg_base;
	struct hns_roce_caps	caps;
983
	struct xarray		qp_table_xa;
984

985
	unsigned char	dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
986 987 988 989 990 991 992 993 994 995 996
	u64			sys_image_guid;
	u32                     vendor_id;
	u32                     vendor_part_id;
	u32                     hw_rev;
	void __iomem            *priv_addr;

	struct hns_roce_cmdq	cmd;
	struct hns_roce_bitmap    pd_bitmap;
	struct hns_roce_uar_table uar_table;
	struct hns_roce_mr_table  mr_table;
	struct hns_roce_cq_table  cq_table;
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	struct hns_roce_srq_table srq_table;
998 999
	struct hns_roce_qp_table  qp_table;
	struct hns_roce_eq_table  eq_table;
1000 1001
	struct hns_roce_hem_table  qpc_timer_table;
	struct hns_roce_hem_table  cqc_timer_table;
1002 1003 1004

	int			cmd_mod;
	int			loop_idc;
1005 1006
	u32			sdb_offset;
	u32			odb_offset;
1007 1008
	dma_addr_t		tptr_dma_addr;	/* only for hw v1 */
	u32			tptr_size;	/* only for hw v1 */
1009
	const struct hns_roce_hw *hw;
1010
	void			*priv;
1011
	struct workqueue_struct *irq_workq;
1012
	const struct hns_roce_dfx_hw *dfx;
1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040
};

static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
{
	return container_of(ib_dev, struct hns_roce_dev, ib_dev);
}

static inline struct hns_roce_ucontext
			*to_hr_ucontext(struct ib_ucontext *ibucontext)
{
	return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
}

static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
{
	return container_of(ibpd, struct hns_roce_pd, ibpd);
}

static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
{
	return container_of(ibah, struct hns_roce_ah, ibah);
}

static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
{
	return container_of(ibmr, struct hns_roce_mr, ibmr);
}

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Yixian Liu 已提交
1041 1042 1043 1044 1045
static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
{
	return container_of(ibmw, struct hns_roce_mw, ibmw);
}

1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060
static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
{
	return container_of(ibqp, struct hns_roce_qp, ibqp);
}

static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
{
	return container_of(ib_cq, struct hns_roce_cq, ib_cq);
}

static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
{
	return container_of(ibsrq, struct hns_roce_srq, ibsrq);
}

1061
static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1062 1063 1064 1065 1066 1067 1068
{
	__raw_writeq(*(u64 *) val, dest);
}

static inline struct hns_roce_qp
	*__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
{
1069
	return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1));
1070 1071
}

1072 1073 1074 1075 1076 1077 1078 1079
static inline bool hns_roce_buf_is_direct(struct hns_roce_buf *buf)
{
	if (buf->page_list)
		return false;

	return true;
}

1080 1081
static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
{
1082 1083
	if (hns_roce_buf_is_direct(buf))
		return (char *)(buf->direct.buf) + (offset & (buf->size - 1));
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1085 1086 1087 1088 1089 1090 1091 1092
	return (char *)(buf->page_list[offset >> buf->page_shift].buf) +
	       (offset & ((1 << buf->page_shift) - 1));
}

static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, int idx)
{
	if (hns_roce_buf_is_direct(buf))
		return buf->direct.map + ((dma_addr_t)idx << buf->page_shift);
1093
	else
1094
		return buf->page_list[idx].map;
1095 1096
}

1097
#define hr_hw_page_align(x)		ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1098

1099 1100
static inline u64 to_hr_hw_page_addr(u64 addr)
{
1101
	return addr >> HNS_HW_PAGE_SHIFT;
1102 1103 1104 1105
}

static inline u32 to_hr_hw_page_shift(u32 page_shift)
{
1106
	return page_shift - HNS_HW_PAGE_SHIFT;
1107 1108
}

1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128
static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
{
	if (count > 0)
		return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;

	return 0;
}

static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
{
	return hr_hw_page_align(count << buf_shift);
}

static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
{
	return hr_hw_page_align(count << buf_shift) >> buf_shift;
}

static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
{
1129 1130 1131
	if (!count)
		return 0;

1132 1133 1134
	return ilog2(to_hr_hem_entries_count(count, buf_shift));
}

1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146
int hns_roce_init_uar_table(struct hns_roce_dev *dev);
int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);

int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
			u64 out_param);
int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);

1147 1148 1149 1150
/* hns roce hw need current block and next block addr from mtt */
#define MTT_MIN_COUNT	 2
int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
		      int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1151
int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1152 1153 1154
			struct hns_roce_buf_attr *buf_attr,
			unsigned int page_shift, struct ib_udata *udata,
			unsigned long user_addr);
1155 1156 1157 1158
void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
			  struct hns_roce_mtr *mtr);
int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
		     dma_addr_t *pages, int page_cnt);
1159

1160 1161 1162 1163
int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
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Lijun Ou 已提交
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int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1165 1166 1167 1168 1169 1170

void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
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Lijun Ou 已提交
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void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev);
1172 1173

int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
1174 1175
void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
			 int rr);
1176 1177 1178 1179 1180 1181 1182
int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
			 u32 reserved_bot, u32 resetrved_top);
void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
				int align, unsigned long *obj);
void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
1183 1184
				unsigned long obj, int cnt,
				int rr);
1185

1186 1187
int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
		       struct ib_udata *udata);
1188
int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1189 1190 1191 1192
static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
{
	return 0;
}
1193

1194
int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1195
int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1196 1197 1198 1199 1200

struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
				   u64 virt_addr, int access_flags,
				   struct ib_udata *udata);
1201 1202 1203
int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length,
			   u64 virt_addr, int mr_access_flags, struct ib_pd *pd,
			   struct ib_udata *udata);
Y
Yixian Liu 已提交
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struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1205
				u32 max_num_sg);
Y
Yixian Liu 已提交
1206 1207
int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
		       unsigned int *sg_offset);
1208
int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1209 1210 1211
int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
			    struct hns_roce_cmd_mailbox *mailbox,
			    unsigned long mpt_index);
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Shaobo Xu 已提交
1212
unsigned long key_to_hw_index(u32 key);
1213

1214
int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
Y
Yixian Liu 已提交
1215 1216
int hns_roce_dealloc_mw(struct ib_mw *ibmw);

1217
void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1218
int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
1219
		       struct hns_roce_buf *buf, u32 page_shift);
1220

1221 1222 1223 1224
int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
			   int buf_cnt, int start, struct hns_roce_buf *buf);
int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
			   int buf_cnt, int start, struct ib_umem *umem,
1225
			   unsigned int page_shift);
1226

1227 1228 1229
int hns_roce_create_srq(struct ib_srq *srq,
			struct ib_srq_init_attr *srq_init_attr,
			struct ib_udata *udata);
1230 1231 1232
int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
			enum ib_srq_attr_mask srq_attr_mask,
			struct ib_udata *udata);
1233
int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1234

1235 1236 1237 1238 1239
struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
				 struct ib_qp_init_attr *init_attr,
				 struct ib_udata *udata);
int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
		       int attr_mask, struct ib_udata *udata);
1240
void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1241 1242 1243
void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n);
void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n);
1244 1245 1246 1247 1248 1249 1250 1251
bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
			  struct ib_cq *ib_cq);
enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
		       struct hns_roce_cq *recv_cq);
void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
			 struct hns_roce_cq *recv_cq);
void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
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Xi Wang 已提交
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void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
			 struct ib_udata *udata);
1254
__be32 send_ieth(const struct ib_send_wr *wr);
1255 1256
int to_hr_qp_type(int qp_type);

1257 1258
int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
		       struct ib_udata *udata);
1259

L
Leon Romanovsky 已提交
1260
int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1261 1262
int hns_roce_db_map_user(struct hns_roce_ucontext *context,
			 struct ib_udata *udata, unsigned long virt,
1263 1264 1265
			 struct hns_roce_db *db);
void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
			    struct hns_roce_db *db);
1266 1267 1268 1269
int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
		      int order);
void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);

1270 1271 1272
void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1273
void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1274
int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
1275
void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1276 1277
int hns_roce_init(struct hns_roce_dev *hr_dev);
void hns_roce_exit(struct hns_roce_dev *hr_dev);
1278

1279 1280
int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
			       struct ib_cq *ib_cq);
1281
#endif /* _HNS_ROCE_DEVICE_H */