netxen_nic.h 44.8 KB
Newer Older
A
Amit S. Kale 已提交
1 2 3
/*
 * Copyright (C) 2003 - 2006 NetXen, Inc.
 * All rights reserved.
4
 *
A
Amit S. Kale 已提交
5 6 7 8
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
9
 *
A
Amit S. Kale 已提交
10 11 12 13
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
14
 *
A
Amit S. Kale 已提交
15 16 17 18
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
 * MA  02111-1307, USA.
19
 *
A
Amit S. Kale 已提交
20 21
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.
22
 *
A
Amit S. Kale 已提交
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65
 * Contact Information:
 *    info@netxen.com
 * NetXen,
 * 3965 Freedom Circle, Fourth floor,
 * Santa Clara, CA 95054
 */

#ifndef _NETXEN_NIC_H_
#define _NETXEN_NIC_H_

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/compiler.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ip.h>
#include <linux/in.h>
#include <linux/tcp.h>
#include <linux/skbuff.h>
#include <linux/version.h>

#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/interrupt.h>
#include <linux/timer.h>

#include <linux/mm.h>
#include <linux/mman.h>

#include <asm/system.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <asm/uaccess.h>
#include <asm/pgtable.h>

#include "netxen_nic_hw.h"

66
#define _NETXEN_NIC_LINUX_MAJOR 3
67
#define _NETXEN_NIC_LINUX_MINOR 4
68 69
#define _NETXEN_NIC_LINUX_SUBVERSION 18
#define NETXEN_NIC_LINUX_VERSIONID  "3.4.18"
70

71 72 73 74
#define NETXEN_NUM_FLASH_SECTORS (64)
#define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
#define NETXEN_FLASH_TOTAL_SIZE  (NETXEN_NUM_FLASH_SECTORS \
					* NETXEN_FLASH_SECTOR_SIZE)
A
Amit S. Kale 已提交
75

76 77
#define PHAN_VENDOR_ID 0x4040

A
Amit S. Kale 已提交
78 79 80 81
#define RCV_DESC_RINGSIZE	\
	(sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
#define STATUS_DESC_RINGSIZE	\
	(sizeof(struct status_desc)* adapter->max_rx_desc_count)
82 83
#define LRO_DESC_RINGSIZE	\
	(sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
A
Amit S. Kale 已提交
84 85 86
#define TX_RINGSIZE	\
	(sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
#define RCV_BUFFSIZE	\
D
Dhananjay Phadke 已提交
87
	(sizeof(struct netxen_rx_buffer) * rds_ring->max_rx_desc_count)
88
#define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
A
Amit S. Kale 已提交
89

90 91 92 93
#define NETXEN_NETDEV_STATUS		0x1
#define NETXEN_RCV_PRODUCER_OFFSET	0
#define NETXEN_RCV_PEG_DB_ID		2
#define NETXEN_HOST_DUMMY_DMA_SIZE 1024
94
#define FLASH_SUCCESS 0
A
Amit S. Kale 已提交
95 96 97 98

#define ADDR_IN_WINDOW1(off)	\
	((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0

99 100
/*
 * normalize a 64MB crb address to 32MB PCI window
A
Amit S. Kale 已提交
101 102
 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
 */
103 104
#define NETXEN_CRB_NORMAL(reg)	\
	((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
105

A
Amit S. Kale 已提交
106
#define NETXEN_CRB_NORMALIZE(adapter, reg) \
107 108
	pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))

109 110 111 112 113
#define DB_NORMALIZE(adapter, off) \
	(adapter->ahw.db_base + (off))

#define NX_P2_C0		0x24
#define NX_P2_C1		0x25
114 115 116 117 118 119 120
#define NX_P3_A0		0x30
#define NX_P3_A2		0x30
#define NX_P3_B0		0x40
#define NX_P3_B1		0x41

#define NX_IS_REVISION_P2(REVISION)     (REVISION <= NX_P2_C1)
#define NX_IS_REVISION_P3(REVISION)     (REVISION >= NX_P3_A0)
121

122
#define FIRST_PAGE_GROUP_START	0
123
#define FIRST_PAGE_GROUP_END	0x100000
124

125 126
#define SECOND_PAGE_GROUP_START	0x6000000
#define SECOND_PAGE_GROUP_END	0x68BC000
127 128 129 130 131 132 133

#define THIRD_PAGE_GROUP_START	0x70E4000
#define THIRD_PAGE_GROUP_END	0x8000000

#define FIRST_PAGE_GROUP_SIZE  FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
#define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
#define THIRD_PAGE_GROUP_SIZE  THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
A
Amit S. Kale 已提交
134

135 136 137 138 139 140 141 142
#define P2_MAX_MTU                     (8000)
#define P3_MAX_MTU                     (9600)
#define NX_ETHERMTU                    1500
#define NX_MAX_ETHERHDR                32 /* This contains some padding */

#define NX_RX_NORMAL_BUF_MAX_LEN       (NX_MAX_ETHERHDR + NX_ETHERMTU)
#define NX_P2_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P2_MAX_MTU)
#define NX_P3_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P3_MAX_MTU)
143
#define NX_CT_DEFAULT_RX_BUF_LEN	2048
144

145
#define MAX_RX_BUFFER_LENGTH		1760
146
#define MAX_RX_JUMBO_BUFFER_LENGTH 	8062
147 148
#define MAX_RX_LRO_BUFFER_LENGTH	((48*1024)-512)
#define RX_DMA_MAP_LEN			(MAX_RX_BUFFER_LENGTH - 2)
A
Amit S. Kale 已提交
149
#define RX_JUMBO_DMA_MAP_LEN	\
150 151
	(MAX_RX_JUMBO_BUFFER_LENGTH - 2)
#define RX_LRO_DMA_MAP_LEN		(MAX_RX_LRO_BUFFER_LENGTH - 2)
A
Amit S. Kale 已提交
152 153 154 155 156 157 158

/*
 * Maximum number of ring contexts
 */
#define MAX_RING_CTX 1

/* Opcodes to be used with the commands */
159 160 161 162 163 164 165 166 167 168
#define TX_ETHER_PKT	0x01
#define TX_TCP_PKT	0x02
#define TX_UDP_PKT	0x03
#define TX_IP_PKT	0x04
#define TX_TCP_LSO	0x05
#define TX_TCP_LSO6	0x06
#define TX_IPSEC	0x07
#define TX_IPSEC_CMD	0x0a
#define TX_TCPV6_PKT	0x0b
#define TX_UDPV6_PKT	0x0c
A
Amit S. Kale 已提交
169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188

/* The following opcodes are for internal consumption. */
#define NETXEN_CONTROL_OP	0x10
#define PEGNET_REQUEST		0x11

#define	MAX_NUM_CARDS		4

#define MAX_BUFFERS_PER_CMD	32

/*
 * Following are the states of the Phantom. Phantom will set them and
 * Host will read to check if the fields are correct.
 */
#define PHAN_INITIALIZE_START		0xff00
#define PHAN_INITIALIZE_FAILED		0xffff
#define PHAN_INITIALIZE_COMPLETE	0xff01

/* Host writes the following to notify that it has done the init-handshake */
#define PHAN_INITIALIZE_ACK	0xf00f

189
#define NUM_RCV_DESC_RINGS	3	/* No of Rcv Descriptor contexts */
A
Amit S. Kale 已提交
190 191 192 193

/* descriptor types */
#define RCV_DESC_NORMAL		0x01
#define RCV_DESC_JUMBO		0x02
194
#define RCV_DESC_LRO		0x04
A
Amit S. Kale 已提交
195 196
#define RCV_DESC_NORMAL_CTXID	0
#define RCV_DESC_JUMBO_CTXID	1
197
#define RCV_DESC_LRO_CTXID	2
A
Amit S. Kale 已提交
198 199

#define RCV_DESC_TYPE(ID) \
200 201 202 203 204
	((ID == RCV_DESC_JUMBO_CTXID)	\
		? RCV_DESC_JUMBO	\
		: ((ID == RCV_DESC_LRO_CTXID)	\
			? RCV_DESC_LRO :	\
			(RCV_DESC_NORMAL)))
A
Amit S. Kale 已提交
205

206
#define MAX_CMD_DESCRIPTORS		4096
207
#define MAX_RCV_DESCRIPTORS		16384
208
#define MAX_CMD_DESCRIPTORS_HOST	(MAX_CMD_DESCRIPTORS / 4)
209
#define MAX_RCV_DESCRIPTORS_1G		(MAX_RCV_DESCRIPTORS / 4)
210
#define MAX_RCV_DESCRIPTORS_10G		8192
211 212
#define MAX_JUMBO_RCV_DESCRIPTORS	1024
#define MAX_LRO_RCV_DESCRIPTORS		64
A
Amit S. Kale 已提交
213 214 215 216 217
#define MAX_RCVSTATUS_DESCRIPTORS	MAX_RCV_DESCRIPTORS
#define MAX_JUMBO_RCV_DESC	MAX_JUMBO_RCV_DESCRIPTORS
#define MAX_RCV_DESC		MAX_RCV_DESCRIPTORS
#define MAX_RCVSTATUS_DESC	MAX_RCV_DESCRIPTORS
#define MAX_EPG_DESCRIPTORS	(MAX_CMD_DESCRIPTORS * 8)
218 219
#define NUM_RCV_DESC		(MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
				 MAX_LRO_RCV_DESCRIPTORS)
A
Amit S. Kale 已提交
220 221
#define MIN_TX_COUNT	4096
#define MIN_RX_COUNT	4096
222 223
#define NETXEN_CTX_SIGNATURE	0xdee0
#define NETXEN_RCV_PRODUCER(ringid)	(ringid)
A
Amit S. Kale 已提交
224 225 226 227 228 229 230 231 232 233 234
#define MAX_FRAME_SIZE	0x10000	/* 64K MAX size for LSO */

#define PHAN_PEG_RCV_INITIALIZED	0xff01
#define PHAN_PEG_RCV_START_INITIALIZE	0xff00

#define get_next_index(index, length)	\
	(((index) + 1) & ((length) - 1))

#define get_index_range(index,length,count)	\
	(((index) + (count)) & ((length) - 1))

235
#define MPORT_SINGLE_FUNCTION_MODE 0x1111
236
#define MPORT_MULTI_FUNCTION_MODE 0x2222
237

238
#include "netxen_nic_phan_reg.h"
239 240 241 242 243 244 245 246 247 248 249 250 251 252

/*
 * NetXen host-peg signal message structure
 *
 *	Bit 0-1		: peg_id => 0x2 for tx and 01 for rx
 *	Bit 2		: priv_id => must be 1
 *	Bit 3-17	: count => for doorbell
 *	Bit 18-27	: ctx_id => Context id
 *	Bit 28-31	: opcode
 */

typedef u32 netxen_ctx_msg;

#define netxen_set_msg_peg_id(config_word, val)	\
A
Al Viro 已提交
253
	((config_word) &= ~3, (config_word) |= val & 3)
254
#define netxen_set_msg_privid(config_word)	\
A
Al Viro 已提交
255
	((config_word) |= 1 << 2)
256
#define netxen_set_msg_count(config_word, val)	\
A
Al Viro 已提交
257
	((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
258
#define netxen_set_msg_ctxid(config_word, val)	\
A
Al Viro 已提交
259
	((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
260
#define netxen_set_msg_opcode(config_word, val)	\
261
	((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
262 263

struct netxen_rcv_context {
A
Al Viro 已提交
264 265 266
	__le64 rcv_ring_addr;
	__le32 rcv_ring_size;
	__le32 rsrvd;
267 268 269 270 271
};

struct netxen_ring_ctx {

	/* one command ring */
A
Al Viro 已提交
272 273 274 275
	__le64 cmd_consumer_offset;
	__le64 cmd_ring_addr;
	__le32 cmd_ring_size;
	__le32 rsrvd;
276 277 278 279 280

	/* three receive rings */
	struct netxen_rcv_context rcv_ctx[3];

	/* one status ring */
A
Al Viro 已提交
281 282
	__le64 sts_ring_addr;
	__le32 sts_ring_size;
283

A
Al Viro 已提交
284
	__le32 ctx_id;
285 286
} __attribute__ ((aligned(64)));

A
Amit S. Kale 已提交
287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303
/*
 * Following data structures describe the descriptors that will be used.
 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
 * we are doing LSO (above the 1500 size packet) only.
 */

/*
 * The size of reference handle been changed to 16 bits to pass the MSS fields
 * for the LSO packet
 */

#define FLAGS_CHECKSUM_ENABLED	0x01
#define FLAGS_LSO_ENABLED	0x02
#define FLAGS_IPSEC_SA_ADD	0x04
#define FLAGS_IPSEC_SA_DELETE	0x08
#define FLAGS_VLAN_TAGGED	0x10

304 305
#define netxen_set_cmd_desc_port(cmd_desc, var)	\
	((cmd_desc)->port_ctxid |= ((var) & 0x0F))
306
#define netxen_set_cmd_desc_ctxid(cmd_desc, var)	\
D
Dhananjay Phadke 已提交
307
	((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
A
Amit S. Kale 已提交
308

309
#define netxen_set_cmd_desc_flags(cmd_desc, val)	\
310 311
	(cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \
		~cpu_to_le16(0x7f)) | cpu_to_le16((val) & 0x7f)
312
#define netxen_set_cmd_desc_opcode(cmd_desc, val)	\
313 314
	(cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \
		~cpu_to_le16((u16)0x3f << 7)) | cpu_to_le16(((val) & 0x3f) << 7)
315 316

#define netxen_set_cmd_desc_num_of_buff(cmd_desc, val)	\
317 318 319
	(cmd_desc)->num_of_buffers_total_length = \
		((cmd_desc)->num_of_buffers_total_length & \
		~cpu_to_le32(0xff)) | cpu_to_le32((val) & 0xff)
320
#define netxen_set_cmd_desc_totallength(cmd_desc, val)	\
321 322 323 324
	(cmd_desc)->num_of_buffers_total_length = \
		((cmd_desc)->num_of_buffers_total_length & \
		~cpu_to_le32((u32)0xffffff << 8)) | \
		cpu_to_le32(((val) & 0xffffff) << 8)
325 326

#define netxen_get_cmd_desc_opcode(cmd_desc)	\
327
	((le16_to_cpu((cmd_desc)->flags_opcode) >> 7) & 0x003f)
328
#define netxen_get_cmd_desc_totallength(cmd_desc)	\
329
	((le32_to_cpu((cmd_desc)->num_of_buffers_total_length) >> 8) & 0xffffff)
A
Amit S. Kale 已提交
330 331

struct cmd_desc_type0 {
332 333 334
	u8 tcp_hdr_offset;	/* For LSO only */
	u8 ip_hdr_offset;	/* For LSO only */
	/* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
A
Al Viro 已提交
335
	__le16 flags_opcode;
336 337
	/* Bit pattern: 0-7 total number of segments,
	   8-31 Total size of the packet */
A
Al Viro 已提交
338
	__le32 num_of_buffers_total_length;
A
Amit S. Kale 已提交
339 340
	union {
		struct {
A
Al Viro 已提交
341 342
			__le32 addr_low_part2;
			__le32 addr_high_part2;
A
Amit S. Kale 已提交
343
		};
A
Al Viro 已提交
344
		__le64 addr_buffer2;
A
Amit S. Kale 已提交
345 346
	};

A
Al Viro 已提交
347 348
	__le16 reference_handle;	/* changed to u16 to add mss */
	__le16 mss;		/* passed by NDIS_PACKET for LSO */
A
Amit S. Kale 已提交
349 350 351
	/* Bit pattern 0-3 port, 0-3 ctx id */
	u8 port_ctxid;
	u8 total_hdr_length;	/* LSO only : MAC+IP+TCP Hdr size */
A
Al Viro 已提交
352
	__le16 conn_id;		/* IPSec offoad only */
A
Amit S. Kale 已提交
353 354 355

	union {
		struct {
A
Al Viro 已提交
356 357
			__le32 addr_low_part3;
			__le32 addr_high_part3;
A
Amit S. Kale 已提交
358
		};
A
Al Viro 已提交
359
		__le64 addr_buffer3;
A
Amit S. Kale 已提交
360 361 362
	};
	union {
		struct {
A
Al Viro 已提交
363 364
			__le32 addr_low_part1;
			__le32 addr_high_part1;
A
Amit S. Kale 已提交
365
		};
A
Al Viro 已提交
366
		__le64 addr_buffer1;
A
Amit S. Kale 已提交
367 368
	};

A
Al Viro 已提交
369 370 371 372
	__le16 buffer1_length;
	__le16 buffer2_length;
	__le16 buffer3_length;
	__le16 buffer4_length;
A
Amit S. Kale 已提交
373 374 375

	union {
		struct {
A
Al Viro 已提交
376 377
			__le32 addr_low_part4;
			__le32 addr_high_part4;
A
Amit S. Kale 已提交
378
		};
A
Al Viro 已提交
379
		__le64 addr_buffer4;
A
Amit S. Kale 已提交
380 381
	};

A
Al Viro 已提交
382
	__le64 unused;
383

A
Amit S. Kale 已提交
384 385 386 387
} __attribute__ ((aligned(64)));

/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
struct rcv_desc {
A
Al Viro 已提交
388 389 390 391
	__le16 reference_handle;
	__le16 reserved;
	__le32 buffer_length;	/* allocated buffer length (usually 2K) */
	__le64 addr_buffer;
A
Amit S. Kale 已提交
392 393 394
};

/* opcode field in status_desc */
395 396
#define NETXEN_NIC_RXPKT_DESC  0x04
#define NETXEN_OLD_RXPKT_DESC  0x3f
A
Amit S. Kale 已提交
397 398 399 400 401 402 403 404 405 406 407 408 409

/* for status field in status_desc */
#define STATUS_NEED_CKSUM	(1)
#define STATUS_CKSUM_OK		(2)

/* owner bits of status_desc */
#define STATUS_OWNER_HOST	(0x1)
#define STATUS_OWNER_PHANTOM	(0x2)

#define NETXEN_PROT_IP		(1)
#define NETXEN_PROT_UNKNOWN	(0)

/* Note: sizeof(status_desc) should always be a mutliple of 2 */
410 411 412 413 414 415

#define netxen_get_sts_desc_lro_cnt(status_desc)	\
	((status_desc)->lro & 0x7F)
#define netxen_get_sts_desc_lro_last_frag(status_desc)	\
	(((status_desc)->lro & 0x80) >> 7)

416 417 418 419 420 421 422 423 424 425 426 427
#define netxen_get_sts_port(sts_data)	\
	((sts_data) & 0x0F)
#define netxen_get_sts_status(sts_data)	\
	(((sts_data) >> 4) & 0x0F)
#define netxen_get_sts_type(sts_data)	\
	(((sts_data) >> 8) & 0x0F)
#define netxen_get_sts_totallength(sts_data)	\
	(((sts_data) >> 12) & 0xFFFF)
#define netxen_get_sts_refhandle(sts_data)	\
	(((sts_data) >> 28) & 0xFFFF)
#define netxen_get_sts_prot(sts_data)	\
	(((sts_data) >> 44) & 0x0F)
428 429
#define netxen_get_sts_pkt_offset(sts_data)	\
	(((sts_data) >> 48) & 0x1F)
430 431 432
#define netxen_get_sts_opcode(sts_data)	\
	(((sts_data) >> 58) & 0x03F)

433
#define netxen_get_sts_owner(status_desc)	\
A
Al Viro 已提交
434
	((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03)
435 436 437 438 439 440
#define netxen_set_sts_owner(status_desc, val)	{ \
	(status_desc)->status_desc_data = \
		((status_desc)->status_desc_data & \
		~cpu_to_le64(0x3ULL << 56)) | \
		cpu_to_le64((u64)((val) & 0x3) << 56); \
}
A
Amit S. Kale 已提交
441 442

struct status_desc {
443
	/* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
444
	   28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
445 446
	   53-55 desc_cnt, 56-57 owner, 58-63 opcode
	 */
A
Al Viro 已提交
447
	__le64 status_desc_data;
448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467
	union {
		struct {
			__le32 hash_value;
			u8 hash_type;
			u8 msg_type;
			u8 unused;
			union {
				/* Bit pattern: 0-6 lro_count indicates frag
				 * sequence, 7 last_frag indicates last frag
				 */
				u8 lro;

				/* chained buffers */
				u8 nr_frags;
			};
		};
		struct {
			__le16 frag_handles[4];
		};
	};
468
} __attribute__ ((aligned(16)));
A
Amit S. Kale 已提交
469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496

enum {
	NETXEN_RCV_PEG_0 = 0,
	NETXEN_RCV_PEG_1
};
/* The version of the main data structure */
#define	NETXEN_BDINFO_VERSION 1

/* Magic number to let user know flash is programmed */
#define	NETXEN_BDINFO_MAGIC 0x12345678

/* Max number of Gig ports on a Phantom board */
#define NETXEN_MAX_PORTS 4

typedef enum {
	NETXEN_BRDTYPE_P1_BD = 0x0000,
	NETXEN_BRDTYPE_P1_SB = 0x0001,
	NETXEN_BRDTYPE_P1_SMAX = 0x0002,
	NETXEN_BRDTYPE_P1_SOCK = 0x0003,

	NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
	NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
	NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
	NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
	NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,

	NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
	NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
497 498 499 500 501 502 503 504 505 506 507 508 509 510
	NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f,

	NETXEN_BRDTYPE_P3_REF_QG = 0x0021,
	NETXEN_BRDTYPE_P3_HMEZ = 0x0022,
	NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023,
	NETXEN_BRDTYPE_P3_4_GB = 0x0024,
	NETXEN_BRDTYPE_P3_IMEZ = 0x0025,
	NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026,
	NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027,
	NETXEN_BRDTYPE_P3_XG_LOM = 0x0028,
	NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029,
	NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031,
	NETXEN_BRDTYPE_P3_10G_XFP = 0x0032

A
Amit S. Kale 已提交
511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709
} netxen_brdtype_t;

typedef enum {
	NETXEN_BRDMFG_INVENTEC = 1
} netxen_brdmfg;

typedef enum {
	MEM_ORG_128Mbx4 = 0x0,	/* DDR1 only */
	MEM_ORG_128Mbx8 = 0x1,	/* DDR1 only */
	MEM_ORG_128Mbx16 = 0x2,	/* DDR1 only */
	MEM_ORG_256Mbx4 = 0x3,
	MEM_ORG_256Mbx8 = 0x4,
	MEM_ORG_256Mbx16 = 0x5,
	MEM_ORG_512Mbx4 = 0x6,
	MEM_ORG_512Mbx8 = 0x7,
	MEM_ORG_512Mbx16 = 0x8,
	MEM_ORG_1Gbx4 = 0x9,
	MEM_ORG_1Gbx8 = 0xa,
	MEM_ORG_1Gbx16 = 0xb,
	MEM_ORG_2Gbx4 = 0xc,
	MEM_ORG_2Gbx8 = 0xd,
	MEM_ORG_2Gbx16 = 0xe,
	MEM_ORG_128Mbx32 = 0x10002,	/* GDDR only */
	MEM_ORG_256Mbx32 = 0x10005	/* GDDR only */
} netxen_mn_mem_org_t;

typedef enum {
	MEM_ORG_512Kx36 = 0x0,
	MEM_ORG_1Mx36 = 0x1,
	MEM_ORG_2Mx36 = 0x2
} netxen_sn_mem_org_t;

typedef enum {
	MEM_DEPTH_4MB = 0x1,
	MEM_DEPTH_8MB = 0x2,
	MEM_DEPTH_16MB = 0x3,
	MEM_DEPTH_32MB = 0x4,
	MEM_DEPTH_64MB = 0x5,
	MEM_DEPTH_128MB = 0x6,
	MEM_DEPTH_256MB = 0x7,
	MEM_DEPTH_512MB = 0x8,
	MEM_DEPTH_1GB = 0x9,
	MEM_DEPTH_2GB = 0xa,
	MEM_DEPTH_4GB = 0xb,
	MEM_DEPTH_8GB = 0xc,
	MEM_DEPTH_16GB = 0xd,
	MEM_DEPTH_32GB = 0xe
} netxen_mem_depth_t;

struct netxen_board_info {
	u32 header_version;

	u32 board_mfg;
	u32 board_type;
	u32 board_num;
	u32 chip_id;
	u32 chip_minor;
	u32 chip_major;
	u32 chip_pkg;
	u32 chip_lot;

	u32 port_mask;		/* available niu ports */
	u32 peg_mask;		/* available pegs */
	u32 icache_ok;		/* can we run with icache? */
	u32 dcache_ok;		/* can we run with dcache? */
	u32 casper_ok;

	u32 mac_addr_lo_0;
	u32 mac_addr_lo_1;
	u32 mac_addr_lo_2;
	u32 mac_addr_lo_3;

	/* MN-related config */
	u32 mn_sync_mode;	/* enable/ sync shift cclk/ sync shift mclk */
	u32 mn_sync_shift_cclk;
	u32 mn_sync_shift_mclk;
	u32 mn_wb_en;
	u32 mn_crystal_freq;	/* in MHz */
	u32 mn_speed;		/* in MHz */
	u32 mn_org;
	u32 mn_depth;
	u32 mn_ranks_0;		/* ranks per slot */
	u32 mn_ranks_1;		/* ranks per slot */
	u32 mn_rd_latency_0;
	u32 mn_rd_latency_1;
	u32 mn_rd_latency_2;
	u32 mn_rd_latency_3;
	u32 mn_rd_latency_4;
	u32 mn_rd_latency_5;
	u32 mn_rd_latency_6;
	u32 mn_rd_latency_7;
	u32 mn_rd_latency_8;
	u32 mn_dll_val[18];
	u32 mn_mode_reg;	/* MIU DDR Mode Register */
	u32 mn_ext_mode_reg;	/* MIU DDR Extended Mode Register */
	u32 mn_timing_0;	/* MIU Memory Control Timing Rgister */
	u32 mn_timing_1;	/* MIU Extended Memory Ctrl Timing Register */
	u32 mn_timing_2;	/* MIU Extended Memory Ctrl Timing2 Register */

	/* SN-related config */
	u32 sn_sync_mode;	/* enable/ sync shift cclk / sync shift mclk */
	u32 sn_pt_mode;		/* pass through mode */
	u32 sn_ecc_en;
	u32 sn_wb_en;
	u32 sn_crystal_freq;
	u32 sn_speed;
	u32 sn_org;
	u32 sn_depth;
	u32 sn_dll_tap;
	u32 sn_rd_latency;

	u32 mac_addr_hi_0;
	u32 mac_addr_hi_1;
	u32 mac_addr_hi_2;
	u32 mac_addr_hi_3;

	u32 magic;		/* indicates flash has been initialized */

	u32 mn_rdimm;
	u32 mn_dll_override;

};

#define FLASH_NUM_PORTS		(4)

struct netxen_flash_mac_addr {
	u32 flash_addr[32];
};

struct netxen_user_old_info {
	u8 flash_md5[16];
	u8 crbinit_md5[16];
	u8 brdcfg_md5[16];
	/* bootloader */
	u32 bootld_version;
	u32 bootld_size;
	u8 bootld_md5[16];
	/* image */
	u32 image_version;
	u32 image_size;
	u8 image_md5[16];
	/* primary image status */
	u32 primary_status;
	u32 secondary_present;

	/* MAC address , 4 ports */
	struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
};
#define FLASH_NUM_MAC_PER_PORT	32
struct netxen_user_info {
	u8 flash_md5[16 * 64];
	/* bootloader */
	u32 bootld_version;
	u32 bootld_size;
	/* image */
	u32 image_version;
	u32 image_size;
	/* primary image status */
	u32 primary_status;
	u32 secondary_present;

	/* MAC address , 4 ports, 32 address per port */
	u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
	u32 sub_sys_id;
	u8 serial_num[32];

	/* Any user defined data */
};

/*
 * Flash Layout - new format.
 */
struct netxen_new_user_info {
	u8 flash_md5[16 * 64];
	/* bootloader */
	u32 bootld_version;
	u32 bootld_size;
	/* image */
	u32 image_version;
	u32 image_size;
	/* primary image status */
	u32 primary_status;
	u32 secondary_present;

	/* MAC address , 4 ports, 32 address per port */
	u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
	u32 sub_sys_id;
	u8 serial_num[32];

	/* Any user defined data */
};

#define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
#define SECONDARY_IMAGE_ABSENT	0xffffffff
#define PRIMARY_IMAGE_GOOD	0x5a5a5a5a
#define PRIMARY_IMAGE_BAD	0xffffffff

/* Flash memory map */
typedef enum {
710 711 712 713 714 715 716 717 718
	NETXEN_CRBINIT_START = 0,	/* Crbinit section */
	NETXEN_BRDCFG_START = 0x4000,	/* board config */
	NETXEN_INITCODE_START = 0x6000,	/* pegtune code */
	NETXEN_BOOTLD_START = 0x10000,	/* bootld */
	NETXEN_IMAGE_START = 0x43000,	/* compressed image */
	NETXEN_SECONDARY_START = 0x200000,	/* backup images */
	NETXEN_PXE_START = 0x3E0000,	/* user defined region */
	NETXEN_USER_START = 0x3E8000,	/* User defined region for new boards */
	NETXEN_FIXED_START = 0x3F0000	/* backup of crbinit */
A
Amit S. Kale 已提交
719 720
} netxen_flash_map_t;

721 722 723 724 725 726 727 728 729 730 731
#define NETXEN_USER_START_OLD NETXEN_PXE_START	/* for backward compatibility */

#define NETXEN_FLASH_START		(NETXEN_CRBINIT_START)
#define NETXEN_INIT_SECTOR		(0)
#define NETXEN_PRIMARY_START 		(NETXEN_BOOTLD_START)
#define NETXEN_FLASH_CRBINIT_SIZE 	(0x4000)
#define NETXEN_FLASH_BRDCFG_SIZE 	(sizeof(struct netxen_board_info))
#define NETXEN_FLASH_USER_SIZE		(sizeof(struct netxen_user_info)/sizeof(u32))
#define NETXEN_FLASH_SECONDARY_SIZE 	(NETXEN_USER_START-NETXEN_SECONDARY_START)
#define NETXEN_NUM_PRIMARY_SECTORS	(0x20)
#define NETXEN_NUM_CONFIG_SECTORS 	(1)
732 733
#define PFX "NetXen: "
extern char netxen_nic_driver_name[];
A
Amit S. Kale 已提交
734 735 736 737 738 739 740 741

/* Note: Make sure to not call this before adapter->port is valid */
#if !defined(NETXEN_DEBUG)
#define DPRINTK(klevel, fmt, args...)	do { \
	} while (0)
#else
#define DPRINTK(klevel, fmt, args...)	do { \
	printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\
742 743
		(adapter != NULL && adapter->netdev != NULL) ? \
		adapter->netdev->name : NULL, \
A
Amit S. Kale 已提交
744 745 746 747 748 749 750 751 752 753 754 755 756 757 758
		## args); } while(0)
#endif

/* Number of status descriptors to handle per interrupt */
#define MAX_STATUS_HANDLE	(128)

/*
 * netxen_skb_frag{} is to contain mapping info for each SG list. This
 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
 */
struct netxen_skb_frag {
	u64 dma;
	u32 length;
};

759 760 761 762 763 764
#define _netxen_set_bits(config_word, start, bits, val)	{\
	unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
	unsigned long long __tvalue = (val);    \
	(config_word) &= ~__tmask;      \
	(config_word) |= (((__tvalue) << (start)) & __tmask); \
}
765

766 767 768
#define _netxen_clear_bits(config_word, start, bits) {\
	unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));  \
	(config_word) &= ~__tmask; \
769
}
770

A
Amit S. Kale 已提交
771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792
/*    Following defines are for the state of the buffers    */
#define	NETXEN_BUFFER_FREE	0
#define	NETXEN_BUFFER_BUSY	1

/*
 * There will be one netxen_buffer per skb packet.    These will be
 * used to save the dma info for pci_unmap_page()
 */
struct netxen_cmd_buffer {
	struct sk_buff *skb;
	struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
	u32 total_length;
	u32 mss;
	u16 port;
	u8 cmd;
	u8 frag_count;
	unsigned long time_stamp;
	u32 state;
};

/* In rx_buffer, we do not need multiple fragments as is a single buffer */
struct netxen_rx_buffer {
793
	struct list_head list;
A
Amit S. Kale 已提交
794 795 796 797
	struct sk_buff *skb;
	u64 dma;
	u16 ref_handle;
	u16 state;
798 799 800
	u32 lro_expected_frags;
	u32 lro_current_frags;
	u32 lro_length;
A
Amit S. Kale 已提交
801 802 803 804 805 806 807 808 809 810 811
};

/* Board types */
#define	NETXEN_NIC_GBE	0x01
#define	NETXEN_NIC_XGBE	0x02

/*
 * One hardware_context{} per adapter
 * contains interrupt info as well shared hardware info.
 */
struct netxen_hardware_context {
812 813 814
	void __iomem *pci_base0;
	void __iomem *pci_base1;
	void __iomem *pci_base2;
815 816
	unsigned long first_page_group_end;
	unsigned long first_page_group_start;
817 818
	void __iomem *db_base;
	unsigned long db_len;
819 820
	unsigned long pci_len0;

821
	u8 cut_through;
822 823 824 825
	int qdr_sn_window;
	int ddr_mn_window;
	unsigned long mn_win_crb;
	unsigned long ms_win_crb;
826

A
Amit S. Kale 已提交
827 828 829
	u8 revision_id;
	u16 board_type;
	struct netxen_board_info boardcfg;
830
	u32 linkup;
A
Amit S. Kale 已提交
831 832 833 834
	/* Address of cmd ring in Phantom */
	struct cmd_desc_type0 *cmd_desc_head;
	dma_addr_t cmd_desc_phys_addr;
	struct netxen_adapter *adapter;
835
	int pci_func;
A
Amit S. Kale 已提交
836 837
};

838 839
#define RCV_RING_LRO	RCV_DESC_LRO

A
Amit S. Kale 已提交
840 841 842 843
#define MINIMUM_ETHERNET_FRAME_SIZE	64	/* With FCS */
#define ETHERNET_FCS_SIZE		4

struct netxen_adapter_stats {
844 845 846 847 848 849 850
	u64  rcvdbadskb;
	u64  xmitcalled;
	u64  xmitedframes;
	u64  xmitfinished;
	u64  badskblen;
	u64  nocmddescriptor;
	u64  polled;
D
Dhananjay Phadke 已提交
851
	u64  rxdropped;
852 853 854 855 856 857
	u64  txdropped;
	u64  csummed;
	u64  no_rcv;
	u64  rxbytes;
	u64  txbytes;
	u64  ints;
A
Amit S. Kale 已提交
858 859 860 861 862 863
};

/*
 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
 */
D
Dhananjay Phadke 已提交
864
struct nx_host_rds_ring {
A
Amit S. Kale 已提交
865 866 867
	u32 flags;
	u32 producer;
	dma_addr_t phys_addr;
868
	u32 crb_rcv_producer;	/* reg offset */
A
Amit S. Kale 已提交
869 870 871 872 873
	struct rcv_desc *desc_head;	/* address of rx ring in Phantom */
	u32 max_rx_desc_count;
	u32 dma_size;
	u32 skb_size;
	struct netxen_rx_buffer *rx_buf_arr;	/* rx buffers for receive   */
874
	struct list_head free_list;
A
Amit S. Kale 已提交
875 876 877 878 879 880 881 882 883 884
	int begin_alloc;
};

/*
 * Receive context. There is one such structure per instance of the
 * receive processing. Any state information that is relevant to
 * the receive, and is must be in this structure. The global data may be
 * present elsewhere.
 */
struct netxen_recv_context {
D
Dhananjay Phadke 已提交
885 886 887 888 889
	u32 state;
	u16 context_id;
	u16 virt_port;

	struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
A
Amit S. Kale 已提交
890
	u32 status_rx_consumer;
891
	u32 crb_sts_consumer;	/* reg offset */
A
Amit S. Kale 已提交
892 893 894 895
	dma_addr_t rcv_status_desc_phys_addr;
	struct status_desc *rcv_status_desc_head;
};

D
Dhananjay Phadke 已提交
896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139
/* New HW context creation */

#define NX_OS_CRB_RETRY_COUNT	4000
#define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
	(((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))

#define NX_CDRP_CLEAR		0x00000000
#define NX_CDRP_CMD_BIT		0x80000000

/*
 * All responses must have the NX_CDRP_CMD_BIT cleared
 * in the crb NX_CDRP_CRB_OFFSET.
 */
#define NX_CDRP_FORM_RSP(rsp)	(rsp)
#define NX_CDRP_IS_RSP(rsp)	(((rsp) & NX_CDRP_CMD_BIT) == 0)

#define NX_CDRP_RSP_OK		0x00000001
#define NX_CDRP_RSP_FAIL	0x00000002
#define NX_CDRP_RSP_TIMEOUT	0x00000003

/*
 * All commands must have the NX_CDRP_CMD_BIT set in
 * the crb NX_CDRP_CRB_OFFSET.
 */
#define NX_CDRP_FORM_CMD(cmd)	(NX_CDRP_CMD_BIT | (cmd))
#define NX_CDRP_IS_CMD(cmd)	(((cmd) & NX_CDRP_CMD_BIT) != 0)

#define NX_CDRP_CMD_SUBMIT_CAPABILITIES     0x00000001
#define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX    0x00000002
#define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX    0x00000003
#define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX  0x00000004
#define NX_CDRP_CMD_READ_MAX_RX_CTX         0x00000005
#define NX_CDRP_CMD_READ_MAX_TX_CTX         0x00000006
#define NX_CDRP_CMD_CREATE_RX_CTX           0x00000007
#define NX_CDRP_CMD_DESTROY_RX_CTX          0x00000008
#define NX_CDRP_CMD_CREATE_TX_CTX           0x00000009
#define NX_CDRP_CMD_DESTROY_TX_CTX          0x0000000a
#define NX_CDRP_CMD_SETUP_STATISTICS        0x0000000e
#define NX_CDRP_CMD_GET_STATISTICS          0x0000000f
#define NX_CDRP_CMD_DELETE_STATISTICS       0x00000010
#define NX_CDRP_CMD_SET_MTU                 0x00000012
#define NX_CDRP_CMD_MAX                     0x00000013

#define NX_RCODE_SUCCESS		0
#define NX_RCODE_NO_HOST_MEM		1
#define NX_RCODE_NO_HOST_RESOURCE	2
#define NX_RCODE_NO_CARD_CRB		3
#define NX_RCODE_NO_CARD_MEM		4
#define NX_RCODE_NO_CARD_RESOURCE	5
#define NX_RCODE_INVALID_ARGS		6
#define NX_RCODE_INVALID_ACTION		7
#define NX_RCODE_INVALID_STATE		8
#define NX_RCODE_NOT_SUPPORTED		9
#define NX_RCODE_NOT_PERMITTED		10
#define NX_RCODE_NOT_READY		11
#define NX_RCODE_DOES_NOT_EXIST		12
#define NX_RCODE_ALREADY_EXISTS		13
#define NX_RCODE_BAD_SIGNATURE		14
#define NX_RCODE_CMD_NOT_IMPL		15
#define NX_RCODE_CMD_INVALID		16
#define NX_RCODE_TIMEOUT		17
#define NX_RCODE_CMD_FAILED		18
#define NX_RCODE_MAX_EXCEEDED		19
#define NX_RCODE_MAX			20

#define NX_DESTROY_CTX_RESET		0
#define NX_DESTROY_CTX_D3_RESET		1
#define NX_DESTROY_CTX_MAX		2

/*
 * Capabilities
 */
#define NX_CAP_BIT(class, bit)		(1 << bit)
#define NX_CAP0_LEGACY_CONTEXT		NX_CAP_BIT(0, 0)
#define NX_CAP0_MULTI_CONTEXT		NX_CAP_BIT(0, 1)
#define NX_CAP0_LEGACY_MN		NX_CAP_BIT(0, 2)
#define NX_CAP0_LEGACY_MS		NX_CAP_BIT(0, 3)
#define NX_CAP0_CUT_THROUGH		NX_CAP_BIT(0, 4)
#define NX_CAP0_LRO			NX_CAP_BIT(0, 5)
#define NX_CAP0_LSO			NX_CAP_BIT(0, 6)
#define NX_CAP0_JUMBO_CONTIGUOUS	NX_CAP_BIT(0, 7)
#define NX_CAP0_LRO_CONTIGUOUS		NX_CAP_BIT(0, 8)

/*
 * Context state
 */
#define NX_HOST_CTX_STATE_FREED		0
#define NX_HOST_CTX_STATE_ALLOCATED	1
#define NX_HOST_CTX_STATE_ACTIVE	2
#define NX_HOST_CTX_STATE_DISABLED	3
#define NX_HOST_CTX_STATE_QUIESCED	4
#define NX_HOST_CTX_STATE_MAX		5

/*
 * Rx context
 */

typedef struct {
	u64 host_phys_addr;	/* Ring base addr */
	u32 ring_size;		/* Ring entries */
	u16 msi_index;
	u16 rsvd;		/* Padding */
} nx_hostrq_sds_ring_t;

typedef struct {
	u64 host_phys_addr;	/* Ring base addr */
	u64 buff_size;		/* Packet buffer size */
	u32 ring_size;		/* Ring entries */
	u32 ring_kind;		/* Class of ring */
} nx_hostrq_rds_ring_t;

typedef struct {
	u64 host_rsp_dma_addr;	/* Response dma'd here */
	u32 capabilities[4];	/* Flag bit vector */
	u32 host_int_crb_mode;	/* Interrupt crb usage */
	u32 host_rds_crb_mode;	/* RDS crb usage */
	/* These ring offsets are relative to data[0] below */
	u32 rds_ring_offset;	/* Offset to RDS config */
	u32 sds_ring_offset;	/* Offset to SDS config */
	u16 num_rds_rings;	/* Count of RDS rings */
	u16 num_sds_rings;	/* Count of SDS rings */
	u16 rsvd1;		/* Padding */
	u16 rsvd2;		/* Padding */
	u8  reserved[128]; 	/* reserve space for future expansion*/
	/* MUST BE 64-bit aligned.
	   The following is packed:
	   - N hostrq_rds_rings
	   - N hostrq_sds_rings */
	char data[0];
} nx_hostrq_rx_ctx_t;

typedef struct {
	u32 host_producer_crb;	/* Crb to use */
	u32 rsvd1;		/* Padding */
} nx_cardrsp_rds_ring_t;

typedef struct {
	u32 host_consumer_crb;	/* Crb to use */
	u32 interrupt_crb;	/* Crb to use */
} nx_cardrsp_sds_ring_t;

typedef struct {
	/* These ring offsets are relative to data[0] below */
	u32 rds_ring_offset;	/* Offset to RDS config */
	u32 sds_ring_offset;	/* Offset to SDS config */
	u32 host_ctx_state;	/* Starting State */
	u32 num_fn_per_port;	/* How many PCI fn share the port */
	u16 num_rds_rings;	/* Count of RDS rings */
	u16 num_sds_rings;	/* Count of SDS rings */
	u16 context_id;		/* Handle for context */
	u8  phys_port;		/* Physical id of port */
	u8  virt_port;		/* Virtual/Logical id of port */
	u8  reserved[128];	/* save space for future expansion */
	/*  MUST BE 64-bit aligned.
	   The following is packed:
	   - N cardrsp_rds_rings
	   - N cardrs_sds_rings */
	char data[0];
} nx_cardrsp_rx_ctx_t;

#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings)	\
	(sizeof(HOSTRQ_RX) + 					\
	(rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) +		\
	(sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))

#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) 	\
	(sizeof(CARDRSP_RX) + 					\
	(rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + 		\
	(sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))

/*
 * Tx context
 */

typedef struct {
	u64 host_phys_addr;	/* Ring base addr */
	u32 ring_size;		/* Ring entries */
	u32 rsvd;		/* Padding */
} nx_hostrq_cds_ring_t;

typedef struct {
	u64 host_rsp_dma_addr;	/* Response dma'd here */
	u64 cmd_cons_dma_addr;	/*  */
	u64 dummy_dma_addr;	/*  */
	u32 capabilities[4];	/* Flag bit vector */
	u32 host_int_crb_mode;	/* Interrupt crb usage */
	u32 rsvd1;		/* Padding */
	u16 rsvd2;		/* Padding */
	u16 interrupt_ctl;
	u16 msi_index;
	u16 rsvd3;		/* Padding */
	nx_hostrq_cds_ring_t cds_ring;	/* Desc of cds ring */
	u8  reserved[128];	/* future expansion */
} nx_hostrq_tx_ctx_t;

typedef struct {
	u32 host_producer_crb;	/* Crb to use */
	u32 interrupt_crb;	/* Crb to use */
} nx_cardrsp_cds_ring_t;

typedef struct {
	u32 host_ctx_state;	/* Starting state */
	u16 context_id;		/* Handle for context */
	u8  phys_port;		/* Physical id of port */
	u8  virt_port;		/* Virtual/Logical id of port */
	nx_cardrsp_cds_ring_t cds_ring;	/* Card cds settings */
	u8  reserved[128];	/* future expansion */
} nx_cardrsp_tx_ctx_t;

#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX)	(sizeof(HOSTRQ_TX))
#define SIZEOF_CARDRSP_TX(CARDRSP_TX)	(sizeof(CARDRSP_TX))

/* CRB */

#define NX_HOST_RDS_CRB_MODE_UNIQUE	0
#define NX_HOST_RDS_CRB_MODE_SHARED	1
#define NX_HOST_RDS_CRB_MODE_CUSTOM	2
#define NX_HOST_RDS_CRB_MODE_MAX	3

#define NX_HOST_INT_CRB_MODE_UNIQUE	0
#define NX_HOST_INT_CRB_MODE_SHARED	1
#define NX_HOST_INT_CRB_MODE_NORX	2
#define NX_HOST_INT_CRB_MODE_NOTX	3
#define NX_HOST_INT_CRB_MODE_NORXTX	4


/* MAC */

#define MC_COUNT_P2	16
#define MC_COUNT_P3	38

#define NETXEN_MAC_NOOP	0
#define NETXEN_MAC_ADD	1
#define NETXEN_MAC_DEL	2

typedef struct nx_mac_list_s {
	struct nx_mac_list_s *next;
	uint8_t mac_addr[MAX_ADDR_LEN];
} nx_mac_list_t;

typedef struct {
	u64 qhdr;
	u64 req_hdr;
	u64 words[6];
1140
} nx_nic_req_t;
D
Dhananjay Phadke 已提交
1141 1142 1143 1144 1145 1146 1147

typedef struct {
	u8 op;
	u8 tag;
	u8 mac_addr[6];
} nx_mac_req_t;

1148
#define MAX_PENDING_DESC_BLOCK_SIZE	64
D
Dhananjay Phadke 已提交
1149

1150 1151 1152 1153 1154 1155 1156 1157 1158 1159
#define NETXEN_NIC_MSI_ENABLED		0x02
#define NETXEN_NIC_MSIX_ENABLED		0x04
#define NETXEN_IS_MSI_FAMILY(adapter) \
	((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))

#define MSIX_ENTRIES_PER_ADAPTER	8
#define NETXEN_MSIX_TBL_SPACE		8192
#define NETXEN_PCI_REG_MSIX_TBL		0x44

#define NETXEN_DB_MAPSIZE_BYTES    	0x1000
1160 1161 1162 1163 1164

struct netxen_dummy_dma {
	void *addr;
	dma_addr_t phys_addr;
};
A
Amit S. Kale 已提交
1165 1166 1167

struct netxen_adapter {
	struct netxen_hardware_context ahw;
1168

1169 1170
	struct net_device *netdev;
	struct pci_dev *pdev;
1171
	int pci_using_dac;
1172
	struct napi_struct napi;
1173
	struct net_device_stats net_stats;
1174 1175
	int mtu;
	int portnum;
1176
	u8 physical_port;
D
Dhananjay Phadke 已提交
1177
	u16 tx_context_id;
1178

1179 1180
	uint8_t		mc_enabled;
	uint8_t		max_mc_count;
1181
	nx_mac_list_t	*mac_list;
1182

1183
	struct netxen_legacy_intr_set legacy_intr;
D
Dhananjay Phadke 已提交
1184
	u32	crb_intr_mask;
1185

A
Amit S. Kale 已提交
1186 1187
	struct work_struct watchdog_task;
	struct timer_list watchdog_timer;
1188
	struct work_struct  tx_timeout_task;
A
Amit S. Kale 已提交
1189 1190

	u32 curr_window;
1191 1192
	u32 crb_win;
	rwlock_t adapter_lock;
A
Amit S. Kale 已提交
1193

1194 1195
	uint64_t dma_mask;

A
Amit S. Kale 已提交
1196
	u32 cmd_producer;
A
Al Viro 已提交
1197
	__le32 *cmd_consumer;
A
Amit S. Kale 已提交
1198
	u32 last_cmd_consumer;
1199 1200
	u32 crb_addr_cmd_producer;
	u32 crb_addr_cmd_consumer;
1201

A
Amit S. Kale 已提交
1202 1203 1204
	u32 max_tx_desc_count;
	u32 max_rx_desc_count;
	u32 max_jumbo_rx_desc_count;
1205
	u32 max_lro_rx_desc_count;
A
Amit S. Kale 已提交
1206

D
Dhananjay Phadke 已提交
1207 1208
	int max_rds_rings;

A
Amit S. Kale 已提交
1209 1210 1211
	u32 flags;
	u32 irq;
	int driver_mismatch;
1212
	u32 temp;
A
Amit S. Kale 已提交
1213

1214 1215 1216 1217 1218 1219
	u32 fw_major;

	u8 msix_supported;
	u8 max_possible_rss_rings;
	struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];

A
Amit S. Kale 已提交
1220
	struct netxen_adapter_stats stats;
1221

1222 1223 1224 1225
	u16 link_speed;
	u16 link_duplex;
	u16 state;
	u16 link_autoneg;
D
Dhananjay Phadke 已提交
1226
	int rx_csum;
1227
	int status;
A
Amit S. Kale 已提交
1228 1229 1230 1231 1232 1233 1234 1235 1236 1237

	struct netxen_cmd_buffer *cmd_buf_arr;	/* Command buffers for xmit */

	/*
	 * Receive instances. These can be either one per port,
	 * or one per peg, etc.
	 */
	struct netxen_recv_context recv_ctx[MAX_RCV_CTX];

	int is_up;
1238 1239 1240 1241 1242
	struct netxen_dummy_dma dummy_dma;

	/* Context interface shared between card and host */
	struct netxen_ring_ctx *ctx_desc;
	dma_addr_t ctx_desc_phys_addr;
1243
	int intr_scheme;
D
Dhananjay Phadke 已提交
1244
	int msi_mode;
1245 1246
	int (*enable_phy_interrupts) (struct netxen_adapter *);
	int (*disable_phy_interrupts) (struct netxen_adapter *);
1247 1248 1249
	int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
	int (*set_mtu) (struct netxen_adapter *, int);
	int (*set_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t);
1250 1251
	int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
	int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1252
	int (*init_port) (struct netxen_adapter *, int);
1253
	int (*stop_port) (struct netxen_adapter *);
1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264

	int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int);
	int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int);
	int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
	int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
	int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
	u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
	void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
	u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
	unsigned long (*pci_set_window)(struct netxen_adapter *,
			unsigned long long);
A
Amit S. Kale 已提交
1265 1266
};				/* netxen_adapter structure */

1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284
/*
 * NetXen dma watchdog control structure
 *
 *	Bit 0		: enabled => R/O: 1 watchdog active, 0 inactive
 *	Bit 1		: disable_request => 1 req disable dma watchdog
 *	Bit 2		: enable_request =>  1 req enable dma watchdog
 *	Bit 3-31	: unused
 */

#define netxen_set_dma_watchdog_disable_req(config_word) \
	_netxen_set_bits(config_word, 1, 1, 1)
#define netxen_set_dma_watchdog_enable_req(config_word) \
	_netxen_set_bits(config_word, 2, 1, 1)
#define netxen_get_dma_watchdog_enabled(config_word) \
	((config_word) & 0x1)
#define netxen_get_dma_watchdog_disabled(config_word) \
	(((config_word) >> 1) & 0x1)

A
Amit S. Kale 已提交
1285 1286 1287
/* Max number of xmit producer threads that can run simultaneously */
#define	MAX_XMIT_PRODUCERS		16

1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324
#define PCI_OFFSET_FIRST_RANGE(adapter, off)    \
	((adapter)->ahw.pci_base0 + (off))
#define PCI_OFFSET_SECOND_RANGE(adapter, off)   \
	((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
#define PCI_OFFSET_THIRD_RANGE(adapter, off)    \
	((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)

static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
					    unsigned long off)
{
	if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
		return (adapter->ahw.pci_base0 + off);
	} else if ((off < SECOND_PAGE_GROUP_END) &&
		   (off >= SECOND_PAGE_GROUP_START)) {
		return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
	} else if ((off < THIRD_PAGE_GROUP_END) &&
		   (off >= THIRD_PAGE_GROUP_START)) {
		return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
	}
	return NULL;
}

static inline void __iomem *pci_base(struct netxen_adapter *adapter,
				     unsigned long off)
{
	if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
		return adapter->ahw.pci_base0;
	} else if ((off < SECOND_PAGE_GROUP_END) &&
		   (off >= SECOND_PAGE_GROUP_START)) {
		return adapter->ahw.pci_base1;
	} else if ((off < THIRD_PAGE_GROUP_END) &&
		   (off >= THIRD_PAGE_GROUP_START)) {
		return adapter->ahw.pci_base2;
	}
	return NULL;
}

1325 1326 1327 1328 1329
int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
A
Al Viro 已提交
1330
			    __u32 * readval);
1331
int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
A
Al Viro 已提交
1332
			     long reg, __u32 val);
A
Amit S. Kale 已提交
1333 1334

/* Functions available from netxen_nic_hw.c */
1335 1336
int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
A
Amit S. Kale 已提交
1337 1338 1339
void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
1340 1341 1342
void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value);
void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value);
void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
A
Amit S. Kale 已提交
1343 1344

int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372

int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
		ulong off, void *data, int len);
int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
		ulong off, void *data, int len);
int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
		u64 off, void *data, int size);
int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
		u64 off, void *data, int size);
int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
		u64 off, u32 data);
u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
		u64 off, u32 data);
u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
		unsigned long long addr);
void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
		u32 wndw);

int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
		ulong off, void *data, int len);
int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
		ulong off, void *data, int len);
int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
		u64 off, void *data, int size);
int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
		u64 off, void *data, int size);
A
Amit S. Kale 已提交
1373 1374
void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
				 unsigned long off, int data);
1375 1376 1377 1378 1379 1380 1381 1382
int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
		u64 off, u32 data);
u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
		u64 off, u32 data);
u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
		unsigned long long addr);
A
Amit S. Kale 已提交
1383 1384

/* Functions from netxen_nic_init.c */
1385 1386
void netxen_free_adapter_offload(struct netxen_adapter *adapter);
int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1387
int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1388
int netxen_receive_peg_ready(struct netxen_adapter *adapter);
1389
int netxen_load_firmware(struct netxen_adapter *adapter);
A
Amit S. Kale 已提交
1390
int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1391

A
Amit S. Kale 已提交
1392
int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1393
int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1394
				u8 *bytes, size_t size);
1395
int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1396 1397 1398 1399 1400
				u8 *bytes, size_t size);
int netxen_flash_unlock(struct netxen_adapter *adapter);
int netxen_backup_crbinit(struct netxen_adapter *adapter);
int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1401
void netxen_halt_pegs(struct netxen_adapter *adapter);
1402

1403
int netxen_rom_se(struct netxen_adapter *adapter, int addr);
A
Amit S. Kale 已提交
1404

1405 1406 1407 1408 1409 1410 1411 1412 1413
int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
void netxen_free_sw_resources(struct netxen_adapter *adapter);

int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
void netxen_free_hw_resources(struct netxen_adapter *adapter);

void netxen_release_rx_buffers(struct netxen_adapter *adapter);
void netxen_release_tx_buffers(struct netxen_adapter *adapter);

A
Amit S. Kale 已提交
1414 1415 1416 1417 1418
void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
int netxen_init_firmware(struct netxen_adapter *adapter);
void netxen_tso_check(struct netxen_adapter *adapter,
		      struct cmd_desc_type0 *desc, struct sk_buff *skb);
void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1419
void netxen_watchdog_task(struct work_struct *work);
A
Amit S. Kale 已提交
1420 1421
void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
			    u32 ringid);
D
Dhananjay Phadke 已提交
1422
int netxen_process_cmd_ring(struct netxen_adapter *adapter);
A
Amit S. Kale 已提交
1423
u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
1424 1425
void netxen_p2_nic_set_multi(struct net_device *netdev);
void netxen_p3_nic_set_multi(struct net_device *netdev);
D
Dhananjay Phadke 已提交
1426 1427

u32 nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, u32 mtu);
A
Amit S. Kale 已提交
1428
int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
D
Dhananjay Phadke 已提交
1429

A
Amit S. Kale 已提交
1430 1431 1432
int netxen_nic_set_mac(struct net_device *netdev, void *p);
struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);

1433 1434
void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
		uint32_t crb_producer);
1435 1436 1437 1438 1439

/*
 * NetXen Board information
 */

1440
#define NETXEN_MAX_SHORT_NAME 32
1441
struct netxen_brdinfo {
1442 1443 1444
	netxen_brdtype_t brdtype;	/* type of board */
	long ports;		/* max no of physical ports */
	char short_name[NETXEN_MAX_SHORT_NAME];
1445
};
1446

1447
static const struct netxen_brdinfo netxen_boards[] = {
1448 1449 1450 1451 1452 1453
	{NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
	{NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
	{NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
	{NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
	{NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
	{NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464
	{NETXEN_BRDTYPE_P3_REF_QG,  4, "Reference Quad Gig "},
	{NETXEN_BRDTYPE_P3_HMEZ,    2, "Dual XGb HMEZ"},
	{NETXEN_BRDTYPE_P3_10G_CX4_LP,   2, "Dual XGb CX4 LP"},
	{NETXEN_BRDTYPE_P3_4_GB,    4, "Quad Gig LP"},
	{NETXEN_BRDTYPE_P3_IMEZ,    2, "Dual XGb IMEZ"},
	{NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
	{NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
	{NETXEN_BRDTYPE_P3_XG_LOM,  2, "Dual XGb LOM"},
	{NETXEN_BRDTYPE_P3_4_GB_MM, 4, "Quad GB - March Madness"},
	{NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
	{NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1465 1466
};

1467
#define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478

static inline void get_brd_name_by_type(u32 type, char *name)
{
	int i, found = 0;
	for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
		if (netxen_boards[i].brdtype == type) {
			strcpy(name, netxen_boards[i].short_name);
			found = 1;
			break;
		}

A
Amit S. Kale 已提交
1479
	}
1480 1481
	if (!found)
		name = "Unknown";
A
Amit S. Kale 已提交
1482 1483
}

1484 1485 1486 1487 1488 1489
static inline int
dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
{
	u32 ctrl;

	/* check if already inactive */
1490
	if (adapter->hw_read_wx(adapter,
1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509
	    NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
		printk(KERN_ERR "failed to read dma watchdog status\n");

	if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
		return 1;

	/* Send the disable request */
	netxen_set_dma_watchdog_disable_req(ctrl);
	netxen_crb_writelit_adapter(adapter,
		NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);

	return 0;
}

static inline int
dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
{
	u32 ctrl;

1510
	if (adapter->hw_read_wx(adapter,
1511 1512 1513
	    NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
		printk(KERN_ERR "failed to read dma watchdog status\n");

1514
	return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1515 1516 1517 1518 1519 1520 1521
}

static inline int
dma_watchdog_wakeup(struct netxen_adapter *adapter)
{
	u32 ctrl;

1522
	if (adapter->hw_read_wx(adapter,
1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538
		NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
		printk(KERN_ERR "failed to read dma watchdog status\n");

	if (netxen_get_dma_watchdog_enabled(ctrl))
		return 1;

	/* send the wakeup request */
	netxen_set_dma_watchdog_enable_req(ctrl);

	netxen_crb_writelit_adapter(adapter,
		NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);

	return 0;
}


A
Amit S. Kale 已提交
1539
int netxen_is_flash_supported(struct netxen_adapter *adapter);
A
Al Viro 已提交
1540
int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]);
A
Amit S. Kale 已提交
1541 1542 1543 1544 1545 1546 1547
extern void netxen_change_ringparam(struct netxen_adapter *adapter);
extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
				int *valp);

extern struct ethtool_ops netxen_nic_ethtool_ops;

#endif				/* __NETXEN_NIC_H_ */