edma.c 66.2 KB
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/*
 * TI EDMA DMA engine driver
 *
 * Copyright 2012 Texas Instruments
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
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#include <linux/edma.h>
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#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <linux/of_dma.h>
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#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
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#include <linux/platform_data/edma.h>
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#include "../dmaengine.h"
#include "../virt-dma.h"
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/* Offsets matching "struct edmacc_param" */
#define PARM_OPT		0x00
#define PARM_SRC		0x04
#define PARM_A_B_CNT		0x08
#define PARM_DST		0x0c
#define PARM_SRC_DST_BIDX	0x10
#define PARM_LINK_BCNTRLD	0x14
#define PARM_SRC_DST_CIDX	0x18
#define PARM_CCNT		0x1c

#define PARM_SIZE		0x20

/* Offsets for EDMA CC global channel registers and their shadows */
#define SH_ER			0x00	/* 64 bits */
#define SH_ECR			0x08	/* 64 bits */
#define SH_ESR			0x10	/* 64 bits */
#define SH_CER			0x18	/* 64 bits */
#define SH_EER			0x20	/* 64 bits */
#define SH_EECR			0x28	/* 64 bits */
#define SH_EESR			0x30	/* 64 bits */
#define SH_SER			0x38	/* 64 bits */
#define SH_SECR			0x40	/* 64 bits */
#define SH_IER			0x50	/* 64 bits */
#define SH_IECR			0x58	/* 64 bits */
#define SH_IESR			0x60	/* 64 bits */
#define SH_IPR			0x68	/* 64 bits */
#define SH_ICR			0x70	/* 64 bits */
#define SH_IEVAL		0x78
#define SH_QER			0x80
#define SH_QEER			0x84
#define SH_QEECR		0x88
#define SH_QEESR		0x8c
#define SH_QSER			0x90
#define SH_QSECR		0x94
#define SH_SIZE			0x200

/* Offsets for EDMA CC global registers */
#define EDMA_REV		0x0000
#define EDMA_CCCFG		0x0004
#define EDMA_QCHMAP		0x0200	/* 8 registers */
#define EDMA_DMAQNUM		0x0240	/* 8 registers (4 on OMAP-L1xx) */
#define EDMA_QDMAQNUM		0x0260
#define EDMA_QUETCMAP		0x0280
#define EDMA_QUEPRI		0x0284
#define EDMA_EMR		0x0300	/* 64 bits */
#define EDMA_EMCR		0x0308	/* 64 bits */
#define EDMA_QEMR		0x0310
#define EDMA_QEMCR		0x0314
#define EDMA_CCERR		0x0318
#define EDMA_CCERRCLR		0x031c
#define EDMA_EEVAL		0x0320
#define EDMA_DRAE		0x0340	/* 4 x 64 bits*/
#define EDMA_QRAE		0x0380	/* 4 registers */
#define EDMA_QUEEVTENTRY	0x0400	/* 2 x 16 registers */
#define EDMA_QSTAT		0x0600	/* 2 registers */
#define EDMA_QWMTHRA		0x0620
#define EDMA_QWMTHRB		0x0624
#define EDMA_CCSTAT		0x0640

#define EDMA_M			0x1000	/* global channel registers */
#define EDMA_ECR		0x1008
#define EDMA_ECRH		0x100C
#define EDMA_SHADOW0		0x2000	/* 4 shadow regions */
#define EDMA_PARM		0x4000	/* PaRAM entries */

#define PARM_OFFSET(param_no)	(EDMA_PARM + ((param_no) << 5))

#define EDMA_DCHMAP		0x0100  /* 64 registers */

/* CCCFG register */
#define GET_NUM_DMACH(x)	(x & 0x7) /* bits 0-2 */
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#define GET_NUM_QDMACH(x)	((x & 0x70) >> 4) /* bits 4-6 */
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#define GET_NUM_PAENTRY(x)	((x & 0x7000) >> 12) /* bits 12-14 */
#define GET_NUM_EVQUE(x)	((x & 0x70000) >> 16) /* bits 16-18 */
#define GET_NUM_REGN(x)		((x & 0x300000) >> 20) /* bits 20-21 */
#define CHMAP_EXIST		BIT(24)

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/* CCSTAT register */
#define EDMA_CCSTAT_ACTV	BIT(4)

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/*
 * Max of 20 segments per channel to conserve PaRAM slots
 * Also note that MAX_NR_SG should be atleast the no.of periods
 * that are required for ASoC, otherwise DMA prep calls will
 * fail. Today davinci-pcm is the only user of this driver and
 * requires atleast 17 slots, so we setup the default to 20.
 */
#define MAX_NR_SG		20
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#define EDMA_MAX_SLOTS		MAX_NR_SG
#define EDMA_DESCRIPTORS	16

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#define EDMA_CHANNEL_ANY		-1	/* for edma_alloc_channel() */
#define EDMA_SLOT_ANY			-1	/* for edma_alloc_slot() */
#define EDMA_CONT_PARAMS_ANY		 1001
#define EDMA_CONT_PARAMS_FIXED_EXACT	 1002
#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003

/* PaRAM slots are laid out like this */
struct edmacc_param {
	u32 opt;
	u32 src;
	u32 a_b_cnt;
	u32 dst;
	u32 src_dst_bidx;
	u32 link_bcntrld;
	u32 src_dst_cidx;
	u32 ccnt;
} __packed;

/* fields in edmacc_param.opt */
#define SAM		BIT(0)
#define DAM		BIT(1)
#define SYNCDIM		BIT(2)
#define STATIC		BIT(3)
#define EDMA_FWID	(0x07 << 8)
#define TCCMODE		BIT(11)
#define EDMA_TCC(t)	((t) << 12)
#define TCINTEN		BIT(20)
#define ITCINTEN	BIT(21)
#define TCCHEN		BIT(22)
#define ITCCHEN		BIT(23)

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struct edma_pset {
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	u32				len;
	dma_addr_t			addr;
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	struct edmacc_param		param;
};

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struct edma_desc {
	struct virt_dma_desc		vdesc;
	struct list_head		node;
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	enum dma_transfer_direction	direction;
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	int				cyclic;
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	int				absync;
	int				pset_nr;
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	struct edma_chan		*echan;
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	int				processed;
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	/*
	 * The following 4 elements are used for residue accounting.
	 *
	 * - processed_stat: the number of SG elements we have traversed
	 * so far to cover accounting. This is updated directly to processed
	 * during edma_callback and is always <= processed, because processed
	 * refers to the number of pending transfer (programmed to EDMA
	 * controller), where as processed_stat tracks number of transfers
	 * accounted for so far.
	 *
	 * - residue: The amount of bytes we have left to transfer for this desc
	 *
	 * - residue_stat: The residue in bytes of data we have covered
	 * so far for accounting. This is updated directly to residue
	 * during callbacks to keep it current.
	 *
	 * - sg_len: Tracks the length of the current intermediate transfer,
	 * this is required to update the residue during intermediate transfer
	 * completion callback.
	 */
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	int				processed_stat;
	u32				sg_len;
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	u32				residue;
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	u32				residue_stat;
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	struct edma_pset		pset[0];
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};

struct edma_cc;

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struct edma_tc {
	struct device_node		*node;
	u16				id;
};

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struct edma_chan {
	struct virt_dma_chan		vchan;
	struct list_head		node;
	struct edma_desc		*edesc;
	struct edma_cc			*ecc;
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	struct edma_tc			*tc;
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	int				ch_num;
	bool				alloced;
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	bool				hw_triggered;
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	int				slot[EDMA_MAX_SLOTS];
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	int				missed;
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	struct dma_slave_config		cfg;
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};

struct edma_cc {
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	struct device			*dev;
	struct edma_soc_info		*info;
	void __iomem			*base;
	int				id;
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	bool				legacy_mode;
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	/* eDMA3 resource information */
	unsigned			num_channels;
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	unsigned			num_qchannels;
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	unsigned			num_region;
	unsigned			num_slots;
	unsigned			num_tc;
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	bool				chmap_exist;
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	enum dma_event_q		default_queue;

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	unsigned int			ccint;
	unsigned int			ccerrint;

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	/*
	 * The slot_inuse bit for each PaRAM slot is clear unless the slot is
	 * in use by Linux or if it is allocated to be used by DSP.
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	 */
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	unsigned long *slot_inuse;
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	struct dma_device		dma_slave;
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	struct dma_device		*dma_memcpy;
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	struct edma_chan		*slave_chans;
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	struct edma_tc			*tc_list;
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	int				dummy_slot;
};

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/* dummy param set used to (re)initialize parameter RAM slots */
static const struct edmacc_param dummy_paramset = {
	.link_bcntrld = 0xffff,
	.ccnt = 1,
};

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#define EDMA_BINDING_LEGACY	0
#define EDMA_BINDING_TPCC	1
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static const u32 edma_binding_type[] = {
	[EDMA_BINDING_LEGACY] = EDMA_BINDING_LEGACY,
	[EDMA_BINDING_TPCC] = EDMA_BINDING_TPCC,
};

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static const struct of_device_id edma_of_ids[] = {
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	{
		.compatible = "ti,edma3",
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		.data = &edma_binding_type[EDMA_BINDING_LEGACY],
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	},
	{
		.compatible = "ti,edma3-tpcc",
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		.data = &edma_binding_type[EDMA_BINDING_TPCC],
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	},
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	{}
};
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MODULE_DEVICE_TABLE(of, edma_of_ids);
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static const struct of_device_id edma_tptc_of_ids[] = {
	{ .compatible = "ti,edma3-tptc", },
	{}
};
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MODULE_DEVICE_TABLE(of, edma_tptc_of_ids);
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static inline unsigned int edma_read(struct edma_cc *ecc, int offset)
{
	return (unsigned int)__raw_readl(ecc->base + offset);
}

static inline void edma_write(struct edma_cc *ecc, int offset, int val)
{
	__raw_writel(val, ecc->base + offset);
}

static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
			       unsigned or)
{
	unsigned val = edma_read(ecc, offset);

	val &= and;
	val |= or;
	edma_write(ecc, offset, val);
}

static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and)
{
	unsigned val = edma_read(ecc, offset);

	val &= and;
	edma_write(ecc, offset, val);
}

static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
{
	unsigned val = edma_read(ecc, offset);

	val |= or;
	edma_write(ecc, offset, val);
}

static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset,
					   int i)
{
	return edma_read(ecc, offset + (i << 2));
}

static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
				    unsigned val)
{
	edma_write(ecc, offset + (i << 2), val);
}

static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
				     unsigned and, unsigned or)
{
	edma_modify(ecc, offset + (i << 2), and, or);
}

static inline void edma_or_array(struct edma_cc *ecc, int offset, int i,
				 unsigned or)
{
	edma_or(ecc, offset + (i << 2), or);
}

static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
				  unsigned or)
{
	edma_or(ecc, offset + ((i * 2 + j) << 2), or);
}

static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i,
				     int j, unsigned val)
{
	edma_write(ecc, offset + ((i * 2 + j) << 2), val);
}

static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
{
	return edma_read(ecc, EDMA_SHADOW0 + offset);
}

static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc,
						   int offset, int i)
{
	return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
}

static inline void edma_shadow0_write(struct edma_cc *ecc, int offset,
				      unsigned val)
{
	edma_write(ecc, EDMA_SHADOW0 + offset, val);
}

static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,
					    int i, unsigned val)
{
	edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
}

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static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset,
					   int param_no)
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{
	return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
}

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static inline void edma_param_write(struct edma_cc *ecc, int offset,
				    int param_no, unsigned val)
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{
	edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
}

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static inline void edma_param_modify(struct edma_cc *ecc, int offset,
				     int param_no, unsigned and, unsigned or)
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{
	edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
}

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static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no,
				  unsigned and)
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{
	edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
}

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static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no,
				 unsigned or)
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{
	edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
}

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static inline void edma_set_bits(int offset, int len, unsigned long *p)
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{
	for (; len > 0; len--)
		set_bit(offset + (len - 1), p);
}

static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
					  int priority)
{
	int bit = queue_no * 4;

	edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
}

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static void edma_set_chmap(struct edma_chan *echan, int slot)
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{
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	struct edma_cc *ecc = echan->ecc;
	int channel = EDMA_CHAN_SLOT(echan->ch_num);

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	if (ecc->chmap_exist) {
		slot = EDMA_CHAN_SLOT(slot);
		edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
	}
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}

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static void edma_setup_interrupt(struct edma_chan *echan, bool enable)
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{
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	struct edma_cc *ecc = echan->ecc;
	int channel = EDMA_CHAN_SLOT(echan->ch_num);
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	if (enable) {
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		edma_shadow0_write_array(ecc, SH_ICR, channel >> 5,
					 BIT(channel & 0x1f));
		edma_shadow0_write_array(ecc, SH_IESR, channel >> 5,
					 BIT(channel & 0x1f));
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	} else {
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		edma_shadow0_write_array(ecc, SH_IECR, channel >> 5,
					 BIT(channel & 0x1f));
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	}
}

/*
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 * paRAM slot management functions
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 */
static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
			    const struct edmacc_param *param)
{
	slot = EDMA_CHAN_SLOT(slot);
	if (slot >= ecc->num_slots)
		return;
	memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
}

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static int edma_read_slot(struct edma_cc *ecc, unsigned slot,
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			   struct edmacc_param *param)
{
	slot = EDMA_CHAN_SLOT(slot);
	if (slot >= ecc->num_slots)
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		return -EINVAL;
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	memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE);
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	return 0;
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}

/**
 * edma_alloc_slot - allocate DMA parameter RAM
 * @ecc: pointer to edma_cc struct
 * @slot: specific slot to allocate; negative for "any unused slot"
 *
 * This allocates a parameter RAM slot, initializing it to hold a
 * dummy transfer.  Slots allocated using this routine have not been
 * mapped to a hardware DMA channel, and will normally be used by
 * linking to them from a slot associated with a DMA channel.
 *
 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
 * slots may be allocated on behalf of DSP firmware.
 *
 * Returns the number of the slot, else negative errno.
 */
static int edma_alloc_slot(struct edma_cc *ecc, int slot)
{
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	if (slot >= 0) {
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		slot = EDMA_CHAN_SLOT(slot);
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		/* Requesting entry paRAM slot for a HW triggered channel. */
		if (ecc->chmap_exist && slot < ecc->num_channels)
			slot = EDMA_SLOT_ANY;
	}

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	if (slot < 0) {
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		if (ecc->chmap_exist)
			slot = 0;
		else
			slot = ecc->num_channels;
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		for (;;) {
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			slot = find_next_zero_bit(ecc->slot_inuse,
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						  ecc->num_slots,
						  slot);
			if (slot == ecc->num_slots)
				return -ENOMEM;
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			if (!test_and_set_bit(slot, ecc->slot_inuse))
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				break;
		}
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	} else if (slot >= ecc->num_slots) {
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		return -EINVAL;
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	} else if (test_and_set_bit(slot, ecc->slot_inuse)) {
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		return -EBUSY;
	}

	edma_write_slot(ecc, slot, &dummy_paramset);

	return EDMA_CTLR_CHAN(ecc->id, slot);
}

static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
{
	slot = EDMA_CHAN_SLOT(slot);
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	if (slot >= ecc->num_slots)
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		return;

	edma_write_slot(ecc, slot, &dummy_paramset);
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	clear_bit(slot, ecc->slot_inuse);
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}

/**
 * edma_link - link one parameter RAM slot to another
 * @ecc: pointer to edma_cc struct
 * @from: parameter RAM slot originating the link
 * @to: parameter RAM slot which is the link target
 *
 * The originating slot should not be part of any active DMA transfer.
 */
static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
{
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	if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to)))
		dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n");

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	from = EDMA_CHAN_SLOT(from);
	to = EDMA_CHAN_SLOT(to);
	if (from >= ecc->num_slots || to >= ecc->num_slots)
		return;

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	edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000,
			  PARM_OFFSET(to));
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}

/**
 * edma_get_position - returns the current transfer point
 * @ecc: pointer to edma_cc struct
 * @slot: parameter RAM slot being examined
 * @dst:  true selects the dest position, false the source
 *
 * Returns the position of the current active slot
 */
static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot,
				    bool dst)
{
	u32 offs;

	slot = EDMA_CHAN_SLOT(slot);
	offs = PARM_OFFSET(slot);
	offs += dst ? PARM_DST : PARM_SRC;

	return edma_read(ecc, offs);
}

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/*
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 * Channels with event associations will be triggered by their hardware
 * events, and channels without such associations will be triggered by
 * software.  (At this writing there is no interface for using software
 * triggers except with channels that don't support hardware triggers.)
 */
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static void edma_start(struct edma_chan *echan)
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{
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	struct edma_cc *ecc = echan->ecc;
	int channel = EDMA_CHAN_SLOT(echan->ch_num);
	int j = (channel >> 5);
	unsigned int mask = BIT(channel & 0x1f);
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	if (!echan->hw_triggered) {
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		/* EDMA channels without event association */
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		dev_dbg(ecc->dev, "ESR%d %08x\n", j,
			edma_shadow0_read_array(ecc, SH_ESR, j));
		edma_shadow0_write_array(ecc, SH_ESR, j, mask);
	} else {
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		/* EDMA channel with event association */
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		dev_dbg(ecc->dev, "ER%d %08x\n", j,
			edma_shadow0_read_array(ecc, SH_ER, j));
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		/* Clear any pending event or error */
		edma_write_array(ecc, EDMA_ECR, j, mask);
		edma_write_array(ecc, EDMA_EMCR, j, mask);
		/* Clear any SER */
		edma_shadow0_write_array(ecc, SH_SECR, j, mask);
		edma_shadow0_write_array(ecc, SH_EESR, j, mask);
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		dev_dbg(ecc->dev, "EER%d %08x\n", j,
			edma_shadow0_read_array(ecc, SH_EER, j));
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	}
}

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static void edma_stop(struct edma_chan *echan)
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{
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	struct edma_cc *ecc = echan->ecc;
	int channel = EDMA_CHAN_SLOT(echan->ch_num);
	int j = (channel >> 5);
	unsigned int mask = BIT(channel & 0x1f);
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	edma_shadow0_write_array(ecc, SH_EECR, j, mask);
	edma_shadow0_write_array(ecc, SH_ECR, j, mask);
	edma_shadow0_write_array(ecc, SH_SECR, j, mask);
	edma_write_array(ecc, EDMA_EMCR, j, mask);
624

625 626
	/* clear possibly pending completion interrupt */
	edma_shadow0_write_array(ecc, SH_ICR, j, mask);
627

628 629
	dev_dbg(ecc->dev, "EER%d %08x\n", j,
		edma_shadow0_read_array(ecc, SH_EER, j));
630

631 632 633
	/* REVISIT:  consider guarding against inappropriate event
	 * chaining by overwriting with dummy_paramset.
	 */
634 635
}

636 637 638
/*
 * Temporarily disable EDMA hardware events on the specified channel,
 * preventing them from triggering new transfers
639
 */
640
static void edma_pause(struct edma_chan *echan)
641
{
642 643
	int channel = EDMA_CHAN_SLOT(echan->ch_num);
	unsigned int mask = BIT(channel & 0x1f);
644

645
	edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask);
646 647
}

648
/* Re-enable EDMA hardware events on the specified channel.  */
649
static void edma_resume(struct edma_chan *echan)
650
{
651 652
	int channel = EDMA_CHAN_SLOT(echan->ch_num);
	unsigned int mask = BIT(channel & 0x1f);
653

654
	edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask);
655 656
}

657
static void edma_trigger_channel(struct edma_chan *echan)
658
{
659 660 661
	struct edma_cc *ecc = echan->ecc;
	int channel = EDMA_CHAN_SLOT(echan->ch_num);
	unsigned int mask = BIT(channel & 0x1f);
662 663 664

	edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);

665 666
	dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
		edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
667 668
}

669
static void edma_clean_channel(struct edma_chan *echan)
670
{
671 672 673 674
	struct edma_cc *ecc = echan->ecc;
	int channel = EDMA_CHAN_SLOT(echan->ch_num);
	int j = (channel >> 5);
	unsigned int mask = BIT(channel & 0x1f);
675

676 677 678 679 680 681 682
	dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j));
	edma_shadow0_write_array(ecc, SH_ECR, j, mask);
	/* Clear the corresponding EMR bits */
	edma_write_array(ecc, EDMA_EMCR, j, mask);
	/* Clear any SER */
	edma_shadow0_write_array(ecc, SH_SECR, j, mask);
	edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
683 684
}

685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703
/* Move channel to a specific event queue */
static void edma_assign_channel_eventq(struct edma_chan *echan,
				       enum dma_event_q eventq_no)
{
	struct edma_cc *ecc = echan->ecc;
	int channel = EDMA_CHAN_SLOT(echan->ch_num);
	int bit = (channel & 0x7) * 4;

	/* default to low priority queue */
	if (eventq_no == EVENTQ_DEFAULT)
		eventq_no = ecc->default_queue;
	if (eventq_no >= ecc->num_tc)
		return;

	eventq_no &= 7;
	edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit),
			  eventq_no << bit);
}

704
static int edma_alloc_channel(struct edma_chan *echan,
705
			      enum dma_event_q eventq_no)
706
{
707 708
	struct edma_cc *ecc = echan->ecc;
	int channel = EDMA_CHAN_SLOT(echan->ch_num);
709 710 711 712 713

	/* ensure access through shadow region 0 */
	edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));

	/* ensure no events are pending */
714
	edma_stop(echan);
715

716
	edma_setup_interrupt(echan, true);
717

718
	edma_assign_channel_eventq(echan, eventq_no);
719

720
	return 0;
721 722
}

723
static void edma_free_channel(struct edma_chan *echan)
724
{
725 726
	/* ensure no events are pending */
	edma_stop(echan);
727
	/* REVISIT should probably take out of shadow region 0 */
728
	edma_setup_interrupt(echan, false);
729 730
}

731 732 733 734 735 736 737 738 739 740
static inline struct edma_cc *to_edma_cc(struct dma_device *d)
{
	return container_of(d, struct edma_cc, dma_slave);
}

static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
{
	return container_of(c, struct edma_chan, vchan.chan);
}

741
static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx)
742 743 744 745 746 747 748 749 750 751 752 753
{
	return container_of(tx, struct edma_desc, vdesc.tx);
}

static void edma_desc_free(struct virt_dma_desc *vdesc)
{
	kfree(container_of(vdesc, struct edma_desc, vdesc));
}

/* Dispatch a queued descriptor to the controller (caller holds lock) */
static void edma_execute(struct edma_chan *echan)
{
754
	struct edma_cc *ecc = echan->ecc;
755
	struct virt_dma_desc *vdesc;
756
	struct edma_desc *edesc;
757 758 759
	struct device *dev = echan->vchan.chan.device->dev;
	int i, j, left, nslots;

760 761
	if (!echan->edesc) {
		/* Setup is needed for the first transfer */
762
		vdesc = vchan_next_desc(&echan->vchan);
763
		if (!vdesc)
764 765 766
			return;
		list_del(&vdesc->node);
		echan->edesc = to_edma_desc(&vdesc->tx);
767 768
	}

769
	edesc = echan->edesc;
770

771 772 773
	/* Find out how many left */
	left = edesc->pset_nr - edesc->processed;
	nslots = min(MAX_NR_SG, left);
774
	edesc->sg_len = 0;
775 776

	/* Write descriptor PaRAM set(s) */
777 778
	for (i = 0; i < nslots; i++) {
		j = i + edesc->processed;
779
		edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
780
		edesc->sg_len += edesc->pset[j].len;
781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801
		dev_vdbg(dev,
			 "\n pset[%d]:\n"
			 "  chnum\t%d\n"
			 "  slot\t%d\n"
			 "  opt\t%08x\n"
			 "  src\t%08x\n"
			 "  dst\t%08x\n"
			 "  abcnt\t%08x\n"
			 "  ccnt\t%08x\n"
			 "  bidx\t%08x\n"
			 "  cidx\t%08x\n"
			 "  lkrld\t%08x\n",
			 j, echan->ch_num, echan->slot[i],
			 edesc->pset[j].param.opt,
			 edesc->pset[j].param.src,
			 edesc->pset[j].param.dst,
			 edesc->pset[j].param.a_b_cnt,
			 edesc->pset[j].param.ccnt,
			 edesc->pset[j].param.src_dst_bidx,
			 edesc->pset[j].param.src_dst_cidx,
			 edesc->pset[j].param.link_bcntrld);
802
		/* Link to the previous slot if not the last set */
803
		if (i != (nslots - 1))
804
			edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
805 806
	}

807 808
	edesc->processed += nslots;

809 810 811 812 813
	/*
	 * If this is either the last set in a set of SG-list transactions
	 * then setup a link to the dummy slot, this results in all future
	 * events being absorbed and that's OK because we're done
	 */
814 815
	if (edesc->processed == edesc->pset_nr) {
		if (edesc->cyclic)
816
			edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
817
		else
818
			edma_link(ecc, echan->slot[nslots - 1],
819 820
				  echan->ecc->dummy_slot);
	}
821

822
	if (echan->missed) {
823 824 825 826 827
		/*
		 * This happens due to setup times between intermediate
		 * transfers in long SG lists which have to be broken up into
		 * transfers of MAX_NR_SG
		 */
828
		dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
829 830 831 832
		edma_clean_channel(echan);
		edma_stop(echan);
		edma_start(echan);
		edma_trigger_channel(echan);
833
		echan->missed = 0;
834 835 836
	} else if (edesc->processed <= MAX_NR_SG) {
		dev_dbg(dev, "first transfer starting on channel %d\n",
			echan->ch_num);
837
		edma_start(echan);
838 839 840
	} else {
		dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
			echan->ch_num, edesc->processed);
841
		edma_resume(echan);
842
	}
843 844
}

845
static int edma_terminate_all(struct dma_chan *chan)
846
{
847
	struct edma_chan *echan = to_edma_chan(chan);
848 849 850 851 852 853 854 855 856 857 858
	unsigned long flags;
	LIST_HEAD(head);

	spin_lock_irqsave(&echan->vchan.lock, flags);

	/*
	 * Stop DMA activity: we assume the callback will not be called
	 * after edma_dma() returns (even if it does, it will see
	 * echan->edesc is NULL and exit.)
	 */
	if (echan->edesc) {
859
		edma_stop(echan);
860
		/* Move the cyclic channel back to default queue */
861
		if (!echan->tc && echan->edesc->cyclic)
862
			edma_assign_channel_eventq(echan, EVENTQ_DEFAULT);
863 864

		vchan_terminate_vdesc(&echan->edesc->vdesc);
865 866 867 868 869 870 871 872 873 874
		echan->edesc = NULL;
	}

	vchan_get_all_descriptors(&echan->vchan, &head);
	spin_unlock_irqrestore(&echan->vchan.lock, flags);
	vchan_dma_desc_free_list(&echan->vchan, &head);

	return 0;
}

875 876 877 878 879 880 881
static void edma_synchronize(struct dma_chan *chan)
{
	struct edma_chan *echan = to_edma_chan(chan);

	vchan_synchronize(&echan->vchan);
}

882
static int edma_slave_config(struct dma_chan *chan,
883
	struct dma_slave_config *cfg)
884
{
885 886
	struct edma_chan *echan = to_edma_chan(chan);

887 888
	if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
	    cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
889 890
		return -EINVAL;

891 892 893 894
	if (cfg->src_maxburst > chan->device->max_burst ||
	    cfg->dst_maxburst > chan->device->max_burst)
		return -EINVAL;

895
	memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
896 897 898 899

	return 0;
}

900
static int edma_dma_pause(struct dma_chan *chan)
901
{
902 903
	struct edma_chan *echan = to_edma_chan(chan);

904
	if (!echan->edesc)
905 906
		return -EINVAL;

907
	edma_pause(echan);
908 909 910
	return 0;
}

911
static int edma_dma_resume(struct dma_chan *chan)
912
{
913 914
	struct edma_chan *echan = to_edma_chan(chan);

915
	edma_resume(echan);
916 917 918
	return 0;
}

919 920 921 922 923 924 925 926 927 928 929
/*
 * A PaRAM set configuration abstraction used by other modes
 * @chan: Channel who's PaRAM set we're configuring
 * @pset: PaRAM set to initialize and setup.
 * @src_addr: Source address of the DMA
 * @dst_addr: Destination address of the DMA
 * @burst: In units of dev_width, how much to send
 * @dev_width: How much is the dev_width
 * @dma_length: Total length of the DMA transfer
 * @direction: Direction of the transfer
 */
930
static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
931
			    dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
932
			    unsigned int acnt, unsigned int dma_length,
933
			    enum dma_transfer_direction direction)
934 935 936
{
	struct edma_chan *echan = to_edma_chan(chan);
	struct device *dev = chan->device->dev;
937
	struct edmacc_param *param = &epset->param;
938
	int bcnt, ccnt, cidx;
939 940 941
	int src_bidx, dst_bidx, src_cidx, dst_cidx;
	int absync;

942 943 944
	/* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
	if (!burst)
		burst = 1;
945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994
	/*
	 * If the maxburst is equal to the fifo width, use
	 * A-synced transfers. This allows for large contiguous
	 * buffer transfers using only one PaRAM set.
	 */
	if (burst == 1) {
		/*
		 * For the A-sync case, bcnt and ccnt are the remainder
		 * and quotient respectively of the division of:
		 * (dma_length / acnt) by (SZ_64K -1). This is so
		 * that in case bcnt over flows, we have ccnt to use.
		 * Note: In A-sync tranfer only, bcntrld is used, but it
		 * only applies for sg_dma_len(sg) >= SZ_64K.
		 * In this case, the best way adopted is- bccnt for the
		 * first frame will be the remainder below. Then for
		 * every successive frame, bcnt will be SZ_64K-1. This
		 * is assured as bcntrld = 0xffff in end of function.
		 */
		absync = false;
		ccnt = dma_length / acnt / (SZ_64K - 1);
		bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
		/*
		 * If bcnt is non-zero, we have a remainder and hence an
		 * extra frame to transfer, so increment ccnt.
		 */
		if (bcnt)
			ccnt++;
		else
			bcnt = SZ_64K - 1;
		cidx = acnt;
	} else {
		/*
		 * If maxburst is greater than the fifo address_width,
		 * use AB-synced transfers where A count is the fifo
		 * address_width and B count is the maxburst. In this
		 * case, we are limited to transfers of C count frames
		 * of (address_width * maxburst) where C count is limited
		 * to SZ_64K-1. This places an upper bound on the length
		 * of an SG segment that can be handled.
		 */
		absync = true;
		bcnt = burst;
		ccnt = dma_length / (acnt * bcnt);
		if (ccnt > (SZ_64K - 1)) {
			dev_err(dev, "Exceeded max SG segment size\n");
			return -EINVAL;
		}
		cidx = acnt * bcnt;
	}

995 996
	epset->len = dma_length;

997 998 999 1000 1001
	if (direction == DMA_MEM_TO_DEV) {
		src_bidx = acnt;
		src_cidx = cidx;
		dst_bidx = 0;
		dst_cidx = 0;
1002
		epset->addr = src_addr;
1003 1004 1005 1006 1007
	} else if (direction == DMA_DEV_TO_MEM)  {
		src_bidx = 0;
		src_cidx = 0;
		dst_bidx = acnt;
		dst_cidx = cidx;
1008
		epset->addr = dst_addr;
1009 1010 1011 1012 1013
	} else if (direction == DMA_MEM_TO_MEM)  {
		src_bidx = acnt;
		src_cidx = cidx;
		dst_bidx = acnt;
		dst_cidx = cidx;
1014 1015 1016 1017 1018
	} else {
		dev_err(dev, "%s: direction not implemented yet\n", __func__);
		return -EINVAL;
	}

1019
	param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
1020 1021
	/* Configure A or AB synchronized transfers */
	if (absync)
1022
		param->opt |= SYNCDIM;
1023

1024 1025
	param->src = src_addr;
	param->dst = dst_addr;
1026

1027 1028
	param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
	param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
1029

1030 1031
	param->a_b_cnt = bcnt << 16 | acnt;
	param->ccnt = ccnt;
1032 1033 1034 1035 1036 1037
	/*
	 * Only time when (bcntrld) auto reload is required is for
	 * A-sync case, and in this case, a requirement of reload value
	 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
	 * and then later will be populated by edma_execute.
	 */
1038
	param->link_bcntrld = 0xffffffff;
1039 1040 1041
	return absync;
}

1042 1043 1044 1045 1046 1047 1048 1049
static struct dma_async_tx_descriptor *edma_prep_slave_sg(
	struct dma_chan *chan, struct scatterlist *sgl,
	unsigned int sg_len, enum dma_transfer_direction direction,
	unsigned long tx_flags, void *context)
{
	struct edma_chan *echan = to_edma_chan(chan);
	struct device *dev = chan->device->dev;
	struct edma_desc *edesc;
1050
	dma_addr_t src_addr = 0, dst_addr = 0;
1051 1052
	enum dma_slave_buswidth dev_width;
	u32 burst;
1053
	struct scatterlist *sg;
1054
	int i, nslots, ret;
1055 1056 1057 1058

	if (unlikely(!echan || !sgl || !sg_len))
		return NULL;

1059
	if (direction == DMA_DEV_TO_MEM) {
1060
		src_addr = echan->cfg.src_addr;
1061 1062 1063
		dev_width = echan->cfg.src_addr_width;
		burst = echan->cfg.src_maxburst;
	} else if (direction == DMA_MEM_TO_DEV) {
1064
		dst_addr = echan->cfg.dst_addr;
1065 1066 1067
		dev_width = echan->cfg.dst_addr_width;
		burst = echan->cfg.dst_maxburst;
	} else {
1068
		dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1069 1070 1071 1072
		return NULL;
	}

	if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1073
		dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1074 1075 1076
		return NULL;
	}

1077 1078
	edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]),
			GFP_ATOMIC);
1079
	if (!edesc)
1080 1081 1082
		return NULL;

	edesc->pset_nr = sg_len;
1083
	edesc->residue = 0;
1084
	edesc->direction = direction;
1085
	edesc->echan = echan;
1086

1087 1088 1089 1090
	/* Allocate a PaRAM slot, if needed */
	nslots = min_t(unsigned, MAX_NR_SG, sg_len);

	for (i = 0; i < nslots; i++) {
1091 1092
		if (echan->slot[i] < 0) {
			echan->slot[i] =
1093
				edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1094
			if (echan->slot[i] < 0) {
1095
				kfree(edesc);
1096 1097
				dev_err(dev, "%s: Failed to allocate slot\n",
					__func__);
1098 1099 1100
				return NULL;
			}
		}
1101 1102 1103 1104
	}

	/* Configure PaRAM sets for each SG */
	for_each_sg(sgl, sg, sg_len, i) {
1105 1106 1107 1108 1109
		/* Get address for each SG */
		if (direction == DMA_DEV_TO_MEM)
			dst_addr = sg_dma_address(sg);
		else
			src_addr = sg_dma_address(sg);
1110

1111 1112 1113
		ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
				       dst_addr, burst, dev_width,
				       sg_dma_len(sg), direction);
1114 1115
		if (ret < 0) {
			kfree(edesc);
1116
			return NULL;
1117 1118
		}

1119
		edesc->absync = ret;
1120
		edesc->residue += sg_dma_len(sg);
1121

1122
		if (i == sg_len - 1)
1123
			/* Enable completion interrupt */
1124
			edesc->pset[i].param.opt |= TCINTEN;
1125 1126 1127 1128 1129 1130 1131 1132
		else if (!((i+1) % MAX_NR_SG))
			/*
			 * Enable early completion interrupt for the
			 * intermediateset. In this case the driver will be
			 * notified when the paRAM set is submitted to TC. This
			 * will allow more time to set up the next set of slots.
			 */
			edesc->pset[i].param.opt |= (TCINTEN | TCCMODE);
1133
	}
1134
	edesc->residue_stat = edesc->residue;
1135 1136 1137 1138

	return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
}

1139
static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
1140 1141 1142
	struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
	size_t len, unsigned long tx_flags)
{
1143
	int ret, nslots;
1144 1145 1146
	struct edma_desc *edesc;
	struct device *dev = chan->device->dev;
	struct edma_chan *echan = to_edma_chan(chan);
1147
	unsigned int width, pset_len, array_size;
1148 1149 1150 1151

	if (unlikely(!echan || !len))
		return NULL;

1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164
	/* Align the array size (acnt block) with the transfer properties */
	switch (__ffs((src | dest | len))) {
	case 0:
		array_size = SZ_32K - 1;
		break;
	case 1:
		array_size = SZ_32K - 2;
		break;
	default:
		array_size = SZ_32K - 4;
		break;
	}

1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185
	if (len < SZ_64K) {
		/*
		 * Transfer size less than 64K can be handled with one paRAM
		 * slot and with one burst.
		 * ACNT = length
		 */
		width = len;
		pset_len = len;
		nslots = 1;
	} else {
		/*
		 * Transfer size bigger than 64K will be handled with maximum of
		 * two paRAM slots.
		 * slot1: (full_length / 32767) times 32767 bytes bursts.
		 *	  ACNT = 32767, length1: (full_length / 32767) * 32767
		 * slot2: the remaining amount of data after slot1.
		 *	  ACNT = full_length - length1, length2 = ACNT
		 *
		 * When the full_length is multibple of 32767 one slot can be
		 * used to complete the transfer.
		 */
1186
		width = array_size;
1187 1188 1189 1190 1191 1192 1193 1194 1195 1196
		pset_len = rounddown(len, width);
		/* One slot is enough for lengths multiple of (SZ_32K -1) */
		if (unlikely(pset_len == len))
			nslots = 1;
		else
			nslots = 2;
	}

	edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
			GFP_ATOMIC);
1197
	if (!edesc)
1198 1199
		return NULL;

1200 1201 1202 1203
	edesc->pset_nr = nslots;
	edesc->residue = edesc->residue_stat = len;
	edesc->direction = DMA_MEM_TO_MEM;
	edesc->echan = echan;
1204

1205
	ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
1206 1207 1208
			       width, pset_len, DMA_MEM_TO_MEM);
	if (ret < 0) {
		kfree(edesc);
1209
		return NULL;
1210
	}
1211 1212 1213

	edesc->absync = ret;

1214
	edesc->pset[0].param.opt |= ITCCHEN;
1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233
	if (nslots == 1) {
		/* Enable transfer complete interrupt */
		edesc->pset[0].param.opt |= TCINTEN;
	} else {
		/* Enable transfer complete chaining for the first slot */
		edesc->pset[0].param.opt |= TCCHEN;

		if (echan->slot[1] < 0) {
			echan->slot[1] = edma_alloc_slot(echan->ecc,
							 EDMA_SLOT_ANY);
			if (echan->slot[1] < 0) {
				kfree(edesc);
				dev_err(dev, "%s: Failed to allocate slot\n",
					__func__);
				return NULL;
			}
		}
		dest += pset_len;
		src += pset_len;
1234
		pset_len = width = len % array_size;
1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245

		ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1,
				       width, pset_len, DMA_MEM_TO_MEM);
		if (ret < 0) {
			kfree(edesc);
			return NULL;
		}

		edesc->pset[1].param.opt |= ITCCHEN;
		edesc->pset[1].param.opt |= TCINTEN;
	}
1246 1247 1248 1249

	return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
}

1250 1251 1252
static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
	struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
	size_t period_len, enum dma_transfer_direction direction,
1253
	unsigned long tx_flags)
1254 1255 1256 1257 1258 1259
{
	struct edma_chan *echan = to_edma_chan(chan);
	struct device *dev = chan->device->dev;
	struct edma_desc *edesc;
	dma_addr_t src_addr, dst_addr;
	enum dma_slave_buswidth dev_width;
1260
	bool use_intermediate = false;
1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277
	u32 burst;
	int i, ret, nslots;

	if (unlikely(!echan || !buf_len || !period_len))
		return NULL;

	if (direction == DMA_DEV_TO_MEM) {
		src_addr = echan->cfg.src_addr;
		dst_addr = buf_addr;
		dev_width = echan->cfg.src_addr_width;
		burst = echan->cfg.src_maxburst;
	} else if (direction == DMA_MEM_TO_DEV) {
		src_addr = buf_addr;
		dst_addr = echan->cfg.dst_addr;
		dev_width = echan->cfg.dst_addr_width;
		burst = echan->cfg.dst_maxburst;
	} else {
1278
		dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1279 1280 1281 1282
		return NULL;
	}

	if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1283
		dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301
		return NULL;
	}

	if (unlikely(buf_len % period_len)) {
		dev_err(dev, "Period should be multiple of Buffer length\n");
		return NULL;
	}

	nslots = (buf_len / period_len) + 1;

	/*
	 * Cyclic DMA users such as audio cannot tolerate delays introduced
	 * by cases where the number of periods is more than the maximum
	 * number of SGs the EDMA driver can handle at a time. For DMA types
	 * such as Slave SGs, such delays are tolerable and synchronized,
	 * but the synchronization is difficult to achieve with Cyclic and
	 * cannot be guaranteed, so we error out early.
	 */
1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316
	if (nslots > MAX_NR_SG) {
		/*
		 * If the burst and period sizes are the same, we can put
		 * the full buffer into a single period and activate
		 * intermediate interrupts. This will produce interrupts
		 * after each burst, which is also after each desired period.
		 */
		if (burst == period_len) {
			period_len = buf_len;
			nslots = 2;
			use_intermediate = true;
		} else {
			return NULL;
		}
	}
1317

1318 1319
	edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
			GFP_ATOMIC);
1320
	if (!edesc)
1321 1322 1323 1324
		return NULL;

	edesc->cyclic = 1;
	edesc->pset_nr = nslots;
1325
	edesc->residue = edesc->residue_stat = buf_len;
1326
	edesc->direction = direction;
1327
	edesc->echan = echan;
1328

1329 1330
	dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
		__func__, echan->ch_num, nslots, period_len, buf_len);
1331 1332 1333 1334 1335

	for (i = 0; i < nslots; i++) {
		/* Allocate a PaRAM slot, if needed */
		if (echan->slot[i] < 0) {
			echan->slot[i] =
1336
				edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1337
			if (echan->slot[i] < 0) {
1338
				kfree(edesc);
1339 1340
				dev_err(dev, "%s: Failed to allocate slot\n",
					__func__);
1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353
				return NULL;
			}
		}

		if (i == nslots - 1) {
			memcpy(&edesc->pset[i], &edesc->pset[0],
			       sizeof(edesc->pset[0]));
			break;
		}

		ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
				       dst_addr, burst, dev_width, period_len,
				       direction);
1354 1355
		if (ret < 0) {
			kfree(edesc);
1356
			return NULL;
1357
		}
1358

1359 1360 1361 1362
		if (direction == DMA_DEV_TO_MEM)
			dst_addr += period_len;
		else
			src_addr += period_len;
1363

1364 1365
		dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
		dev_vdbg(dev,
1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377
			"\n pset[%d]:\n"
			"  chnum\t%d\n"
			"  slot\t%d\n"
			"  opt\t%08x\n"
			"  src\t%08x\n"
			"  dst\t%08x\n"
			"  abcnt\t%08x\n"
			"  ccnt\t%08x\n"
			"  bidx\t%08x\n"
			"  cidx\t%08x\n"
			"  lkrld\t%08x\n",
			i, echan->ch_num, echan->slot[i],
1378 1379 1380 1381 1382 1383 1384 1385
			edesc->pset[i].param.opt,
			edesc->pset[i].param.src,
			edesc->pset[i].param.dst,
			edesc->pset[i].param.a_b_cnt,
			edesc->pset[i].param.ccnt,
			edesc->pset[i].param.src_dst_bidx,
			edesc->pset[i].param.src_dst_cidx,
			edesc->pset[i].param.link_bcntrld);
1386 1387 1388 1389

		edesc->absync = ret;

		/*
1390
		 * Enable period interrupt only if it is requested
1391
		 */
1392
		if (tx_flags & DMA_PREP_INTERRUPT) {
1393
			edesc->pset[i].param.opt |= TCINTEN;
1394 1395 1396 1397 1398

			/* Also enable intermediate interrupts if necessary */
			if (use_intermediate)
				edesc->pset[i].param.opt |= ITCINTEN;
		}
1399 1400
	}

1401
	/* Place the cyclic channel to highest priority queue */
1402 1403
	if (!echan->tc)
		edma_assign_channel_eventq(echan, EVENTQ_0);
1404

1405 1406 1407
	return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
}

1408
static void edma_completion_handler(struct edma_chan *echan)
1409 1410
{
	struct device *dev = echan->vchan.chan.device->dev;
1411
	struct edma_desc *edesc;
1412

1413
	spin_lock(&echan->vchan.lock);
1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439
	edesc = echan->edesc;
	if (edesc) {
		if (edesc->cyclic) {
			vchan_cyclic_callback(&edesc->vdesc);
			spin_unlock(&echan->vchan.lock);
			return;
		} else if (edesc->processed == edesc->pset_nr) {
			edesc->residue = 0;
			edma_stop(echan);
			vchan_cookie_complete(&edesc->vdesc);
			echan->edesc = NULL;

			dev_dbg(dev, "Transfer completed on channel %d\n",
				echan->ch_num);
		} else {
			dev_dbg(dev, "Sub transfer completed on channel %d\n",
				echan->ch_num);

			edma_pause(echan);

			/* Update statistics for tx_status */
			edesc->residue -= edesc->sg_len;
			edesc->residue_stat = edesc->residue;
			edesc->processed_stat = edesc->processed;
		}
		edma_execute(echan);
1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483
	}

	spin_unlock(&echan->vchan.lock);
}

/* eDMA interrupt handler */
static irqreturn_t dma_irq_handler(int irq, void *data)
{
	struct edma_cc *ecc = data;
	int ctlr;
	u32 sh_ier;
	u32 sh_ipr;
	u32 bank;

	ctlr = ecc->id;
	if (ctlr < 0)
		return IRQ_NONE;

	dev_vdbg(ecc->dev, "dma_irq_handler\n");

	sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
	if (!sh_ipr) {
		sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
		if (!sh_ipr)
			return IRQ_NONE;
		sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
		bank = 1;
	} else {
		sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
		bank = 0;
	}

	do {
		u32 slot;
		u32 channel;

		slot = __ffs(sh_ipr);
		sh_ipr &= ~(BIT(slot));

		if (sh_ier & BIT(slot)) {
			channel = (bank << 5) | slot;
			/* Clear the corresponding IPR bits */
			edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
			edma_completion_handler(&ecc->slave_chans[channel]);
1484
		}
1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495
	} while (sh_ipr);

	edma_shadow0_write(ecc, SH_IEVAL, 1);
	return IRQ_HANDLED;
}

static void edma_error_handler(struct edma_chan *echan)
{
	struct edma_cc *ecc = echan->ecc;
	struct device *dev = echan->vchan.chan.device->dev;
	struct edmacc_param p;
1496
	int err;
1497 1498 1499 1500 1501

	if (!echan->edesc)
		return;

	spin_lock(&echan->vchan.lock);
1502

1503 1504
	err = edma_read_slot(ecc, echan->slot[0], &p);

1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516
	/*
	 * Issue later based on missed flag which will be sure
	 * to happen as:
	 * (1) we finished transmitting an intermediate slot and
	 *     edma_execute is coming up.
	 * (2) or we finished current transfer and issue will
	 *     call edma_execute.
	 *
	 * Important note: issuing can be dangerous here and
	 * lead to some nasty recursion when we are in a NULL
	 * slot. So we avoid doing so and set the missed flag.
	 */
1517
	if (err || (p.a_b_cnt == 0 && p.ccnt == 0)) {
1518 1519 1520
		dev_dbg(dev, "Error on null slot, setting miss\n");
		echan->missed = 1;
	} else {
1521
		/*
1522 1523
		 * The slot is already programmed but the event got
		 * missed, so its safe to issue it here.
1524
		 */
1525
		dev_dbg(dev, "Missed event, TRIGGERING\n");
1526 1527 1528 1529
		edma_clean_channel(echan);
		edma_stop(echan);
		edma_start(echan);
		edma_trigger_channel(echan);
1530 1531 1532 1533
	}
	spin_unlock(&echan->vchan.lock);
}

1534 1535 1536 1537 1538 1539 1540 1541 1542 1543
static inline bool edma_error_pending(struct edma_cc *ecc)
{
	if (edma_read_array(ecc, EDMA_EMR, 0) ||
	    edma_read_array(ecc, EDMA_EMR, 1) ||
	    edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR))
		return true;

	return false;
}

1544 1545 1546 1547
/* eDMA error interrupt handler */
static irqreturn_t dma_ccerr_handler(int irq, void *data)
{
	struct edma_cc *ecc = data;
1548
	int i, j;
1549 1550
	int ctlr;
	unsigned int cnt = 0;
1551
	unsigned int val;
1552 1553 1554 1555 1556 1557 1558

	ctlr = ecc->id;
	if (ctlr < 0)
		return IRQ_NONE;

	dev_vdbg(ecc->dev, "dma_ccerr_handler\n");

1559 1560 1561 1562 1563 1564 1565 1566 1567
	if (!edma_error_pending(ecc)) {
		/*
		 * The registers indicate no pending error event but the irq
		 * handler has been called.
		 * Ask eDMA to re-evaluate the error registers.
		 */
		dev_err(ecc->dev, "%s: Error interrupt without error event!\n",
			__func__);
		edma_write(ecc, EDMA_EEVAL, 1);
1568
		return IRQ_NONE;
1569
	}
1570 1571

	while (1) {
1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583
		/* Event missed register(s) */
		for (j = 0; j < 2; j++) {
			unsigned long emr;

			val = edma_read_array(ecc, EDMA_EMR, j);
			if (!val)
				continue;

			dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val);
			emr = val;
			for (i = find_next_bit(&emr, 32, 0); i < 32;
			     i = find_next_bit(&emr, 32, i + 1)) {
1584 1585
				int k = (j << 5) + i;

1586 1587 1588 1589
				/* Clear the corresponding EMR bits */
				edma_write_array(ecc, EDMA_EMCR, j, BIT(i));
				/* Clear any SER */
				edma_shadow0_write_array(ecc, SH_SECR, j,
1590
							 BIT(i));
1591
				edma_error_handler(&ecc->slave_chans[k]);
1592
			}
1593
		}
1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609

		val = edma_read(ecc, EDMA_QEMR);
		if (val) {
			dev_dbg(ecc->dev, "QEMR 0x%02x\n", val);
			/* Not reported, just clear the interrupt reason. */
			edma_write(ecc, EDMA_QEMCR, val);
			edma_shadow0_write(ecc, SH_QSECR, val);
		}

		val = edma_read(ecc, EDMA_CCERR);
		if (val) {
			dev_warn(ecc->dev, "CCERR 0x%08x\n", val);
			/* Not reported, just clear the interrupt reason. */
			edma_write(ecc, EDMA_CCERRCLR, val);
		}

1610
		if (!edma_error_pending(ecc))
1611 1612 1613 1614
			break;
		cnt++;
		if (cnt > 10)
			break;
1615
	}
1616 1617
	edma_write(ecc, EDMA_EEVAL, 1);
	return IRQ_HANDLED;
1618 1619 1620 1621 1622 1623
}

/* Alloc channel resources */
static int edma_alloc_chan_resources(struct dma_chan *chan)
{
	struct edma_chan *echan = to_edma_chan(chan);
1624 1625 1626
	struct edma_cc *ecc = echan->ecc;
	struct device *dev = ecc->dev;
	enum dma_event_q eventq_no = EVENTQ_DEFAULT;
1627 1628
	int ret;

1629 1630 1631 1632 1633 1634 1635 1636 1637
	if (echan->tc) {
		eventq_no = echan->tc->id;
	} else if (ecc->tc_list) {
		/* memcpy channel */
		echan->tc = &ecc->tc_list[ecc->info->default_queue];
		eventq_no = echan->tc->id;
	}

	ret = edma_alloc_channel(echan, eventq_no);
1638 1639
	if (ret)
		return ret;
1640

1641
	echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num);
1642 1643 1644
	if (echan->slot[0] < 0) {
		dev_err(dev, "Entry slot allocation failed for channel %u\n",
			EDMA_CHAN_SLOT(echan->ch_num));
1645
		ret = echan->slot[0];
1646
		goto err_slot;
1647 1648 1649
	}

	/* Set up channel -> slot mapping for the entry slot */
1650 1651
	edma_set_chmap(echan, echan->slot[0]);
	echan->alloced = true;
1652

1653 1654 1655 1656
	dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n",
		EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id,
		echan->hw_triggered ? "HW" : "SW");

1657 1658
	return 0;

1659 1660
err_slot:
	edma_free_channel(echan);
1661 1662 1663 1664 1665 1666 1667
	return ret;
}

/* Free channel resources */
static void edma_free_chan_resources(struct dma_chan *chan)
{
	struct edma_chan *echan = to_edma_chan(chan);
1668
	struct device *dev = echan->ecc->dev;
1669 1670 1671
	int i;

	/* Terminate transfers */
1672
	edma_stop(echan);
1673 1674 1675 1676

	vchan_free_chan_resources(&echan->vchan);

	/* Free EDMA PaRAM slots */
1677
	for (i = 0; i < EDMA_MAX_SLOTS; i++) {
1678
		if (echan->slot[i] >= 0) {
1679
			edma_free_slot(echan->ecc, echan->slot[i]);
1680 1681 1682 1683
			echan->slot[i] = -1;
		}
	}

1684
	/* Set entry slot to the dummy slot */
1685
	edma_set_chmap(echan, echan->ecc->dummy_slot);
1686

1687 1688
	/* Free EDMA channel */
	if (echan->alloced) {
1689
		edma_free_channel(echan);
1690 1691 1692
		echan->alloced = false;
	}

1693 1694 1695 1696 1697
	echan->tc = NULL;
	echan->hw_triggered = false;

	dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n",
		EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id);
1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711
}

/* Send pending descriptor to hardware */
static void edma_issue_pending(struct dma_chan *chan)
{
	struct edma_chan *echan = to_edma_chan(chan);
	unsigned long flags;

	spin_lock_irqsave(&echan->vchan.lock, flags);
	if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
		edma_execute(echan);
	spin_unlock_irqrestore(&echan->vchan.lock, flags);
}

1712 1713 1714 1715 1716 1717 1718 1719 1720
/*
 * This limit exists to avoid a possible infinite loop when waiting for proof
 * that a particular transfer is completed. This limit can be hit if there
 * are large bursts to/from slow devices or the CPU is never able to catch
 * the DMA hardware idle. On an AM335x transfering 48 bytes from the UART
 * RX-FIFO, as many as 55 loops have been seen.
 */
#define EDMA_MAX_TR_WAIT_LOOPS 1000

1721 1722 1723
static u32 edma_residue(struct edma_desc *edesc)
{
	bool dst = edesc->direction == DMA_DEV_TO_MEM;
1724 1725
	int loop_count = EDMA_MAX_TR_WAIT_LOOPS;
	struct edma_chan *echan = edesc->echan;
1726 1727 1728 1729 1730 1731 1732 1733
	struct edma_pset *pset = edesc->pset;
	dma_addr_t done, pos;
	int i;

	/*
	 * We always read the dst/src position from the first RamPar
	 * pset. That's the one which is active now.
	 */
1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759
	pos = edma_get_position(echan->ecc, echan->slot[0], dst);

	/*
	 * "pos" may represent a transfer request that is still being
	 * processed by the EDMACC or EDMATC. We will busy wait until
	 * any one of the situations occurs:
	 *   1. the DMA hardware is idle
	 *   2. a new transfer request is setup
	 *   3. we hit the loop limit
	 */
	while (edma_read(echan->ecc, EDMA_CCSTAT) & EDMA_CCSTAT_ACTV) {
		/* check if a new transfer request is setup */
		if (edma_get_position(echan->ecc,
				      echan->slot[0], dst) != pos) {
			break;
		}

		if (!--loop_count) {
			dev_dbg_ratelimited(echan->vchan.chan.device->dev,
				"%s: timeout waiting for PaRAM update\n",
				__func__);
			break;
		}

		cpu_relax();
	}
1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795

	/*
	 * Cyclic is simple. Just subtract pset[0].addr from pos.
	 *
	 * We never update edesc->residue in the cyclic case, so we
	 * can tell the remaining room to the end of the circular
	 * buffer.
	 */
	if (edesc->cyclic) {
		done = pos - pset->addr;
		edesc->residue_stat = edesc->residue - done;
		return edesc->residue_stat;
	}

	/*
	 * For SG operation we catch up with the last processed
	 * status.
	 */
	pset += edesc->processed_stat;

	for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) {
		/*
		 * If we are inside this pset address range, we know
		 * this is the active one. Get the current delta and
		 * stop walking the psets.
		 */
		if (pos >= pset->addr && pos < pset->addr + pset->len)
			return edesc->residue_stat - (pos - pset->addr);

		/* Otherwise mark it done and update residue_stat. */
		edesc->processed_stat++;
		edesc->residue_stat -= pset->len;
	}
	return edesc->residue_stat;
}

1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806
/* Check request completion status */
static enum dma_status edma_tx_status(struct dma_chan *chan,
				      dma_cookie_t cookie,
				      struct dma_tx_state *txstate)
{
	struct edma_chan *echan = to_edma_chan(chan);
	struct virt_dma_desc *vdesc;
	enum dma_status ret;
	unsigned long flags;

	ret = dma_cookie_status(chan, cookie, txstate);
1807
	if (ret == DMA_COMPLETE || !txstate)
1808 1809 1810
		return ret;

	spin_lock_irqsave(&echan->vchan.lock, flags);
1811
	if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie)
1812
		txstate->residue = edma_residue(echan->edesc);
1813 1814
	else if ((vdesc = vchan_find_desc(&echan->vchan, cookie)))
		txstate->residue = to_edma_desc(&vdesc->tx)->residue;
1815 1816 1817 1818 1819
	spin_unlock_irqrestore(&echan->vchan.lock, flags);

	return ret;
}

1820
static bool edma_is_memcpy_channel(int ch_num, s32 *memcpy_channels)
1821 1822 1823
{
	if (!memcpy_channels)
		return false;
1824 1825
	while (*memcpy_channels != -1) {
		if (*memcpy_channels == ch_num)
1826
			return true;
1827
		memcpy_channels++;
1828 1829 1830 1831
	}
	return false;
}

1832 1833 1834 1835 1836
#define EDMA_DMA_BUSWIDTHS	(BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
				 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
				 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
				 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))

1837
static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode)
1838
{
1839 1840
	struct dma_device *s_ddev = &ecc->dma_slave;
	struct dma_device *m_ddev = NULL;
1841
	s32 *memcpy_channels = ecc->info->memcpy_channels;
1842 1843
	int i, j;

1844 1845 1846 1847 1848 1849
	dma_cap_zero(s_ddev->cap_mask);
	dma_cap_set(DMA_SLAVE, s_ddev->cap_mask);
	dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask);
	if (ecc->legacy_mode && !memcpy_channels) {
		dev_warn(ecc->dev,
			 "Legacy memcpy is enabled, things might not work\n");
1850

1851 1852 1853 1854
		dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask);
		s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
		s_ddev->directions = BIT(DMA_MEM_TO_MEM);
	}
1855

1856 1857 1858 1859 1860 1861 1862 1863 1864 1865
	s_ddev->device_prep_slave_sg = edma_prep_slave_sg;
	s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic;
	s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
	s_ddev->device_free_chan_resources = edma_free_chan_resources;
	s_ddev->device_issue_pending = edma_issue_pending;
	s_ddev->device_tx_status = edma_tx_status;
	s_ddev->device_config = edma_slave_config;
	s_ddev->device_pause = edma_dma_pause;
	s_ddev->device_resume = edma_dma_resume;
	s_ddev->device_terminate_all = edma_terminate_all;
1866
	s_ddev->device_synchronize = edma_synchronize;
1867 1868 1869 1870 1871

	s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
	s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
	s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV));
	s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1872
	s_ddev->max_burst = SZ_32K - 1; /* CIDX: 16bit signed */
1873 1874 1875 1876 1877 1878

	s_ddev->dev = ecc->dev;
	INIT_LIST_HEAD(&s_ddev->channels);

	if (memcpy_channels) {
		m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL);
1879 1880 1881 1882 1883
		if (!m_ddev) {
			dev_warn(ecc->dev, "memcpy is disabled due to OoM\n");
			memcpy_channels = NULL;
			goto ch_setup;
		}
1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897
		ecc->dma_memcpy = m_ddev;

		dma_cap_zero(m_ddev->cap_mask);
		dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask);

		m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
		m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
		m_ddev->device_free_chan_resources = edma_free_chan_resources;
		m_ddev->device_issue_pending = edma_issue_pending;
		m_ddev->device_tx_status = edma_tx_status;
		m_ddev->device_config = edma_slave_config;
		m_ddev->device_pause = edma_dma_pause;
		m_ddev->device_resume = edma_dma_resume;
		m_ddev->device_terminate_all = edma_terminate_all;
1898
		m_ddev->device_synchronize = edma_synchronize;
1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909

		m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
		m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
		m_ddev->directions = BIT(DMA_MEM_TO_MEM);
		m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;

		m_ddev->dev = ecc->dev;
		INIT_LIST_HEAD(&m_ddev->channels);
	} else if (!ecc->legacy_mode) {
		dev_info(ecc->dev, "memcpy is disabled\n");
	}
1910

1911
ch_setup:
1912
	for (i = 0; i < ecc->num_channels; i++) {
1913
		struct edma_chan *echan = &ecc->slave_chans[i];
1914
		echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
1915 1916 1917
		echan->ecc = ecc;
		echan->vchan.desc_free = edma_desc_free;

1918 1919 1920 1921
		if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels))
			vchan_init(&echan->vchan, m_ddev);
		else
			vchan_init(&echan->vchan, s_ddev);
1922 1923 1924 1925 1926 1927 1928

		INIT_LIST_HEAD(&echan->node);
		for (j = 0; j < EDMA_MAX_SLOTS; j++)
			echan->slot[j] = -1;
	}
}

1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944
static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
			      struct edma_cc *ecc)
{
	int i;
	u32 value, cccfg;
	s8 (*queue_priority_map)[2];

	/* Decode the eDMA3 configuration from CCCFG register */
	cccfg = edma_read(ecc, EDMA_CCCFG);

	value = GET_NUM_REGN(cccfg);
	ecc->num_region = BIT(value);

	value = GET_NUM_DMACH(cccfg);
	ecc->num_channels = BIT(value + 1);

1945 1946 1947
	value = GET_NUM_QDMACH(cccfg);
	ecc->num_qchannels = value * 2;

1948 1949 1950 1951 1952 1953
	value = GET_NUM_PAENTRY(cccfg);
	ecc->num_slots = BIT(value + 4);

	value = GET_NUM_EVQUE(cccfg);
	ecc->num_tc = value + 1;

1954 1955
	ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;

1956 1957 1958
	dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
	dev_dbg(dev, "num_region: %u\n", ecc->num_region);
	dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
1959
	dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels);
1960 1961
	dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
	dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
1962
	dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977

	/* Nothing need to be done if queue priority is provided */
	if (pdata->queue_priority_mapping)
		return 0;

	/*
	 * Configure TC/queue priority as follows:
	 * Q0 - priority 0
	 * Q1 - priority 1
	 * Q2 - priority 2
	 * ...
	 * The meaning of priority numbers: 0 highest priority, 7 lowest
	 * priority. So Q0 is the highest priority queue and the last queue has
	 * the lowest priority.
	 */
1978
	queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8),
1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008
					  GFP_KERNEL);
	if (!queue_priority_map)
		return -ENOMEM;

	for (i = 0; i < ecc->num_tc; i++) {
		queue_priority_map[i][0] = i;
		queue_priority_map[i][1] = i;
	}
	queue_priority_map[i][0] = -1;
	queue_priority_map[i][1] = -1;

	pdata->queue_priority_mapping = queue_priority_map;
	/* Default queue has the lowest priority */
	pdata->default_queue = i - 1;

	return 0;
}

#if IS_ENABLED(CONFIG_OF)
static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata,
			       size_t sz)
{
	const char pname[] = "ti,edma-xbar-event-map";
	struct resource res;
	void __iomem *xbar;
	s16 (*xbar_chans)[2];
	size_t nelm = sz / sizeof(s16);
	u32 shift, offset, mux;
	int ret, i;

2009
	xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL);
2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043
	if (!xbar_chans)
		return -ENOMEM;

	ret = of_address_to_resource(dev->of_node, 1, &res);
	if (ret)
		return -ENOMEM;

	xbar = devm_ioremap(dev, res.start, resource_size(&res));
	if (!xbar)
		return -ENOMEM;

	ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans,
					 nelm);
	if (ret)
		return -EIO;

	/* Invalidate last entry for the other user of this mess */
	nelm >>= 1;
	xbar_chans[nelm][0] = -1;
	xbar_chans[nelm][1] = -1;

	for (i = 0; i < nelm; i++) {
		shift = (xbar_chans[i][1] & 0x03) << 3;
		offset = xbar_chans[i][1] & 0xfffffffc;
		mux = readl(xbar + offset);
		mux &= ~(0xff << shift);
		mux |= xbar_chans[i][0] << shift;
		writel(mux, (xbar + offset));
	}

	pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
	return 0;
}

2044 2045
static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
						     bool legacy_mode)
2046 2047
{
	struct edma_soc_info *info;
2048
	struct property *prop;
2049
	int sz, ret;
2050 2051 2052 2053 2054

	info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
	if (!info)
		return ERR_PTR(-ENOMEM);

2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069
	if (legacy_mode) {
		prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map",
					&sz);
		if (prop) {
			ret = edma_xbar_event_map(dev, info, sz);
			if (ret)
				return ERR_PTR(ret);
		}
		return info;
	}

	/* Get the list of channels allocated to be used for memcpy */
	prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz);
	if (prop) {
		const char pname[] = "ti,edma-memcpy-channels";
2070 2071
		size_t nelm = sz / sizeof(s32);
		s32 *memcpy_ch;
2072

2073
		memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s32),
2074 2075 2076 2077
					 GFP_KERNEL);
		if (!memcpy_ch)
			return ERR_PTR(-ENOMEM);

2078 2079
		ret = of_property_read_u32_array(dev->of_node, pname,
						 (u32 *)memcpy_ch, nelm);
2080 2081 2082 2083 2084 2085 2086 2087 2088
		if (ret)
			return ERR_PTR(ret);

		memcpy_ch[nelm] = -1;
		info->memcpy_channels = memcpy_ch;
	}

	prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges",
				&sz);
2089
	if (prop) {
2090
		const char pname[] = "ti,edma-reserved-slot-ranges";
2091
		u32 (*tmp)[2];
2092
		s16 (*rsv_slots)[2];
2093
		size_t nelm = sz / sizeof(*tmp);
2094
		struct edma_rsv_info *rsv_info;
2095
		int i;
2096 2097 2098 2099

		if (!nelm)
			return info;

2100 2101 2102 2103
		tmp = kcalloc(nelm, sizeof(*tmp), GFP_KERNEL);
		if (!tmp)
			return ERR_PTR(-ENOMEM);

2104
		rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL);
2105 2106
		if (!rsv_info) {
			kfree(tmp);
2107
			return ERR_PTR(-ENOMEM);
2108
		}
2109 2110 2111

		rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots),
					 GFP_KERNEL);
2112 2113
		if (!rsv_slots) {
			kfree(tmp);
2114
			return ERR_PTR(-ENOMEM);
2115
		}
2116

2117 2118 2119 2120
		ret = of_property_read_u32_array(dev->of_node, pname,
						 (u32 *)tmp, nelm * 2);
		if (ret) {
			kfree(tmp);
2121
			return ERR_PTR(ret);
2122
		}
2123

2124 2125 2126 2127
		for (i = 0; i < nelm; i++) {
			rsv_slots[i][0] = tmp[i][0];
			rsv_slots[i][1] = tmp[i][1];
		}
2128 2129
		rsv_slots[nelm][0] = -1;
		rsv_slots[nelm][1] = -1;
2130

2131 2132
		info->rsv = rsv_info;
		info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots;
2133 2134

		kfree(tmp);
2135
	}
2136 2137 2138

	return info;
}
2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176

static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
				      struct of_dma *ofdma)
{
	struct edma_cc *ecc = ofdma->of_dma_data;
	struct dma_chan *chan = NULL;
	struct edma_chan *echan;
	int i;

	if (!ecc || dma_spec->args_count < 1)
		return NULL;

	for (i = 0; i < ecc->num_channels; i++) {
		echan = &ecc->slave_chans[i];
		if (echan->ch_num == dma_spec->args[0]) {
			chan = &echan->vchan.chan;
			break;
		}
	}

	if (!chan)
		return NULL;

	if (echan->ecc->legacy_mode && dma_spec->args_count == 1)
		goto out;

	if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 &&
	    dma_spec->args[1] < echan->ecc->num_tc) {
		echan->tc = &echan->ecc->tc_list[dma_spec->args[1]];
		goto out;
	}

	return NULL;
out:
	/* The channel is going to be used as HW synchronized */
	echan->hw_triggered = true;
	return dma_get_slave_channel(chan);
}
2177
#else
2178 2179
static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
						     bool legacy_mode)
2180 2181 2182
{
	return ERR_PTR(-EINVAL);
}
2183 2184 2185 2186 2187 2188

static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
				      struct of_dma *ofdma)
{
	return NULL;
}
2189 2190
#endif

2191
static int edma_probe(struct platform_device *pdev)
2192
{
2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203
	struct edma_soc_info	*info = pdev->dev.platform_data;
	s8			(*queue_priority_mapping)[2];
	int			i, off, ln;
	const s16		(*rsv_slots)[2];
	const s16		(*xbar_chans)[2];
	int			irq;
	char			*irq_name;
	struct resource		*mem;
	struct device_node	*node = pdev->dev.of_node;
	struct device		*dev = &pdev->dev;
	struct edma_cc		*ecc;
2204
	bool			legacy_mode = true;
2205 2206
	int ret;

2207
	if (node) {
2208 2209 2210
		const struct of_device_id *match;

		match = of_match_node(edma_of_ids, node);
2211
		if (match && (*(u32 *)match->data) == EDMA_BINDING_TPCC)
2212 2213 2214
			legacy_mode = false;

		info = edma_setup_info_from_dt(dev, legacy_mode);
2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230
		if (IS_ERR(info)) {
			dev_err(dev, "failed to get DT data\n");
			return PTR_ERR(info);
		}
	}

	if (!info)
		return -ENODEV;

	pm_runtime_enable(dev);
	ret = pm_runtime_get_sync(dev);
	if (ret < 0) {
		dev_err(dev, "pm_runtime_get_sync() failed\n");
		return ret;
	}

2231
	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2232 2233 2234
	if (ret)
		return ret;

2235
	ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
2236
	if (!ecc)
2237 2238
		return -ENOMEM;

2239 2240
	ecc->dev = dev;
	ecc->id = pdev->id;
2241
	ecc->legacy_mode = legacy_mode;
2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265
	/* When booting with DT the pdev->id is -1 */
	if (ecc->id < 0)
		ecc->id = 0;

	mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
	if (!mem) {
		dev_dbg(dev, "mem resource not found, using index 0\n");
		mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (!mem) {
			dev_err(dev, "no mem resource?\n");
			return -ENODEV;
		}
	}
	ecc->base = devm_ioremap_resource(dev, mem);
	if (IS_ERR(ecc->base))
		return PTR_ERR(ecc->base);

	platform_set_drvdata(pdev, ecc);

	/* Get eDMA3 configuration from IP */
	ret = edma_setup_from_hw(dev, info, ecc);
	if (ret)
		return ret;

2266 2267 2268 2269 2270 2271
	/* Allocate memory based on the information we got from the IP */
	ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
					sizeof(*ecc->slave_chans), GFP_KERNEL);
	if (!ecc->slave_chans)
		return -ENOMEM;

2272
	ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
2273
				       sizeof(unsigned long), GFP_KERNEL);
2274
	if (!ecc->slot_inuse)
2275 2276
		return -ENOMEM;

2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288
	ecc->default_queue = info->default_queue;

	for (i = 0; i < ecc->num_slots; i++)
		edma_write_slot(ecc, i, &dummy_paramset);

	if (info->rsv) {
		/* Set the reserved slots in inuse list */
		rsv_slots = info->rsv->rsv_slots;
		if (rsv_slots) {
			for (i = 0; rsv_slots[i][0] != -1; i++) {
				off = rsv_slots[i][0];
				ln = rsv_slots[i][1];
2289
				edma_set_bits(off, ln, ecc->slot_inuse);
2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314
			}
		}
	}

	/* Clear the xbar mapped channels in unused list */
	xbar_chans = info->xbar_chans;
	if (xbar_chans) {
		for (i = 0; xbar_chans[i][1] != -1; i++) {
			off = xbar_chans[i][1];
		}
	}

	irq = platform_get_irq_byname(pdev, "edma3_ccint");
	if (irq < 0 && node)
		irq = irq_of_parse_and_map(node, 0);

	if (irq >= 0) {
		irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint",
					  dev_name(dev));
		ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
				       ecc);
		if (ret) {
			dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
			return ret;
		}
2315
		ecc->ccint = irq;
2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330
	}

	irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
	if (irq < 0 && node)
		irq = irq_of_parse_and_map(node, 2);

	if (irq >= 0) {
		irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint",
					  dev_name(dev));
		ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
				       ecc);
		if (ret) {
			dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
			return ret;
		}
2331
		ecc->ccerrint = irq;
2332 2333
	}

2334 2335 2336 2337 2338 2339
	ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
	if (ecc->dummy_slot < 0) {
		dev_err(dev, "Can't allocate PaRAM dummy slot\n");
		return ecc->dummy_slot;
	}

2340 2341
	queue_priority_mapping = info->queue_priority_mapping;

2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366
	if (!ecc->legacy_mode) {
		int lowest_priority = 0;
		struct of_phandle_args tc_args;

		ecc->tc_list = devm_kcalloc(dev, ecc->num_tc,
					    sizeof(*ecc->tc_list), GFP_KERNEL);
		if (!ecc->tc_list)
			return -ENOMEM;

		for (i = 0;; i++) {
			ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs",
							       1, i, &tc_args);
			if (ret || i == ecc->num_tc)
				break;

			ecc->tc_list[i].node = tc_args.np;
			ecc->tc_list[i].id = i;
			queue_priority_mapping[i][1] = tc_args.args[0];
			if (queue_priority_mapping[i][1] > lowest_priority) {
				lowest_priority = queue_priority_mapping[i][1];
				info->default_queue = i;
			}
		}
	}

2367 2368 2369 2370
	/* Event queue priority mapping */
	for (i = 0; queue_priority_mapping[i][0] != -1; i++)
		edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
					      queue_priority_mapping[i][1]);
2371

2372 2373 2374 2375 2376 2377 2378
	for (i = 0; i < ecc->num_region; i++) {
		edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
		edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
		edma_write_array(ecc, EDMA_QRAE, i, 0x0);
	}
	ecc->info = info;

2379
	/* Init the dma device and channels */
2380
	edma_dma_init(ecc, legacy_mode);
2381

2382 2383
	for (i = 0; i < ecc->num_channels; i++) {
		/* Assign all channels to the default queue */
2384 2385
		edma_assign_channel_eventq(&ecc->slave_chans[i],
					   info->default_queue);
2386 2387 2388 2389
		/* Set entry slot to the dummy slot */
		edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot);
	}

2390 2391 2392 2393
	ecc->dma_slave.filter.map = info->slave_map;
	ecc->dma_slave.filter.mapcnt = info->slavecnt;
	ecc->dma_slave.filter.fn = edma_filter_fn;

2394
	ret = dma_async_device_register(&ecc->dma_slave);
2395 2396
	if (ret) {
		dev_err(dev, "slave ddev registration failed (%d)\n", ret);
2397
		goto err_reg1;
2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408
	}

	if (ecc->dma_memcpy) {
		ret = dma_async_device_register(ecc->dma_memcpy);
		if (ret) {
			dev_err(dev, "memcpy ddev registration failed (%d)\n",
				ret);
			dma_async_device_unregister(&ecc->dma_slave);
			goto err_reg1;
		}
	}
2409

2410
	if (node)
2411
		of_dma_controller_register(node, of_edma_xlate, ecc);
2412

2413
	dev_info(dev, "TI EDMA DMA engine driver\n");
2414 2415 2416 2417

	return 0;

err_reg1:
2418
	edma_free_slot(ecc, ecc->dummy_slot);
2419 2420 2421
	return ret;
}

2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432
static void edma_cleanupp_vchan(struct dma_device *dmadev)
{
	struct edma_chan *echan, *_echan;

	list_for_each_entry_safe(echan, _echan,
			&dmadev->channels, vchan.chan.device_node) {
		list_del(&echan->vchan.chan.device_node);
		tasklet_kill(&echan->vchan.task);
	}
}

2433
static int edma_remove(struct platform_device *pdev)
2434 2435 2436 2437
{
	struct device *dev = &pdev->dev;
	struct edma_cc *ecc = dev_get_drvdata(dev);

2438 2439 2440
	devm_free_irq(dev, ecc->ccint, ecc);
	devm_free_irq(dev, ecc->ccerrint, ecc);

2441 2442
	edma_cleanupp_vchan(&ecc->dma_slave);

2443 2444
	if (dev->of_node)
		of_dma_controller_free(dev->of_node);
2445
	dma_async_device_unregister(&ecc->dma_slave);
2446 2447
	if (ecc->dma_memcpy)
		dma_async_device_unregister(ecc->dma_memcpy);
2448
	edma_free_slot(ecc, ecc->dummy_slot);
2449 2450 2451 2452

	return 0;
}

2453
#ifdef CONFIG_PM_SLEEP
2454 2455 2456 2457 2458 2459 2460
static int edma_pm_suspend(struct device *dev)
{
	struct edma_cc *ecc = dev_get_drvdata(dev);
	struct edma_chan *echan = ecc->slave_chans;
	int i;

	for (i = 0; i < ecc->num_channels; i++) {
2461
		if (echan[i].alloced)
2462 2463 2464 2465 2466 2467
			edma_setup_interrupt(&echan[i], false);
	}

	return 0;
}

2468 2469 2470
static int edma_pm_resume(struct device *dev)
{
	struct edma_cc *ecc = dev_get_drvdata(dev);
2471
	struct edma_chan *echan = ecc->slave_chans;
2472 2473 2474
	int i;
	s8 (*queue_priority_mapping)[2];

2475 2476 2477
	/* re initialize dummy slot to dummy param set */
	edma_write_slot(ecc, ecc->dummy_slot, &dummy_paramset);

2478 2479 2480 2481 2482 2483 2484 2485
	queue_priority_mapping = ecc->info->queue_priority_mapping;

	/* Event queue priority mapping */
	for (i = 0; queue_priority_mapping[i][0] != -1; i++)
		edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
					      queue_priority_mapping[i][1]);

	for (i = 0; i < ecc->num_channels; i++) {
2486
		if (echan[i].alloced) {
2487 2488 2489 2490
			/* ensure access through shadow region 0 */
			edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5,
				       BIT(i & 0x1f));

2491
			edma_setup_interrupt(&echan[i], true);
2492 2493

			/* Set up channel -> slot mapping for the entry slot */
2494
			edma_set_chmap(&echan[i], echan[i].slot[0]);
2495 2496 2497 2498 2499 2500 2501 2502
		}
	}

	return 0;
}
#endif

static const struct dev_pm_ops edma_pm_ops = {
2503
	SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume)
2504 2505
};

2506 2507
static struct platform_driver edma_driver = {
	.probe		= edma_probe,
2508
	.remove		= edma_remove,
2509
	.driver = {
2510 2511 2512
		.name	= "edma",
		.pm	= &edma_pm_ops,
		.of_match_table = edma_of_ids,
2513 2514 2515
	},
};

2516 2517
static int edma_tptc_probe(struct platform_device *pdev)
{
2518 2519
	pm_runtime_enable(&pdev->dev);
	return pm_runtime_get_sync(&pdev->dev);
2520 2521
}

2522
static struct platform_driver edma_tptc_driver = {
2523
	.probe		= edma_tptc_probe,
2524 2525 2526 2527 2528 2529
	.driver = {
		.name	= "edma3-tptc",
		.of_match_table = edma_tptc_of_ids,
	},
};

2530 2531
bool edma_filter_fn(struct dma_chan *chan, void *param)
{
2532 2533
	bool match = false;

2534 2535 2536
	if (chan->device->dev->driver == &edma_driver.driver) {
		struct edma_chan *echan = to_edma_chan(chan);
		unsigned ch_req = *(unsigned *)param;
2537 2538 2539 2540 2541
		if (ch_req == echan->ch_num) {
			/* The channel is going to be used as HW synchronized */
			echan->hw_triggered = true;
			match = true;
		}
2542
	}
2543
	return match;
2544 2545 2546 2547 2548
}
EXPORT_SYMBOL(edma_filter_fn);

static int edma_init(void)
{
2549 2550 2551 2552 2553 2554
	int ret;

	ret = platform_driver_register(&edma_tptc_driver);
	if (ret)
		return ret;

2555
	return platform_driver_register(&edma_driver);
2556 2557 2558 2559 2560 2561
}
subsys_initcall(edma_init);

static void __exit edma_exit(void)
{
	platform_driver_unregister(&edma_driver);
2562
	platform_driver_unregister(&edma_tptc_driver);
2563 2564 2565
}
module_exit(edma_exit);

2566
MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
2567 2568
MODULE_DESCRIPTION("TI EDMA DMA engine driver");
MODULE_LICENSE("GPL v2");
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