pm80xx_hwi.c 166.0 KB
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/*
 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
 *
 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 * notice, this list of conditions, and the following disclaimer,
 * without modification.
 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 * substantially similar to the "NO WARRANTY" disclaimer below
 * ("Disclaimer") and any redistribution must be conditioned upon
 * including a substantially similar Disclaimer requirement for further
 * binary redistribution.
 * 3. Neither the names of the above-listed copyright holders nor the names
 * of any contributors may be used to endorse or promote products derived
 * from this software without specific prior written permission.
 *
 * Alternatively, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2 as published by the Free
 * Software Foundation.
 *
 * NO WARRANTY
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGES.
 *
 */
 #include <linux/slab.h>
 #include "pm8001_sas.h"
 #include "pm80xx_hwi.h"
 #include "pm8001_chips.h"
 #include "pm8001_ctl.h"

#define SMP_DIRECT 1
#define SMP_INDIRECT 2
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int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
{
	u32 reg_val;
	unsigned long start;
	pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
	/* confirm the setting is written */
	start = jiffies + HZ; /* 1 sec */
	do {
		reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
	} while ((reg_val != shift_value) && time_before(jiffies, start));
	if (reg_val != shift_value) {
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
			" = 0x%x\n", reg_val));
		return -1;
	}
	return 0;
}

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static void pm80xx_pci_mem_copy(struct pm8001_hba_info  *pm8001_ha, u32 soffset,
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				const void *destination,
				u32 dw_count, u32 bus_base_number)
{
	u32 index, value, offset;
	u32 *destination1;
	destination1 = (u32 *)destination;

	for (index = 0; index < dw_count; index += 4, destination1++) {
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		offset = (soffset + index);
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		if (offset < (64 * 1024)) {
			value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
			*destination1 =  cpu_to_le32(value);
		}
	}
	return;
}

ssize_t pm80xx_get_fatal_dump(struct device *cdev,
	struct device_attribute *attr, char *buf)
{
	struct Scsi_Host *shost = class_to_shost(cdev);
	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
	struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
	void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
	u32 accum_len , reg_val, index, *temp;
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	u32 status = 1;
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	unsigned long start;
	u8 *direct_data;
	char *fatal_error_data = buf;
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	u32 length_to_read;
	u32 offset;
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	pm8001_ha->forensic_info.data_buf.direct_data = buf;
	if (pm8001_ha->chip_id == chip_8001) {
		pm8001_ha->forensic_info.data_buf.direct_data +=
			sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
			"Not supported for SPC controller");
		return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
			(char *)buf;
	}
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	/* initialize variables for very first call from host application */
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	if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
		PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
		direct_data = (u8 *)fatal_error_data;
		pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
		pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
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		pm8001_ha->forensic_info.data_buf.direct_offset = 0;
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		pm8001_ha->forensic_info.data_buf.read_len = 0;
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		pm8001_ha->forensic_preserved_accumulated_transfer = 0;
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		/* Write signature to fatal dump table */
		pm8001_mw32(fatal_table_address,
				MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
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		pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("ossaHwCB: status1 %d\n", status));
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("ossaHwCB: read_len 0x%x\n",
			pm8001_ha->forensic_info.data_buf.read_len));
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("ossaHwCB: direct_len 0x%x\n",
			pm8001_ha->forensic_info.data_buf.direct_len));
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("ossaHwCB: direct_offset 0x%x\n",
			pm8001_ha->forensic_info.data_buf.direct_offset));
	}
	if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
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		/* start to get data */
		/* Program the MEMBASE II Shifting Register with 0x00.*/
		pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
				pm8001_ha->fatal_forensic_shift_offset);
		pm8001_ha->forensic_last_offset = 0;
		pm8001_ha->forensic_fatal_step = 0;
		pm8001_ha->fatal_bar_loc = 0;
	}
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	/* Read until accum_len is retrived */
	accum_len = pm8001_mr32(fatal_table_address,
				MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
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	/* Determine length of data between previously stored transfer length
	 * and current accumulated transfer length
	 */
	length_to_read =
		accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
	PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("get_fatal_spcv: accum_len 0x%x\n", accum_len));
	PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("get_fatal_spcv: length_to_read 0x%x\n",
		length_to_read));
	PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("get_fatal_spcv: last_offset 0x%x\n",
		pm8001_ha->forensic_last_offset));
	PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("get_fatal_spcv: read_len 0x%x\n",
		pm8001_ha->forensic_info.data_buf.read_len));
	PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("get_fatal_spcv:: direct_len 0x%x\n",
		pm8001_ha->forensic_info.data_buf.direct_len));
	PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("get_fatal_spcv:: direct_offset 0x%x\n",
		pm8001_ha->forensic_info.data_buf.direct_offset));

	/* If accumulated length failed to read correctly fail the attempt.*/
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	if (accum_len == 0xFFFFFFFF) {
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("Possible PCI issue 0x%x not expected\n",
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			accum_len));
		return status;
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	}
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	/* If accumulated length is zero fail the attempt */
	if (accum_len == 0) {
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		pm8001_ha->forensic_info.data_buf.direct_data +=
			sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
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			"%08x ", 0xFFFFFFFF);
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		return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
			(char *)buf;
	}
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	/* Accumulated length is good so start capturing the first data */
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	temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
	if (pm8001_ha->forensic_fatal_step == 0) {
moreData:
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		/* If data to read is less than SYSFS_OFFSET then reduce the
		 * length of dataLen
		 */
		if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
				> length_to_read) {
			pm8001_ha->forensic_info.data_buf.direct_len =
				length_to_read -
				pm8001_ha->forensic_last_offset;
		} else {
			pm8001_ha->forensic_info.data_buf.direct_len =
				SYSFS_OFFSET;
		}
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		if (pm8001_ha->forensic_info.data_buf.direct_data) {
			/* Data is in bar, copy to host memory */
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			pm80xx_pci_mem_copy(pm8001_ha,
			pm8001_ha->fatal_bar_loc,
			pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
			pm8001_ha->forensic_info.data_buf.direct_len, 1);
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		}
		pm8001_ha->fatal_bar_loc +=
			pm8001_ha->forensic_info.data_buf.direct_len;
		pm8001_ha->forensic_info.data_buf.direct_offset +=
			pm8001_ha->forensic_info.data_buf.direct_len;
		pm8001_ha->forensic_last_offset	+=
			pm8001_ha->forensic_info.data_buf.direct_len;
		pm8001_ha->forensic_info.data_buf.read_len =
			pm8001_ha->forensic_info.data_buf.direct_len;

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		if (pm8001_ha->forensic_last_offset  >= length_to_read) {
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			pm8001_ha->forensic_info.data_buf.direct_data +=
			sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
				"%08x ", 3);
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			for (index = 0; index <
				(pm8001_ha->forensic_info.data_buf.direct_len
				 / 4); index++) {
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				pm8001_ha->forensic_info.data_buf.direct_data +=
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				sprintf(
				pm8001_ha->forensic_info.data_buf.direct_data,
				"%08x ", *(temp + index));
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			}

			pm8001_ha->fatal_bar_loc = 0;
			pm8001_ha->forensic_fatal_step = 1;
			pm8001_ha->fatal_forensic_shift_offset = 0;
			pm8001_ha->forensic_last_offset	= 0;
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			status = 0;
			offset = (int)
			((char *)pm8001_ha->forensic_info.data_buf.direct_data
			- (char *)buf);
			PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("get_fatal_spcv:return1 0x%x\n", offset));
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			return (char *)pm8001_ha->
				forensic_info.data_buf.direct_data -
				(char *)buf;
		}
		if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
			pm8001_ha->forensic_info.data_buf.direct_data +=
				sprintf(pm8001_ha->
					forensic_info.data_buf.direct_data,
					"%08x ", 2);
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			for (index = 0; index <
				(pm8001_ha->forensic_info.data_buf.direct_len
				 / 4); index++) {
				pm8001_ha->forensic_info.data_buf.direct_data
					+= sprintf(pm8001_ha->
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					forensic_info.data_buf.direct_data,
					"%08x ", *(temp + index));
			}
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			status = 0;
			offset = (int)
			((char *)pm8001_ha->forensic_info.data_buf.direct_data
			- (char *)buf);
			PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("get_fatal_spcv:return2 0x%x\n", offset));
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			return (char *)pm8001_ha->
				forensic_info.data_buf.direct_data -
				(char *)buf;
		}

		/* Increment the MEMBASE II Shifting Register value by 0x100.*/
		pm8001_ha->forensic_info.data_buf.direct_data +=
			sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
				"%08x ", 2);
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		for (index = 0; index <
			(pm8001_ha->forensic_info.data_buf.direct_len
			 / 4) ; index++) {
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			pm8001_ha->forensic_info.data_buf.direct_data +=
				sprintf(pm8001_ha->
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				forensic_info.data_buf.direct_data,
				"%08x ", *(temp + index));
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		}
		pm8001_ha->fatal_forensic_shift_offset += 0x100;
		pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
			pm8001_ha->fatal_forensic_shift_offset);
		pm8001_ha->fatal_bar_loc = 0;
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		status = 0;
		offset = (int)
			((char *)pm8001_ha->forensic_info.data_buf.direct_data
			- (char *)buf);
		PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("get_fatal_spcv: return3 0x%x\n", offset));
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		return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
			(char *)buf;
	}
	if (pm8001_ha->forensic_fatal_step == 1) {
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		/* store previous accumulated length before triggering next
		 * accumulated length update
		 */
		pm8001_ha->forensic_preserved_accumulated_transfer =
			pm8001_mr32(fatal_table_address,
			MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);

		/* continue capturing the fatal log until Dump status is 0x3 */
		if (pm8001_mr32(fatal_table_address,
			MPI_FATAL_EDUMP_TABLE_STATUS) <
			MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {

			/* reset fddstat bit by writing to zero*/
			pm8001_mw32(fatal_table_address,
					MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);

			/* set dump control value to '1' so that new data will
			 * be transferred to shared memory
			 */
			pm8001_mw32(fatal_table_address,
				MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
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				MPI_FATAL_EDUMP_HANDSHAKE_RDY);

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			/*Poll FDDHSHK  until clear */
			start = jiffies + (2 * HZ); /* 2 sec */
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			do {
				reg_val = pm8001_mr32(fatal_table_address,
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					MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
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			} while ((reg_val) && time_before(jiffies, start));
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			if (reg_val != 0) {
				PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
				"TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
				reg_val));
			       /* Fail the dump if a timeout occurs */
				pm8001_ha->forensic_info.data_buf.direct_data +=
				sprintf(
				pm8001_ha->forensic_info.data_buf.direct_data,
				"%08x ", 0xFFFFFFFF);
				return((char *)
				pm8001_ha->forensic_info.data_buf.direct_data
				- (char *)buf);
			}
			/* Poll status register until set to 2 or
			 * 3 for up to 2 seconds
			 */
			start = jiffies + (2 * HZ); /* 2 sec */
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			do {
				reg_val = pm8001_mr32(fatal_table_address,
					MPI_FATAL_EDUMP_TABLE_STATUS);
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			} while (((reg_val != 2) && (reg_val != 3)) &&
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					time_before(jiffies, start));

			if (reg_val < 2) {
				PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
				"TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
				reg_val));
				/* Fail the dump if a timeout occurs */
				pm8001_ha->forensic_info.data_buf.direct_data +=
				sprintf(
				pm8001_ha->forensic_info.data_buf.direct_data,
				"%08x ", 0xFFFFFFFF);
				pm8001_cw32(pm8001_ha, 0,
					MEMBASE_II_SHIFT_REGISTER,
					pm8001_ha->fatal_forensic_shift_offset);
			}
			/* Read the next block of the debug data.*/
			length_to_read = pm8001_mr32(fatal_table_address,
			MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
			pm8001_ha->forensic_preserved_accumulated_transfer;
			if (length_to_read != 0x0) {
				pm8001_ha->forensic_fatal_step = 0;
				goto moreData;
			} else {
				pm8001_ha->forensic_info.data_buf.direct_data +=
				sprintf(
				pm8001_ha->forensic_info.data_buf.direct_data,
				"%08x ", 4);
				pm8001_ha->forensic_info.data_buf.read_len
								= 0xFFFFFFFF;
				pm8001_ha->forensic_info.data_buf.direct_len
								=  0;
				pm8001_ha->forensic_info.data_buf.direct_offset
								= 0;
				pm8001_ha->forensic_info.data_buf.read_len = 0;
			}
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		}
	}
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	offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
			- (char *)buf);
	PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("get_fatal_spcv: return4 0x%x\n", offset));
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	return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
		(char *)buf;
}

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/* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
 * location by the firmware.
 */
ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
	struct device_attribute *attr, char *buf)
{
	struct Scsi_Host *shost = class_to_shost(cdev);
	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
	struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
	void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
	u32 accum_len = 0;
	u32 total_len = 0;
	u32 reg_val = 0;
	u32 *temp = NULL;
	u32 index = 0;
	u32 output_length;
	unsigned long start = 0;
	char *buf_copy = buf;

	temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
	if (++pm8001_ha->non_fatal_count == 1) {
		if (pm8001_ha->chip_id == chip_8001) {
			snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
				PAGE_SIZE, "Not supported for SPC controller");
			return 0;
		}
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("forensic_info TYPE_NON_FATAL...\n"));
		/*
		 * Step 1: Write the host buffer parameters in the MPI Fatal and
		 * Non-Fatal Error Dump Capture Table.This is the buffer
		 * where debug data will be DMAed to.
		 */
		pm8001_mw32(nonfatal_table_address,
		MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
		pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);

		pm8001_mw32(nonfatal_table_address,
		MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
		pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);

		pm8001_mw32(nonfatal_table_address,
		MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);

		/* Optionally, set the DUMPCTRL bit to 1 if the host
		 * keeps sending active I/Os while capturing the non-fatal
		 * debug data. Otherwise, leave this bit set to zero
		 */
		pm8001_mw32(nonfatal_table_address,
		MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);

		/*
		 * Step 2: Clear Accumulative Length of Debug Data Transferred
		 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump
		 * Capture Table to zero.
		 */
		pm8001_mw32(nonfatal_table_address,
				MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);

		/* initiallize previous accumulated length to 0 */
		pm8001_ha->forensic_preserved_accumulated_transfer = 0;
		pm8001_ha->non_fatal_read_length = 0;
	}

	total_len = pm8001_mr32(nonfatal_table_address,
			MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
	/*
	 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]
	 * field and then request that the SPCv controller transfer the debug
	 * data by setting bit 7 of the Inbound Doorbell Set Register.
	 */
	pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
	pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
			SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);

	/*
	 * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for
	 * 2 seconds) until register bit 7 is cleared.
	 * This step only indicates the request is accepted by the controller.
	 */
	start = jiffies + (2 * HZ); /* 2 sec */
	do {
		reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
			SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
	} while ((reg_val != 0) && time_before(jiffies, start));

	/* Step 4.2: To check the completion of the transfer, poll the Fatal/Non
	 * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in
	 * the MPI Fatal and Non-Fatal Error Dump Capture Table.
	 */
	start = jiffies + (2 * HZ); /* 2 sec */
	do {
		reg_val = pm8001_mr32(nonfatal_table_address,
				MPI_FATAL_EDUMP_TABLE_STATUS);
	} while ((!reg_val) && time_before(jiffies, start));

	if ((reg_val == 0x00) ||
		(reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
		(reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
		pm8001_ha->non_fatal_read_length = 0;
		buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
		pm8001_ha->non_fatal_count = 0;
		return (buf_copy - buf);
	} else if (reg_val ==
			MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
		buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
	} else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
		(pm8001_ha->non_fatal_read_length >= total_len)) {
		pm8001_ha->non_fatal_read_length = 0;
		buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
		pm8001_ha->non_fatal_count = 0;
	}
	accum_len = pm8001_mr32(nonfatal_table_address,
			MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
	output_length = accum_len -
		pm8001_ha->forensic_preserved_accumulated_transfer;

	for (index = 0; index < output_length/4; index++)
		buf_copy += snprintf(buf_copy, PAGE_SIZE,
				"%08x ", *(temp+index));

	pm8001_ha->non_fatal_read_length += output_length;

	/* store current accumulated length to use in next iteration as
	 * the previous accumulated length
	 */
	pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
	return (buf_copy - buf);
}

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/**
 * read_main_config_table - read the configure table and save it.
 * @pm8001_ha: our hba card information
 */
static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
{
	void __iomem *address = pm8001_ha->main_cfg_tbl_addr;

	pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature	=
		pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
		pm8001_mr32(address, MAIN_INTERFACE_REVISION);
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev	=
		pm8001_mr32(address, MAIN_FW_REVISION);
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io	=
		pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl	=
		pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
		pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset	=
		pm8001_mr32(address, MAIN_GST_OFFSET);
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
		pm8001_mr32(address, MAIN_IBQ_OFFSET);
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
		pm8001_mr32(address, MAIN_OBQ_OFFSET);

	/* read Error Dump Offset and Length */
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
		pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
		pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
		pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
		pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);

	/* read GPIO LED settings from the configuration table */
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
		pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);

	/* read analog Setting offset from the configuration table */
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
		pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);

	pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
		pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
		pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
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	/* read port recover and reset timeout */
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
		pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
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	/* read ILA and inactive firmware version */
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
		pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
		pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
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	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev));

	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset));

	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"Main cfg table; ila rev:%x Inactive fw rev:%x\n",
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version));
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}

/**
 * read_general_status_table - read the general status table and save it.
 * @pm8001_ha: our hba card information
 */
static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
{
	void __iomem *address = pm8001_ha->general_stat_tbl_addr;
	pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate	=
			pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
	pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0	=
			pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
	pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1	=
			pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
	pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt		=
			pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
	pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt		=
			pm8001_mr32(address, GST_IOPTCNT_OFFSET);
	pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val	=
			pm8001_mr32(address, GST_GPIO_INPUT_VAL);
	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
			pm8001_mr32(address, GST_RERRINFO_OFFSET0);
	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
			pm8001_mr32(address, GST_RERRINFO_OFFSET1);
	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
			pm8001_mr32(address, GST_RERRINFO_OFFSET2);
	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
			pm8001_mr32(address, GST_RERRINFO_OFFSET3);
	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
			pm8001_mr32(address, GST_RERRINFO_OFFSET4);
	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
			pm8001_mr32(address, GST_RERRINFO_OFFSET5);
	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
			pm8001_mr32(address, GST_RERRINFO_OFFSET6);
	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
			 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
}
/**
 * read_phy_attr_table - read the phy attribute table and save it.
 * @pm8001_ha: our hba card information
 */
static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
{
	void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
	pm8001_ha->phy_attr_table.phystart1_16[0] =
			pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[1] =
			pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[2] =
			pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[3] =
			pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[4] =
			pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[5] =
			pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[6] =
			pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[7] =
			pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[8] =
			pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[9] =
			pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[10] =
			pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[11] =
			pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[12] =
			pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[13] =
			pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[14] =
			pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
	pm8001_ha->phy_attr_table.phystart1_16[15] =
			pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);

	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
			pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);

}

/**
 * read_inbnd_queue_table - read the inbound queue table and save it.
 * @pm8001_ha: our hba card information
 */
static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
{
	int i;
	void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
723
	for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
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		u32 offset = i * 0x20;
		pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
			get_pci_bar_index(pm8001_mr32(address,
				(offset + IB_PIPCI_BAR)));
		pm8001_ha->inbnd_q_tbl[i].pi_offset =
			pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
	}
}

/**
 * read_outbnd_queue_table - read the outbound queue table and save it.
 * @pm8001_ha: our hba card information
 */
static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
{
	int i;
	void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
741
	for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760
		u32 offset = i * 0x24;
		pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
			get_pci_bar_index(pm8001_mr32(address,
				(offset + OB_CIPCI_BAR)));
		pm8001_ha->outbnd_q_tbl[i].ci_offset =
			pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
	}
}

/**
 * init_default_table_values - init the default table.
 * @pm8001_ha: our hba card information
 */
static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
{
	int i;
	u32 offsetib, offsetob;
	void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
	void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
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	u32 ib_offset = pm8001_ha->ib_offset;
	u32 ob_offset = pm8001_ha->ob_offset;
	u32 ci_offset = pm8001_ha->ci_offset;
	u32 pi_offset = pm8001_ha->pi_offset;
765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781

	pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr		=
		pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr		=
		pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size		=
							PM8001_EVENT_LOG_SIZE;
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity		= 0x01;
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr	=
		pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr	=
		pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size		=
							PM8001_EVENT_LOG_SIZE;
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity	= 0x01;
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt		= 0x01;

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	/* Disable end to end CRC checking */
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);

785
	for (i = 0; i < pm8001_ha->max_q_num; i++) {
786
		pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt	=
787
			PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
788
		pm8001_ha->inbnd_q_tbl[i].upper_base_addr	=
789
			pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
790
		pm8001_ha->inbnd_q_tbl[i].lower_base_addr	=
791
		pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
792
		pm8001_ha->inbnd_q_tbl[i].base_virt		=
793
		  (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
794
		pm8001_ha->inbnd_q_tbl[i].total_length		=
795
			pm8001_ha->memoryMap.region[ib_offset + i].total_len;
796
		pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr	=
797
			pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
798
		pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr	=
799
			pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
800
		pm8001_ha->inbnd_q_tbl[i].ci_virt		=
801
			pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
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		offsetib = i * 0x20;
		pm8001_ha->inbnd_q_tbl[i].pi_pci_bar		=
			get_pci_bar_index(pm8001_mr32(addressib,
				(offsetib + 0x14)));
		pm8001_ha->inbnd_q_tbl[i].pi_offset		=
			pm8001_mr32(addressib, (offsetib + 0x18));
		pm8001_ha->inbnd_q_tbl[i].producer_idx		= 0;
		pm8001_ha->inbnd_q_tbl[i].consumer_index	= 0;
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		PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
			"IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
			pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
			pm8001_ha->inbnd_q_tbl[i].pi_offset));
815
	}
816
	for (i = 0; i < pm8001_ha->max_q_num; i++) {
817
		pm8001_ha->outbnd_q_tbl[i].element_size_cnt	=
818
			PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
819
		pm8001_ha->outbnd_q_tbl[i].upper_base_addr	=
820
			pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
821
		pm8001_ha->outbnd_q_tbl[i].lower_base_addr	=
822
			pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
823
		pm8001_ha->outbnd_q_tbl[i].base_virt		=
824
		  (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
825
		pm8001_ha->outbnd_q_tbl[i].total_length		=
826
			pm8001_ha->memoryMap.region[ob_offset + i].total_len;
827
		pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr	=
828
			pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
829
		pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr	=
830
			pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
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		/* interrupt vector based on oq */
		pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
		pm8001_ha->outbnd_q_tbl[i].pi_virt		=
834
			pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
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		offsetob = i * 0x24;
		pm8001_ha->outbnd_q_tbl[i].ci_pci_bar		=
			get_pci_bar_index(pm8001_mr32(addressob,
			offsetob + 0x14));
		pm8001_ha->outbnd_q_tbl[i].ci_offset		=
			pm8001_mr32(addressob, (offsetob + 0x18));
		pm8001_ha->outbnd_q_tbl[i].consumer_idx		= 0;
		pm8001_ha->outbnd_q_tbl[i].producer_index	= 0;
843 844 845 846 847

		PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
			"OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
			pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
			pm8001_ha->outbnd_q_tbl[i].ci_offset));
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	}
}

/**
 * update_main_config_table - update the main default table to the HBA.
 * @pm8001_ha: our hba card information
 */
static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
{
	void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
	pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
	pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
	pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
	pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
	pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
	pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
	pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
	pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
	pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
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	/* Update Fatal error interrupt vector */
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
878
					((pm8001_ha->max_q_num - 1) << 8);
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	pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
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	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"Updated Fatal error interrupt vector 0x%x\n",
		pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)));

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	pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
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	/* SPCv specific */
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
	/* Set GPIOLED to 0x2 for LED indicator */
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
	pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
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	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"Programming DW 0x21 in main cfg table with 0x%x\n",
		pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)));
897 898 899 900 901

	pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
	pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
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	pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
	pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
							PORT_RECOVERY_TIMEOUT;
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	if (pm8001_ha->chip_id == chip_8006) {
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
					0x0000ffff;
		pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
910
					CHIP_8006_PORT_RECOVERY_TIMEOUT;
911
	}
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	pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
			pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
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}

/**
 * update_inbnd_queue_table - update the inbound queue table to the HBA.
 * @pm8001_ha: our hba card information
919
 * @number: entry in the queue
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 */
static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
					 int number)
{
	void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
	u16 offset = number * 0x20;
	pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
		pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
	pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
		pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
	pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
		pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
	pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
		pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
	pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
		pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
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	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"IQ %d: Element pri size 0x%x\n",
		number,
		pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt));

	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
		pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
		pm8001_ha->inbnd_q_tbl[number].lower_base_addr));

	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"CI upper base addr 0x%x CI lower base addr 0x%x\n",
		pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
		pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr));
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}

/**
 * update_outbnd_queue_table - update the outbound queue table to the HBA.
 * @pm8001_ha: our hba card information
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 * @number: entry in the queue
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 */
static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
						 int number)
{
	void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
	u16 offset = number * 0x24;
	pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
		pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
	pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
		pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
	pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
		pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
	pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
		pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
	pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
		pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
	pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
		pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
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	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"OQ %d: Element pri size 0x%x\n",
		number,
		pm8001_ha->outbnd_q_tbl[number].element_size_cnt));

	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
		pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
		pm8001_ha->outbnd_q_tbl[number].lower_base_addr));

	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"PI upper base addr 0x%x PI lower base addr 0x%x\n",
		pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
		pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr));
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}

/**
 * mpi_init_check - check firmware initialization status.
 * @pm8001_ha: our hba card information
 */
static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
{
	u32 max_wait_count;
	u32 value;
	u32 gst_len_mpistate;

	/* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
	table is updated */
	pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
	/* wait until Inbound DoorBell Clear Register toggled */
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	if (IS_SPCV_12G(pm8001_ha->pdev)) {
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		max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
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	} else {
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		max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
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	}
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	do {
		udelay(1);
		value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
		value &= SPCv_MSGU_CFG_TABLE_UPDATE;
	} while ((value != 0) && (--max_wait_count));

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	if (!max_wait_count) {
		/* additional check */
		PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
			"Inb doorbell clear not toggled[value:%x]\n", value));
		return -EBUSY;
	}
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	/* check the MPI-State for initialization upto 100ms*/
	max_wait_count = 100 * 1000;/* 100 msec */
	do {
		udelay(1);
		gst_len_mpistate =
			pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
					GST_GSTLEN_MPIS_OFFSET);
	} while ((GST_MPI_STATE_INIT !=
		(gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
	if (!max_wait_count)
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		return -EBUSY;
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	/* check MPI Initialization error */
	gst_len_mpistate = gst_len_mpistate >> 16;
	if (0x0000 != gst_len_mpistate)
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		return -EBUSY;
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	return 0;
}

/**
 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 * @pm8001_ha: our hba card information
 */
static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
{
	u32 value;
	u32 max_wait_count;
	u32 max_wait_time;
	int ret = 0;

	/* reset / PCIe ready */
	max_wait_time = max_wait_count = 100 * 1000;	/* 100 milli sec */
	do {
		udelay(1);
		value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
	} while ((value == 0xFFFFFFFF) && (--max_wait_count));

	/* check ila status */
	max_wait_time = max_wait_count = 1000 * 1000;	/* 1000 milli sec */
	do {
		udelay(1);
		value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
	} while (((value & SCRATCH_PAD_ILA_READY) !=
			SCRATCH_PAD_ILA_READY) && (--max_wait_count));
	if (!max_wait_count)
		ret = -1;
	else {
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" ila ready status in %d millisec\n",
				(max_wait_time - max_wait_count)));
	}

	/* check RAAE status */
	max_wait_time = max_wait_count = 1800 * 1000;	/* 1800 milli sec */
	do {
		udelay(1);
		value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
	} while (((value & SCRATCH_PAD_RAAE_READY) !=
				SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
	if (!max_wait_count)
		ret = -1;
	else {
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" raae ready status in %d millisec\n",
					(max_wait_time - max_wait_count)));
	}

	/* check iop0 status */
	max_wait_time = max_wait_count = 600 * 1000;	/* 600 milli sec */
	do {
		udelay(1);
		value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
	} while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
			(--max_wait_count));
	if (!max_wait_count)
		ret = -1;
	else {
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" iop0 ready status in %d millisec\n",
				(max_wait_time - max_wait_count)));
	}

	/* check iop1 status only for 16 port controllers */
	if ((pm8001_ha->chip_id != chip_8008) &&
			(pm8001_ha->chip_id != chip_8009)) {
		/* 200 milli sec */
		max_wait_time = max_wait_count = 200 * 1000;
		do {
			udelay(1);
			value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
		} while (((value & SCRATCH_PAD_IOP1_READY) !=
				SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
		if (!max_wait_count)
			ret = -1;
		else {
			PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
				"iop1 ready status in %d millisec\n",
				(max_wait_time - max_wait_count)));
		}
	}

	return ret;
}

static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
{
	void __iomem *base_addr;
	u32	value;
	u32	offset;
	u32	pcibar;
	u32	pcilogic;

	value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
	offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */

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	PM8001_DEV_DBG(pm8001_ha,
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		pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
				offset, value));
	pcilogic = (value & 0xFC000000) >> 26;
	pcibar = get_pci_bar_index(pcilogic);
	PM8001_INIT_DBG(pm8001_ha,
		pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
	pm8001_ha->main_cfg_tbl_addr = base_addr =
		pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
	pm8001_ha->general_stat_tbl_addr =
		base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
					0xFFFFFF);
	pm8001_ha->inbnd_q_tbl_addr =
		base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
					0xFFFFFF);
	pm8001_ha->outbnd_q_tbl_addr =
		base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
					0xFFFFFF);
	pm8001_ha->ivt_tbl_addr =
		base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
					0xFFFFFF);
	pm8001_ha->pspa_q_tbl_addr =
		base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
					0xFFFFFF);
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	pm8001_ha->fatal_tbl_addr =
		base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
					0xFFFFFF);
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	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("GST OFFSET 0x%x\n",
			pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("INBND OFFSET 0x%x\n",
			pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("OBND OFFSET 0x%x\n",
			pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("IVT OFFSET 0x%x\n",
			pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("PSPA OFFSET 0x%x\n",
			pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("addr - main cfg %p general status %p\n",
			pm8001_ha->main_cfg_tbl_addr,
			pm8001_ha->general_stat_tbl_addr));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("addr - inbnd %p obnd %p\n",
			pm8001_ha->inbnd_q_tbl_addr,
			pm8001_ha->outbnd_q_tbl_addr));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("addr - pspa %p ivt %p\n",
			pm8001_ha->pspa_q_tbl_addr,
			pm8001_ha->ivt_tbl_addr));
}

/**
 * pm80xx_set_thermal_config - support the thermal configuration
 * @pm8001_ha: our hba card information.
 */
1200
int
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pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
{
	struct set_ctrl_cfg_req payload;
	struct inbound_queue_table *circularQ;
	int rc;
	u32 tag;
	u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
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	u32 page_code;
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	memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
	rc = pm8001_tag_alloc(pm8001_ha, &tag);
	if (rc)
		return -1;

	circularQ = &pm8001_ha->inbnd_q_tbl[0];
	payload.tag = cpu_to_le32(tag);
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	if (IS_SPCV_12G(pm8001_ha->pdev))
		page_code = THERMAL_PAGE_CODE_7H;
	else
		page_code = THERMAL_PAGE_CODE_8H;

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	payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
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				(THERMAL_ENABLE << 8) | page_code;
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	payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);

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	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
		payload.cfg_pg[0], payload.cfg_pg[1]));

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	rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
			sizeof(payload), 0);
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	if (rc)
		pm8001_tag_free(pm8001_ha, tag);
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	return rc;

}

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/**
* pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
* Timer configuration page
* @pm8001_ha: our hba card information.
*/
static int
pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
{
	struct set_ctrl_cfg_req payload;
	struct inbound_queue_table *circularQ;
	SASProtocolTimerConfig_t SASConfigPage;
	int rc;
	u32 tag;
	u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;

	memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
	memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));

	rc = pm8001_tag_alloc(pm8001_ha, &tag);

	if (rc)
		return -1;

	circularQ = &pm8001_ha->inbnd_q_tbl[0];
	payload.tag = cpu_to_le32(tag);

	SASConfigPage.pageCode        =  SAS_PROTOCOL_TIMER_CONFIG_PAGE;
	SASConfigPage.MST_MSI         =  3 << 15;
	SASConfigPage.STP_SSP_MCT_TMO =  (STP_MCT_TMO << 16) | SSP_MCT_TMO;
	SASConfigPage.STP_FRM_TMO     = (SAS_MAX_OPEN_TIME << 24) |
				(SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
	SASConfigPage.STP_IDLE_TMO    =  STP_IDLE_TIME;

	if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
		SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;


	SASConfigPage.OPNRJT_RTRY_INTVL =         (SAS_MFD << 16) |
						SAS_OPNRJT_RTRY_INTVL;
	SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =  (SAS_DOPNRJT_RTRY_TMO << 16)
						| SAS_COPNRJT_RTRY_TMO;
	SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =  (SAS_DOPNRJT_RTRY_THR << 16)
						| SAS_COPNRJT_RTRY_THR;
	SASConfigPage.MAX_AIP =  SAS_MAX_AIP;

	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("SASConfigPage.pageCode "
			"0x%08x\n", SASConfigPage.pageCode));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("SASConfigPage.MST_MSI "
			" 0x%08x\n", SASConfigPage.MST_MSI));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
			" 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("SASConfigPage.STP_FRM_TMO "
			" 0x%08x\n", SASConfigPage.STP_FRM_TMO));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("SASConfigPage.STP_IDLE_TMO "
			" 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
			" 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
			" 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
	PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
			" 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
	PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
			" 0x%08x\n", SASConfigPage.MAX_AIP));

	memcpy(&payload.cfg_pg, &SASConfigPage,
			 sizeof(SASProtocolTimerConfig_t));

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	rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
			sizeof(payload), 0);
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Tomas Henzl 已提交
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	if (rc)
		pm8001_tag_free(pm8001_ha, tag);
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	return rc;
}

1322 1323 1324 1325 1326 1327 1328 1329
/**
 * pm80xx_get_encrypt_info - Check for encryption
 * @pm8001_ha: our hba card information.
 */
static int
pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
{
	u32 scratch3_value;
1330
	int ret = -1;
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	/* Read encryption status from SCRATCH PAD 3 */
	scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);

	if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
					SCRATCH_PAD3_ENC_READY) {
		if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
			pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
		if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
						SCRATCH_PAD3_SMF_ENABLED)
			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
		if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
						SCRATCH_PAD3_SMA_ENABLED)
			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
		if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
						SCRATCH_PAD3_SMB_ENABLED)
			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
		pm8001_ha->encrypt_info.status = 0;
		PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
			"Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
			"Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
			scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
			pm8001_ha->encrypt_info.sec_mode,
			pm8001_ha->encrypt_info.status));
		ret = 0;
	} else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
					SCRATCH_PAD3_ENC_DISABLED) {
		PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
			"Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
			scratch3_value));
		pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
		pm8001_ha->encrypt_info.cipher_mode = 0;
		pm8001_ha->encrypt_info.sec_mode = 0;
1364
		ret = 0;
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	} else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
				SCRATCH_PAD3_ENC_DIS_ERR) {
		pm8001_ha->encrypt_info.status =
			(scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
		if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
			pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
		if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
					SCRATCH_PAD3_SMF_ENABLED)
			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
		if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
					SCRATCH_PAD3_SMA_ENABLED)
			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
		if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
					SCRATCH_PAD3_SMB_ENABLED)
			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
		PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
			"Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
			"Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
			scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
			pm8001_ha->encrypt_info.sec_mode,
			pm8001_ha->encrypt_info.status));
	} else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
				 SCRATCH_PAD3_ENC_ENA_ERR) {

		pm8001_ha->encrypt_info.status =
			(scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
		if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
			pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
		if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
					SCRATCH_PAD3_SMF_ENABLED)
			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
		if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
					SCRATCH_PAD3_SMA_ENABLED)
			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
		if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
					SCRATCH_PAD3_SMB_ENABLED)
			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;

		PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
			"Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
			"Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
			scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
			pm8001_ha->encrypt_info.sec_mode,
			pm8001_ha->encrypt_info.status));
	}
	return ret;
}

/**
 * pm80xx_encrypt_update - update flash with encryption informtion
 * @pm8001_ha: our hba card information.
 */
static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
{
	struct kek_mgmt_req payload;
	struct inbound_queue_table *circularQ;
	int rc;
	u32 tag;
	u32 opc = OPC_INB_KEK_MANAGEMENT;

	memset(&payload, 0, sizeof(struct kek_mgmt_req));
	rc = pm8001_tag_alloc(pm8001_ha, &tag);
	if (rc)
		return -1;

	circularQ = &pm8001_ha->inbnd_q_tbl[0];
	payload.tag = cpu_to_le32(tag);
	/* Currently only one key is used. New KEK index is 1.
	 * Current KEK index is 1. Store KEK to NVRAM is 1.
	 */
	payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
					KEK_MGMT_SUBOP_KEYCARDUPDATE);

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	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"Saving Encryption info to flash. payload 0x%x\n",
		payload.new_curidx_ksop));

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	rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
			sizeof(payload), 0);
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Tomas Henzl 已提交
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	if (rc)
		pm8001_tag_free(pm8001_ha, tag);
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	return rc;
}

/**
 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 * @pm8001_ha: our hba card information
 */
static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
{
	int ret;
	u8 i = 0;

	/* check the firmware status */
	if (-1 == check_fw_ready(pm8001_ha)) {
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("Firmware is not ready!\n"));
		return -EBUSY;
	}

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	/* Initialize the controller fatal error flag */
	pm8001_ha->controller_fatal_error = false;

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	/* Initialize pci space address eg: mpi offset */
	init_pci_device_addresses(pm8001_ha);
	init_default_table_values(pm8001_ha);
	read_main_config_table(pm8001_ha);
	read_general_status_table(pm8001_ha);
	read_inbnd_queue_table(pm8001_ha);
	read_outbnd_queue_table(pm8001_ha);
	read_phy_attr_table(pm8001_ha);

	/* update main config table ,inbound table and outbound table */
	update_main_config_table(pm8001_ha);
1480
	for (i = 0; i < pm8001_ha->max_q_num; i++) {
1481 1482
		update_inbnd_queue_table(pm8001_ha, i);
		update_outbnd_queue_table(pm8001_ha, i);
1483
	}
1484 1485 1486 1487 1488 1489 1490
	/* notify firmware update finished and check initialization status */
	if (0 == mpi_init_check(pm8001_ha)) {
		PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("MPI initialize successful!\n"));
	} else
		return -EBUSY;

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	/* send SAS protocol timer configuration page to FW */
	ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
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	/* Check for encryption */
	if (pm8001_ha->chip->encrypt) {
		PM8001_INIT_DBG(pm8001_ha,
			pm8001_printk("Checking for encryption\n"));
		ret = pm80xx_get_encrypt_info(pm8001_ha);
		if (ret == -1) {
			PM8001_INIT_DBG(pm8001_ha,
				pm8001_printk("Encryption error !!\n"));
			if (pm8001_ha->encrypt_info.status == 0x81) {
				PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
					"Encryption enabled with error."
					"Saving encryption key to flash\n"));
				pm80xx_encrypt_update(pm8001_ha);
			}
		}
	}
	return 0;
}

static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
{
	u32 max_wait_count;
	u32 value;
	u32 gst_len_mpistate;
	init_pci_device_addresses(pm8001_ha);
	/* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
	table is stop */
	pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);

	/* wait until Inbound DoorBell Clear Register toggled */
1524 1525 1526 1527 1528
	if (IS_SPCV_12G(pm8001_ha->pdev)) {
		max_wait_count = 4 * 1000 * 1000;/* 4 sec */
	} else {
		max_wait_count = 2 * 1000 * 1000;/* 2 sec */
	}
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	do {
		udelay(1);
		value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
		value &= SPCv_MSGU_CFG_TABLE_RESET;
	} while ((value != 0) && (--max_wait_count));

	if (!max_wait_count) {
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
		return -1;
	}

	/* check the MPI-State for termination in progress */
	/* wait until Inbound DoorBell Clear Register toggled */
	max_wait_count = 2 * 1000 * 1000;	/* 2 sec for spcv/ve */
	do {
		udelay(1);
		gst_len_mpistate =
			pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
			GST_GSTLEN_MPIS_OFFSET);
		if (GST_MPI_STATE_UNINIT ==
			(gst_len_mpistate & GST_MPI_STATE_MASK))
			break;
	} while (--max_wait_count);
	if (!max_wait_count) {
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk(" TIME OUT MPI State = 0x%x\n",
				gst_len_mpistate & GST_MPI_STATE_MASK));
		return -1;
	}

	return 0;
}

/**
 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 * the FW register status to the originated status.
 * @pm8001_ha: our hba card information
 */

static int
pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
{
	u32 regval;
	u32 bootloader_state;
1574
	u32 ibutton0, ibutton1;
1575

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	/* Process MPI table uninitialization only if FW is ready */
	if (!pm8001_ha->controller_fatal_error) {
		/* Check if MPI is in ready state to reset */
		if (mpi_uninit_check(pm8001_ha) != 0) {
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			u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
			u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
			u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
			u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1584
			PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1585 1586 1587 1588 1589 1590 1591
				"MPI state is not ready scratch: %x:%x:%x:%x\n",
				r0, r1, r2, r3));
			/* if things aren't ready but the bootloader is ok then
			 * try the reset anyway.
			 */
			if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
				return -1;
1592
		}
1593 1594 1595 1596 1597 1598 1599
	}
	/* checked for reset register normal state; 0x0 */
	regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
	PM8001_INIT_DBG(pm8001_ha,
		pm8001_printk("reset register before write : 0x%x\n", regval));

	pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1600
	msleep(500);
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	regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
	PM8001_INIT_DBG(pm8001_ha,
	pm8001_printk("reset register after write 0x%x\n", regval));

	if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
			SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" soft reset successful [regval: 0x%x]\n",
					regval));
	} else {
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" soft reset failed [regval: 0x%x]\n",
					regval));

		/* check bootloader is successfully executed or in HDA mode */
		bootloader_state =
			pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
			SCRATCH_PAD1_BOOTSTATE_MASK;

		if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
			PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
				"Bootloader state - HDA mode SEEPROM\n"));
		} else if (bootloader_state ==
				SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
			PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
				"Bootloader state - HDA mode Bootstrap Pin\n"));
		} else if (bootloader_state ==
				SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
			PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
				"Bootloader state - HDA mode soft reset\n"));
		} else if (bootloader_state ==
					SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
			PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
				"Bootloader state-HDA mode critical error\n"));
		}
		return -EBUSY;
	}

	/* check the firmware status after reset */
	if (-1 == check_fw_ready(pm8001_ha)) {
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("Firmware is not ready!\n"));
1644 1645 1646
		/* check iButton feature support for motherboard controller */
		if (pm8001_ha->pdev->subsystem_vendor !=
			PCI_VENDOR_ID_ADAPTEC2 &&
1647 1648
			pm8001_ha->pdev->subsystem_vendor !=
			PCI_VENDOR_ID_ATTO &&
1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666
			pm8001_ha->pdev->subsystem_vendor != 0) {
			ibutton0 = pm8001_cr32(pm8001_ha, 0,
					MSGU_HOST_SCRATCH_PAD_6);
			ibutton1 = pm8001_cr32(pm8001_ha, 0,
					MSGU_HOST_SCRATCH_PAD_7);
			if (!ibutton0 && !ibutton1) {
				PM8001_FAIL_DBG(pm8001_ha,
					pm8001_printk("iButton Feature is"
					" not Available!!!\n"));
				return -EBUSY;
			}
			if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
				PM8001_FAIL_DBG(pm8001_ha,
					pm8001_printk("CRC Check for iButton"
					" Feature Failed!!!\n"));
				return -EBUSY;
			}
		}
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	}
	PM8001_INIT_DBG(pm8001_ha,
		pm8001_printk("SPCv soft reset Complete\n"));
	return 0;
}

static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
{
1675
	u32 i;
1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722

	PM8001_INIT_DBG(pm8001_ha,
		pm8001_printk("chip reset start\n"));

	/* do SPCv chip reset. */
	pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
	PM8001_INIT_DBG(pm8001_ha,
		pm8001_printk("SPC soft reset Complete\n"));

	/* Check this ..whether delay is required or no */
	/* delay 10 usec */
	udelay(10);

	/* wait for 20 msec until the firmware gets reloaded */
	i = 20;
	do {
		mdelay(1);
	} while ((--i) != 0);

	PM8001_INIT_DBG(pm8001_ha,
		pm8001_printk("chip reset finished\n"));
}

/**
 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
 * @pm8001_ha: our hba card information
 */
static void
pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
{
	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
	pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
}

/**
 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
 * @pm8001_ha: our hba card information
 */
static void
pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
{
	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
}

/**
 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
 * @pm8001_ha: our hba card information
1723
 * @vec: interrupt number to enable
1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741
 */
static void
pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
{
#ifdef PM8001_USE_MSIX
	u32 mask;
	mask = (u32)(1 << vec);

	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
	return;
#endif
	pm80xx_chip_intx_interrupt_enable(pm8001_ha);

}

/**
 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
 * @pm8001_ha: our hba card information
1742
 * @vec: interrupt number to disable
1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758
 */
static void
pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
{
#ifdef PM8001_USE_MSIX
	u32 mask;
	if (vec == 0xFF)
		mask = 0xFFFFFFFF;
	else
		mask = (u32)(1 << vec);
	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
	return;
#endif
	pm80xx_chip_intx_interrupt_disable(pm8001_ha);
}

1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786
static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
		struct pm8001_device *pm8001_ha_dev)
{
	int res;
	u32 ccb_tag;
	struct pm8001_ccb_info *ccb;
	struct sas_task *task = NULL;
	struct task_abort_req task_abort;
	struct inbound_queue_table *circularQ;
	u32 opc = OPC_INB_SATA_ABORT;
	int ret;

	if (!pm8001_ha_dev) {
		PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
		return;
	}

	task = sas_alloc_slow_task(GFP_ATOMIC);

	if (!task) {
		PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
						"allocate task\n"));
		return;
	}

	task->task_done = pm8001_task_done;

	res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
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	if (res) {
		sas_free_task(task);
1789
		return;
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	}
1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803

	ccb = &pm8001_ha->ccb_info[ccb_tag];
	ccb->device = pm8001_ha_dev;
	ccb->ccb_tag = ccb_tag;
	ccb->task = task;

	circularQ = &pm8001_ha->inbnd_q_tbl[0];

	memset(&task_abort, 0, sizeof(task_abort));
	task_abort.abort_all = cpu_to_le32(1);
	task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
	task_abort.tag = cpu_to_le32(ccb_tag);

1804 1805 1806 1807
	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
			sizeof(task_abort), 0);
	PM8001_FAIL_DBG(pm8001_ha,
		pm8001_printk("Executing abort task end\n"));
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	if (ret) {
		sas_free_task(task);
		pm8001_tag_free(pm8001_ha, ccb_tag);
	}
1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837
}

static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
		struct pm8001_device *pm8001_ha_dev)
{
	struct sata_start_req sata_cmd;
	int res;
	u32 ccb_tag;
	struct pm8001_ccb_info *ccb;
	struct sas_task *task = NULL;
	struct host_to_dev_fis fis;
	struct domain_device *dev;
	struct inbound_queue_table *circularQ;
	u32 opc = OPC_INB_SATA_HOST_OPSTART;

	task = sas_alloc_slow_task(GFP_ATOMIC);

	if (!task) {
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("cannot allocate task !!!\n"));
		return;
	}
	task->task_done = pm8001_task_done;

	res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
	if (res) {
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		sas_free_task(task);
1839 1840 1841 1842 1843 1844 1845 1846 1847 1848
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("cannot allocate tag !!!\n"));
		return;
	}

	/* allocate domain device by ourselves as libsas
	 * is not going to provide any
	*/
	dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
	if (!dev) {
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		sas_free_task(task);
		pm8001_tag_free(pm8001_ha, ccb_tag);
1851 1852 1853 1854 1855
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("Domain device cannot be allocated\n"));
		return;
	}

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	task->dev = dev;
	task->dev->lldd_dev = pm8001_ha_dev;

1859 1860 1861 1862
	ccb = &pm8001_ha->ccb_info[ccb_tag];
	ccb->device = pm8001_ha_dev;
	ccb->ccb_tag = ccb_tag;
	ccb->task = task;
1863
	ccb->n_elem = 0;
1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882
	pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
	pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;

	memset(&sata_cmd, 0, sizeof(sata_cmd));
	circularQ = &pm8001_ha->inbnd_q_tbl[0];

	/* construct read log FIS */
	memset(&fis, 0, sizeof(struct host_to_dev_fis));
	fis.fis_type = 0x27;
	fis.flags = 0x80;
	fis.command = ATA_CMD_READ_LOG_EXT;
	fis.lbal = 0x10;
	fis.sector_count = 0x1;

	sata_cmd.tag = cpu_to_le32(ccb_tag);
	sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
	sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
	memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));

1883 1884 1885
	res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
			sizeof(sata_cmd), 0);
	PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Executing read log end\n"));
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	if (res) {
		sas_free_task(task);
		pm8001_tag_free(pm8001_ha, ccb_tag);
		kfree(dev);
	}
1891 1892
}

1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935
/**
 * mpi_ssp_completion- process the event that FW response to the SSP request.
 * @pm8001_ha: our hba card information
 * @piomb: the message contents of this outbound message.
 *
 * When FW has completed a ssp request for example a IO request, after it has
 * filled the SG data with the data, it will trigger this event represent
 * that he has finished the job,please check the coresponding buffer.
 * So we will tell the caller who maybe waiting the result to tell upper layer
 * that the task has been finished.
 */
static void
mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
{
	struct sas_task *t;
	struct pm8001_ccb_info *ccb;
	unsigned long flags;
	u32 status;
	u32 param;
	u32 tag;
	struct ssp_completion_resp *psspPayload;
	struct task_status_struct *ts;
	struct ssp_response_iu *iu;
	struct pm8001_device *pm8001_dev;
	psspPayload = (struct ssp_completion_resp *)(piomb + 4);
	status = le32_to_cpu(psspPayload->status);
	tag = le32_to_cpu(psspPayload->tag);
	ccb = &pm8001_ha->ccb_info[tag];
	if ((status == IO_ABORTED) && ccb->open_retry) {
		/* Being completed by another */
		ccb->open_retry = 0;
		return;
	}
	pm8001_dev = ccb->device;
	param = le32_to_cpu(psspPayload->param);
	t = ccb->task;

	if (status && status != IO_UNDERFLOW)
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("sas IO status 0x%x\n", status));
	if (unlikely(!t || !t->lldd_task || !t->dev))
		return;
	ts = &t->task_status;
1936 1937 1938 1939

	PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
		"tag::0x%x, status::0x%x task::0x%p\n", tag, status, t));

1940 1941 1942 1943 1944 1945 1946
	/* Print sas address of IO failed device */
	if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
		(status != IO_UNDERFLOW))
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("SAS Address of IO Failure Drive"
			":%016llx", SAS_ADDR(t->dev->sas_addr)));

1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962
	switch (status) {
	case IO_SUCCESS:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
				param));
		if (param == 0) {
			ts->resp = SAS_TASK_COMPLETE;
			ts->stat = SAM_STAT_GOOD;
		} else {
			ts->resp = SAS_TASK_COMPLETE;
			ts->stat = SAS_PROTO_RESPONSE;
			ts->residual = param;
			iu = &psspPayload->ssp_resp_iu;
			sas_ssp_task_response(pm8001_ha->dev, t, iu);
		}
		if (pm8001_dev)
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			atomic_dec(&pm8001_dev->running_req);
1964 1965 1966 1967 1968 1969
		break;
	case IO_ABORTED:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_ABORTED IOMB Tag\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_ABORTED_TASK;
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		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
1972 1973 1974 1975 1976 1977 1978 1979 1980 1981
		break;
	case IO_UNDERFLOW:
		/* SSP Completion with error */
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
				param));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_UNDERRUN;
		ts->residual = param;
		if (pm8001_dev)
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			atomic_dec(&pm8001_dev->running_req);
1983 1984 1985 1986 1987 1988
		break;
	case IO_NO_DEVICE:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_NO_DEVICE\n"));
		ts->resp = SAS_TASK_UNDELIVERED;
		ts->stat = SAS_PHY_DOWN;
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		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
1991 1992 1993 1994 1995 1996 1997 1998
		break;
	case IO_XFER_ERROR_BREAK:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_BREAK\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		/* Force the midlayer to retry */
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
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		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2001 2002 2003 2004 2005
		break;
	case IO_XFER_ERROR_PHY_NOT_READY:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
		ts->resp = SAS_TASK_COMPLETE;
2006 2007
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
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		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2010 2011 2012 2013 2014
		break;
	case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"));
		ts->resp = SAS_TASK_COMPLETE;
2015 2016
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
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		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2019 2020 2021 2022 2023 2024 2025
		break;
	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
		PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_EPROTO;
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		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2028 2029 2030 2031 2032 2033 2034
		break;
	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
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2035 2036
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2037 2038 2039 2040 2041 2042 2043
		break;
	case IO_OPEN_CNX_ERROR_BREAK:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
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2044 2045
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2046 2047
		break;
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2048 2049 2050 2051 2052
	case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
		if (!t->uldd_task)
			pm8001_handle_event(pm8001_ha,
				pm8001_dev,
				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
		break;
	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
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		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2071 2072 2073 2074 2075 2076 2077
		break;
	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
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2078 2079
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2080 2081 2082 2083 2084 2085 2086
		break;
	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
		ts->resp = SAS_TASK_UNDELIVERED;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
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2087 2088
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2089 2090 2091 2092 2093 2094 2095
		break;
	case IO_XFER_ERROR_NAK_RECEIVED:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
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2096 2097
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2098 2099 2100 2101 2102 2103
		break;
	case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_NAK_R_ERR;
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2104 2105
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2106 2107 2108 2109 2110 2111
		break;
	case IO_XFER_ERROR_DMA:
		PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("IO_XFER_ERROR_DMA\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
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2112 2113
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2114 2115 2116 2117 2118 2119 2120
		break;
	case IO_XFER_OPEN_RETRY_TIMEOUT:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
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2121 2122
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2123 2124 2125 2126 2127 2128
		break;
	case IO_XFER_ERROR_OFFSET_MISMATCH:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
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2129 2130
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2131 2132 2133 2134 2135 2136
		break;
	case IO_PORT_IN_RESET:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_PORT_IN_RESET\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
V
Viswas G 已提交
2137 2138
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154
		break;
	case IO_DS_NON_OPERATIONAL:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		if (!t->uldd_task)
			pm8001_handle_event(pm8001_ha,
				pm8001_dev,
				IO_DS_NON_OPERATIONAL);
		break;
	case IO_DS_IN_RECOVERY:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_DS_IN_RECOVERY\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
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Viswas G 已提交
2155 2156
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2157 2158 2159 2160 2161 2162
		break;
	case IO_TM_TAG_NOT_FOUND:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
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2163 2164
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2165 2166 2167 2168 2169 2170
		break;
	case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
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2171 2172
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2173 2174 2175 2176 2177 2178 2179
		break;
	case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
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2180 2181
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2182 2183
		break;
	default:
2184
		PM8001_DEVIO_DBG(pm8001_ha,
2185 2186 2187 2188
			pm8001_printk("Unknown status 0x%x\n", status));
		/* not allowed case. Therefore, return failed status */
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
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2189 2190
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205
		break;
	}
	PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("scsi_status = 0x%x\n ",
		psspPayload->ssp_resp_iu.status));
	spin_lock_irqsave(&t->task_state_lock, flags);
	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
	t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
	t->task_state_flags |= SAS_TASK_STATE_DONE;
	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
		spin_unlock_irqrestore(&t->task_state_lock, flags);
		PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
			"task 0x%p done with io_status 0x%x resp 0x%x "
			"stat 0x%x but aborted by upper layer!\n",
			t, status, ts->resp, ts->stat));
2206 2207
		if (t->slow_task)
			complete(&t->slow_task->completion);
2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239
		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
	} else {
		spin_unlock_irqrestore(&t->task_state_lock, flags);
		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
		mb();/* in order to force CPU ordering */
		t->task_done(t);
	}
}

/*See the comments for mpi_ssp_completion */
static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
{
	struct sas_task *t;
	unsigned long flags;
	struct task_status_struct *ts;
	struct pm8001_ccb_info *ccb;
	struct pm8001_device *pm8001_dev;
	struct ssp_event_resp *psspPayload =
		(struct ssp_event_resp *)(piomb + 4);
	u32 event = le32_to_cpu(psspPayload->event);
	u32 tag = le32_to_cpu(psspPayload->tag);
	u32 port_id = le32_to_cpu(psspPayload->port_id);

	ccb = &pm8001_ha->ccb_info[tag];
	t = ccb->task;
	pm8001_dev = ccb->device;
	if (event)
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("sas IO status 0x%x\n", event));
	if (unlikely(!t || !t->lldd_task || !t->dev))
		return;
	ts = &t->task_status;
2240
	PM8001_IOERR_DBG(pm8001_ha,
2241 2242 2243 2244 2245 2246 2247 2248 2249
		pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
				port_id, tag, event));
	switch (event) {
	case IO_OVERFLOW:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_OVERRUN;
		ts->residual = 0;
		if (pm8001_dev)
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			atomic_dec(&pm8001_dev->running_req);
2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285
		break;
	case IO_XFER_ERROR_BREAK:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_BREAK\n"));
		pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
		return;
	case IO_XFER_ERROR_PHY_NOT_READY:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
		break;
	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_EPROTO;
		break;
	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
		break;
	case IO_OPEN_CNX_ERROR_BREAK:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
		break;
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2286 2287 2288 2289 2290
	case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
		if (!t->uldd_task)
			pm8001_handle_event(pm8001_ha,
				pm8001_dev,
				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
		break;
	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
		break;
	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
		break;
	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
		break;
	case IO_XFER_ERROR_NAK_RECEIVED:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
		break;
	case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_NAK_R_ERR;
		break;
	case IO_XFER_OPEN_RETRY_TIMEOUT:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
		pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
		return;
	case IO_XFER_ERROR_UNEXPECTED_PHASE:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_OVERRUN;
		break;
	case IO_XFER_ERROR_XFER_RDY_OVERRUN:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_OVERRUN;
		break;
	case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_OVERRUN;
		break;
	case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
		PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_OVERRUN;
		break;
	case IO_XFER_ERROR_OFFSET_MISMATCH:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_OVERRUN;
		break;
	case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_OVERRUN;
		break;
2376
	case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2377
		PM8001_IOERR_DBG(pm8001_ha,
2378 2379 2380 2381 2382
			pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
		/* TBC: used default set values */
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_OVERRUN;
		break;
2383 2384 2385 2386 2387
	case IO_XFER_CMD_FRAME_ISSUED:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
		return;
	default:
2388
		PM8001_DEVIO_DBG(pm8001_ha,
2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422
			pm8001_printk("Unknown status 0x%x\n", event));
		/* not allowed case. Therefore, return failed status */
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_OVERRUN;
		break;
	}
	spin_lock_irqsave(&t->task_state_lock, flags);
	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
	t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
	t->task_state_flags |= SAS_TASK_STATE_DONE;
	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
		spin_unlock_irqrestore(&t->task_state_lock, flags);
		PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
			"task 0x%p done with event 0x%x resp 0x%x "
			"stat 0x%x but aborted by upper layer!\n",
			t, event, ts->resp, ts->stat));
		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
	} else {
		spin_unlock_irqrestore(&t->task_state_lock, flags);
		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
		mb();/* in order to force CPU ordering */
		t->task_done(t);
	}
}

/*See the comments for mpi_ssp_completion */
static void
mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
{
	struct sas_task *t;
	struct pm8001_ccb_info *ccb;
	u32 param;
	u32 status;
	u32 tag;
2423 2424 2425 2426
	int i, j;
	u8 sata_addr_low[4];
	u32 temp_sata_addr_low, temp_sata_addr_hi;
	u8 sata_addr_hi[4];
2427 2428 2429 2430 2431
	struct sata_completion_resp *psataPayload;
	struct task_status_struct *ts;
	struct ata_task_resp *resp ;
	u32 *sata_resp;
	struct pm8001_device *pm8001_dev;
2432
	unsigned long flags;
2433 2434 2435 2436 2437

	psataPayload = (struct sata_completion_resp *)(piomb + 4);
	status = le32_to_cpu(psataPayload->status);
	tag = le32_to_cpu(psataPayload->tag);

2438 2439 2440 2441 2442
	if (!tag) {
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("tag null\n"));
		return;
	}
2443 2444
	ccb = &pm8001_ha->ccb_info[tag];
	param = le32_to_cpu(psataPayload->param);
2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469
	if (ccb) {
		t = ccb->task;
		pm8001_dev = ccb->device;
	} else {
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("ccb null\n"));
		return;
	}

	if (t) {
		if (t->dev && (t->dev->lldd_dev))
			pm8001_dev = t->dev->lldd_dev;
	} else {
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("task null\n"));
		return;
	}

	if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
		&& unlikely(!t || !t->lldd_task || !t->dev)) {
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("task or dev null\n"));
		return;
	}

2470
	ts = &t->task_status;
2471
	if (!ts) {
2472
		PM8001_FAIL_DBG(pm8001_ha,
2473
			pm8001_printk("ts null\n"));
2474
		return;
2475
	}
2476 2477 2478 2479 2480 2481

	if (unlikely(status))
		PM8001_IOERR_DBG(pm8001_ha, pm8001_printk(
			"status:0x%x, tag:0x%x, task::0x%p\n",
			status, tag, t));

2482 2483 2484 2485
	/* Print sas address of IO failed device */
	if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
		(status != IO_UNDERFLOW)) {
		if (!((t->dev->parent) &&
2486
			(dev_is_expander(t->dev->parent->dev_type)))) {
2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515
			for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
				sata_addr_low[i] = pm8001_ha->sas_addr[j];
			for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
				sata_addr_hi[i] = pm8001_ha->sas_addr[j];
			memcpy(&temp_sata_addr_low, sata_addr_low,
				sizeof(sata_addr_low));
			memcpy(&temp_sata_addr_hi, sata_addr_hi,
				sizeof(sata_addr_hi));
			temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
						|((temp_sata_addr_hi << 8) &
						0xff0000) |
						((temp_sata_addr_hi >> 8)
						& 0xff00) |
						((temp_sata_addr_hi << 24) &
						0xff000000));
			temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
						& 0xff) |
						((temp_sata_addr_low << 8)
						& 0xff0000) |
						((temp_sata_addr_low >> 8)
						& 0xff00) |
						((temp_sata_addr_low << 24)
						& 0xff000000)) +
						pm8001_dev->attached_phy +
						0x10);
			PM8001_FAIL_DBG(pm8001_ha,
				pm8001_printk("SAS Address of IO Failure Drive:"
				"%08x%08x", temp_sata_addr_hi,
					temp_sata_addr_low));
2516

2517 2518 2519 2520 2521 2522
		} else {
			PM8001_FAIL_DBG(pm8001_ha,
				pm8001_printk("SAS Address of IO Failure Drive:"
				"%016llx", SAS_ADDR(t->dev->sas_addr)));
		}
	}
2523 2524 2525 2526 2527 2528
	switch (status) {
	case IO_SUCCESS:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
		if (param == 0) {
			ts->resp = SAS_TASK_COMPLETE;
			ts->stat = SAM_STAT_GOOD;
2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541
			/* check if response is for SEND READ LOG */
			if (pm8001_dev &&
				(pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
				/* set new bit for abort_all */
				pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
				/* clear bit for read log */
				pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
				pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
				/* Free the tag */
				pm8001_tag_free(pm8001_ha, tag);
				sas_free_task(t);
				return;
			}
2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552
		} else {
			u8 len;
			ts->resp = SAS_TASK_COMPLETE;
			ts->stat = SAS_PROTO_RESPONSE;
			ts->residual = param;
			PM8001_IO_DBG(pm8001_ha,
				pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
				param));
			sata_resp = &psataPayload->sata_resp[0];
			resp = (struct ata_task_resp *)ts->buf;
			if (t->ata_task.dma_xfer == 0 &&
2553
			    t->data_dir == DMA_FROM_DEVICE) {
2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571
				len = sizeof(struct pio_setup_fis);
				PM8001_IO_DBG(pm8001_ha,
				pm8001_printk("PIO read len = %d\n", len));
			} else if (t->ata_task.use_ncq) {
				len = sizeof(struct set_dev_bits_fis);
				PM8001_IO_DBG(pm8001_ha,
					pm8001_printk("FPDMA len = %d\n", len));
			} else {
				len = sizeof(struct dev_to_host_fis);
				PM8001_IO_DBG(pm8001_ha,
				pm8001_printk("other len = %d\n", len));
			}
			if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
				resp->frame_len = len;
				memcpy(&resp->ending_fis[0], sata_resp, len);
				ts->buf_valid_size = sizeof(*resp);
			} else
				PM8001_IO_DBG(pm8001_ha,
2572
					pm8001_printk("response too large\n"));
2573 2574
		}
		if (pm8001_dev)
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			atomic_dec(&pm8001_dev->running_req);
2576 2577 2578 2579 2580 2581 2582
		break;
	case IO_ABORTED:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_ABORTED IOMB Tag\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_ABORTED_TASK;
		if (pm8001_dev)
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			atomic_dec(&pm8001_dev->running_req);
2584 2585 2586 2587 2588 2589 2590 2591 2592 2593
		break;
		/* following cases are to do cases */
	case IO_UNDERFLOW:
		/* SATA Completion with error */
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_UNDERFLOW param = %d\n", param));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_UNDERRUN;
		ts->residual = param;
		if (pm8001_dev)
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			atomic_dec(&pm8001_dev->running_req);
2595 2596 2597 2598 2599 2600
		break;
	case IO_NO_DEVICE:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_NO_DEVICE\n"));
		ts->resp = SAS_TASK_UNDELIVERED;
		ts->stat = SAS_PHY_DOWN;
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		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2603 2604 2605 2606 2607 2608
		break;
	case IO_XFER_ERROR_BREAK:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_BREAK\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_INTERRUPTED;
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		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2611 2612 2613 2614 2615 2616 2617
		break;
	case IO_XFER_ERROR_PHY_NOT_READY:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
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		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2620 2621 2622 2623 2624 2625 2626
		break;
	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_EPROTO;
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2627 2628
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2629 2630 2631 2632 2633 2634 2635
		break;
	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
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2636 2637
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2638 2639 2640 2641 2642 2643 2644
		break;
	case IO_OPEN_CNX_ERROR_BREAK:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
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		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2647 2648
		break;
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2649 2650 2651 2652 2653
	case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2654 2655 2656 2657 2658 2659 2660 2661 2662 2663
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DEV_NO_RESPONSE;
		if (!t->uldd_task) {
			pm8001_handle_event(pm8001_ha,
				pm8001_dev,
				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
			ts->resp = SAS_TASK_UNDELIVERED;
			ts->stat = SAS_QUEUE_FULL;
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			pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679
			return;
		}
		break;
	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
		ts->resp = SAS_TASK_UNDELIVERED;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
		if (!t->uldd_task) {
			pm8001_handle_event(pm8001_ha,
				pm8001_dev,
				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
			ts->resp = SAS_TASK_UNDELIVERED;
			ts->stat = SAS_QUEUE_FULL;
S
Suresh Thiagarajan 已提交
2680
			pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2681 2682 2683 2684 2685 2686 2687 2688 2689
			return;
		}
		break;
	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
V
Viswas G 已提交
2690 2691
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703
		break;
	case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DEV_NO_RESPONSE;
		if (!t->uldd_task) {
			pm8001_handle_event(pm8001_ha,
				pm8001_dev,
				IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
			ts->resp = SAS_TASK_UNDELIVERED;
			ts->stat = SAS_QUEUE_FULL;
S
Suresh Thiagarajan 已提交
2704
			pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2705 2706 2707 2708 2709 2710 2711 2712 2713
			return;
		}
		break;
	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
V
Viswas G 已提交
2714 2715
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2716 2717 2718 2719 2720 2721
		break;
	case IO_XFER_ERROR_NAK_RECEIVED:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_NAK_R_ERR;
V
Viswas G 已提交
2722 2723
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2724 2725 2726 2727 2728 2729
		break;
	case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_NAK_R_ERR;
V
Viswas G 已提交
2730 2731
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2732 2733 2734 2735 2736 2737
		break;
	case IO_XFER_ERROR_DMA:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_DMA\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_ABORTED_TASK;
V
Viswas G 已提交
2738 2739
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2740 2741 2742 2743 2744 2745
		break;
	case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
		ts->resp = SAS_TASK_UNDELIVERED;
		ts->stat = SAS_DEV_NO_RESPONSE;
V
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2746 2747
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2748 2749 2750 2751 2752 2753
		break;
	case IO_XFER_ERROR_REJECTED_NCQ_MODE:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_UNDERRUN;
V
Viswas G 已提交
2754 2755
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2756 2757 2758 2759 2760 2761
		break;
	case IO_XFER_OPEN_RETRY_TIMEOUT:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_TO;
V
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2762 2763
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2764 2765 2766 2767 2768 2769
		break;
	case IO_PORT_IN_RESET:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_PORT_IN_RESET\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DEV_NO_RESPONSE;
V
Viswas G 已提交
2770 2771
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782
		break;
	case IO_DS_NON_OPERATIONAL:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DEV_NO_RESPONSE;
		if (!t->uldd_task) {
			pm8001_handle_event(pm8001_ha, pm8001_dev,
					IO_DS_NON_OPERATIONAL);
			ts->resp = SAS_TASK_UNDELIVERED;
			ts->stat = SAS_QUEUE_FULL;
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Suresh Thiagarajan 已提交
2783
			pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2784 2785 2786 2787 2788 2789 2790 2791
			return;
		}
		break;
	case IO_DS_IN_RECOVERY:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_DS_IN_RECOVERY\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DEV_NO_RESPONSE;
V
Viswas G 已提交
2792 2793
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804
		break;
	case IO_DS_IN_ERROR:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_DS_IN_ERROR\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DEV_NO_RESPONSE;
		if (!t->uldd_task) {
			pm8001_handle_event(pm8001_ha, pm8001_dev,
					IO_DS_IN_ERROR);
			ts->resp = SAS_TASK_UNDELIVERED;
			ts->stat = SAS_QUEUE_FULL;
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Suresh Thiagarajan 已提交
2805
			pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2806 2807 2808 2809 2810 2811 2812 2813 2814
			return;
		}
		break;
	case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
V
Viswas G 已提交
2815 2816
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2817
		break;
2818
	default:
2819
		PM8001_DEVIO_DBG(pm8001_ha,
2820 2821 2822 2823
			pm8001_printk("Unknown status 0x%x\n", status));
		/* not allowed case. Therefore, return failed status */
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DEV_NO_RESPONSE;
V
Viswas G 已提交
2824 2825
		if (pm8001_dev)
			atomic_dec(&pm8001_dev->running_req);
2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837
		break;
	}
	spin_lock_irqsave(&t->task_state_lock, flags);
	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
	t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
	t->task_state_flags |= SAS_TASK_STATE_DONE;
	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
		spin_unlock_irqrestore(&t->task_state_lock, flags);
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("task 0x%p done with io_status 0x%x"
			" resp 0x%x stat 0x%x but aborted by upper layer!\n",
			t, status, ts->resp, ts->stat));
2838 2839
		if (t->slow_task)
			complete(&t->slow_task->completion);
2840
		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
S
Suresh Thiagarajan 已提交
2841
	} else {
2842
		spin_unlock_irqrestore(&t->task_state_lock, flags);
S
Suresh Thiagarajan 已提交
2843
		pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858
	}
}

/*See the comments for mpi_ssp_completion */
static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
{
	struct sas_task *t;
	struct task_status_struct *ts;
	struct pm8001_ccb_info *ccb;
	struct pm8001_device *pm8001_dev;
	struct sata_event_resp *psataPayload =
		(struct sata_event_resp *)(piomb + 4);
	u32 event = le32_to_cpu(psataPayload->event);
	u32 tag = le32_to_cpu(psataPayload->tag);
	u32 port_id = le32_to_cpu(psataPayload->port_id);
2859 2860
	u32 dev_id = le32_to_cpu(psataPayload->device_id);
	unsigned long flags;
2861 2862

	ccb = &pm8001_ha->ccb_info[tag];
2863 2864 2865 2866 2867 2868 2869 2870 2871

	if (ccb) {
		t = ccb->task;
		pm8001_dev = ccb->device;
	} else {
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("No CCB !!!. returning\n"));
		return;
	}
2872 2873
	if (event)
		PM8001_FAIL_DBG(pm8001_ha,
2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888
			pm8001_printk("SATA EVENT 0x%x\n", event));

	/* Check if this is NCQ error */
	if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
		/* find device using device id */
		pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
		/* send read log extension */
		if (pm8001_dev)
			pm80xx_send_read_log(pm8001_ha, pm8001_dev);
		return;
	}

	if (unlikely(!t || !t->lldd_task || !t->dev)) {
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("task or dev null\n"));
2889
		return;
2890 2891
	}

2892
	ts = &t->task_status;
2893
	PM8001_IOERR_DBG(pm8001_ha,
2894 2895 2896 2897 2898 2899 2900 2901 2902
		pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
				port_id, tag, event));
	switch (event) {
	case IO_OVERFLOW:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_OVERRUN;
		ts->residual = 0;
		if (pm8001_dev)
V
Viswas G 已提交
2903
			atomic_dec(&pm8001_dev->running_req);
2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939
		break;
	case IO_XFER_ERROR_BREAK:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_BREAK\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_INTERRUPTED;
		break;
	case IO_XFER_ERROR_PHY_NOT_READY:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
		break;
	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_EPROTO;
		break;
	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
		break;
	case IO_OPEN_CNX_ERROR_BREAK:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
		break;
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2940 2941 2942 2943 2944 2945
	case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
		PM8001_FAIL_DBG(pm8001_ha,
2946 2947 2948 2949 2950 2951 2952 2953 2954
			pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
		ts->resp = SAS_TASK_UNDELIVERED;
		ts->stat = SAS_DEV_NO_RESPONSE;
		if (!t->uldd_task) {
			pm8001_handle_event(pm8001_ha,
				pm8001_dev,
				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
			ts->resp = SAS_TASK_COMPLETE;
			ts->stat = SAS_QUEUE_FULL;
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Suresh Thiagarajan 已提交
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			pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043
			return;
		}
		break;
	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
		ts->resp = SAS_TASK_UNDELIVERED;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
		break;
	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
		break;
	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
		break;
	case IO_XFER_ERROR_NAK_RECEIVED:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_NAK_R_ERR;
		break;
	case IO_XFER_ERROR_PEER_ABORTED:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_NAK_R_ERR;
		break;
	case IO_XFER_ERROR_REJECTED_NCQ_MODE:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_UNDERRUN;
		break;
	case IO_XFER_OPEN_RETRY_TIMEOUT:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_TO;
		break;
	case IO_XFER_ERROR_UNEXPECTED_PHASE:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_TO;
		break;
	case IO_XFER_ERROR_XFER_RDY_OVERRUN:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_TO;
		break;
	case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_TO;
		break;
	case IO_XFER_ERROR_OFFSET_MISMATCH:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_TO;
		break;
	case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_TO;
		break;
	case IO_XFER_CMD_FRAME_ISSUED:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
		break;
	case IO_XFER_PIO_SETUP_ERROR:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_TO;
		break;
3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057
	case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
		/* TBC: used default set values */
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_TO;
		break;
	case IO_XFER_DMA_ACTIVATE_TIMEOUT:
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
		/* TBC: used default set values */
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_TO;
		break;
3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076
	default:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("Unknown status 0x%x\n", event));
		/* not allowed case. Therefore, return failed status */
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_TO;
		break;
	}
	spin_lock_irqsave(&t->task_state_lock, flags);
	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
	t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
	t->task_state_flags |= SAS_TASK_STATE_DONE;
	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
		spin_unlock_irqrestore(&t->task_state_lock, flags);
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("task 0x%p done with io_status 0x%x"
			" resp 0x%x stat 0x%x but aborted by upper layer!\n",
			t, event, ts->resp, ts->stat));
		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
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Suresh Thiagarajan 已提交
3077
	} else {
3078
		spin_unlock_irqrestore(&t->task_state_lock, flags);
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Suresh Thiagarajan 已提交
3079
		pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112
	}
}

/*See the comments for mpi_ssp_completion */
static void
mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
{
	u32 param, i;
	struct sas_task *t;
	struct pm8001_ccb_info *ccb;
	unsigned long flags;
	u32 status;
	u32 tag;
	struct smp_completion_resp *psmpPayload;
	struct task_status_struct *ts;
	struct pm8001_device *pm8001_dev;
	char *pdma_respaddr = NULL;

	psmpPayload = (struct smp_completion_resp *)(piomb + 4);
	status = le32_to_cpu(psmpPayload->status);
	tag = le32_to_cpu(psmpPayload->tag);

	ccb = &pm8001_ha->ccb_info[tag];
	param = le32_to_cpu(psmpPayload->param);
	t = ccb->task;
	ts = &t->task_status;
	pm8001_dev = ccb->device;
	if (status)
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("smp IO status 0x%x\n", status));
	if (unlikely(!t || !t->lldd_task || !t->dev))
		return;

3113 3114 3115
	PM8001_DEV_DBG(pm8001_ha,
		pm8001_printk("tag::0x%x status::0x%x\n", tag, status));

3116 3117 3118 3119 3120 3121 3122
	switch (status) {

	case IO_SUCCESS:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAM_STAT_GOOD;
		if (pm8001_dev)
V
Viswas G 已提交
3123
			atomic_dec(&pm8001_dev->running_req);
3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145
		if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
			PM8001_IO_DBG(pm8001_ha,
				pm8001_printk("DIRECT RESPONSE Length:%d\n",
						param));
			pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
						((u64)sg_dma_address
						(&t->smp_task.smp_resp))));
			for (i = 0; i < param; i++) {
				*(pdma_respaddr+i) = psmpPayload->_r_a[i];
				PM8001_IO_DBG(pm8001_ha, pm8001_printk(
					"SMP Byte%d DMA data 0x%x psmp 0x%x\n",
					i, *(pdma_respaddr+i),
					psmpPayload->_r_a[i]));
			}
		}
		break;
	case IO_ABORTED:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_ABORTED IOMB\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_ABORTED_TASK;
		if (pm8001_dev)
V
Viswas G 已提交
3146
			atomic_dec(&pm8001_dev->running_req);
3147 3148 3149 3150 3151 3152 3153
		break;
	case IO_OVERFLOW:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DATA_OVERRUN;
		ts->residual = 0;
		if (pm8001_dev)
V
Viswas G 已提交
3154
			atomic_dec(&pm8001_dev->running_req);
3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200
		break;
	case IO_NO_DEVICE:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_PHY_DOWN;
		break;
	case IO_ERROR_HW_TIMEOUT:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAM_STAT_BUSY;
		break;
	case IO_XFER_ERROR_BREAK:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_BREAK\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAM_STAT_BUSY;
		break;
	case IO_XFER_ERROR_PHY_NOT_READY:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAM_STAT_BUSY;
		break;
	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
		PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
		break;
	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
		break;
	case IO_OPEN_CNX_ERROR_BREAK:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
		break;
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3201 3202 3203 3204 3205
	case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
		pm8001_handle_event(pm8001_ha,
				pm8001_dev,
				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
		break;
	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
		break;
	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
			"IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
		break;
	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
		break;
	case IO_XFER_ERROR_RX_FRAME:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DEV_NO_RESPONSE;
		break;
	case IO_XFER_OPEN_RETRY_TIMEOUT:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
		break;
	case IO_ERROR_INTERNAL_SMP_RESOURCE:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_QUEUE_FULL;
		break;
	case IO_PORT_IN_RESET:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_PORT_IN_RESET\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
		break;
	case IO_DS_NON_OPERATIONAL:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DEV_NO_RESPONSE;
		break;
	case IO_DS_IN_RECOVERY:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_DS_IN_RECOVERY\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
		break;
	case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_OPEN_REJECT;
		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
		break;
	default:
3283
		PM8001_DEVIO_DBG(pm8001_ha,
3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333
			pm8001_printk("Unknown status 0x%x\n", status));
		ts->resp = SAS_TASK_COMPLETE;
		ts->stat = SAS_DEV_NO_RESPONSE;
		/* not allowed case. Therefore, return failed status */
		break;
	}
	spin_lock_irqsave(&t->task_state_lock, flags);
	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
	t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
	t->task_state_flags |= SAS_TASK_STATE_DONE;
	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
		spin_unlock_irqrestore(&t->task_state_lock, flags);
		PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
			"task 0x%p done with io_status 0x%x resp 0x%x"
			"stat 0x%x but aborted by upper layer!\n",
			t, status, ts->resp, ts->stat));
		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
	} else {
		spin_unlock_irqrestore(&t->task_state_lock, flags);
		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
		mb();/* in order to force CPU ordering */
		t->task_done(t);
	}
}

/**
 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
 * @pm8001_ha: our hba card information
 * @Qnum: the outbound queue message number.
 * @SEA: source of event to ack
 * @port_id: port id.
 * @phyId: phy id.
 * @param0: parameter 0.
 * @param1: parameter 1.
 */
static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
	u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
{
	struct hw_event_ack_req	 payload;
	u32 opc = OPC_INB_SAS_HW_EVENT_ACK;

	struct inbound_queue_table *circularQ;

	memset((u8 *)&payload, 0, sizeof(payload));
	circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
	payload.tag = cpu_to_le32(1);
	payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
		((phyId & 0xFF) << 24) | (port_id & 0xFF));
	payload.param0 = cpu_to_le32(param0);
	payload.param1 = cpu_to_le32(param1);
3334 3335
	pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
			sizeof(payload), 0);
3336 3337 3338 3339 3340
}

static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
	u32 phyId, u32 phy_op);

3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366
static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
					void *piomb)
{
	struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
	u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
	u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
	u32 lr_status_evt_portid =
		le32_to_cpu(pPayload->lr_status_evt_portid);
	u8 deviceType = pPayload->sas_identify.dev_type;
	u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
	u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
	struct pm8001_port *port = &pm8001_ha->port[port_id];

	if (deviceType == SAS_END_DEVICE) {
		pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
					PHY_NOTIFY_ENABLE_SPINUP);
	}

	port->wide_port_phymap |= (1U << phy_id);
	pm8001_get_lrate_mode(phy, link_rate);
	phy->sas_phy.oob_mode = SAS_OOB_MODE;
	phy->phy_state = PHY_STATE_LINK_UP_SPCV;
	phy->phy_attached = 1;
}

3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393
/**
 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static void
hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
{
	struct hw_event_resp *pPayload =
		(struct hw_event_resp *)(piomb + 4);
	u32 lr_status_evt_portid =
		le32_to_cpu(pPayload->lr_status_evt_portid);
	u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);

	u8 link_rate =
		(u8)((lr_status_evt_portid & 0xF0000000) >> 28);
	u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
	u8 phy_id =
		(u8)((phyid_npip_portstate & 0xFF0000) >> 16);
	u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);

	struct pm8001_port *port = &pm8001_ha->port[port_id];
	struct sas_ha_struct *sas_ha = pm8001_ha->sas;
	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
	unsigned long flags;
	u8 deviceType = pPayload->sas_identify.dev_type;
	port->port_state = portstate;
3394
	port->wide_port_phymap |= (1U << phy_id);
3395
	phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425
	PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
		"portid:%d; phyid:%d; linkrate:%d; "
		"portstate:%x; devicetype:%x\n",
		port_id, phy_id, link_rate, portstate, deviceType));

	switch (deviceType) {
	case SAS_PHY_UNUSED:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("device type no device.\n"));
		break;
	case SAS_END_DEVICE:
		PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
		pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
			PHY_NOTIFY_ENABLE_SPINUP);
		port->port_attached = 1;
		pm8001_get_lrate_mode(phy, link_rate);
		break;
	case SAS_EDGE_EXPANDER_DEVICE:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("expander device.\n"));
		port->port_attached = 1;
		pm8001_get_lrate_mode(phy, link_rate);
		break;
	case SAS_FANOUT_EXPANDER_DEVICE:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("fanout expander device.\n"));
		port->port_attached = 1;
		pm8001_get_lrate_mode(phy, link_rate);
		break;
	default:
3426
		PM8001_DEVIO_DBG(pm8001_ha,
3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445
			pm8001_printk("unknown device type(%x)\n", deviceType));
		break;
	}
	phy->phy_type |= PORT_TYPE_SAS;
	phy->identify.device_type = deviceType;
	phy->phy_attached = 1;
	if (phy->identify.device_type == SAS_END_DEVICE)
		phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
	else if (phy->identify.device_type != SAS_PHY_UNUSED)
		phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
	phy->sas_phy.oob_mode = SAS_OOB_MODE;
	sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
	spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
	memcpy(phy->frame_rcvd, &pPayload->sas_identify,
		sizeof(struct sas_identify_frame)-4);
	phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
	pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
	spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
	if (pm8001_ha->flags == PM8001F_RUN_TIME)
3446
		mdelay(200); /* delay a moment to wait for disk to spin up */
3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474
	pm8001_bytes_dmaed(pm8001_ha, phy_id);
}

/**
 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static void
hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
{
	struct hw_event_resp *pPayload =
		(struct hw_event_resp *)(piomb + 4);
	u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
	u32 lr_status_evt_portid =
		le32_to_cpu(pPayload->lr_status_evt_portid);
	u8 link_rate =
		(u8)((lr_status_evt_portid & 0xF0000000) >> 28);
	u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
	u8 phy_id =
		(u8)((phyid_npip_portstate & 0xFF0000) >> 16);

	u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);

	struct pm8001_port *port = &pm8001_ha->port[port_id];
	struct sas_ha_struct *sas_ha = pm8001_ha->sas;
	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
	unsigned long flags;
3475
	PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
3476 3477 3478 3479
		"port id %d, phy id %d link_rate %d portstate 0x%x\n",
				port_id, phy_id, link_rate, portstate));

	port->port_state = portstate;
3480
	phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491
	port->port_attached = 1;
	pm8001_get_lrate_mode(phy, link_rate);
	phy->phy_type |= PORT_TYPE_SATA;
	phy->phy_attached = 1;
	phy->sas_phy.oob_mode = SATA_OOB_MODE;
	sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
	spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
	memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
		sizeof(struct dev_to_host_fis));
	phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
	phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3492
	phy->identify.device_type = SAS_SATA_DEV;
3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518
	pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
	spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
	pm8001_bytes_dmaed(pm8001_ha, phy_id);
}

/**
 * hw_event_phy_down -we should notify the libsas the phy is down.
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static void
hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
{
	struct hw_event_resp *pPayload =
		(struct hw_event_resp *)(piomb + 4);

	u32 lr_status_evt_portid =
		le32_to_cpu(pPayload->lr_status_evt_portid);
	u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
	u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
	u8 phy_id =
		(u8)((phyid_npip_portstate & 0xFF0000) >> 16);
	u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);

	struct pm8001_port *port = &pm8001_ha->port[port_id];
	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3519
	u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530
	port->port_state = portstate;
	phy->identify.device_type = 0;
	phy->phy_attached = 0;
	switch (portstate) {
	case PORT_VALID:
		break;
	case PORT_INVALID:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" PortInvalid portID %d\n", port_id));
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" Last phy Down and port invalid\n"));
3531
		if (port_sata) {
3532 3533 3534 3535 3536 3537
			phy->phy_type = 0;
			port->port_attached = 0;
			pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
					port_id, phy_id, 0, 0);
		}
		sas_phy_disconnected(&phy->sas_phy);
3538 3539 3540 3541 3542 3543 3544
		break;
	case PORT_IN_RESET:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" Port In Reset portID %d\n", port_id));
		break;
	case PORT_NOT_ESTABLISHED:
		PM8001_MSG_DBG(pm8001_ha,
3545
			pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n"));
3546 3547 3548 3549
		port->port_attached = 0;
		break;
	case PORT_LOSTCOMM:
		PM8001_MSG_DBG(pm8001_ha,
3550
			pm8001_printk(" Phy Down and PORT_LOSTCOMM\n"));
3551 3552
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" Last phy Down and port invalid\n"));
3553
		if (port_sata) {
3554 3555 3556 3557 3558 3559
			port->port_attached = 0;
			phy->phy_type = 0;
			pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
					port_id, phy_id, 0, 0);
		}
		sas_phy_disconnected(&phy->sas_phy);
3560 3561 3562
		break;
	default:
		port->port_attached = 0;
3563
		PM8001_DEVIO_DBG(pm8001_ha,
3564
			pm8001_printk(" Phy Down and(default) = 0x%x\n",
3565 3566 3567 3568
			portstate));
		break;

	}
3569 3570 3571 3572 3573
	if (port_sata && (portstate != PORT_IN_RESET)) {
		struct sas_ha_struct *sas_ha = pm8001_ha->sas;

		sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
	}
3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589
}

static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
{
	struct phy_start_resp *pPayload =
		(struct phy_start_resp *)(piomb + 4);
	u32 status =
		le32_to_cpu(pPayload->status);
	u32 phy_id =
		le32_to_cpu(pPayload->phyid);
	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];

	PM8001_INIT_DBG(pm8001_ha,
		pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
				status, phy_id));
	if (status == 0) {
3590 3591
		phy->phy_state = PHY_LINK_DOWN;
		if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3592
				phy->enable_completion != NULL) {
3593
			complete(phy->enable_completion);
3594 3595
			phy->enable_completion = NULL;
		}
3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637
	}
	return 0;

}

/**
 * mpi_thermal_hw_event -The hw event has come.
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
{
	struct thermal_hw_event *pPayload =
		(struct thermal_hw_event *)(piomb + 4);

	u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
	u32 rht_lht = le32_to_cpu(pPayload->rht_lht);

	if (thermal_event & 0x40) {
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"Thermal Event: Local high temperature violated!\n"));
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"Thermal Event: Measured local high temperature %d\n",
				((rht_lht & 0xFF00) >> 8)));
	}
	if (thermal_event & 0x10) {
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"Thermal Event: Remote high temperature violated!\n"));
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"Thermal Event: Measured remote high temperature %d\n",
				((rht_lht & 0xFF000000) >> 24)));
	}
	return 0;
}

/**
 * mpi_hw_event -The hw event has come.
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
{
3638
	unsigned long flags, i;
3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652
	struct hw_event_resp *pPayload =
		(struct hw_event_resp *)(piomb + 4);
	u32 lr_status_evt_portid =
		le32_to_cpu(pPayload->lr_status_evt_portid);
	u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
	u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
	u8 phy_id =
		(u8)((phyid_npip_portstate & 0xFF0000) >> 16);
	u16 eventType =
		(u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
	u8 status =
		(u8)((lr_status_evt_portid & 0x0F000000) >> 24);
	struct sas_ha_struct *sas_ha = pm8001_ha->sas;
	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3653
	struct pm8001_port *port = &pm8001_ha->port[port_id];
3654
	struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3655
	PM8001_DEV_DBG(pm8001_ha,
3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678
		pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
				port_id, phy_id, eventType, status));

	switch (eventType) {

	case HW_EVENT_SAS_PHY_UP:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
		hw_event_sas_phy_up(pm8001_ha, piomb);
		break;
	case HW_EVENT_SATA_PHY_UP:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
		hw_event_sata_phy_up(pm8001_ha, piomb);
		break;
	case HW_EVENT_SATA_SPINUP_HOLD:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
		sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
		break;
	case HW_EVENT_PHY_DOWN:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3679 3680 3681 3682 3683 3684
		hw_event_phy_down(pm8001_ha, piomb);
		if (pm8001_ha->reset_in_progress) {
			PM8001_MSG_DBG(pm8001_ha,
				pm8001_printk("Reset in progress\n"));
			return 0;
		}
3685
		phy->phy_attached = 0;
3686
		phy->phy_state = PHY_LINK_DISABLE;
3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792
		break;
	case HW_EVENT_PORT_INVALID:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_PORT_INVALID\n"));
		sas_phy_disconnected(sas_phy);
		phy->phy_attached = 0;
		sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
		break;
	/* the broadcast change primitive received, tell the LIBSAS this event
	to revalidate the sas domain*/
	case HW_EVENT_BROADCAST_CHANGE:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
		pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
			port_id, phy_id, 1, 0);
		spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
		sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
		spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
		sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
		break;
	case HW_EVENT_PHY_ERROR:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_PHY_ERROR\n"));
		sas_phy_disconnected(&phy->sas_phy);
		phy->phy_attached = 0;
		sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
		break;
	case HW_EVENT_BROADCAST_EXP:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
		spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
		sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
		spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
		sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
		break;
	case HW_EVENT_LINK_ERR_INVALID_DWORD:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
		pm80xx_hw_event_ack_req(pm8001_ha, 0,
			HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
		break;
	case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
		pm80xx_hw_event_ack_req(pm8001_ha, 0,
			HW_EVENT_LINK_ERR_DISPARITY_ERROR,
			port_id, phy_id, 0, 0);
		break;
	case HW_EVENT_LINK_ERR_CODE_VIOLATION:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
		pm80xx_hw_event_ack_req(pm8001_ha, 0,
			HW_EVENT_LINK_ERR_CODE_VIOLATION,
			port_id, phy_id, 0, 0);
		break;
	case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
		PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
				"HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
		pm80xx_hw_event_ack_req(pm8001_ha, 0,
			HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
			port_id, phy_id, 0, 0);
		break;
	case HW_EVENT_MALFUNCTION:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_MALFUNCTION\n"));
		break;
	case HW_EVENT_BROADCAST_SES:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
		spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
		sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
		spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
		sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
		break;
	case HW_EVENT_INBOUND_CRC_ERROR:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
		pm80xx_hw_event_ack_req(pm8001_ha, 0,
			HW_EVENT_INBOUND_CRC_ERROR,
			port_id, phy_id, 0, 0);
		break;
	case HW_EVENT_HARD_RESET_RECEIVED:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
		sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
		break;
	case HW_EVENT_ID_FRAME_TIMEOUT:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
		sas_phy_disconnected(sas_phy);
		phy->phy_attached = 0;
		sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
		break;
	case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
		pm80xx_hw_event_ack_req(pm8001_ha, 0,
			HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
			port_id, phy_id, 0, 0);
		sas_phy_disconnected(sas_phy);
		phy->phy_attached = 0;
		sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
		break;
	case HW_EVENT_PORT_RESET_TIMER_TMO:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3793 3794
		pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
			port_id, phy_id, 0, 0);
3795 3796 3797
		sas_phy_disconnected(sas_phy);
		phy->phy_attached = 0;
		sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3798 3799 3800 3801 3802 3803
		if (pm8001_ha->phy[phy_id].reset_completion) {
			pm8001_ha->phy[phy_id].port_reset_status =
					PORT_RESET_TMO;
			complete(pm8001_ha->phy[phy_id].reset_completion);
			pm8001_ha->phy[phy_id].reset_completion = NULL;
		}
3804 3805 3806 3807
		break;
	case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3808 3809 3810
		pm80xx_hw_event_ack_req(pm8001_ha, 0,
			HW_EVENT_PORT_RECOVERY_TIMER_TMO,
			port_id, phy_id, 0, 0);
3811 3812 3813 3814 3815 3816 3817 3818
		for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
			if (port->wide_port_phymap & (1 << i)) {
				phy = &pm8001_ha->phy[i];
				sas_ha->notify_phy_event(&phy->sas_phy,
						PHYE_LOSS_OF_SIGNAL);
				port->wide_port_phymap &= ~(1 << i);
			}
		}
3819 3820 3821 3822
		break;
	case HW_EVENT_PORT_RECOVER:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3823
		hw_event_port_recover(pm8001_ha, piomb);
3824 3825 3826 3827
		break;
	case HW_EVENT_PORT_RESET_COMPLETE:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3828 3829 3830 3831 3832 3833
		if (pm8001_ha->phy[phy_id].reset_completion) {
			pm8001_ha->phy[phy_id].port_reset_status =
					PORT_RESET_SUCCESS;
			complete(pm8001_ha->phy[phy_id].reset_completion);
			pm8001_ha->phy[phy_id].reset_completion = NULL;
		}
3834 3835 3836 3837 3838 3839
		break;
	case EVENT_BROADCAST_ASYNCH_EVENT:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
		break;
	default:
3840
		PM8001_DEVIO_DBG(pm8001_ha,
3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858
			pm8001_printk("Unknown event type 0x%x\n", eventType));
		break;
	}
	return 0;
}

/**
 * mpi_phy_stop_resp - SPCv specific
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
{
	struct phy_stop_resp *pPayload =
		(struct phy_stop_resp *)(piomb + 4);
	u32 status =
		le32_to_cpu(pPayload->status);
	u32 phyid =
3859
		le32_to_cpu(pPayload->phyid) & 0xFF;
3860 3861 3862 3863
	struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
	PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("phy:0x%x status:0x%x\n",
					phyid, status));
3864 3865 3866
	if (status == PHY_STOP_SUCCESS ||
		status == PHY_STOP_ERR_DEVICE_ATTACHED)
		phy->phy_state = PHY_LINK_DISABLE;
3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938
	return 0;
}

/**
 * mpi_set_controller_config_resp - SPCv specific
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
			void *piomb)
{
	struct set_ctrl_cfg_resp *pPayload =
			(struct set_ctrl_cfg_resp *)(piomb + 4);
	u32 status = le32_to_cpu(pPayload->status);
	u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);

	PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
			"SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
			status, err_qlfr_pgcd));

	return 0;
}

/**
 * mpi_get_controller_config_resp - SPCv specific
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
			void *piomb)
{
	PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" pm80xx_addition_functionality\n"));

	return 0;
}

/**
 * mpi_get_phy_profile_resp - SPCv specific
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
			void *piomb)
{
	PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" pm80xx_addition_functionality\n"));

	return 0;
}

/**
 * mpi_flash_op_ext_resp - SPCv specific
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
{
	PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" pm80xx_addition_functionality\n"));

	return 0;
}

/**
 * mpi_set_phy_profile_resp - SPCv specific
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
			void *piomb)
{
3939
	u32 tag;
3940
	u8 page_code;
3941
	int rc = 0;
3942 3943 3944 3945
	struct set_phy_profile_resp *pPayload =
		(struct set_phy_profile_resp *)(piomb + 4);
	u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
	u32 status = le32_to_cpu(pPayload->status);
3946

3947
	tag = le32_to_cpu(pPayload->tag);
3948 3949 3950 3951 3952 3953
	page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
	if (status) {
		/* status is FAILED */
		PM8001_FAIL_DBG(pm8001_ha,
			pm8001_printk("PhyProfile command failed  with status "
			"0x%08X \n", status));
3954
		rc = -1;
3955 3956 3957 3958 3959
	} else {
		if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
			PM8001_FAIL_DBG(pm8001_ha,
				pm8001_printk("Invalid page code 0x%X\n",
					page_code));
3960
			rc = -1;
3961 3962
		}
	}
3963 3964
	pm8001_tag_free(pm8001_ha, tag);
	return rc;
3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061
}

/**
 * mpi_kek_management_resp - SPCv specific
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
			void *piomb)
{
	struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);

	u32 status = le32_to_cpu(pPayload->status);
	u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
	u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);

	PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
		"KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
		status, kidx_new_curr_ksop, err_qlfr));

	return 0;
}

/**
 * mpi_dek_management_resp - SPCv specific
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
			void *piomb)
{
	PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" pm80xx_addition_functionality\n"));

	return 0;
}

/**
 * ssp_coalesced_comp_resp - SPCv specific
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
			void *piomb)
{
	PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk(" pm80xx_addition_functionality\n"));

	return 0;
}

/**
 * process_one_iomb - process one outbound Queue memory block
 * @pm8001_ha: our hba card information
 * @piomb: IO message buffer
 */
static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
{
	__le32 pHeader = *(__le32 *)piomb;
	u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);

	switch (opc) {
	case OPC_OUB_ECHO:
		PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
		break;
	case OPC_OUB_HW_EVENT:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_HW_EVENT\n"));
		mpi_hw_event(pm8001_ha, piomb);
		break;
	case OPC_OUB_THERM_HW_EVENT:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
		mpi_thermal_hw_event(pm8001_ha, piomb);
		break;
	case OPC_OUB_SSP_COMP:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SSP_COMP\n"));
		mpi_ssp_completion(pm8001_ha, piomb);
		break;
	case OPC_OUB_SMP_COMP:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SMP_COMP\n"));
		mpi_smp_completion(pm8001_ha, piomb);
		break;
	case OPC_OUB_LOCAL_PHY_CNTRL:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
		pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
		break;
	case OPC_OUB_DEV_REGIST:
		PM8001_MSG_DBG(pm8001_ha,
		pm8001_printk("OPC_OUB_DEV_REGIST\n"));
		pm8001_mpi_reg_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_DEREG_DEV:
		PM8001_MSG_DBG(pm8001_ha,
M
Masanari Iida 已提交
4062
			pm8001_printk("unregister the device\n"));
4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225
		pm8001_mpi_dereg_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_GET_DEV_HANDLE:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
		break;
	case OPC_OUB_SATA_COMP:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SATA_COMP\n"));
		mpi_sata_completion(pm8001_ha, piomb);
		break;
	case OPC_OUB_SATA_EVENT:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SATA_EVENT\n"));
		mpi_sata_event(pm8001_ha, piomb);
		break;
	case OPC_OUB_SSP_EVENT:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SSP_EVENT\n"));
		mpi_ssp_event(pm8001_ha, piomb);
		break;
	case OPC_OUB_DEV_HANDLE_ARRIV:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
		/*This is for target*/
		break;
	case OPC_OUB_SSP_RECV_EVENT:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
		/*This is for target*/
		break;
	case OPC_OUB_FW_FLASH_UPDATE:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
		pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_GPIO_RESPONSE:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
		break;
	case OPC_OUB_GPIO_EVENT:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
		break;
	case OPC_OUB_GENERAL_EVENT:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
		pm8001_mpi_general_event(pm8001_ha, piomb);
		break;
	case OPC_OUB_SSP_ABORT_RSP:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
		pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_SATA_ABORT_RSP:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
		pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_SAS_DIAG_MODE_START_END:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
		break;
	case OPC_OUB_SAS_DIAG_EXECUTE:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
		break;
	case OPC_OUB_GET_TIME_STAMP:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
		break;
	case OPC_OUB_SAS_HW_EVENT_ACK:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
		break;
	case OPC_OUB_PORT_CONTROL:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
		break;
	case OPC_OUB_SMP_ABORT_RSP:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
		pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_GET_NVMD_DATA:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
		pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_SET_NVMD_DATA:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
		pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_DEVICE_HANDLE_REMOVAL:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
		break;
	case OPC_OUB_SET_DEVICE_STATE:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
		pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_GET_DEVICE_STATE:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
		break;
	case OPC_OUB_SET_DEV_INFO:
		PM8001_MSG_DBG(pm8001_ha,
			pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
		break;
	/* spcv specifc commands */
	case OPC_OUB_PHY_START_RESP:
		PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
			"OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
		mpi_phy_start_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_PHY_STOP_RESP:
		PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
			"OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
		mpi_phy_stop_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_SET_CONTROLLER_CONFIG:
		PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
			"OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
		mpi_set_controller_config_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_GET_CONTROLLER_CONFIG:
		PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
			"OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
		mpi_get_controller_config_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_GET_PHY_PROFILE:
		PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
			"OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
		mpi_get_phy_profile_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_FLASH_OP_EXT:
		PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
			"OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
		mpi_flash_op_ext_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_SET_PHY_PROFILE:
		PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
			"OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
		mpi_set_phy_profile_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_KEK_MANAGEMENT_RESP:
		PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
			"OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
		mpi_kek_management_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_DEK_MANAGEMENT_RESP:
		PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
			"OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
		mpi_dek_management_resp(pm8001_ha, piomb);
		break;
	case OPC_OUB_SSP_COALESCED_COMP_RESP:
		PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
			"OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
		ssp_coalesced_comp_resp(pm8001_ha, piomb);
		break;
	default:
4226
		PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
4227 4228 4229 4230 4231
			"Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
		break;
	}
}

4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271
static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
{
	PM8001_FAIL_DBG(pm8001_ha,
		pm8001_printk("MSGU_SCRATCH_PAD_0: 0x%x\n",
			pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
	PM8001_FAIL_DBG(pm8001_ha,
		pm8001_printk("MSGU_SCRATCH_PAD_1:0x%x\n",
			pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)));
	PM8001_FAIL_DBG(pm8001_ha,
		pm8001_printk("MSGU_SCRATCH_PAD_2: 0x%x\n",
			pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)));
	PM8001_FAIL_DBG(pm8001_ha,
		pm8001_printk("MSGU_SCRATCH_PAD_3: 0x%x\n",
			pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
	PM8001_FAIL_DBG(pm8001_ha,
		pm8001_printk("MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
			pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)));
	PM8001_FAIL_DBG(pm8001_ha,
		pm8001_printk("MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
			pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)));
	PM8001_FAIL_DBG(pm8001_ha,
		pm8001_printk("MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
			pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)));
	PM8001_FAIL_DBG(pm8001_ha,
		pm8001_printk("MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
			pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)));
	PM8001_FAIL_DBG(pm8001_ha,
		pm8001_printk("MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
			pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)));
	PM8001_FAIL_DBG(pm8001_ha,
		pm8001_printk("MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
			pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)));
	PM8001_FAIL_DBG(pm8001_ha,
		pm8001_printk("MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
			pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)));
	PM8001_FAIL_DBG(pm8001_ha,
		pm8001_printk("MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
			pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)));
}

4272 4273 4274 4275
static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
{
	struct outbound_queue_table *circularQ;
	void *pMsg1 = NULL;
4276
	u8 bc;
4277 4278
	u32 ret = MPI_IO_STATUS_FAIL;
	unsigned long flags;
4279
	u32 regval;
4280

4281
	if (vec == (pm8001_ha->max_q_num - 1)) {
4282 4283 4284 4285 4286 4287 4288 4289 4290 4291
		regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
		if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
					SCRATCH_PAD_MIPSALL_READY) {
			pm8001_ha->controller_fatal_error = true;
			PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
				"Firmware Fatal error! Regval:0x%x\n", regval));
			print_scratchpad_registers(pm8001_ha);
			return ret;
		}
	}
4292 4293 4294
	spin_lock_irqsave(&pm8001_ha->lock, flags);
	circularQ = &pm8001_ha->outbnd_q_tbl[vec];
	do {
4295 4296 4297 4298 4299 4300
		/* spurious interrupt during setup if kexec-ing and
		 * driver doing a doorbell access w/ the pre-kexec oq
		 * interrupt setup.
		 */
		if (!circularQ->pi_virt)
			break;
4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322
		ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
		if (MPI_IO_STATUS_SUCCESS == ret) {
			/* process the outbound message */
			process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
			/* free the message from the outbound circular buffer */
			pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
							circularQ, bc);
		}
		if (MPI_IO_STATUS_BUSY == ret) {
			/* Update the producer index from SPC */
			circularQ->producer_index =
				cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
			if (le32_to_cpu(circularQ->producer_index) ==
				circularQ->consumer_idx)
				/* OQ is empty */
				break;
		}
	} while (1);
	spin_unlock_irqrestore(&pm8001_ha->lock, flags);
	return ret;
}

4323
/* DMA_... to our direction translation. */
4324
static const u8 data_dir_flags[] = {
4325 4326 4327 4328
	[DMA_BIDIRECTIONAL]	= DATA_DIR_BYRECIPIENT,	/* UNSPECIFIED */
	[DMA_TO_DEVICE]		= DATA_DIR_OUT,		/* OUTBOUND */
	[DMA_FROM_DEVICE]	= DATA_DIR_IN,		/* INBOUND */
	[DMA_NONE]		= DATA_DIR_NONE,	/* NO TRANSFER */
4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369
};

static void build_smp_cmd(u32 deviceID, __le32 hTag,
			struct smp_req *psmp_cmd, int mode, int length)
{
	psmp_cmd->tag = hTag;
	psmp_cmd->device_id = cpu_to_le32(deviceID);
	if (mode == SMP_DIRECT) {
		length = length - 4; /* subtract crc */
		psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
	} else {
		psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
	}
}

/**
 * pm8001_chip_smp_req - send a SMP task to FW
 * @pm8001_ha: our hba card information.
 * @ccb: the ccb information this request used.
 */
static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
	struct pm8001_ccb_info *ccb)
{
	int elem, rc;
	struct sas_task *task = ccb->task;
	struct domain_device *dev = task->dev;
	struct pm8001_device *pm8001_dev = dev->lldd_dev;
	struct scatterlist *sg_req, *sg_resp;
	u32 req_len, resp_len;
	struct smp_req smp_cmd;
	u32 opc;
	struct inbound_queue_table *circularQ;
	char *preq_dma_addr = NULL;
	__le64 tmp_addr;
	u32 i, length;

	memset(&smp_cmd, 0, sizeof(smp_cmd));
	/*
	 * DMA-map SMP request, response buffers
	 */
	sg_req = &task->smp_task.smp_req;
4370
	elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4371 4372 4373 4374 4375
	if (!elem)
		return -ENOMEM;
	req_len = sg_dma_len(sg_req);

	sg_resp = &task->smp_task.smp_resp;
4376
	elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414
	if (!elem) {
		rc = -ENOMEM;
		goto err_out;
	}
	resp_len = sg_dma_len(sg_resp);
	/* must be in dwords */
	if ((req_len & 0x3) || (resp_len & 0x3)) {
		rc = -EINVAL;
		goto err_out_2;
	}

	opc = OPC_INB_SMP_REQUEST;
	circularQ = &pm8001_ha->inbnd_q_tbl[0];
	smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);

	length = sg_req->length;
	PM8001_IO_DBG(pm8001_ha,
		pm8001_printk("SMP Frame Length %d\n", sg_req->length));
	if (!(length - 8))
		pm8001_ha->smp_exp_mode = SMP_DIRECT;
	else
		pm8001_ha->smp_exp_mode = SMP_INDIRECT;


	tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
	preq_dma_addr = (char *)phys_to_virt(tmp_addr);

	/* INDIRECT MODE command settings. Use DMA */
	if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
		/* for SPCv indirect mode. Place the top 4 bytes of
		 * SMP Request header here. */
		for (i = 0; i < 4; i++)
			smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
		/* exclude top 4 bytes for SMP req header */
		smp_cmd.long_smp_req.long_req_addr =
			cpu_to_le64((u64)sg_dma_address
4415
				(&task->smp_task.smp_req) + 4);
4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458
		/* exclude 4 bytes for SMP req header and CRC */
		smp_cmd.long_smp_req.long_req_size =
			cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
		smp_cmd.long_smp_req.long_resp_addr =
				cpu_to_le64((u64)sg_dma_address
					(&task->smp_task.smp_resp));
		smp_cmd.long_smp_req.long_resp_size =
				cpu_to_le32((u32)sg_dma_len
					(&task->smp_task.smp_resp)-4);
	} else { /* DIRECT MODE */
		smp_cmd.long_smp_req.long_req_addr =
			cpu_to_le64((u64)sg_dma_address
					(&task->smp_task.smp_req));
		smp_cmd.long_smp_req.long_req_size =
			cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
		smp_cmd.long_smp_req.long_resp_addr =
			cpu_to_le64((u64)sg_dma_address
				(&task->smp_task.smp_resp));
		smp_cmd.long_smp_req.long_resp_size =
			cpu_to_le32
			((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
	}
	if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
		PM8001_IO_DBG(pm8001_ha,
			pm8001_printk("SMP REQUEST DIRECT MODE\n"));
		for (i = 0; i < length; i++)
			if (i < 16) {
				smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
				PM8001_IO_DBG(pm8001_ha, pm8001_printk(
					"Byte[%d]:%x (DMA data:%x)\n",
					i, smp_cmd.smp_req16[i],
					*(preq_dma_addr)));
			} else {
				smp_cmd.smp_req[i] = *(preq_dma_addr+i);
				PM8001_IO_DBG(pm8001_ha, pm8001_printk(
					"Byte[%d]:%x (DMA data:%x)\n",
					i, smp_cmd.smp_req[i],
					*(preq_dma_addr)));
			}
	}

	build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
				&smp_cmd, pm8001_ha->smp_exp_mode, length);
4459 4460
	rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd,
			sizeof(smp_cmd), 0);
T
Tomas Henzl 已提交
4461 4462
	if (rc)
		goto err_out_2;
4463 4464 4465 4466
	return 0;

err_out_2:
	dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4467
			DMA_FROM_DEVICE);
4468 4469
err_out:
	dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4470
			DMA_TO_DEVICE);
4471 4472 4473 4474 4475
	return rc;
}

static int check_enc_sas_cmd(struct sas_task *task)
{
4476 4477 4478
	u8 cmd = task->ssp_task.cmd->cmnd[0];

	if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520
		return 1;
	else
		return 0;
}

static int check_enc_sat_cmd(struct sas_task *task)
{
	int ret = 0;
	switch (task->ata_task.fis.command) {
	case ATA_CMD_FPDMA_READ:
	case ATA_CMD_READ_EXT:
	case ATA_CMD_READ:
	case ATA_CMD_FPDMA_WRITE:
	case ATA_CMD_WRITE_EXT:
	case ATA_CMD_WRITE:
	case ATA_CMD_PIO_READ:
	case ATA_CMD_PIO_READ_EXT:
	case ATA_CMD_PIO_WRITE:
	case ATA_CMD_PIO_WRITE_EXT:
		ret = 1;
		break;
	default:
		ret = 0;
		break;
	}
	return ret;
}

/**
 * pm80xx_chip_ssp_io_req - send a SSP task to FW
 * @pm8001_ha: our hba card information.
 * @ccb: the ccb information this request used.
 */
static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
	struct pm8001_ccb_info *ccb)
{
	struct sas_task *task = ccb->task;
	struct domain_device *dev = task->dev;
	struct pm8001_device *pm8001_dev = dev->lldd_dev;
	struct ssp_ini_io_start_req ssp_cmd;
	u32 tag = ccb->ccb_tag;
	int ret;
4521 4522
	u64 phys_addr, start_addr, end_addr;
	u32 end_addr_high, end_addr_low;
4523
	struct inbound_queue_table *circularQ;
4524
	u32 q_index, cpu_id;
4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540
	u32 opc = OPC_INB_SSPINIIOSTART;
	memset(&ssp_cmd, 0, sizeof(ssp_cmd));
	memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
	/* data address domain added for spcv; set to 0 by host,
	 * used internally by controller
	 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
	 */
	ssp_cmd.dad_dir_m_tlr =
		cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
	ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
	ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
	ssp_cmd.tag = cpu_to_le32(tag);
	if (task->ssp_task.enable_first_burst)
		ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
	ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
	ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4541 4542
	memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
		       task->ssp_task.cmd->cmd_len);
4543 4544
	cpu_id = smp_processor_id();
	q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4545
	circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4546 4547 4548 4549 4550 4551

	/* Check if encryption is set */
	if (pm8001_ha->chip->encrypt &&
		!(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4552
			task->ssp_task.cmd->cmnd[0]));
4553 4554 4555 4556 4557 4558 4559 4560 4561
		opc = OPC_INB_SSP_INI_DIF_ENC_IO;
		/* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
		ssp_cmd.dad_dir_m_tlr =	cpu_to_le32
			((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);

		/* fill in PRD (scatter/gather) table, if any */
		if (task->num_scatter > 1) {
			pm8001_chip_make_sg(task->scatter,
						ccb->n_elem, ccb->buf_prd);
4562
			phys_addr = ccb->ccb_dma_handle;
4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575
			ssp_cmd.enc_addr_low =
				cpu_to_le32(lower_32_bits(phys_addr));
			ssp_cmd.enc_addr_high =
				cpu_to_le32(upper_32_bits(phys_addr));
			ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
		} else if (task->num_scatter == 1) {
			u64 dma_addr = sg_dma_address(task->scatter);
			ssp_cmd.enc_addr_low =
				cpu_to_le32(lower_32_bits(dma_addr));
			ssp_cmd.enc_addr_high =
				cpu_to_le32(upper_32_bits(dma_addr));
			ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
			ssp_cmd.enc_esgl = 0;
4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590
			/* Check 4G Boundary */
			start_addr = cpu_to_le64(dma_addr);
			end_addr = (start_addr + ssp_cmd.enc_len) - 1;
			end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
			end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
			if (end_addr_high != ssp_cmd.enc_addr_high) {
				PM8001_FAIL_DBG(pm8001_ha,
					pm8001_printk("The sg list address "
					"start_addr=0x%016llx data_len=0x%x "
					"end_addr_high=0x%08x end_addr_low="
					"0x%08x has crossed 4G boundary\n",
						start_addr, ssp_cmd.enc_len,
						end_addr_high, end_addr_low));
				pm8001_chip_make_sg(task->scatter, 1,
					ccb->buf_prd);
4591
				phys_addr = ccb->ccb_dma_handle;
4592 4593 4594 4595 4596 4597
				ssp_cmd.enc_addr_low =
					cpu_to_le32(lower_32_bits(phys_addr));
				ssp_cmd.enc_addr_high =
					cpu_to_le32(upper_32_bits(phys_addr));
				ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
			}
4598 4599 4600 4601 4602 4603 4604 4605 4606
		} else if (task->num_scatter == 0) {
			ssp_cmd.enc_addr_low = 0;
			ssp_cmd.enc_addr_high = 0;
			ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
			ssp_cmd.enc_esgl = 0;
		}
		/* XTS mode. All other fields are 0 */
		ssp_cmd.key_cmode = 0x6 << 4;
		/* set tweak values. Should be the start lba */
4607 4608 4609 4610
		ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
						(task->ssp_task.cmd->cmnd[3] << 16) |
						(task->ssp_task.cmd->cmnd[4] << 8) |
						(task->ssp_task.cmd->cmnd[5]));
4611 4612 4613
	} else {
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"Sending Normal SAS command 0x%x inb q %x\n",
4614
			task->ssp_task.cmd->cmnd[0], q_index));
4615 4616 4617 4618
		/* fill in PRD (scatter/gather) table, if any */
		if (task->num_scatter > 1) {
			pm8001_chip_make_sg(task->scatter, ccb->n_elem,
					ccb->buf_prd);
4619
			phys_addr = ccb->ccb_dma_handle;
4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631
			ssp_cmd.addr_low =
				cpu_to_le32(lower_32_bits(phys_addr));
			ssp_cmd.addr_high =
				cpu_to_le32(upper_32_bits(phys_addr));
			ssp_cmd.esgl = cpu_to_le32(1<<31);
		} else if (task->num_scatter == 1) {
			u64 dma_addr = sg_dma_address(task->scatter);
			ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
			ssp_cmd.addr_high =
				cpu_to_le32(upper_32_bits(dma_addr));
			ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
			ssp_cmd.esgl = 0;
4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646
			/* Check 4G Boundary */
			start_addr = cpu_to_le64(dma_addr);
			end_addr = (start_addr + ssp_cmd.len) - 1;
			end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
			end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
			if (end_addr_high != ssp_cmd.addr_high) {
				PM8001_FAIL_DBG(pm8001_ha,
					pm8001_printk("The sg list address "
					"start_addr=0x%016llx data_len=0x%x "
					"end_addr_high=0x%08x end_addr_low="
					"0x%08x has crossed 4G boundary\n",
						 start_addr, ssp_cmd.len,
						 end_addr_high, end_addr_low));
				pm8001_chip_make_sg(task->scatter, 1,
					ccb->buf_prd);
4647
				phys_addr = ccb->ccb_dma_handle;
4648 4649 4650 4651 4652 4653
				ssp_cmd.addr_low =
					cpu_to_le32(lower_32_bits(phys_addr));
				ssp_cmd.addr_high =
					cpu_to_le32(upper_32_bits(phys_addr));
				ssp_cmd.esgl = cpu_to_le32(1<<31);
			}
4654 4655 4656 4657 4658 4659 4660
		} else if (task->num_scatter == 0) {
			ssp_cmd.addr_low = 0;
			ssp_cmd.addr_high = 0;
			ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
			ssp_cmd.esgl = 0;
		}
	}
4661
	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4662
			&ssp_cmd, sizeof(ssp_cmd), q_index);
4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673
	return ret;
}

static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
	struct pm8001_ccb_info *ccb)
{
	struct sas_task *task = ccb->task;
	struct domain_device *dev = task->dev;
	struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
	u32 tag = ccb->ccb_tag;
	int ret;
4674
	u32 q_index, cpu_id;
4675 4676
	struct sata_start_req sata_cmd;
	u32 hdr_tag, ncg_tag = 0;
4677 4678
	u64 phys_addr, start_addr, end_addr;
	u32 end_addr_high, end_addr_low;
4679 4680 4681
	u32 ATAP = 0x0;
	u32 dir;
	struct inbound_queue_table *circularQ;
4682
	unsigned long flags;
4683 4684
	u32 opc = OPC_INB_SATA_HOST_OPSTART;
	memset(&sata_cmd, 0, sizeof(sata_cmd));
4685 4686
	cpu_id = smp_processor_id();
	q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4687
	circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4688

4689
	if (task->data_dir == DMA_NONE) {
4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700
		ATAP = 0x04; /* no data*/
		PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
	} else if (likely(!task->ata_task.device_control_reg_update)) {
		if (task->ata_task.dma_xfer) {
			ATAP = 0x06; /* DMA */
			PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
		} else {
			ATAP = 0x05; /* PIO*/
			PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
		}
		if (task->ata_task.use_ncq &&
H
Hannes Reinecke 已提交
4701
		    dev->sata_dev.class != ATA_DEV_ATAPI) {
4702 4703 4704 4705
			ATAP = 0x07; /* FPDMA */
			PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
		}
	}
4706 4707
	if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
		task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4708
		ncg_tag = hdr_tag;
4709
	}
4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736
	dir = data_dir_flags[task->data_dir] << 8;
	sata_cmd.tag = cpu_to_le32(tag);
	sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
	sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);

	sata_cmd.sata_fis = task->ata_task.fis;
	if (likely(!task->ata_task.device_control_reg_update))
		sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
	sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */

	/* Check if encryption is set */
	if (pm8001_ha->chip->encrypt &&
		!(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
			sata_cmd.sata_fis.command));
		opc = OPC_INB_SATA_DIF_ENC_IO;

		/* set encryption bit */
		sata_cmd.ncqtag_atap_dir_m_dad =
			cpu_to_le32(((ncg_tag & 0xff)<<16)|
				((ATAP & 0x3f) << 10) | 0x20 | dir);
							/* dad (bit 0-1) is 0 */
		/* fill in PRD (scatter/gather) table, if any */
		if (task->num_scatter > 1) {
			pm8001_chip_make_sg(task->scatter,
						ccb->n_elem, ccb->buf_prd);
4737
			phys_addr = ccb->ccb_dma_handle;
4738 4739 4740 4741 4742 4743 4744 4745 4746
			sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
			sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
			sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
		} else if (task->num_scatter == 1) {
			u64 dma_addr = sg_dma_address(task->scatter);
			sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
			sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
			sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
			sata_cmd.enc_esgl = 0;
4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761
			/* Check 4G Boundary */
			start_addr = cpu_to_le64(dma_addr);
			end_addr = (start_addr + sata_cmd.enc_len) - 1;
			end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
			end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
			if (end_addr_high != sata_cmd.enc_addr_high) {
				PM8001_FAIL_DBG(pm8001_ha,
					pm8001_printk("The sg list address "
					"start_addr=0x%016llx data_len=0x%x "
					"end_addr_high=0x%08x end_addr_low"
					"=0x%08x has crossed 4G boundary\n",
						start_addr, sata_cmd.enc_len,
						end_addr_high, end_addr_low));
				pm8001_chip_make_sg(task->scatter, 1,
					ccb->buf_prd);
4762
				phys_addr = ccb->ccb_dma_handle;
4763 4764 4765 4766 4767 4768 4769
				sata_cmd.enc_addr_low =
					lower_32_bits(phys_addr);
				sata_cmd.enc_addr_high =
					upper_32_bits(phys_addr);
				sata_cmd.enc_esgl =
					cpu_to_le32(1 << 31);
			}
4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789
		} else if (task->num_scatter == 0) {
			sata_cmd.enc_addr_low = 0;
			sata_cmd.enc_addr_high = 0;
			sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
			sata_cmd.enc_esgl = 0;
		}
		/* XTS mode. All other fields are 0 */
		sata_cmd.key_index_mode = 0x6 << 4;
		/* set tweak values. Should be the start lba */
		sata_cmd.twk_val0 =
			cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
					(sata_cmd.sata_fis.lbah << 16) |
					(sata_cmd.sata_fis.lbam << 8) |
					(sata_cmd.sata_fis.lbal));
		sata_cmd.twk_val1 =
			cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
					 (sata_cmd.sata_fis.lbam_exp));
	} else {
		PM8001_IO_DBG(pm8001_ha, pm8001_printk(
			"Sending Normal SATA command 0x%x inb %x\n",
4790
			sata_cmd.sata_fis.command, q_index));
4791 4792 4793 4794 4795 4796 4797 4798 4799
		/* dad (bit 0-1) is 0 */
		sata_cmd.ncqtag_atap_dir_m_dad =
			cpu_to_le32(((ncg_tag & 0xff)<<16) |
					((ATAP & 0x3f) << 10) | dir);

		/* fill in PRD (scatter/gather) table, if any */
		if (task->num_scatter > 1) {
			pm8001_chip_make_sg(task->scatter,
					ccb->n_elem, ccb->buf_prd);
4800
			phys_addr = ccb->ccb_dma_handle;
4801 4802 4803 4804 4805 4806 4807 4808 4809
			sata_cmd.addr_low = lower_32_bits(phys_addr);
			sata_cmd.addr_high = upper_32_bits(phys_addr);
			sata_cmd.esgl = cpu_to_le32(1 << 31);
		} else if (task->num_scatter == 1) {
			u64 dma_addr = sg_dma_address(task->scatter);
			sata_cmd.addr_low = lower_32_bits(dma_addr);
			sata_cmd.addr_high = upper_32_bits(dma_addr);
			sata_cmd.len = cpu_to_le32(task->total_xfer_len);
			sata_cmd.esgl = 0;
4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824
			/* Check 4G Boundary */
			start_addr = cpu_to_le64(dma_addr);
			end_addr = (start_addr + sata_cmd.len) - 1;
			end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
			end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
			if (end_addr_high != sata_cmd.addr_high) {
				PM8001_FAIL_DBG(pm8001_ha,
					pm8001_printk("The sg list address "
					"start_addr=0x%016llx data_len=0x%x"
					"end_addr_high=0x%08x end_addr_low="
					"0x%08x has crossed 4G boundary\n",
						start_addr, sata_cmd.len,
						end_addr_high, end_addr_low));
				pm8001_chip_make_sg(task->scatter, 1,
					ccb->buf_prd);
4825
				phys_addr = ccb->ccb_dma_handle;
4826 4827 4828 4829 4830 4831
				sata_cmd.addr_low =
					lower_32_bits(phys_addr);
				sata_cmd.addr_high =
					upper_32_bits(phys_addr);
				sata_cmd.esgl = cpu_to_le32(1 << 31);
			}
4832 4833 4834 4835 4836 4837
		} else if (task->num_scatter == 0) {
			sata_cmd.addr_low = 0;
			sata_cmd.addr_high = 0;
			sata_cmd.len = cpu_to_le32(task->total_xfer_len);
			sata_cmd.esgl = 0;
		}
4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858
		/* scsi cdb */
		sata_cmd.atapi_scsi_cdb[0] =
			cpu_to_le32(((task->ata_task.atapi_packet[0]) |
			(task->ata_task.atapi_packet[1] << 8) |
			(task->ata_task.atapi_packet[2] << 16) |
			(task->ata_task.atapi_packet[3] << 24)));
		sata_cmd.atapi_scsi_cdb[1] =
			cpu_to_le32(((task->ata_task.atapi_packet[4]) |
			(task->ata_task.atapi_packet[5] << 8) |
			(task->ata_task.atapi_packet[6] << 16) |
			(task->ata_task.atapi_packet[7] << 24)));
		sata_cmd.atapi_scsi_cdb[2] =
			cpu_to_le32(((task->ata_task.atapi_packet[8]) |
			(task->ata_task.atapi_packet[9] << 8) |
			(task->ata_task.atapi_packet[10] << 16) |
			(task->ata_task.atapi_packet[11] << 24)));
		sata_cmd.atapi_scsi_cdb[3] =
			cpu_to_le32(((task->ata_task.atapi_packet[12]) |
			(task->ata_task.atapi_packet[13] << 8) |
			(task->ata_task.atapi_packet[14] << 16) |
			(task->ata_task.atapi_packet[15] << 24)));
4859
	}
4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886

	/* Check for read log for failed drive and return */
	if (sata_cmd.sata_fis.command == 0x2f) {
		if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
			(pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
			(pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
			struct task_status_struct *ts;

			pm8001_ha_dev->id &= 0xDFFFFFFF;
			ts = &task->task_status;

			spin_lock_irqsave(&task->task_state_lock, flags);
			ts->resp = SAS_TASK_COMPLETE;
			ts->stat = SAM_STAT_GOOD;
			task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
			task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
			task->task_state_flags |= SAS_TASK_STATE_DONE;
			if (unlikely((task->task_state_flags &
					SAS_TASK_STATE_ABORTED))) {
				spin_unlock_irqrestore(&task->task_state_lock,
							flags);
				PM8001_FAIL_DBG(pm8001_ha,
					pm8001_printk("task 0x%p resp 0x%x "
					" stat 0x%x but aborted by upper layer "
					"\n", task, ts->resp, ts->stat));
				pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
				return 0;
S
Suresh Thiagarajan 已提交
4887
			} else {
4888 4889
				spin_unlock_irqrestore(&task->task_state_lock,
							flags);
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Suresh Thiagarajan 已提交
4890 4891
				pm8001_ccb_task_free_done(pm8001_ha, task,
								ccb, tag);
V
Viswas G 已提交
4892
				atomic_dec(&pm8001_ha_dev->running_req);
4893 4894 4895 4896
				return 0;
			}
		}
	}
4897
	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4898
			&sata_cmd, sizeof(sata_cmd), q_index);
4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920
	return ret;
}

/**
 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
 * @pm8001_ha: our hba card information.
 * @phy_id: the phy id which we wanted to start up.
 */
static int
pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
{
	struct phy_start_req payload;
	struct inbound_queue_table *circularQ;
	int ret;
	u32 tag = 0x01;
	u32 opcode = OPC_INB_PHYSTART;
	circularQ = &pm8001_ha->inbnd_q_tbl[0];
	memset(&payload, 0, sizeof(payload));
	payload.tag = cpu_to_le32(tag);

	PM8001_INIT_DBG(pm8001_ha,
		pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4921

4922 4923
	payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
			LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4924 4925 4926 4927 4928 4929 4930 4931 4932
	/* SSC Disable and SAS Analog ST configuration */
	/**
	payload.ase_sh_lm_slr_phyid =
		cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
		LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
		phy_id);
	Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
	**/

4933
	payload.sas_identify.dev_type = SAS_END_DEVICE;
4934 4935
	payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
	memcpy(payload.sas_identify.sas_addr,
4936
	  &pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4937
	payload.sas_identify.phy_id = phy_id;
4938 4939
	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
			sizeof(payload), 0);
4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959
	return ret;
}

/**
 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
 * @pm8001_ha: our hba card information.
 * @phy_id: the phy id which we wanted to start up.
 */
static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
	u8 phy_id)
{
	struct phy_stop_req payload;
	struct inbound_queue_table *circularQ;
	int ret;
	u32 tag = 0x01;
	u32 opcode = OPC_INB_PHYSTOP;
	circularQ = &pm8001_ha->inbnd_q_tbl[0];
	memset(&payload, 0, sizeof(payload));
	payload.tag = cpu_to_le32(tag);
	payload.phy_id = cpu_to_le32(phy_id);
4960 4961
	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
			sizeof(payload), 0);
4962 4963 4964
	return ret;
}

4965
/*
4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996
 * see comments on pm8001_mpi_reg_resp.
 */
static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
	struct pm8001_device *pm8001_dev, u32 flag)
{
	struct reg_dev_req payload;
	u32	opc;
	u32 stp_sspsmp_sata = 0x4;
	struct inbound_queue_table *circularQ;
	u32 linkrate, phy_id;
	int rc, tag = 0xdeadbeef;
	struct pm8001_ccb_info *ccb;
	u8 retryFlag = 0x1;
	u16 firstBurstSize = 0;
	u16 ITNT = 2000;
	struct domain_device *dev = pm8001_dev->sas_device;
	struct domain_device *parent_dev = dev->parent;
	circularQ = &pm8001_ha->inbnd_q_tbl[0];

	memset(&payload, 0, sizeof(payload));
	rc = pm8001_tag_alloc(pm8001_ha, &tag);
	if (rc)
		return rc;
	ccb = &pm8001_ha->ccb_info[tag];
	ccb->device = pm8001_dev;
	ccb->ccb_tag = tag;
	payload.tag = cpu_to_le32(tag);

	if (flag == 1) {
		stp_sspsmp_sata = 0x02; /*direct attached sata */
	} else {
4997
		if (pm8001_dev->dev_type == SAS_SATA_DEV)
4998
			stp_sspsmp_sata = 0x00; /* stp*/
4999 5000 5001
		else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
			pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
			pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
5002 5003
			stp_sspsmp_sata = 0x01; /*ssp or smp*/
	}
5004
	if (parent_dev && dev_is_expander(parent_dev->dev_type))
5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026
		phy_id = parent_dev->ex_dev.ex_phy->phy_id;
	else
		phy_id = pm8001_dev->attached_phy;

	opc = OPC_INB_REG_DEV;

	linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
			pm8001_dev->sas_device->linkrate : dev->port->linkrate;

	payload.phyid_portid =
		cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
		((phy_id & 0xFF) << 8));

	payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
		((linkrate & 0x0F) << 24) |
		((stp_sspsmp_sata & 0x03) << 28));
	payload.firstburstsize_ITNexustimeout =
		cpu_to_le32(ITNT | (firstBurstSize * 0x10000));

	memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
		SAS_ADDR_SIZE);

5027 5028
	rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
			sizeof(payload), 0);
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Tomas Henzl 已提交
5029 5030
	if (rc)
		pm8001_tag_free(pm8001_ha, tag);
5031 5032 5033 5034 5035 5036 5037

	return rc;
}

/**
 * pm80xx_chip_phy_ctl_req - support the local phy operation
 * @pm8001_ha: our hba card information.
5038 5039
 * @phyId: the phy id which we wanted to operate
 * @phy_op: phy operation to request
5040 5041 5042 5043
 */
static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
	u32 phyId, u32 phy_op)
{
5044 5045
	u32 tag;
	int rc;
5046 5047 5048 5049
	struct local_phy_ctl_req payload;
	struct inbound_queue_table *circularQ;
	u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
	memset(&payload, 0, sizeof(payload));
5050 5051 5052
	rc = pm8001_tag_alloc(pm8001_ha, &tag);
	if (rc)
		return rc;
5053
	circularQ = &pm8001_ha->inbnd_q_tbl[0];
5054
	payload.tag = cpu_to_le32(tag);
5055 5056
	payload.phyop_phyid =
		cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
5057 5058
	return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
			sizeof(payload), 0);
5059 5060
}

5061
static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
5062 5063 5064
{
#ifdef PM8001_USE_MSIX
	return 1;
5065 5066 5067
#else
	u32 value;

5068 5069 5070 5071
	value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
	if (value)
		return 1;
	return 0;
5072
#endif
5073 5074 5075 5076 5077
}

/**
 * pm8001_chip_isr - PM8001 isr handler.
 * @pm8001_ha: our hba card information.
5078
 * @vec: irq number.
5079 5080 5081 5082 5083
 */
static irqreturn_t
pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
{
	pm80xx_chip_interrupt_disable(pm8001_ha, vec);
5084 5085 5086
	PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
		"irq vec %d, ODMR:0x%x\n",
		vec, pm8001_cr32(pm8001_ha, 0, 0x30)));
5087 5088 5089 5090 5091
	process_oq(pm8001_ha, vec);
	pm80xx_chip_interrupt_enable(pm8001_ha, vec);
	return IRQ_HANDLED;
}

5092 5093 5094
static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
				    u32 operation, u32 phyid,
				    u32 length, u32 *buf)
5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115
{
	u32 tag , i, j = 0;
	int rc;
	struct set_phy_profile_req payload;
	struct inbound_queue_table *circularQ;
	u32 opc = OPC_INB_SET_PHY_PROFILE;

	memset(&payload, 0, sizeof(payload));
	rc = pm8001_tag_alloc(pm8001_ha, &tag);
	if (rc)
		PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
	circularQ = &pm8001_ha->inbnd_q_tbl[0];
	payload.tag = cpu_to_le32(tag);
	payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid  & 0xFF));
	PM8001_INIT_DBG(pm8001_ha,
		pm8001_printk(" phy profile command for phy %x ,length is %d\n",
			payload.ppc_phyid, length));
	for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
		payload.reserved[j] =  cpu_to_le32(*((u32 *)buf + i));
		j++;
	}
5116 5117
	rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
			sizeof(payload), 0);
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Tomas Henzl 已提交
5118 5119
	if (rc)
		pm8001_tag_free(pm8001_ha, tag);
5120 5121 5122 5123 5124
}

void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
	u32 length, u8 *buf)
{
5125
	u32 i;
5126 5127 5128 5129 5130 5131 5132 5133

	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
		mpi_set_phy_profile_req(pm8001_ha,
			SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
		length = length + PHY_DWORD_LENGTH;
	}
	PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
}
5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145 5146 5147 5148 5149 5150 5151 5152 5153 5154 5155 5156 5157 5158

void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
		u32 phy, u32 length, u32 *buf)
{
	u32 tag, opc;
	int rc, i;
	struct set_phy_profile_req payload;
	struct inbound_queue_table *circularQ;

	memset(&payload, 0, sizeof(payload));

	rc = pm8001_tag_alloc(pm8001_ha, &tag);
	if (rc)
		PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag"));

	circularQ = &pm8001_ha->inbnd_q_tbl[0];
	opc = OPC_INB_SET_PHY_PROFILE;

	payload.tag = cpu_to_le32(tag);
	payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
				| (phy & 0xFF));

	for (i = 0; i < length; i++)
		payload.reserved[i] = cpu_to_le32(*(buf + i));

5159 5160
	rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
			sizeof(payload), 0);
5161 5162 5163 5164 5165 5166
	if (rc)
		pm8001_tag_free(pm8001_ha, tag);

	PM8001_INIT_DBG(pm8001_ha,
		pm8001_printk("PHY %d settings applied", phy));
}
5167 5168 5169 5170 5171 5172 5173
const struct pm8001_dispatch pm8001_80xx_dispatch = {
	.name			= "pmc80xx",
	.chip_init		= pm80xx_chip_init,
	.chip_soft_rst		= pm80xx_chip_soft_rst,
	.chip_rst		= pm80xx_hw_chip_rst,
	.chip_iounmap		= pm8001_chip_iounmap,
	.isr			= pm80xx_chip_isr,
5174
	.is_our_interrupt	= pm80xx_chip_is_our_interrupt,
5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193
	.isr_process_oq		= process_oq,
	.interrupt_enable	= pm80xx_chip_interrupt_enable,
	.interrupt_disable	= pm80xx_chip_interrupt_disable,
	.make_prd		= pm8001_chip_make_sg,
	.smp_req		= pm80xx_chip_smp_req,
	.ssp_io_req		= pm80xx_chip_ssp_io_req,
	.sata_req		= pm80xx_chip_sata_req,
	.phy_start_req		= pm80xx_chip_phy_start_req,
	.phy_stop_req		= pm80xx_chip_phy_stop_req,
	.reg_dev_req		= pm80xx_chip_reg_dev_req,
	.dereg_dev_req		= pm8001_chip_dereg_dev_req,
	.phy_ctl_req		= pm80xx_chip_phy_ctl_req,
	.task_abort		= pm8001_chip_abort_task,
	.ssp_tm_req		= pm8001_chip_ssp_tm_req,
	.get_nvmd_req		= pm8001_chip_get_nvmd_req,
	.set_nvmd_req		= pm8001_chip_set_nvmd_req,
	.fw_flash_update_req	= pm8001_chip_fw_flash_update_req,
	.set_dev_state_req	= pm8001_chip_set_dev_state_req,
};