omap4-common.c 5.9 KB
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/*
 * OMAP4 specific common source file.
 *
 * Copyright (C) 2010 Texas Instruments, Inc.
 * Author:
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 *
 * This program is free software,you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/platform_device.h>
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#include <linux/memblock.h>
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#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/export.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip/irq-crossbar.h>
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#include <linux/of_address.h>
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#include <linux/reboot.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/map.h>
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#include <asm/memblock.h>
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#include <asm/smp_twd.h>
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#include "omap-wakeupgen.h"
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#include "soc.h"
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#include "iomap.h"
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#include "common.h"
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#include "mmc.h"
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#include "prminst44xx.h"
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#include "prcm_mpu44xx.h"
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#include "omap4-sar-layout.h"
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#include "omap-secure.h"
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#include "sram.h"
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#ifdef CONFIG_CACHE_L2X0
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static void __iomem *l2cache_base;
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#endif

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static void __iomem *sar_ram_base;
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static void __iomem *gic_dist_base_addr;
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static void __iomem *twd_base;

#define IRQ_LOCALTIMER		29
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#ifdef CONFIG_OMAP4_ERRATA_I688
/* Used to implement memory barrier on DRAM path */
#define OMAP4_DRAM_BARRIER_VA			0xfe600000

void __iomem *dram_sync, *sram_sync;

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static phys_addr_t paddr;
static u32 size;

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void omap_bus_sync(void)
{
	if (dram_sync && sram_sync) {
		writel_relaxed(readl_relaxed(dram_sync), dram_sync);
		writel_relaxed(readl_relaxed(sram_sync), sram_sync);
		isb();
	}
}
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EXPORT_SYMBOL(omap_bus_sync);
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/* Steal one page physical memory for barrier implementation */
int __init omap_barrier_reserve_memblock(void)
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{

	size = ALIGN(PAGE_SIZE, SZ_1M);
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	paddr = arm_memblock_steal(size, SZ_1M);

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	return 0;
}

void __init omap_barriers_init(void)
{
	struct map_desc dram_io_desc[1];

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	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
	dram_io_desc[0].length = size;
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	dram_io_desc[0].type = MT_MEMORY_RW_SO;
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	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	sram_sync = (void __iomem *) OMAP4_SRAM_VA;

	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
		(long long) paddr, dram_io_desc[0].virtual);

}
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#else
void __init omap_barriers_init(void)
{}
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#endif

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void gic_dist_disable(void)
{
	if (gic_dist_base_addr)
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		writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
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}

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void gic_dist_enable(void)
{
	if (gic_dist_base_addr)
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		writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
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}

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bool gic_dist_disabled(void)
{
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	return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
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}

void gic_timer_retrigger(void)
{
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	u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
	u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
	u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
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	if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
		/*
		 * The local timer interrupt got lost while the distributor was
		 * disabled.  Ack the pending interrupt, and retrigger it.
		 */
		pr_warn("%s: lost localtimer interrupt\n", __func__);
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		writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
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		if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
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			writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
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			twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
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			writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
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		}
	}
}

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#ifdef CONFIG_CACHE_L2X0
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void __iomem *omap4_get_l2cache_base(void)
{
	return l2cache_base;
}

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static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
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{
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	unsigned smc_op;
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	switch (reg) {
	case L2X0_CTRL:
		smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
		break;

	case L2X0_AUX_CTRL:
		smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
		break;

	case L2X0_DEBUG_CTRL:
		smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
		break;

	case L310_PREFETCH_CTRL:
		smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
		break;

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	case L310_POWER_CTRL:
		pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
		return;

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	default:
		WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
		return;
	}

	omap_smc1(smc_op, val);
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}

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int __init omap_l2_cache_init(void)
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{
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	u32 aux_ctrl;
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	/* Static mapping, never released */
	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
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	if (WARN_ON(!l2cache_base))
		return -ENOMEM;
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	/* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
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	aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE |
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		   L310_AUX_CTRL_DATA_PREFETCH |
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		   L310_AUX_CTRL_INSTR_PREFETCH;
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	outer_cache.write_sec = omap4_l2c310_write_sec;
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	if (of_have_populated_dt())
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		l2x0_of_init(aux_ctrl, 0xcf9fffff);
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	else
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		l2x0_init(l2cache_base, aux_ctrl, 0xcf9fffff);
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	return 0;
}
#endif
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void __iomem *omap4_get_sar_ram_base(void)
{
	return sar_ram_base;
}

/*
 * SAR RAM used to save and restore the HW
 * context in low power modes
 */
static int __init omap4_sar_ram_init(void)
{
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	unsigned long sar_base;

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	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
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	if (cpu_is_omap44xx())
		sar_base = OMAP44XX_SAR_RAM_BASE;
	else if (soc_is_omap54xx())
		sar_base = OMAP54XX_SAR_RAM_BASE;
	else
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		return -ENOMEM;

	/* Static mapping, never released */
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	sar_ram_base = ioremap(sar_base, SZ_16K);
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	if (WARN_ON(!sar_ram_base))
		return -ENOMEM;

	return 0;
}
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omap_early_initcall(omap4_sar_ram_init);
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void __init omap_gic_of_init(void)
{
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	struct device_node *np;

	/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
	if (!cpu_is_omap446x())
		goto skip_errata_init;

	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
	gic_dist_base_addr = of_iomap(np, 0);
	WARN_ON(!gic_dist_base_addr);

	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
	twd_base = of_iomap(np, 0);
	WARN_ON(!twd_base);

skip_errata_init:
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	omap_wakeupgen_init();
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#ifdef CONFIG_IRQ_CROSSBAR
	irqcrossbar_init();
#endif
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	irqchip_init();
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}