armada-xp-mv78460.dtsi

/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * Contains definitions specific to the Armada XP MV78460 SoC that are not
 * common to all Armada XP SoCs.
 */

/include/ "armada-xp.dtsi"

/ {
	model = "Marvell Armada XP MV78460 SoC";
	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};


	cpus {
	    #address-cells = <1>;
	    #size-cells = <0>;

	    cpu@0 {
		device_type = "cpu";
		compatible = "marvell,sheeva-v7";
		reg = <0>;
		clocks = <&cpuclk 0>;
	    };

	    cpu@1 {
		device_type = "cpu";
		compatible = "marvell,sheeva-v7";
		reg = <1>;
		clocks = <&cpuclk 1>;
	    };

	    cpu@2 {
		device_type = "cpu";
		compatible = "marvell,sheeva-v7";
		reg = <2>;
		clocks = <&cpuclk 2>;
	    };

	    cpu@3 {
		device_type = "cpu";
		compatible = "marvell,sheeva-v7";
		reg = <3>;
		clocks = <&cpuclk 3>;
	    };
	};

	soc {
		pinctrl {
			compatible = "marvell,mv78460-pinctrl";
			reg = <0xd0018000 0x38>;

			sdio_pins: sdio-pins {
				marvell,pins = "mpp30", "mpp31", "mpp32",
					       "mpp33", "mpp34", "mpp35";
				marvell,function = "sd0";
			};
		};

		gpio0: gpio@d0018100 {
			compatible = "marvell,orion-gpio";
			reg = <0xd0018100 0x40>;
			ngpios = <32>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupts-cells = <2>;
			interrupts = <82>, <83>, <84>, <85>;
		};

		gpio1: gpio@d0018140 {
			compatible = "marvell,orion-gpio";
			reg = <0xd0018140 0x40>;
			ngpios = <32>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupts-cells = <2>;
			interrupts = <87>, <88>, <89>, <90>;
		};

		gpio2: gpio@d0018180 {
			compatible = "marvell,orion-gpio";
			reg = <0xd0018180 0x40>;
			ngpios = <3>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupts-cells = <2>;
			interrupts = <91>;
		};

		ethernet@d0034000 {
				compatible = "marvell,armada-370-neta";
				reg = <0xd0034000 0x2500>;
				interrupts = <14>;
				clocks = <&gateclk 1>;
				status = "disabled";
		};

		/*
		 * MV78460 has 4 PCIe units Gen2.0: Two units can be
		 * configured as x4 or quad x1 lanes. Two units are
		 * x4/x1.
		 */
		pcie-controller {
			compatible = "marvell,armada-xp-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			bus-range = <0x00 0xff>;

			ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
				  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
				  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
				  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
				  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
				  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
				  0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
				  0x82000000 0 0xd0084000 0xd0084000 0 0x00002000   /* Port 1.1 registers */
				  0x82000000 0 0xd0088000 0xd0088000 0 0x00002000   /* Port 1.2 registers */
				  0x82000000 0 0xd008c000 0xd008c000 0 0x00002000   /* Port 1.3 registers */
				  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
				  0x81000000 0 0	  0xe8000000 0 0x00100000>; /* downstream I/O */

			pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 58>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};

			pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 59>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";
			};

			pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 60>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 7>;
				status = "disabled";
			};

			pcie@4,0 {
				device_type = "pci";
				assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
				reg = <0x2000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 61>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 8>;
				status = "disabled";
			};

			pcie@5,0 {
				device_type = "pci";
				assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
				reg = <0x2800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 62>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 9>;
				status = "disabled";
			};

			pcie@6,0 {
				device_type = "pci";
				assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
				reg = <0x3000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 63>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 10>;
				status = "disabled";
			};

			pcie@7,0 {
				device_type = "pci";
				assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
				reg = <0x3800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 64>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 11>;
				status = "disabled";
			};

			pcie@8,0 {
				device_type = "pci";
				assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
				reg = <0x4000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 65>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 12>;
				status = "disabled";
			};
			pcie@9,0 {
				device_type = "pci";
				assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
				reg = <0x4800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 99>;
				marvell,pcie-port = <2>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 26>;
				status = "disabled";
			};

			pcie@10,0 {
				device_type = "pci";
				assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
				reg = <0x5000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 103>;
				marvell,pcie-port = <3>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 27>;
				status = "disabled";
			};
		};
	};
 };