r8a77995-draak.dts 8.3 KB
Newer Older
1
// SPDX-License-Identifier: GPL-2.0
2 3 4
/*
 * Device Tree Source for the Draak board
 *
5
 * Copyright (C) 2016-2018 Renesas Electronics Corp.
6 7 8 9 10
 * Copyright (C) 2017 Glider bvba
 */

/dts-v1/;
#include "r8a77995.dtsi"
11
#include <dt-bindings/gpio/gpio.h>
12 13 14 15 16 17 18

/ {
	model = "Renesas Draak board based on r8a77995";
	compatible = "renesas,draak", "renesas,r8a77995";

	aliases {
		serial0 = &scif2;
19
		ethernet0 = &avb;
20 21 22
	};

	chosen {
23
		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
24 25 26
		stdout-path = "serial0:115200n8";
	};

27 28 29 30
	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm1 0 50000>;

31 32
		brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
		default-brightness-level = <10>;
33 34 35 36 37

		power-supply = <&reg_12p0v>;
		enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
	};

38 39 40 41 42 43 44 45 46 47
	composite-in {
		compatible = "composite-video-connector";

		port {
			composite_con_in: endpoint {
				remote-endpoint = <&adv7180_in>;
			};
		};
	};

48 49 50 51 52 53 54 55 56 57 58
	hdmi-in {
		compatible = "hdmi-connector";
		type = "a";

		port {
			hdmi_con_in: endpoint {
				remote-endpoint = <&adv7612_in>;
			};
		};
	};

59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93
	hdmi-out {
		compatible = "hdmi-connector";
		type = "a";

		port {
			hdmi_con_out: endpoint {
				remote-endpoint = <&adv7511_out>;
			};
		};
	};

	lvds-decoder {
		compatible = "thine,thc63lvd1024";
		vcc-supply = <&reg_3p3v>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				thc63lvd1024_in: endpoint {
					remote-endpoint = <&lvds0_out>;
				};
			};

			port@2 {
				reg = <2>;
				thc63lvd1024_out: endpoint {
					remote-endpoint = <&adv7511_in>;
				};
			};
		};
	};

94 95 96 97 98
	memory@48000000 {
		device_type = "memory";
		/* first 128MB is reserved for secure area. */
		reg = <0x0 0x48000000 0x0 0x18000000>;
	};
99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116

	reg_1p8v: regulator0 {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_3p3v: regulator1 {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};
117

118 119 120 121 122 123 124 125 126
	reg_12p0v: regulator1 {
		compatible = "regulator-fixed";
		regulator-name = "D12.0V";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-boot-on;
		regulator-always-on;
	};

127 128
	vga {
		compatible = "vga-connector";
129

130 131 132 133
		port {
			vga_in: endpoint {
				remote-endpoint = <&adv7123_out>;
			};
134 135 136
		};
	};

137 138
	vga-encoder {
		compatible = "adi,adv7123";
139

140 141 142
		ports {
			#address-cells = <1>;
			#size-cells = <0>;
143

144 145 146 147 148 149 150 151 152 153 154 155 156
			port@0 {
				reg = <0>;
				adv7123_in: endpoint {
					remote-endpoint = <&du_out_rgb>;
				};
			};
			port@1 {
				reg = <1>;
				adv7123_out: endpoint {
					remote-endpoint = <&vga_in>;
				};
			};
		};
157 158
	};

159 160 161 162
	x12_clk: x12 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <74250000>;
163
	};
164
};
165

166 167 168 169 170 171
&avb {
	pinctrl-0 = <&avb0_pins>;
	pinctrl-names = "default";
	renesas,no-ether-link;
	phy-handle = <&phy0>;
	status = "okay";
172

173 174 175 176 177
	phy0: ethernet-phy@0 {
		rxc-skew-ps = <1500>;
		reg = <0>;
		interrupt-parent = <&gpio5>;
		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
178
	};
179
};
180

181 182 183 184 185 186 187 188 189 190 191 192
&can0 {
	pinctrl-0 = <&can0_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&can1 {
	pinctrl-0 = <&can1_pins>;
	pinctrl-names = "default";
	status = "okay";
};

193 194 195 196
&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";
197

198 199 200 201
	clocks = <&cpg CPG_MOD 724>,
		 <&cpg CPG_MOD 723>,
		 <&x12_clk>;
	clock-names = "du.0", "du.1", "dclkin.0";
202

203 204 205 206 207 208
	ports {
		port@0 {
			endpoint {
				remote-endpoint = <&adv7123_in>;
			};
		};
209
	};
210
};
211

212
&ehci0 {
213
	dr_mode = "host";
214 215 216 217 218
	status = "okay";
};

&extal_clk {
	clock-frequency = <48000000>;
219 220
};

221 222 223 224 225
&hsusb {
	dr_mode = "host";
	status = "okay";
};

226 227 228 229 230
&i2c0 {
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";
	status = "okay";

231 232 233 234
	composite-in@20 {
		compatible = "adi,adv7180cp";
		reg = <0x20>;

235
		ports {
236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				adv7180_in: endpoint {
					remote-endpoint = <&composite_con_in>;
				};
			};

			port@3 {
				reg = <3>;

				/*
				 * The VIN4 video input path is shared between
				 * CVBS and HDMI inputs through SW[49-53]
				 * switches.
				 *
				 * CVBS is the default selection, link it to
				 * VIN4 here.
				 */
				adv7180_out: endpoint {
					remote-endpoint = <&vin4_in>;
				};
			};
		};
262 263 264

	};

265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301
	hdmi-encoder@39 {
		compatible = "adi,adv7511w";
		reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
		reg-names = "main", "edid", "packet", "cec";
		interrupt-parent = <&gpio1>;
		interrupts = <28 IRQ_TYPE_LEVEL_LOW>;

		/* Depends on LVDS */
		max-clock = <135000000>;
		min-vrefresh = <50>;

		adi,input-depth = <8>;
		adi,input-colorspace = "rgb";
		adi,input-clock = "1x";
		adi,input-style = <1>;
		adi,input-justification = "evenly";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				adv7511_in: endpoint {
					remote-endpoint = <&thc63lvd1024_out>;
				};
			};

			port@1 {
				reg = <1>;
				adv7511_out: endpoint {
					remote-endpoint = <&hdmi_con_out>;
				};
			};
		};
	};

302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336
	hdmi-decoder@4c {
		compatible = "adi,adv7612";
		reg = <0x4c>;
		default-input = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				adv7612_in: endpoint {
					remote-endpoint = <&hdmi_con_in>;
				};
			};

			port@2 {
				reg = <2>;

				/*
				 * The VIN4 video input path is shared between
				 * CVBS and HDMI inputs through SW[49-53]
				 * switches.
				 *
				 * CVBS is the default selection, leave HDMI
				 * not connected here.
				 */
				adv7612_out: endpoint {
					pclk-sample = <0>;
					hsync-active = <0>;
					vsync-active = <0>;
				};
			};
		};
337
	};
338 339 340 341 342 343

	eeprom@50 {
		compatible = "rohm,br24t01", "atmel,24c01";
		reg = <0x50>;
		pagesize = <8>;
	};
344 345
};

346 347 348 349 350 351
&i2c1 {
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "default";
	status = "okay";
};

352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369
&lvds0 {
	status = "okay";

	clocks = <&cpg CPG_MOD 727>,
		 <&x12_clk>,
		 <&extal_clk>;
	clock-names = "fck", "dclkin.0", "extal";

	ports {
		port@1 {
			lvds0_out: endpoint {
				remote-endpoint = <&thc63lvd1024_in>;
			};
		};
	};
};

&lvds1 {
370 371 372 373 374 375 376
	/*
	 * Even though the LVDS1 output is not connected, the encoder must be
	 * enabled to supply a pixel clock to the DU for the DPAD output when
	 * LVDS0 is in use.
	 */
	status = "okay";

377 378 379 380 381 382
	clocks = <&cpg CPG_MOD 727>,
		 <&x12_clk>,
		 <&extal_clk>;
	clock-names = "fck", "dclkin.0", "extal";
};

383
&ohci0 {
384
	dr_mode = "host";
385
	status = "okay";
386
};
387

388 389 390 391 392
&pfc {
	avb0_pins: avb {
		mux {
			groups = "avb0_link", "avb0_mdio", "avb0_mii";
			function = "avb0";
393 394 395
		};
	};

396 397 398 399 400 401 402 403 404 405
	can0_pins: can0 {
		groups = "can0_data_a";
		function = "can0";
	};

	can1_pins: can1 {
		groups = "can1_data_a";
		function = "can1";
	};

406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456
	du_pins: du {
		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
		function = "du";
	};

	i2c0_pins: i2c0 {
		groups = "i2c0";
		function = "i2c0";
	};

	i2c1_pins: i2c1 {
		groups = "i2c1";
		function = "i2c1";
	};

	pwm0_pins: pwm0 {
		groups = "pwm0_c";
		function = "pwm0";
	};

	pwm1_pins: pwm1 {
		groups = "pwm1_c";
		function = "pwm1";
	};

	scif2_pins: scif2 {
		groups = "scif2_data";
		function = "scif2";
	};

	sdhi2_pins: sd2 {
		groups = "mmc_data8", "mmc_ctrl";
		function = "mmc";
		power-source = <1800>;
	};

	sdhi2_pins_uhs: sd2_uhs {
		groups = "mmc_data8", "mmc_ctrl";
		function = "mmc";
		power-source = <1800>;
	};

	usb0_pins: usb0 {
		groups = "usb0";
		function = "usb0";
	};

	vin4_pins_cvbs: vin4 {
		groups = "vin4_data8", "vin4_sync", "vin4_clk";
		function = "vin4";
	};
457 458
};

459 460 461 462
&pwm0 {
	pinctrl-0 = <&pwm0_pins>;
	pinctrl-names = "default";

463 464 465
	status = "okay";
};

466 467
&pwm1 {
	pinctrl-0 = <&pwm1_pins>;
468
	pinctrl-names = "default";
469

470
	status = "okay";
471
};
472

473 474 475
&rwdt {
	timeout-sec = <60>;
	status = "okay";
476 477
};

478
&scif2 {
479 480 481
	pinctrl-0 = <&scif2_pins>;
	pinctrl-names = "default";

482 483 484
	status = "okay";
};

485 486 487 488 489 490 491 492 493 494 495 496 497 498
&sdhi2 {
	/* used for on-board eMMC */
	pinctrl-0 = <&sdhi2_pins>;
	pinctrl-1 = <&sdhi2_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	bus-width = <8>;
	mmc-hs200-1_8v;
	non-removable;
	status = "okay";
};

499 500 501 502
&usb2_phy0 {
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";

503
	renesas,no-otg-pins;
504 505 506
	status = "okay";
};

507 508 509 510 511 512 513
&vin4 {
	pinctrl-0 = <&vin4_pins_cvbs>;
	pinctrl-names = "default";

	status = "okay";

	ports {
514
		port {
515 516 517 518 519 520
			vin4_in: endpoint {
				remote-endpoint = <&adv7180_out>;
			};
		};
	};
};
新手
引导
客服 返回
顶部