sdhci-esdhc-imx.c 40.1 KB
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/*
 * Freescale eSDHC i.MX controller driver for the platform bus.
 *
 * derived from the OF-version.
 *
 * Copyright (c) 2010 Pengutronix e.K.
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 *   Author: Wolfram Sang <kernel@pengutronix.de>
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */

#include <linux/io.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
#include <linux/mmc/sdio.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_data/mmc-esdhc-imx.h>
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#include <linux/pm_runtime.h>
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#include "sdhci-pltfm.h"
#include "sdhci-esdhc.h"

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#define ESDHC_SYS_CTRL_DTOCV_MASK	0x0f
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#define	ESDHC_CTRL_D3CD			0x08
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#define ESDHC_BURST_LEN_EN_INCR		(1 << 27)
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/* VENDOR SPEC register */
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#define ESDHC_VENDOR_SPEC		0xc0
#define  ESDHC_VENDOR_SPEC_SDIO_QUIRK	(1 << 1)
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#define  ESDHC_VENDOR_SPEC_VSELECT	(1 << 1)
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#define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON	(1 << 8)
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#define ESDHC_WTMK_LVL			0x44
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#define  ESDHC_WTMK_DEFAULT_VAL		0x10401040
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#define ESDHC_MIX_CTRL			0x48
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#define  ESDHC_MIX_CTRL_DDREN		(1 << 3)
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#define  ESDHC_MIX_CTRL_AC23EN		(1 << 7)
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#define  ESDHC_MIX_CTRL_EXE_TUNE	(1 << 22)
#define  ESDHC_MIX_CTRL_SMPCLK_SEL	(1 << 23)
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#define  ESDHC_MIX_CTRL_AUTO_TUNE_EN	(1 << 24)
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#define  ESDHC_MIX_CTRL_FBCLK_SEL	(1 << 25)
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#define  ESDHC_MIX_CTRL_HS400_EN	(1 << 26)
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/* Bits 3 and 6 are not SDHCI standard definitions */
#define  ESDHC_MIX_CTRL_SDHCI_MASK	0xb7
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/* Tuning bits */
#define  ESDHC_MIX_CTRL_TUNING_MASK	0x03c00000
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/* dll control register */
#define ESDHC_DLL_CTRL			0x60
#define ESDHC_DLL_OVERRIDE_VAL_SHIFT	9
#define ESDHC_DLL_OVERRIDE_EN_SHIFT	8

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/* tune control register */
#define ESDHC_TUNE_CTRL_STATUS		0x68
#define  ESDHC_TUNE_CTRL_STEP		1
#define  ESDHC_TUNE_CTRL_MIN		0
#define  ESDHC_TUNE_CTRL_MAX		((1 << 7) - 1)

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/* strobe dll register */
#define ESDHC_STROBE_DLL_CTRL		0x70
#define ESDHC_STROBE_DLL_CTRL_ENABLE	(1 << 0)
#define ESDHC_STROBE_DLL_CTRL_RESET	(1 << 1)
#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT	3

#define ESDHC_STROBE_DLL_STATUS		0x74
#define ESDHC_STROBE_DLL_STS_REF_LOCK	(1 << 1)
#define ESDHC_STROBE_DLL_STS_SLV_LOCK	0x1

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#define ESDHC_TUNING_CTRL		0xcc
#define ESDHC_STD_TUNING_EN		(1 << 24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
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#define ESDHC_TUNING_START_TAP_DEFAULT	0x1
#define ESDHC_TUNING_START_TAP_MASK	0xff
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#define ESDHC_TUNING_STEP_MASK		0x00070000
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#define ESDHC_TUNING_STEP_SHIFT		16
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/* pinctrl state */
#define ESDHC_PINCTRL_STATE_100MHZ	"state_100mhz"
#define ESDHC_PINCTRL_STATE_200MHZ	"state_200mhz"

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/*
 * Our interpretation of the SDHCI_HOST_CONTROL register
 */
#define ESDHC_CTRL_4BITBUS		(0x1 << 1)
#define ESDHC_CTRL_8BITBUS		(0x2 << 1)
#define ESDHC_CTRL_BUSWIDTH_MASK	(0x3 << 1)

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/*
 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
 * Define this macro DMA error INT for fsl eSDHC
 */
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#define ESDHC_INT_VENDOR_SPEC_DMA_ERR	(1 << 28)
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/*
 * The CMDTYPE of the CMD register (offset 0xE) should be set to
 * "11" when the STOP CMD12 is issued on imx53 to abort one
 * open ended multi-blk IO. Otherwise the TC INT wouldn't
 * be generated.
 * In exact block transfer, the controller doesn't complete the
 * operations automatically as required at the end of the
 * transfer and remains on hold if the abort command is not sent.
 * As a result, the TC flag is not asserted and SW  received timeout
 * exeception. Bit1 of Vendor Spec registor is used to fix it.
 */
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#define ESDHC_FLAG_MULTIBLK_NO_INT	BIT(1)
/*
 * The flag enables the workaround for ESDHC errata ENGcm07207 which
 * affects i.MX25 and i.MX35.
 */
#define ESDHC_FLAG_ENGCM07207		BIT(2)
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/*
 * The flag tells that the ESDHC controller is an USDHC block that is
 * integrated on the i.MX6 series.
 */
#define ESDHC_FLAG_USDHC		BIT(3)
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/* The IP supports manual tuning process */
#define ESDHC_FLAG_MAN_TUNING		BIT(4)
/* The IP supports standard tuning process */
#define ESDHC_FLAG_STD_TUNING		BIT(5)
/* The IP has SDHCI_CAPABILITIES_1 register */
#define ESDHC_FLAG_HAVE_CAP1		BIT(6)
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/*
 * The IP has errata ERR004536
 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
 * when reading data from the card
 */
#define ESDHC_FLAG_ERR004536		BIT(7)
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/* The IP supports HS200 mode */
#define ESDHC_FLAG_HS200		BIT(8)
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/* The IP supports HS400 mode */
#define ESDHC_FLAG_HS400		BIT(9)

/* A higher clock ferquency than this rate requires strobell dll control */
#define ESDHC_STROBE_DLL_CLK_FREQ	100000000
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struct esdhc_soc_data {
	u32 flags;
};

static struct esdhc_soc_data esdhc_imx25_data = {
	.flags = ESDHC_FLAG_ENGCM07207,
};

static struct esdhc_soc_data esdhc_imx35_data = {
	.flags = ESDHC_FLAG_ENGCM07207,
};

static struct esdhc_soc_data esdhc_imx51_data = {
	.flags = 0,
};

static struct esdhc_soc_data esdhc_imx53_data = {
	.flags = ESDHC_FLAG_MULTIBLK_NO_INT,
};

static struct esdhc_soc_data usdhc_imx6q_data = {
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	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
};

static struct esdhc_soc_data usdhc_imx6sl_data = {
	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
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			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
			| ESDHC_FLAG_HS200,
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};

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static struct esdhc_soc_data usdhc_imx6sx_data = {
	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
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			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
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};

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static struct esdhc_soc_data usdhc_imx7d_data = {
	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
			| ESDHC_FLAG_HS400,
};

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struct pltfm_imx_data {
	u32 scratchpad;
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	struct pinctrl *pinctrl;
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	struct pinctrl_state *pins_default;
	struct pinctrl_state *pins_100mhz;
	struct pinctrl_state *pins_200mhz;
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	const struct esdhc_soc_data *socdata;
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	struct esdhc_platform_data boarddata;
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	struct clk *clk_ipg;
	struct clk *clk_ahb;
	struct clk *clk_per;
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	enum {
		NO_CMD_PENDING,      /* no multiblock command pending*/
		MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
		WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
	} multiblock_status;
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	u32 is_ddr;
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};

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static const struct platform_device_id imx_esdhc_devtype[] = {
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	{
		.name = "sdhci-esdhc-imx25",
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		.driver_data = (kernel_ulong_t) &esdhc_imx25_data,
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	}, {
		.name = "sdhci-esdhc-imx35",
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		.driver_data = (kernel_ulong_t) &esdhc_imx35_data,
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	}, {
		.name = "sdhci-esdhc-imx51",
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		.driver_data = (kernel_ulong_t) &esdhc_imx51_data,
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	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);

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static const struct of_device_id imx_esdhc_dt_ids[] = {
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	{ .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
	{ .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
	{ .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
	{ .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
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	{ .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
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	{ .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
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	{ .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
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	{ .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
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	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);

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static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
{
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	return data->socdata == &esdhc_imx25_data;
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}

static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
{
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	return data->socdata == &esdhc_imx53_data;
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}

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static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
{
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	return data->socdata == &usdhc_imx6q_data;
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}

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static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
{
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	return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
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}

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static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
{
	void __iomem *base = host->ioaddr + (reg & ~0x3);
	u32 shift = (reg & 0x3) * 8;

	writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
}

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static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
{
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	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
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	u32 val = readl(host->ioaddr + reg);

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	if (unlikely(reg == SDHCI_PRESENT_STATE)) {
		u32 fsl_prss = val;
		/* save the least 20 bits */
		val = fsl_prss & 0x000FFFFF;
		/* move dat[0-3] bits */
		val |= (fsl_prss & 0x0F000000) >> 4;
		/* move cmd line bit */
		val |= (fsl_prss & 0x00800000) << 1;
	}

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	if (unlikely(reg == SDHCI_CAPABILITIES)) {
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		/* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
		if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
			val &= 0xffff0000;

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		/* In FSL esdhc IC module, only bit20 is used to indicate the
		 * ADMA2 capability of esdhc, but this bit is messed up on
		 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
		 * don't actually support ADMA2). So set the BROKEN_ADMA
		 * uirk on MX25/35 platforms.
		 */

		if (val & SDHCI_CAN_DO_ADMA1) {
			val &= ~SDHCI_CAN_DO_ADMA1;
			val |= SDHCI_CAN_DO_ADMA2;
		}
	}

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	if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
		if (esdhc_is_usdhc(imx_data)) {
			if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
				val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
			else
				/* imx6q/dl does not have cap_1 register, fake one */
				val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
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					| SDHCI_SUPPORT_SDR50
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					| SDHCI_USE_SDR50_TUNING
					| (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
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			if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
				val |= SDHCI_SUPPORT_HS400;
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		}
	}
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	if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
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		val = 0;
		val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
		val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
		val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
	}

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	if (unlikely(reg == SDHCI_INT_STATUS)) {
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		if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
			val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
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			val |= SDHCI_INT_ADMA_ERROR;
		}
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		/*
		 * mask off the interrupt we get in response to the manually
		 * sent CMD12
		 */
		if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
		    ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
			val &= ~SDHCI_INT_RESPONSE;
			writel(SDHCI_INT_RESPONSE, host->ioaddr +
						   SDHCI_INT_STATUS);
			imx_data->multiblock_status = NO_CMD_PENDING;
		}
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	}

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	return val;
}

static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
{
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	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
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	u32 data;

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	if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
			reg == SDHCI_INT_STATUS)) {
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		if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
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			/*
			 * Clear and then set D3CD bit to avoid missing the
			 * card interrupt.  This is a eSDHC controller problem
			 * so we need to apply the following workaround: clear
			 * and set D3CD bit will make eSDHC re-sample the card
			 * interrupt. In case a card interrupt was lost,
			 * re-sample it by the following steps.
			 */
			data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
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			data &= ~ESDHC_CTRL_D3CD;
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			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
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			data |= ESDHC_CTRL_D3CD;
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			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
		}
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		if (val & SDHCI_INT_ADMA_ERROR) {
			val &= ~SDHCI_INT_ADMA_ERROR;
			val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
		}
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	}
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	if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
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				&& (reg == SDHCI_INT_STATUS)
				&& (val & SDHCI_INT_DATA_END))) {
			u32 v;
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			v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
			v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
			writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
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			if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
			{
				/* send a manual CMD12 with RESPTYP=none */
				data = MMC_STOP_TRANSMISSION << 24 |
				       SDHCI_CMD_ABORTCMD << 16;
				writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
				imx_data->multiblock_status = WAIT_FOR_INT;
			}
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	}

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	writel(val, host->ioaddr + reg);
}

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static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
{
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	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
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	u16 ret = 0;
	u32 val;
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	if (unlikely(reg == SDHCI_HOST_VERSION)) {
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		reg ^= 2;
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		if (esdhc_is_usdhc(imx_data)) {
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			/*
			 * The usdhc register returns a wrong host version.
			 * Correct it here.
			 */
			return SDHCI_SPEC_300;
		}
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	}
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	if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
		val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
		if (val & ESDHC_VENDOR_SPEC_VSELECT)
			ret |= SDHCI_CTRL_VDD_180;

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		if (esdhc_is_usdhc(imx_data)) {
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			if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
				val = readl(host->ioaddr + ESDHC_MIX_CTRL);
			else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
				/* the std tuning bits is in ACMD12_ERR for imx6sl */
				val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
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		}

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		if (val & ESDHC_MIX_CTRL_EXE_TUNE)
			ret |= SDHCI_CTRL_EXEC_TUNING;
		if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
			ret |= SDHCI_CTRL_TUNED_CLK;

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		ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;

		return ret;
	}

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	if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
		if (esdhc_is_usdhc(imx_data)) {
			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
			ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
			/* Swap AC23 bit */
			if (m & ESDHC_MIX_CTRL_AC23EN) {
				ret &= ~ESDHC_MIX_CTRL_AC23EN;
				ret |= SDHCI_TRNS_AUTO_CMD23;
			}
		} else {
			ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
		}

		return ret;
	}

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	return readw(host->ioaddr + reg);
}

static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
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	u32 new_val = 0;
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	switch (reg) {
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	case SDHCI_CLOCK_CONTROL:
		new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
		if (val & SDHCI_CLOCK_CARD_EN)
			new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
		else
			new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
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		writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
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		return;
	case SDHCI_HOST_CONTROL2:
		new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
		if (val & SDHCI_CTRL_VDD_180)
			new_val |= ESDHC_VENDOR_SPEC_VSELECT;
		else
			new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
		writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
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		if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
			new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
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			if (val & SDHCI_CTRL_TUNED_CLK) {
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				new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
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				new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
			} else {
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				new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
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				new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
			}
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			writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
		} else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
			u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
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			if (val & SDHCI_CTRL_TUNED_CLK) {
				v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
			} else {
				v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
				m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
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				m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
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			}

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			if (val & SDHCI_CTRL_EXEC_TUNING) {
				v |= ESDHC_MIX_CTRL_EXE_TUNE;
				m |= ESDHC_MIX_CTRL_FBCLK_SEL;
500
				m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
501 502 503 504 505 506 507
			} else {
				v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
			}

			writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
			writel(m, host->ioaddr + ESDHC_MIX_CTRL);
		}
508
		return;
509
	case SDHCI_TRANSFER_MODE:
510
		if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
511 512 513 514
				&& (host->cmd->opcode == SD_IO_RW_EXTENDED)
				&& (host->cmd->data->blocks > 1)
				&& (host->cmd->data->flags & MMC_DATA_READ)) {
			u32 v;
515 516 517
			v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
			v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
			writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
518
		}
519

520
		if (esdhc_is_usdhc(imx_data)) {
521
			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
522 523 524 525 526 527
			/* Swap AC23 bit */
			if (val & SDHCI_TRNS_AUTO_CMD23) {
				val &= ~SDHCI_TRNS_AUTO_CMD23;
				val |= ESDHC_MIX_CTRL_AC23EN;
			}
			m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
528 529 530 531 532 533 534 535
			writel(m, host->ioaddr + ESDHC_MIX_CTRL);
		} else {
			/*
			 * Postpone this write, we must do it together with a
			 * command write that is down below.
			 */
			imx_data->scratchpad = val;
		}
536 537
		return;
	case SDHCI_COMMAND:
538
		if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
539
			val |= SDHCI_CMD_ABORTCMD;
540

541
		if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
542
		    (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
543 544
			imx_data->multiblock_status = MULTIBLK_IN_PROCESS;

545
		if (esdhc_is_usdhc(imx_data))
546 547
			writel(val << 16,
			       host->ioaddr + SDHCI_TRANSFER_MODE);
548
		else
549 550
			writel(val << 16 | imx_data->scratchpad,
			       host->ioaddr + SDHCI_TRANSFER_MODE);
551 552 553 554 555 556 557 558
		return;
	case SDHCI_BLOCK_SIZE:
		val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
		break;
	}
	esdhc_clrset_le(host, 0xffff, val, reg);
}

559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577
static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
{
	u8 ret;
	u32 val;

	switch (reg) {
	case SDHCI_HOST_CONTROL:
		val = readl(host->ioaddr + reg);

		ret = val & SDHCI_CTRL_LED;
		ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
		ret |= (val & ESDHC_CTRL_4BITBUS);
		ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
		return ret;
	}

	return readb(host->ioaddr + reg);
}

578 579
static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
{
580
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
581
	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
582
	u32 new_val;
583
	u32 mask;
584 585 586 587 588 589 590 591 592

	switch (reg) {
	case SDHCI_POWER_CONTROL:
		/*
		 * FSL put some DMA bits here
		 * If your board has a regulator, code should be here
		 */
		return;
	case SDHCI_HOST_CONTROL:
593
		/* FSL messed up here, so we need to manually compose it. */
594
		new_val = val & SDHCI_CTRL_LED;
M
Masanari Iida 已提交
595
		/* ensure the endianness */
596
		new_val |= ESDHC_HOST_CONTROL_LE;
597 598 599 600 601
		/* bits 8&9 are reserved on mx25 */
		if (!is_imx25_esdhc(imx_data)) {
			/* DMA mode bits are shifted */
			new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
		}
602

603 604 605
		/*
		 * Do not touch buswidth bits here. This is done in
		 * esdhc_pltfm_bus_width.
606 607
		 * Do not touch the D3CD bit either which is used for the
		 * SDIO interrupt errata workaround.
608
		 */
609
		mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
610 611

		esdhc_clrset_le(host, mask, new_val, reg);
612 613 614
		return;
	}
	esdhc_clrset_le(host, 0xff, val, reg);
615 616 617 618 619 620 621 622 623

	/*
	 * The esdhc has a design violation to SDHC spec which tells
	 * that software reset should not affect card detection circuit.
	 * But esdhc clears its SYSCTL register bits [0..2] during the
	 * software reset.  This will stop those clocks that card detection
	 * circuit relies on.  To work around it, we turn the clocks on back
	 * to keep card detection circuit functional.
	 */
624
	if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
625
		esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
626 627 628 629
		/*
		 * The reset on usdhc fails to clear MIX_CTRL register.
		 * Do it manually here.
		 */
630
		if (esdhc_is_usdhc(imx_data)) {
631 632 633 634
			/* the tuning bits should be kept during reset */
			new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
			writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
					host->ioaddr + ESDHC_MIX_CTRL);
635 636
			imx_data->is_ddr = 0;
		}
637
	}
638 639
}

640 641 642 643
static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

644
	return pltfm_host->clock;
645 646
}

647 648 649 650
static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

651
	return pltfm_host->clock / 256 / 16;
652 653
}

654 655 656 657
static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
					 unsigned int clock)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
658
	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
659
	unsigned int host_clock = pltfm_host->clock;
660 661
	int pre_div = 2;
	int div = 1;
662
	u32 temp, val;
663

664
	if (clock == 0) {
665 666
		host->mmc->actual_clock = 0;

667
		if (esdhc_is_usdhc(imx_data)) {
668 669 670 671
			val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
			writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
					host->ioaddr + ESDHC_VENDOR_SPEC);
		}
672
		return;
673
	}
674

675
	if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
676 677
		pre_div = 1;

678 679 680 681 682 683 684 685 686 687 688
	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
	temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
		| ESDHC_CLOCK_MASK);
	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);

	while (host_clock / pre_div / 16 > clock && pre_div < 256)
		pre_div *= 2;

	while (host_clock / pre_div / div > clock && div < 16)
		div++;

689
	host->mmc->actual_clock = host_clock / pre_div / div;
690
	dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
691
		clock, host->mmc->actual_clock);
692

693 694 695 696
	if (imx_data->is_ddr)
		pre_div >>= 2;
	else
		pre_div >>= 1;
697 698 699 700 701 702 703
	div--;

	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
	temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
		| (div << ESDHC_DIVIDER_SHIFT)
		| (pre_div << ESDHC_PREDIV_SHIFT));
	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
704

705
	if (esdhc_is_usdhc(imx_data)) {
706 707 708 709 710
		val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
		writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
		host->ioaddr + ESDHC_VENDOR_SPEC);
	}

711
	mdelay(1);
712 713
}

714 715
static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
{
716
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
717
	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
718
	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
719 720 721

	switch (boarddata->wp_type) {
	case ESDHC_WP_GPIO:
722
		return mmc_gpio_get_ro(host->mmc);
723 724 725 726 727 728 729 730 731 732
	case ESDHC_WP_CONTROLLER:
		return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
			       SDHCI_WRITE_PROTECT);
	case ESDHC_WP_NONE:
		break;
	}

	return -ENOSYS;
}

733
static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752
{
	u32 ctrl;

	switch (width) {
	case MMC_BUS_WIDTH_8:
		ctrl = ESDHC_CTRL_8BITBUS;
		break;
	case MMC_BUS_WIDTH_4:
		ctrl = ESDHC_CTRL_4BITBUS;
		break;
	default:
		ctrl = 0;
		break;
	}

	esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
			SDHCI_HOST_CONTROL);
}

753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775
static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
{
	u32 reg;

	/* FIXME: delay a bit for card to be ready for next tuning due to errors */
	mdelay(1);

	reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
	reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
			ESDHC_MIX_CTRL_FBCLK_SEL;
	writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
	writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
	dev_dbg(mmc_dev(host->mmc),
		"tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
			val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
}

static void esdhc_post_tuning(struct sdhci_host *host)
{
	u32 reg;

	reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
	reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
776
	reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
777 778 779 780 781 782 783 784 785 786 787
	writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
}

static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
{
	int min, max, avg, ret;

	/* find the mininum delay first which can pass tuning */
	min = ESDHC_TUNE_CTRL_MIN;
	while (min < ESDHC_TUNE_CTRL_MAX) {
		esdhc_prepare_tuning(host, min);
788
		if (!mmc_send_tuning(host->mmc, opcode, NULL))
789 790 791 792 793 794 795 796
			break;
		min += ESDHC_TUNE_CTRL_STEP;
	}

	/* find the maxinum delay which can not pass tuning */
	max = min + ESDHC_TUNE_CTRL_STEP;
	while (max < ESDHC_TUNE_CTRL_MAX) {
		esdhc_prepare_tuning(host, max);
797
		if (mmc_send_tuning(host->mmc, opcode, NULL)) {
798 799 800 801 802 803 804 805 806
			max -= ESDHC_TUNE_CTRL_STEP;
			break;
		}
		max += ESDHC_TUNE_CTRL_STEP;
	}

	/* use average delay to get the best timing */
	avg = (min + max) / 2;
	esdhc_prepare_tuning(host, avg);
807
	ret = mmc_send_tuning(host->mmc, opcode, NULL);
808 809 810 811 812 813 814 815
	esdhc_post_tuning(host);

	dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
		ret ? "failed" : "passed", avg, ret);

	return ret;
}

816 817 818 819
static int esdhc_change_pinstate(struct sdhci_host *host,
						unsigned int uhs)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
820
	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
821 822 823 824 825 826 827 828 829 830 831 832
	struct pinctrl_state *pinctrl;

	dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);

	if (IS_ERR(imx_data->pinctrl) ||
		IS_ERR(imx_data->pins_default) ||
		IS_ERR(imx_data->pins_100mhz) ||
		IS_ERR(imx_data->pins_200mhz))
		return -EINVAL;

	switch (uhs) {
	case MMC_TIMING_UHS_SDR50:
833
	case MMC_TIMING_UHS_DDR50:
834 835 836
		pinctrl = imx_data->pins_100mhz;
		break;
	case MMC_TIMING_UHS_SDR104:
837
	case MMC_TIMING_MMC_HS200:
838
	case MMC_TIMING_MMC_HS400:
839 840 841 842 843 844 845 846 847 848
		pinctrl = imx_data->pins_200mhz;
		break;
	default:
		/* back to default state for other legacy timing */
		pinctrl = imx_data->pins_default;
	}

	return pinctrl_select_state(imx_data->pinctrl, pinctrl);
}

849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864
/*
 * For HS400 eMMC, there is a data_strobe line, this signal is generated
 * by the device and used for data output and CRC status response output
 * in HS400 mode. The frequency of this signal follows the frequency of
 * CLK generated by host. Host receive the data which is aligned to the
 * edge of data_strobe line. Due to the time delay between CLK line and
 * data_strobe line, if the delay time is larger than one clock cycle,
 * then CLK and data_strobe line will misaligned, read error shows up.
 * So when the CLK is higher than 100MHz, each clock cycle is short enough,
 * host should config the delay target.
 */
static void esdhc_set_strobe_dll(struct sdhci_host *host)
{
	u32 v;

	if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
865 866 867 868 869
		/* disable clock before enabling strobe dll */
		writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
		       ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
		       host->ioaddr + ESDHC_VENDOR_SPEC);

870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891
		/* force a reset on strobe dll */
		writel(ESDHC_STROBE_DLL_CTRL_RESET,
			host->ioaddr + ESDHC_STROBE_DLL_CTRL);
		/*
		 * enable strobe dll ctrl and adjust the delay target
		 * for the uSDHC loopback read clock
		 */
		v = ESDHC_STROBE_DLL_CTRL_ENABLE |
			(7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
		writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
		/* wait 1us to make sure strobe dll status register stable */
		udelay(1);
		v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
		if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
			dev_warn(mmc_dev(host->mmc),
				"warning! HS400 strobe DLL status REF not lock!\n");
		if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
			dev_warn(mmc_dev(host->mmc),
				"warning! HS400 strobe DLL status SLV not lock!\n");
	}
}

892
static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
893
{
894
	u32 m;
895
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
896
	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
897
	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
898

899 900 901 902 903
	/* disable ddr mode and disable HS400 mode */
	m = readl(host->ioaddr + ESDHC_MIX_CTRL);
	m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
	imx_data->is_ddr = 0;

904
	switch (timing) {
905 906 907 908
	case MMC_TIMING_UHS_SDR12:
	case MMC_TIMING_UHS_SDR25:
	case MMC_TIMING_UHS_SDR50:
	case MMC_TIMING_UHS_SDR104:
909
	case MMC_TIMING_MMC_HS200:
910
		writel(m, host->ioaddr + ESDHC_MIX_CTRL);
911 912
		break;
	case MMC_TIMING_UHS_DDR50:
913
	case MMC_TIMING_MMC_DDR52:
914 915
		m |= ESDHC_MIX_CTRL_DDREN;
		writel(m, host->ioaddr + ESDHC_MIX_CTRL);
916
		imx_data->is_ddr = 1;
917 918 919 920 921 922 923 924 925
		if (boarddata->delay_line) {
			u32 v;
			v = boarddata->delay_line <<
				ESDHC_DLL_OVERRIDE_VAL_SHIFT |
				(1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
			if (is_imx53_esdhc(imx_data))
				v <<= 1;
			writel(v, host->ioaddr + ESDHC_DLL_CTRL);
		}
926
		break;
927 928 929 930
	case MMC_TIMING_MMC_HS400:
		m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
		writel(m, host->ioaddr + ESDHC_MIX_CTRL);
		imx_data->is_ddr = 1;
931 932
		/* update clock after enable DDR for strobe DLL lock */
		host->ops->set_clock(host, host->clock);
933 934
		esdhc_set_strobe_dll(host);
		break;
935 936
	}

937
	esdhc_change_pinstate(host, timing);
938 939
}

940 941 942 943 944 945 946 947
static void esdhc_reset(struct sdhci_host *host, u8 mask)
{
	sdhci_reset(host, mask);

	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
}

948 949 950
static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
951
	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
952

953 954
	/* Doc Errata: the uSDHC actual maximum timeout count is 1 << 29 */
	return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
955 956
}

957 958 959
static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
960
	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
961 962

	/* use maximum timeout counter */
963 964
	esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
			esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
965 966 967
			SDHCI_TIMEOUT_CONTROL);
}

968
static struct sdhci_ops sdhci_esdhc_ops = {
969
	.read_l = esdhc_readl_le,
970
	.read_w = esdhc_readw_le,
971
	.read_b = esdhc_readb_le,
972
	.write_l = esdhc_writel_le,
973 974
	.write_w = esdhc_writew_le,
	.write_b = esdhc_writeb_le,
975
	.set_clock = esdhc_pltfm_set_clock,
976
	.get_max_clock = esdhc_pltfm_get_max_clock,
977
	.get_min_clock = esdhc_pltfm_get_min_clock,
978
	.get_max_timeout_count = esdhc_get_max_timeout_count,
979
	.get_ro = esdhc_pltfm_get_ro,
980
	.set_timeout = esdhc_set_timeout,
981
	.set_bus_width = esdhc_pltfm_set_bus_width,
982
	.set_uhs_signaling = esdhc_set_uhs_signaling,
983
	.reset = esdhc_reset,
984 985
};

986
static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
R
Richard Zhu 已提交
987 988 989
	.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
			| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
			| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
990 991 992 993
			| SDHCI_QUIRK_BROKEN_CARD_DETECTION,
	.ops = &sdhci_esdhc_ops,
};

994 995 996 997
static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
998
	int tmp;
999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029

	if (esdhc_is_usdhc(imx_data)) {
		/*
		 * The imx6q ROM code will change the default watermark
		 * level setting to something insane.  Change it back here.
		 */
		writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);

		/*
		 * ROM code will change the bit burst_length_enable setting
		 * to zero if this usdhc is choosed to boot system. Change
		 * it back here, otherwise it will impact the performance a
		 * lot. This bit is used to enable/disable the burst length
		 * for the external AHB2AXI bridge, it's usefully especially
		 * for INCR transfer because without burst length indicator,
		 * the AHB2AXI bridge does not know the burst length in
		 * advance. And without burst length indicator, AHB INCR
		 * transfer can only be converted to singles on the AXI side.
		 */
		writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
			| ESDHC_BURST_LEN_EN_INCR,
			host->ioaddr + SDHCI_HOST_CONTROL);
		/*
		* errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
		* TO1.1, it's harmless for MX6SL
		*/
		writel(readl(host->ioaddr + 0x6c) | BIT(7),
			host->ioaddr + 0x6c);

		/* disable DLL_CTRL delay line settings */
		writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046

		if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
			tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
			tmp |= ESDHC_STD_TUNING_EN |
				ESDHC_TUNING_START_TAP_DEFAULT;
			if (imx_data->boarddata.tuning_start_tap) {
				tmp &= ~ESDHC_TUNING_START_TAP_MASK;
				tmp |= imx_data->boarddata.tuning_start_tap;
			}

			if (imx_data->boarddata.tuning_step) {
				tmp &= ~ESDHC_TUNING_STEP_MASK;
				tmp |= imx_data->boarddata.tuning_step
					<< ESDHC_TUNING_STEP_SHIFT;
			}
			writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
		}
1047 1048 1049
	}
}

1050
#ifdef CONFIG_OF
B
Bill Pemberton 已提交
1051
static int
1052
sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1053
			 struct sdhci_host *host,
1054
			 struct pltfm_imx_data *imx_data)
1055 1056
{
	struct device_node *np = pdev->dev.of_node;
1057
	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1058
	int ret;
1059 1060 1061 1062 1063 1064 1065 1066

	if (of_get_property(np, "fsl,wp-controller", NULL))
		boarddata->wp_type = ESDHC_WP_CONTROLLER;

	boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
	if (gpio_is_valid(boarddata->wp_gpio))
		boarddata->wp_type = ESDHC_WP_GPIO;

1067
	of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1068 1069
	of_property_read_u32(np, "fsl,tuning-start-tap",
			     &boarddata->tuning_start_tap);
1070

1071 1072 1073 1074 1075
	if (of_find_property(np, "no-1-8-v", NULL))
		boarddata->support_vsel = false;
	else
		boarddata->support_vsel = true;

1076 1077 1078
	if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
		boarddata->delay_line = 0;

1079 1080
	mmc_of_parse_voltage(np, &host->ocr_mask);

1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100
	/* sdr50 and sdr104 needs work on 1.8v signal voltage */
	if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
	    !IS_ERR(imx_data->pins_default)) {
		imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
						ESDHC_PINCTRL_STATE_100MHZ);
		imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
						ESDHC_PINCTRL_STATE_200MHZ);
		if (IS_ERR(imx_data->pins_100mhz) ||
				IS_ERR(imx_data->pins_200mhz)) {
			dev_warn(mmc_dev(host->mmc),
				"could not get ultra high speed state, work on normal mode\n");
			/*
			 * fall back to not support uhs by specify no 1.8v quirk
			 */
			host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
		}
	} else {
		host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
	}

1101
	/* call to generic mmc_of_parse to support additional capabilities */
1102 1103 1104 1105
	ret = mmc_of_parse(host->mmc);
	if (ret)
		return ret;

1106
	if (mmc_gpio_get_cd(host->mmc) >= 0)
1107 1108 1109
		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;

	return 0;
1110 1111 1112 1113
}
#else
static inline int
sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1114
			 struct sdhci_host *host,
1115
			 struct pltfm_imx_data *imx_data)
1116 1117 1118 1119 1120
{
	return -ENODEV;
}
#endif

1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185
static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
			 struct sdhci_host *host,
			 struct pltfm_imx_data *imx_data)
{
	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
	int err;

	if (!host->mmc->parent->platform_data) {
		dev_err(mmc_dev(host->mmc), "no board data!\n");
		return -EINVAL;
	}

	imx_data->boarddata = *((struct esdhc_platform_data *)
				host->mmc->parent->platform_data);
	/* write_protect */
	if (boarddata->wp_type == ESDHC_WP_GPIO) {
		err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
		if (err) {
			dev_err(mmc_dev(host->mmc),
				"failed to request write-protect gpio!\n");
			return err;
		}
		host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
	}

	/* card_detect */
	switch (boarddata->cd_type) {
	case ESDHC_CD_GPIO:
		err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
		if (err) {
			dev_err(mmc_dev(host->mmc),
				"failed to request card-detect gpio!\n");
			return err;
		}
		/* fall through */

	case ESDHC_CD_CONTROLLER:
		/* we have a working card_detect back */
		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
		break;

	case ESDHC_CD_PERMANENT:
		host->mmc->caps |= MMC_CAP_NONREMOVABLE;
		break;

	case ESDHC_CD_NONE:
		break;
	}

	switch (boarddata->max_bus_width) {
	case 8:
		host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
		break;
	case 4:
		host->mmc->caps |= MMC_CAP_4_BIT_DATA;
		break;
	case 1:
	default:
		host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
		break;
	}

	return 0;
}

B
Bill Pemberton 已提交
1186
static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1187
{
1188 1189
	const struct of_device_id *of_id =
			of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1190 1191
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_host *host;
1192
	int err;
1193
	struct pltfm_imx_data *imx_data;
1194

1195 1196
	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
				sizeof(*imx_data));
1197 1198 1199 1200 1201
	if (IS_ERR(host))
		return PTR_ERR(host);

	pltfm_host = sdhci_priv(host);

1202
	imx_data = sdhci_pltfm_priv(pltfm_host);
1203

1204 1205
	imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
						  pdev->id_entry->driver_data;
1206

1207 1208 1209
	imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(imx_data->clk_ipg)) {
		err = PTR_ERR(imx_data->clk_ipg);
1210
		goto free_sdhci;
1211
	}
1212 1213 1214 1215

	imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
	if (IS_ERR(imx_data->clk_ahb)) {
		err = PTR_ERR(imx_data->clk_ahb);
1216
		goto free_sdhci;
1217 1218 1219 1220 1221
	}

	imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
	if (IS_ERR(imx_data->clk_per)) {
		err = PTR_ERR(imx_data->clk_per);
1222
		goto free_sdhci;
1223 1224 1225
	}

	pltfm_host->clk = imx_data->clk_per;
1226
	pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1227 1228 1229
	clk_prepare_enable(imx_data->clk_per);
	clk_prepare_enable(imx_data->clk_ipg);
	clk_prepare_enable(imx_data->clk_ahb);
1230

1231
	imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1232 1233
	if (IS_ERR(imx_data->pinctrl)) {
		err = PTR_ERR(imx_data->pinctrl);
1234
		goto disable_clk;
1235 1236
	}

1237 1238
	imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
						PINCTRL_STATE_DEFAULT);
1239 1240
	if (IS_ERR(imx_data->pins_default))
		dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1241

1242
	if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1243
		/* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
R
Richard Zhu 已提交
1244 1245
		host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
			| SDHCI_QUIRK_BROKEN_ADMA;
1246

1247 1248
	if (esdhc_is_usdhc(imx_data)) {
		host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1249
		host->mmc->caps |= MMC_CAP_1_8V_DDR;
1250 1251
		if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
			host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1252 1253 1254 1255 1256

		/* clear tuning bits in case ROM has set it already */
		writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
		writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR);
		writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1257
	}
1258

1259 1260 1261
	if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
		sdhci_esdhc_ops.platform_execute_tuning =
					esdhc_executing_tuning;
1262

1263 1264 1265
	if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
		host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;

1266 1267 1268
	if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
		host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;

1269 1270 1271 1272 1273 1274
	if (of_id)
		err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
	else
		err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
	if (err)
		goto disable_clk;
1275

1276 1277
	sdhci_esdhc_imx_hwinit(host);

1278 1279
	err = sdhci_add_host(host);
	if (err)
1280
		goto disable_clk;
1281

1282 1283 1284 1285
	pm_runtime_set_active(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_suspend_ignore_children(&pdev->dev, 1);
1286
	pm_runtime_enable(&pdev->dev);
1287

1288
	return 0;
1289

1290
disable_clk:
1291 1292 1293
	clk_disable_unprepare(imx_data->clk_per);
	clk_disable_unprepare(imx_data->clk_ipg);
	clk_disable_unprepare(imx_data->clk_ahb);
1294
free_sdhci:
1295 1296
	sdhci_pltfm_free(pdev);
	return err;
1297 1298
}

B
Bill Pemberton 已提交
1299
static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1300
{
1301
	struct sdhci_host *host = platform_get_drvdata(pdev);
1302
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1303
	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1304 1305
	int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);

1306
	pm_runtime_get_sync(&pdev->dev);
1307
	pm_runtime_disable(&pdev->dev);
1308
	pm_runtime_put_noidle(&pdev->dev);
1309

1310 1311 1312 1313 1314
	sdhci_remove_host(host, dead);

	clk_disable_unprepare(imx_data->clk_per);
	clk_disable_unprepare(imx_data->clk_ipg);
	clk_disable_unprepare(imx_data->clk_ahb);
1315

1316 1317 1318
	sdhci_pltfm_free(pdev);

	return 0;
1319 1320
}

1321
#ifdef CONFIG_PM_SLEEP
1322 1323
static int sdhci_esdhc_suspend(struct device *dev)
{
1324 1325
	struct sdhci_host *host = dev_get_drvdata(dev);

1326 1327 1328
	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
		mmc_retune_needed(host->mmc);

1329
	return sdhci_suspend_host(host);
1330 1331 1332 1333
}

static int sdhci_esdhc_resume(struct device *dev)
{
1334 1335
	struct sdhci_host *host = dev_get_drvdata(dev);

1336 1337
	/* re-initialize hw state in case it's lost in low power mode */
	sdhci_esdhc_imx_hwinit(host);
1338

1339
	return sdhci_resume_host(host);
1340
}
1341
#endif
1342

1343
#ifdef CONFIG_PM
1344 1345 1346 1347
static int sdhci_esdhc_runtime_suspend(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1348
	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1349 1350 1351 1352
	int ret;

	ret = sdhci_runtime_suspend_host(host);

1353 1354 1355
	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
		mmc_retune_needed(host->mmc);

1356 1357 1358 1359
	if (!sdhci_sdio_irq_enabled(host)) {
		clk_disable_unprepare(imx_data->clk_per);
		clk_disable_unprepare(imx_data->clk_ipg);
	}
1360 1361 1362 1363 1364 1365 1366 1367 1368
	clk_disable_unprepare(imx_data->clk_ahb);

	return ret;
}

static int sdhci_esdhc_runtime_resume(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1369
	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1370

1371 1372 1373 1374
	if (!sdhci_sdio_irq_enabled(host)) {
		clk_prepare_enable(imx_data->clk_per);
		clk_prepare_enable(imx_data->clk_ipg);
	}
1375 1376 1377 1378 1379 1380 1381
	clk_prepare_enable(imx_data->clk_ahb);

	return sdhci_runtime_resume_host(host);
}
#endif

static const struct dev_pm_ops sdhci_esdhc_pmops = {
1382
	SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1383 1384 1385 1386
	SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
				sdhci_esdhc_runtime_resume, NULL)
};

1387 1388 1389
static struct platform_driver sdhci_esdhc_imx_driver = {
	.driver		= {
		.name	= "sdhci-esdhc-imx",
1390
		.of_match_table = imx_esdhc_dt_ids,
1391
		.pm	= &sdhci_esdhc_pmops,
1392
	},
1393
	.id_table	= imx_esdhc_devtype,
1394
	.probe		= sdhci_esdhc_imx_probe,
B
Bill Pemberton 已提交
1395
	.remove		= sdhci_esdhc_imx_remove,
1396
};
1397

1398
module_platform_driver(sdhci_esdhc_imx_driver);
1399 1400

MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1401
MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1402
MODULE_LICENSE("GPL v2");