pciehp_hpc.c 29.4 KB
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/*
 * PCI Express PCI Hot Plug Driver
 *
 * Copyright (C) 1995,2001 Compaq Computer Corporation
 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
 * Copyright (C) 2001 IBM Corp.
 * Copyright (C) 2003-2004 Intel Corporation
 *
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 * NON INFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
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 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
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 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
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#include <linux/signal.h>
#include <linux/jiffies.h>
#include <linux/timer.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include "../pci.h"
#include "pciehp.h"

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static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);

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struct ctrl_reg {
	u8 cap_id;
	u8 nxt_ptr;
	u16 cap_reg;
	u32 dev_cap;
	u16 dev_ctrl;
	u16 dev_status;
	u32 lnk_cap;
	u16 lnk_ctrl;
	u16 lnk_status;
	u32 slot_cap;
	u16 slot_ctrl;
	u16 slot_status;
	u16 root_ctrl;
	u16 rsvp;
	u32 root_status;
} __attribute__ ((packed));

/* offsets to the controller registers based on the above structure layout */
enum ctrl_offsets {
	PCIECAPID	=	offsetof(struct ctrl_reg, cap_id),
	NXTCAPPTR	=	offsetof(struct ctrl_reg, nxt_ptr),
	CAPREG		=	offsetof(struct ctrl_reg, cap_reg),
	DEVCAP		=	offsetof(struct ctrl_reg, dev_cap),
	DEVCTRL		=	offsetof(struct ctrl_reg, dev_ctrl),
	DEVSTATUS	=	offsetof(struct ctrl_reg, dev_status),
	LNKCAP		=	offsetof(struct ctrl_reg, lnk_cap),
	LNKCTRL		=	offsetof(struct ctrl_reg, lnk_ctrl),
	LNKSTATUS	=	offsetof(struct ctrl_reg, lnk_status),
	SLOTCAP		=	offsetof(struct ctrl_reg, slot_cap),
	SLOTCTRL	=	offsetof(struct ctrl_reg, slot_ctrl),
	SLOTSTATUS	=	offsetof(struct ctrl_reg, slot_status),
	ROOTCTRL	=	offsetof(struct ctrl_reg, root_ctrl),
	ROOTSTATUS	=	offsetof(struct ctrl_reg, root_status),
};

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static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
{
	struct pci_dev *dev = ctrl->pci_dev;
	return pci_read_config_word(dev, ctrl->cap_base + reg, value);
}

static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
{
	struct pci_dev *dev = ctrl->pci_dev;
	return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
}

static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
{
	struct pci_dev *dev = ctrl->pci_dev;
	return pci_write_config_word(dev, ctrl->cap_base + reg, value);
}

static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
{
	struct pci_dev *dev = ctrl->pci_dev;
	return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
}
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/* Field definitions in PCI Express Capabilities Register */
#define CAP_VER			0x000F
#define DEV_PORT_TYPE		0x00F0
#define SLOT_IMPL		0x0100
#define MSG_NUM			0x3E00

/* Device or Port Type */
#define NAT_ENDPT		0x00
#define LEG_ENDPT		0x01
#define ROOT_PORT		0x04
#define UP_STREAM		0x05
#define	DN_STREAM		0x06
#define PCIE_PCI_BRDG		0x07
#define PCI_PCIE_BRDG		0x10

/* Field definitions in Device Capabilities Register */
#define DATTN_BUTTN_PRSN	0x1000
#define DATTN_LED_PRSN		0x2000
#define DPWR_LED_PRSN		0x4000

/* Field definitions in Link Capabilities Register */
#define MAX_LNK_SPEED		0x000F
#define MAX_LNK_WIDTH		0x03F0

/* Link Width Encoding */
#define LNK_X1		0x01
#define LNK_X2		0x02
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#define LNK_X4		0x04
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#define LNK_X8		0x08
#define LNK_X12		0x0C
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#define LNK_X16		0x10
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#define LNK_X32		0x20

/*Field definitions of Link Status Register */
#define LNK_SPEED	0x000F
#define NEG_LINK_WD	0x03F0
#define LNK_TRN_ERR	0x0400
#define	LNK_TRN		0x0800
#define SLOT_CLK_CONF	0x1000

/* Field definitions in Slot Capabilities Register */
#define ATTN_BUTTN_PRSN	0x00000001
#define	PWR_CTRL_PRSN	0x00000002
#define MRL_SENS_PRSN	0x00000004
#define ATTN_LED_PRSN	0x00000008
#define PWR_LED_PRSN	0x00000010
#define HP_SUPR_RM_SUP	0x00000020
#define HP_CAP		0x00000040
#define SLOT_PWR_VALUE	0x000003F8
#define SLOT_PWR_LIMIT	0x00000C00
#define PSN		0xFFF80000	/* PSN: Physical Slot Number */

/* Field definitions in Slot Control Register */
#define ATTN_BUTTN_ENABLE		0x0001
#define PWR_FAULT_DETECT_ENABLE		0x0002
#define MRL_DETECT_ENABLE		0x0004
#define PRSN_DETECT_ENABLE		0x0008
#define CMD_CMPL_INTR_ENABLE		0x0010
#define HP_INTR_ENABLE			0x0020
#define ATTN_LED_CTRL			0x00C0
#define PWR_LED_CTRL			0x0300
#define PWR_CTRL			0x0400
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#define EMI_CTRL			0x0800
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/* Attention indicator and Power indicator states */
#define LED_ON		0x01
#define LED_BLINK	0x10
#define LED_OFF		0x11

/* Power Control Command */
#define POWER_ON	0
#define POWER_OFF	0x0400

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/* EMI Status defines */
#define EMI_DISENGAGED	0
#define EMI_ENGAGED	1

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/* Field definitions in Slot Status Register */
#define ATTN_BUTTN_PRESSED	0x0001
#define PWR_FAULT_DETECTED	0x0002
#define MRL_SENS_CHANGED	0x0004
#define PRSN_DETECT_CHANGED	0x0008
#define CMD_COMPLETED		0x0010
#define MRL_STATE		0x0020
#define PRSN_STATE		0x0040
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#define EMI_STATE		0x0080
#define EMI_STATUS_BIT		7
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static irqreturn_t pcie_isr(int irq, void *dev_id);
static void start_int_poll_timer(struct controller *ctrl, int sec);
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/* This is the interrupt polling timeout function. */
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static void int_poll_timeout(unsigned long data)
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{
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	struct controller *ctrl = (struct controller *)data;
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	/* Poll for interrupt events.  regs == NULL => polling */
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	pcie_isr(0, ctrl);
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	init_timer(&ctrl->poll_timer);
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	if (!pciehp_poll_time)
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		pciehp_poll_time = 2; /* default polling interval is 2 sec */
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	start_int_poll_timer(ctrl, pciehp_poll_time);
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}

/* This function starts the interrupt polling timer. */
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static void start_int_poll_timer(struct controller *ctrl, int sec)
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{
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	/* Clamp to sane value */
	if ((sec <= 0) || (sec > 60))
        	sec = 2;

	ctrl->poll_timer.function = &int_poll_timeout;
	ctrl->poll_timer.data = (unsigned long)ctrl;
	ctrl->poll_timer.expires = jiffies + sec * HZ;
	add_timer(&ctrl->poll_timer);
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}

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static inline int pciehp_request_irq(struct controller *ctrl)
{
	int retval, irq = ctrl->pci_dev->irq;

	/* Install interrupt polling timer. Start with 10 sec delay */
	if (pciehp_poll_mode) {
		init_timer(&ctrl->poll_timer);
		start_int_poll_timer(ctrl, 10);
		return 0;
	}

	/* Installs the interrupt handler */
	retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
	if (retval)
		err("Cannot get irq %d for the hotplug controller\n", irq);
	return retval;
}

static inline void pciehp_free_irq(struct controller *ctrl)
{
	if (pciehp_poll_mode)
		del_timer_sync(&ctrl->poll_timer);
	else
		free_irq(ctrl->pci_dev->irq, ctrl);
}

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static int pcie_poll_cmd(struct controller *ctrl)
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{
	u16 slot_status;
	int timeout = 1000;

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	if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) {
		if (slot_status & CMD_COMPLETED) {
			pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED);
			return 1;
		}
	}
	while (timeout > 1000) {
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		msleep(10);
		timeout -= 10;
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		if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) {
			if (slot_status & CMD_COMPLETED) {
				pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED);
				return 1;
			}
		}
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	}
	return 0;	/* timeout */
}

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static void pcie_wait_cmd(struct controller *ctrl, int poll)
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{
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	unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
	unsigned long timeout = msecs_to_jiffies(msecs);
	int rc;

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	if (poll)
		rc = pcie_poll_cmd(ctrl);
	else
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		rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
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	if (!rc)
		dbg("Command not completed in 1000 msec\n");
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}

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/**
 * pcie_write_cmd - Issue controller command
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 * @ctrl: controller to which the command is issued
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 * @cmd:  command value written to slot control register
 * @mask: bitmask of slot control register to be modified
 */
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static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
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{
	int retval = 0;
	u16 slot_status;
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	u16 slot_ctrl;
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	mutex_lock(&ctrl->ctrl_lock);

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	retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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	if (retval) {
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		err("%s: Cannot read SLOTSTATUS register\n", __func__);
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		goto out;
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	}

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	if (slot_status & CMD_COMPLETED) {
		if (!ctrl->no_cmd_complete) {
			/*
			 * After 1 sec and CMD_COMPLETED still not set, just
			 * proceed forward to issue the next command according
			 * to spec. Just print out the error message.
			 */
			dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
			    __func__);
		} else if (!NO_CMD_CMPL(ctrl)) {
			/*
			 * This controller semms to notify of command completed
			 * event even though it supports none of power
			 * controller, attention led, power led and EMI.
			 */
			dbg("%s: Unexpected CMD_COMPLETED. Need to wait for "
			    "command completed event.\n", __func__);
			ctrl->no_cmd_complete = 0;
		} else {
			dbg("%s: Unexpected CMD_COMPLETED. Maybe the "
			    "controller is broken.\n", __func__);
		}
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	}

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	retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
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	if (retval) {
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		err("%s: Cannot read SLOTCTRL register\n", __func__);
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		goto out;
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	}

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	slot_ctrl &= ~mask;
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	slot_ctrl |= (cmd & mask);
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	ctrl->cmd_busy = 1;
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	smp_mb();
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	retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
	if (retval)
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		err("%s: Cannot write to SLOTCTRL register\n", __func__);
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	/*
	 * Wait for command completion.
	 */
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	if (!retval && !ctrl->no_cmd_complete) {
		int poll = 0;
		/*
		 * if hotplug interrupt is not enabled or command
		 * completed interrupt is not enabled, we need to poll
		 * command completed event.
		 */
		if (!(slot_ctrl & HP_INTR_ENABLE) ||
		    !(slot_ctrl & CMD_CMPL_INTR_ENABLE))
			poll = 1;
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                pcie_wait_cmd(ctrl, poll);
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	}
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	mutex_unlock(&ctrl->ctrl_lock);
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	return retval;
}

static int hpc_check_lnk_status(struct controller *ctrl)
{
	u16 lnk_status;
	int retval = 0;

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	retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
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	if (retval) {
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		err("%s: Cannot read LNKSTATUS register\n", __func__);
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		return retval;
	}

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	dbg("%s: lnk_status = %x\n", __func__, lnk_status);
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	if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
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		!(lnk_status & NEG_LINK_WD)) {
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		err("%s : Link Training Error occurs \n", __func__);
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		retval = -1;
		return retval;
	}

	return retval;
}

static int hpc_get_attention_status(struct slot *slot, u8 *status)
{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_ctrl;
	u8 atten_led_state;
	int retval = 0;

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	retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
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	if (retval) {
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		err("%s: Cannot read SLOTCTRL register\n", __func__);
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		return retval;
	}

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	dbg("%s: SLOTCTRL %x, value read %x\n",
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	    __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
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	atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;

	switch (atten_led_state) {
	case 0:
		*status = 0xFF;	/* Reserved */
		break;
	case 1:
		*status = 1;	/* On */
		break;
	case 2:
		*status = 2;	/* Blink */
		break;
	case 3:
		*status = 0;	/* Off */
		break;
	default:
		*status = 0xFF;
		break;
	}

	return 0;
}

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static int hpc_get_power_status(struct slot *slot, u8 *status)
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{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_ctrl;
	u8 pwr_state;
	int	retval = 0;

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	retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
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	if (retval) {
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		err("%s: Cannot read SLOTCTRL register\n", __func__);
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		return retval;
	}
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	dbg("%s: SLOTCTRL %x value read %x\n",
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	    __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
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	pwr_state = (slot_ctrl & PWR_CTRL) >> 10;

	switch (pwr_state) {
	case 0:
		*status = 1;
		break;
	case 1:
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		*status = 0;
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		break;
	default:
		*status = 0xFF;
		break;
	}

	return retval;
}

static int hpc_get_latch_status(struct slot *slot, u8 *status)
{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_status;
	int retval = 0;

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	retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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	if (retval) {
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		err("%s: Cannot read SLOTSTATUS register\n", __func__);
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		return retval;
	}

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	*status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
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	return 0;
}

static int hpc_get_adapter_status(struct slot *slot, u8 *status)
{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_status;
	u8 card_state;
	int retval = 0;

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	retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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	if (retval) {
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		err("%s: Cannot read SLOTSTATUS register\n", __func__);
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		return retval;
	}
	card_state = (u8)((slot_status & PRSN_STATE) >> 6);
	*status = (card_state == 1) ? 1 : 0;

	return 0;
}

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static int hpc_query_power_fault(struct slot *slot)
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{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_status;
	u8 pwr_fault;
	int retval = 0;

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	retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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	if (retval) {
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		err("%s: Cannot check for power fault\n", __func__);
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		return retval;
	}
	pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
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	return pwr_fault;
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}

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static int hpc_get_emi_status(struct slot *slot, u8 *status)
{
	struct controller *ctrl = slot->ctrl;
	u16 slot_status;
	int retval = 0;

	retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
	if (retval) {
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		err("%s : Cannot check EMI status\n", __func__);
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		return retval;
	}
	*status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;

	return retval;
}

static int hpc_toggle_emi(struct slot *slot)
{
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	u16 slot_cmd;
	u16 cmd_mask;
	int rc;
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	slot_cmd = EMI_CTRL;
	cmd_mask = EMI_CTRL;
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	rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
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	slot->last_emi_toggle = get_seconds();
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	return rc;
}

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static int hpc_set_attention_status(struct slot *slot, u8 value)
{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_cmd;
	u16 cmd_mask;
	int rc;
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	cmd_mask = ATTN_LED_CTRL;
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	switch (value) {
		case 0 :	/* turn off */
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			slot_cmd = 0x00C0;
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			break;
		case 1:		/* turn on */
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			slot_cmd = 0x0040;
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			break;
		case 2:		/* turn blink */
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			slot_cmd = 0x0080;
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			break;
		default:
			return -1;
	}
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	rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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	dbg("%s: SLOTCTRL %x write cmd %x\n",
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	    __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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	return rc;
}

static void hpc_set_green_led_on(struct slot *slot)
{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_cmd;
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	u16 cmd_mask;
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	slot_cmd = 0x0100;
	cmd_mask = PWR_LED_CTRL;
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	pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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	dbg("%s: SLOTCTRL %x write cmd %x\n",
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	    __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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}

static void hpc_set_green_led_off(struct slot *slot)
{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_cmd;
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	u16 cmd_mask;
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588 589
	slot_cmd = 0x0300;
	cmd_mask = PWR_LED_CTRL;
590
	pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
591
	dbg("%s: SLOTCTRL %x write cmd %x\n",
592
	    __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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}

static void hpc_set_green_led_blink(struct slot *slot)
{
597
	struct controller *ctrl = slot->ctrl;
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598
	u16 slot_cmd;
599
	u16 cmd_mask;
600

601 602
	slot_cmd = 0x0200;
	cmd_mask = PWR_LED_CTRL;
603
	pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
604
	dbg("%s: SLOTCTRL %x write cmd %x\n",
605
	    __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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}

static int hpc_power_on_slot(struct slot * slot)
{
610
	struct controller *ctrl = slot->ctrl;
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611
	u16 slot_cmd;
612 613
	u16 cmd_mask;
	u16 slot_status;
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614 615
	int retval = 0;

616
	dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
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617

618
	/* Clear sticky power-fault bit from previous power failures */
619 620
	retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
	if (retval) {
621
		err("%s: Cannot read SLOTSTATUS register\n", __func__);
622 623
		return retval;
	}
624
	slot_status &= PWR_FAULT_DETECTED;
625 626 627 628
	if (slot_status) {
		retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
		if (retval) {
			err("%s: Cannot write to SLOTSTATUS register\n",
629
			    __func__);
630 631 632
			return retval;
		}
	}
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633

634 635
	slot_cmd = POWER_ON;
	cmd_mask = PWR_CTRL;
636
	/* Enable detection that we turned off at slot power-off time */
637
	if (!pciehp_poll_mode) {
638 639 640 641
		slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
			     PRSN_DETECT_ENABLE);
		cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
			     PRSN_DETECT_ENABLE);
642
	}
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643

644
	retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
L
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645 646

	if (retval) {
647
		err("%s: Write %x command failed!\n", __func__, slot_cmd);
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		return -1;
	}
650
	dbg("%s: SLOTCTRL %x write cmd %x\n",
651
	    __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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	return retval;
}

656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688
static inline int pcie_mask_bad_dllp(struct controller *ctrl)
{
	struct pci_dev *dev = ctrl->pci_dev;
	int pos;
	u32 reg;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
	if (!pos)
		return 0;
	pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
	if (reg & PCI_ERR_COR_BAD_DLLP)
		return 0;
	reg |= PCI_ERR_COR_BAD_DLLP;
	pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
	return 1;
}

static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
{
	struct pci_dev *dev = ctrl->pci_dev;
	u32 reg;
	int pos;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
	if (!pos)
		return;
	pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
	if (!(reg & PCI_ERR_COR_BAD_DLLP))
		return;
	reg &= ~PCI_ERR_COR_BAD_DLLP;
	pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
}

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static int hpc_power_off_slot(struct slot * slot)
{
691
	struct controller *ctrl = slot->ctrl;
L
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692
	u16 slot_cmd;
693
	u16 cmd_mask;
L
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694
	int retval = 0;
695
	int changed;
L
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696

697
	dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
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698

699 700 701 702 703 704 705 706
	/*
	 * Set Bad DLLP Mask bit in Correctable Error Mask
	 * Register. This is the workaround against Bad DLLP error
	 * that sometimes happens during turning power off the slot
	 * which conforms to PCI Express 1.0a spec.
	 */
	changed = pcie_mask_bad_dllp(ctrl);

707 708
	slot_cmd = POWER_OFF;
	cmd_mask = PWR_CTRL;
709 710 711 712 713 714 715
	/*
	 * If we get MRL or presence detect interrupts now, the isr
	 * will notice the sticky power-fault bit too and issue power
	 * indicator change commands. This will lead to an endless loop
	 * of command completions, since the power-fault bit remains on
	 * till the slot is powered on again.
	 */
716
	if (!pciehp_poll_mode) {
717 718 719 720
		slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
			      PRSN_DETECT_ENABLE);
		cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
			     PRSN_DETECT_ENABLE);
721
	}
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723
	retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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	if (retval) {
725
		err("%s: Write command failed!\n", __func__);
726 727
		retval = -1;
		goto out;
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	}
729
	dbg("%s: SLOTCTRL %x write cmd %x\n",
730
	    __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
731
 out:
732 733 734
	if (changed)
		pcie_unmask_bad_dllp(ctrl);

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	return retval;
}

738
static irqreturn_t pcie_isr(int irq, void *dev_id)
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{
740
	struct controller *ctrl = (struct controller *)dev_id;
741
	u16 detected, intr_loc;
742
	struct slot *p_slot;
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743

744 745 746 747 748 749 750 751 752
	/*
	 * In order to guarantee that all interrupt events are
	 * serviced, we need to re-inspect Slot Status register after
	 * clearing what is presumed to be the last pending interrupt.
	 */
	intr_loc = 0;
	do {
		if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) {
			err("%s: Cannot read SLOTSTATUS\n", __func__);
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			return IRQ_NONE;
		}

756 757 758 759 760
		detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
			     MRL_SENS_CHANGED | PRSN_DETECT_CHANGED |
			     CMD_COMPLETED);
		intr_loc |= detected;
		if (!intr_loc)
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			return IRQ_NONE;
762
		if (detected && pciehp_writew(ctrl, SLOTSTATUS, detected)) {
763
			err("%s: Cannot write to SLOTSTATUS\n", __func__);
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			return IRQ_NONE;
		}
766
	} while (detected);
767

768
	dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
769

770
	/* Check Command Complete Interrupt Pending */
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	if (intr_loc & CMD_COMPLETED) {
772
		ctrl->cmd_busy = 0;
773
		smp_mb();
774
		wake_up(&ctrl->queue);
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	}

777 778 779 780 781
	if (!(intr_loc & ~CMD_COMPLETED))
		return IRQ_HANDLED;

	p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);

782
	/* Check MRL Sensor Changed */
783
	if (intr_loc & MRL_SENS_CHANGED)
784
		pciehp_handle_switch_change(p_slot);
785

786
	/* Check Attention Button Pressed */
787
	if (intr_loc & ATTN_BUTTN_PRESSED)
788
		pciehp_handle_attention_button(p_slot);
789

790
	/* Check Presence Detect Changed */
791
	if (intr_loc & PRSN_DETECT_CHANGED)
792
		pciehp_handle_presence_change(p_slot);
793

794
	/* Check Power Fault Detected */
795
	if (intr_loc & PWR_FAULT_DETECTED)
796
		pciehp_handle_power_fault(p_slot);
797

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	return IRQ_HANDLED;
}

801
static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
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{
803
	struct controller *ctrl = slot->ctrl;
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	enum pcie_link_speed lnk_speed;
	u32	lnk_cap;
	int retval = 0;

808
	retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
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809
	if (retval) {
810
		err("%s: Cannot read LNKCAP register\n", __func__);
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		return retval;
	}

	switch (lnk_cap & 0x000F) {
	case 1:
		lnk_speed = PCIE_2PT5GB;
		break;
	default:
		lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
		break;
	}

	*value = lnk_speed;
	dbg("Max link speed = %d\n", lnk_speed);
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	return retval;
}

829 830
static int hpc_get_max_lnk_width(struct slot *slot,
				 enum pcie_link_width *value)
L
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831
{
832
	struct controller *ctrl = slot->ctrl;
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833 834 835 836
	enum pcie_link_width lnk_wdth;
	u32	lnk_cap;
	int retval = 0;

837
	retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
L
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838
	if (retval) {
839
		err("%s: Cannot read LNKCAP register\n", __func__);
L
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840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874
		return retval;
	}

	switch ((lnk_cap & 0x03F0) >> 4){
	case 0:
		lnk_wdth = PCIE_LNK_WIDTH_RESRV;
		break;
	case 1:
		lnk_wdth = PCIE_LNK_X1;
		break;
	case 2:
		lnk_wdth = PCIE_LNK_X2;
		break;
	case 4:
		lnk_wdth = PCIE_LNK_X4;
		break;
	case 8:
		lnk_wdth = PCIE_LNK_X8;
		break;
	case 12:
		lnk_wdth = PCIE_LNK_X12;
		break;
	case 16:
		lnk_wdth = PCIE_LNK_X16;
		break;
	case 32:
		lnk_wdth = PCIE_LNK_X32;
		break;
	default:
		lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
		break;
	}

	*value = lnk_wdth;
	dbg("Max link width = %d\n", lnk_wdth);
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	return retval;
}

879
static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
L
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880
{
881
	struct controller *ctrl = slot->ctrl;
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882 883 884 885
	enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
	int retval = 0;
	u16 lnk_status;

886
	retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
L
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887
	if (retval) {
888
		err("%s: Cannot read LNKSTATUS register\n", __func__);
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889 890 891 892 893 894 895 896 897 898 899 900 901 902
		return retval;
	}

	switch (lnk_status & 0x0F) {
	case 1:
		lnk_speed = PCIE_2PT5GB;
		break;
	default:
		lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
		break;
	}

	*value = lnk_speed;
	dbg("Current link speed = %d\n", lnk_speed);
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903

L
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904 905 906
	return retval;
}

907 908
static int hpc_get_cur_lnk_width(struct slot *slot,
				 enum pcie_link_width *value)
L
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909
{
910
	struct controller *ctrl = slot->ctrl;
L
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911 912 913 914
	enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
	int retval = 0;
	u16 lnk_status;

915
	retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
L
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916
	if (retval) {
917
		err("%s: Cannot read LNKSTATUS register\n", __func__);
L
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918 919
		return retval;
	}
920

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Linus Torvalds 已提交
921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952
	switch ((lnk_status & 0x03F0) >> 4){
	case 0:
		lnk_wdth = PCIE_LNK_WIDTH_RESRV;
		break;
	case 1:
		lnk_wdth = PCIE_LNK_X1;
		break;
	case 2:
		lnk_wdth = PCIE_LNK_X2;
		break;
	case 4:
		lnk_wdth = PCIE_LNK_X4;
		break;
	case 8:
		lnk_wdth = PCIE_LNK_X8;
		break;
	case 12:
		lnk_wdth = PCIE_LNK_X12;
		break;
	case 16:
		lnk_wdth = PCIE_LNK_X16;
		break;
	case 32:
		lnk_wdth = PCIE_LNK_X32;
		break;
	default:
		lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
		break;
	}

	*value = lnk_wdth;
	dbg("Current link width = %d\n", lnk_wdth);
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L
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954 955 956
	return retval;
}

957
static void pcie_release_ctrl(struct controller *ctrl);
L
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958 959 960 961 962 963 964 965
static struct hpc_ops pciehp_hpc_ops = {
	.power_on_slot			= hpc_power_on_slot,
	.power_off_slot			= hpc_power_off_slot,
	.set_attention_status		= hpc_set_attention_status,
	.get_power_status		= hpc_get_power_status,
	.get_attention_status		= hpc_get_attention_status,
	.get_latch_status		= hpc_get_latch_status,
	.get_adapter_status		= hpc_get_adapter_status,
966 967
	.get_emi_status			= hpc_get_emi_status,
	.toggle_emi			= hpc_toggle_emi,
L
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968 969 970 971 972

	.get_max_bus_speed		= hpc_get_max_lnk_speed,
	.get_cur_bus_speed		= hpc_get_cur_lnk_speed,
	.get_max_lnk_width		= hpc_get_max_lnk_width,
	.get_cur_lnk_width		= hpc_get_cur_lnk_width,
973

L
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974 975 976 977
	.query_power_fault		= hpc_query_power_fault,
	.green_led_on			= hpc_set_green_led_on,
	.green_led_off			= hpc_set_green_led_off,
	.green_led_blink		= hpc_set_green_led_blink,
978

979
	.release_ctlr			= pcie_release_ctrl,
L
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980 981 982
	.check_lnk_status		= hpc_check_lnk_status,
};

983
int pcie_enable_notification(struct controller *ctrl)
M
Mark Lord 已提交
984
{
985
	u16 cmd, mask;
L
Linus Torvalds 已提交
986

987
	cmd = PRSN_DETECT_ENABLE;
988
	if (ATTN_BUTTN(ctrl))
989
		cmd |= ATTN_BUTTN_ENABLE;
990
	if (POWER_CTRL(ctrl))
991
		cmd |= PWR_FAULT_DETECT_ENABLE;
992
	if (MRL_SENS(ctrl))
993 994
		cmd |= MRL_DETECT_ENABLE;
	if (!pciehp_poll_mode)
995
		cmd |= HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE;
996

997 998
	mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE |
	       PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE;
999 1000 1001

	if (pcie_write_cmd(ctrl, cmd, mask)) {
		err("%s: Cannot enable software notification\n", __func__);
1002
		return -1;
L
Linus Torvalds 已提交
1003
	}
1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046
	return 0;
}

static void pcie_disable_notification(struct controller *ctrl)
{
	u16 mask;
	mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE |
	       PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE;
	if (pcie_write_cmd(ctrl, 0, mask))
		warn("%s: Cannot disable software notification\n", __func__);
}

static int pcie_init_notification(struct controller *ctrl)
{
	if (pciehp_request_irq(ctrl))
		return -1;
	if (pcie_enable_notification(ctrl)) {
		pciehp_free_irq(ctrl);
		return -1;
	}
	return 0;
}

static void pcie_shutdown_notification(struct controller *ctrl)
{
	pcie_disable_notification(ctrl);
	pciehp_free_irq(ctrl);
}

static int pcie_init_slot(struct controller *ctrl)
{
	struct slot *slot;

	slot = kzalloc(sizeof(*slot), GFP_KERNEL);
	if (!slot)
		return -ENOMEM;

	slot->hp_slot = 0;
	slot->ctrl = ctrl;
	slot->bus = ctrl->pci_dev->subordinate->number;
	slot->device = ctrl->slot_device_offset + slot->hp_slot;
	slot->hpc_ops = ctrl->hpc_ops;
	slot->number = ctrl->first_slot;
1047
	snprintf(slot->name, SLOT_NAME_SIZE, "%d", slot->number);
1048 1049 1050
	mutex_init(&slot->lock);
	INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
	list_add(&slot->slot_list, &ctrl->slot_list);
L
Linus Torvalds 已提交
1051 1052
	return 0;
}
1053

1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064
static void pcie_cleanup_slot(struct controller *ctrl)
{
	struct slot *slot;
	slot = list_first_entry(&ctrl->slot_list, struct slot, slot_list);
	list_del(&slot->slot_list);
	cancel_delayed_work(&slot->work);
	flush_scheduled_work();
	flush_workqueue(pciehp_wq);
	kfree(slot);
}

K
Kenji Kaneshige 已提交
1065
static inline void dbg_ctrl(struct controller *ctrl)
1066
{
K
Kenji Kaneshige 已提交
1067 1068 1069
	int i;
	u16 reg16;
	struct pci_dev *pdev = ctrl->pci_dev;
1070

K
Kenji Kaneshige 已提交
1071 1072
	if (!pciehp_debug)
		return;
1073

K
Kenji Kaneshige 已提交
1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086
	dbg("Hotplug Controller:\n");
	dbg("  Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq);
	dbg("  Vendor ID            : 0x%04x\n", pdev->vendor);
	dbg("  Device ID            : 0x%04x\n", pdev->device);
	dbg("  Subsystem ID         : 0x%04x\n", pdev->subsystem_device);
	dbg("  Subsystem Vendor ID  : 0x%04x\n", pdev->subsystem_vendor);
	dbg("  PCIe Cap offset      : 0x%02x\n", ctrl->cap_base);
	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
		if (!pci_resource_len(pdev, i))
			continue;
		dbg("  PCI resource [%d]     : 0x%llx@0x%llx\n", i,
		    (unsigned long long)pci_resource_len(pdev, i),
		    (unsigned long long)pci_resource_start(pdev, i));
1087
	}
K
Kenji Kaneshige 已提交
1088 1089 1090 1091 1092 1093 1094 1095 1096
	dbg("Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
	dbg("  Physical Slot Number : %d\n", ctrl->first_slot);
	dbg("  Attention Button     : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no");
	dbg("  Power Controller     : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no");
	dbg("  MRL Sensor           : %3s\n", MRL_SENS(ctrl)   ? "yes" : "no");
	dbg("  Attention Indicator  : %3s\n", ATTN_LED(ctrl)   ? "yes" : "no");
	dbg("  Power Indicator      : %3s\n", PWR_LED(ctrl)    ? "yes" : "no");
	dbg("  Hot-Plug Surprise    : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no");
	dbg("  EMI Present          : %3s\n", EMI(ctrl)        ? "yes" : "no");
1097
	dbg("  Command Completed    : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes");
K
Kenji Kaneshige 已提交
1098 1099
	pciehp_readw(ctrl, SLOTSTATUS, &reg16);
	dbg("Slot Status            : 0x%04x\n", reg16);
1100
	pciehp_readw(ctrl, SLOTCTRL, &reg16);
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Kenji Kaneshige 已提交
1101 1102
	dbg("Slot Control           : 0x%04x\n", reg16);
}
1103

1104
struct controller *pcie_init(struct pcie_device *dev)
K
Kenji Kaneshige 已提交
1105
{
1106
	struct controller *ctrl;
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1107 1108
	u32 slot_cap;
	struct pci_dev *pdev = dev->port;
1109

1110 1111 1112 1113 1114 1115 1116
	ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
	if (!ctrl) {
		err("%s : out of memory\n", __func__);
		goto abort;
	}
	INIT_LIST_HEAD(&ctrl->slot_list);

K
Kenji Kaneshige 已提交
1117 1118 1119 1120
	ctrl->pci_dev = pdev;
	ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
	if (!ctrl->cap_base) {
		err("%s: Cannot find PCI Express capability\n", __func__);
1121 1122
		goto abort;
	}
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Kenji Kaneshige 已提交
1123
	if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) {
1124
		err("%s: Cannot read SLOTCAP register\n", __func__);
1125 1126 1127
		goto abort;
	}

K
Kenji Kaneshige 已提交
1128 1129 1130 1131 1132
	ctrl->slot_cap = slot_cap;
	ctrl->first_slot = slot_cap >> 19;
	ctrl->slot_device_offset = 0;
	ctrl->num_slots = 1;
	ctrl->hpc_ops = &pciehp_hpc_ops;
1133 1134 1135
	mutex_init(&ctrl->crit_sect);
	mutex_init(&ctrl->ctrl_lock);
	init_waitqueue_head(&ctrl->queue);
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Kenji Kaneshige 已提交
1136
	dbg_ctrl(ctrl);
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1137 1138 1139 1140 1141 1142 1143 1144 1145
	/*
	 * Controller doesn't notify of command completion if the "No
	 * Command Completed Support" bit is set in Slot Capability
	 * register or the controller supports none of power
	 * controller, attention led, power led and EMI.
	 */
	if (NO_CMD_CMPL(ctrl) ||
	    !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
	    ctrl->no_cmd_complete = 1;
1146

1147 1148 1149
	/* Clear all remaining event bits in Slot Status register */
	if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f))
		goto abort_ctrl;
1150

1151 1152
	/* Disable sotfware notification */
	pcie_disable_notification(ctrl);
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1153 1154 1155 1156 1157 1158 1159

	/*
	 * If this is the first controller to be initialized,
	 * initialize the pciehp work queue
	 */
	if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
		pciehp_wq = create_singlethread_workqueue("pciehpd");
1160 1161
		if (!pciehp_wq)
			goto abort_ctrl;
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1162 1163
	}

1164 1165 1166 1167 1168 1169
	info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
	     pdev->vendor, pdev->device,
	     pdev->subsystem_vendor, pdev->subsystem_device);

	if (pcie_init_slot(ctrl))
		goto abort_ctrl;
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Kenji Kaneshige 已提交
1170

1171 1172
	if (pcie_init_notification(ctrl))
		goto abort_slot;
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Kenji Kaneshige 已提交
1173

1174 1175 1176 1177 1178 1179
	return ctrl;

abort_slot:
	pcie_cleanup_slot(ctrl);
abort_ctrl:
	kfree(ctrl);
1180
abort:
1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194
	return NULL;
}

void pcie_release_ctrl(struct controller *ctrl)
{
	pcie_shutdown_notification(ctrl);
	pcie_cleanup_slot(ctrl);
	/*
	 * If this is the last controller to be released, destroy the
	 * pciehp work queue
	 */
	if (atomic_dec_and_test(&pciehp_num_controllers))
		destroy_workqueue(pciehp_wq);
	kfree(ctrl);
1195
}