savagefb_driver.c 64.9 KB
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/*
 * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
 *
 * Copyright (c) 2001-2002  Denis Oliver Kropp <dok@directfb.org>
 *                          Sven Neumann <neo@directfb.org>
 *
 *
 * Card specific code is based on XFree86's savage driver.
 * Framebuffer framework code is based on code of cyber2000fb and tdfxfb.
 *
 * This file is subject to the terms and conditions of the GNU General
 * Public License.  See the file COPYING in the main directory of this
 * archive for more details.
 *
 * 0.4.0 (neo)
 *  - hardware accelerated clear and move
 *
 * 0.3.2 (dok)
 *  - wait for vertical retrace before writing to cr67
 *    at the beginning of savagefb_set_par
 *  - use synchronization registers cr23 and cr26
 *
 * 0.3.1 (dok)
 *  - reset 3D engine
 *  - don't return alpha bits for 32bit format
 *
 * 0.3.0 (dok)
 *  - added WaitIdle functions for all Savage types
 *  - do WaitIdle before mode switching
 *  - code cleanup
 *
 * 0.2.0 (dok)
 *  - first working version
 *
 *
 * TODO
 * - clock validations in decode_var
 *
 * BUGS
 * - white margin on bootup
 *
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/console.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pgtable.h>

#ifdef CONFIG_MTRR
#include <asm/mtrr.h>
#endif

#include "savagefb.h"


#define SAVAGEFB_VERSION "0.4.0_2.6"

/* --------------------------------------------------------------------- */


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static char *mode_option __devinitdata = NULL;
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#ifdef MODULE

MODULE_AUTHOR("(c) 2001-2002  Denis Oliver Kropp <dok@directfb.org>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips");

#endif


/* --------------------------------------------------------------------- */

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static void vgaHWSeqReset(struct savagefb_par *par, int start)
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{
	if (start)
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		VGAwSEQ(0x00, 0x01, par);	/* Synchronous Reset */
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	else
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		VGAwSEQ(0x00, 0x03, par);	/* End Reset */
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}

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static void vgaHWProtect(struct savagefb_par *par, int on)
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{
	unsigned char tmp;

	if (on) {
		/*
		 * Turn off screen and disable sequencer.
		 */
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		tmp = VGArSEQ(0x01, par);
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		vgaHWSeqReset(par, 1);	        /* start synchronous reset */
		VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */
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		VGAenablePalette(par);
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	} else {
		/*
		 * Reenable sequencer, then turn on screen.
		 */

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		tmp = VGArSEQ(0x01, par);
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		VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */
		vgaHWSeqReset(par, 0);	        /* clear synchronous reset */
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		VGAdisablePalette(par);
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	}
}

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static void vgaHWRestore(struct savagefb_par  *par, struct savage_reg *reg)
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{
	int i;

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	VGAwMISC(reg->MiscOutReg, par);
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	for (i = 1; i < 5; i++)
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		VGAwSEQ(i, reg->Sequencer[i], par);
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	/* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
	   CRTC[17] */
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	VGAwCR(17, reg->CRTC[17] & ~0x80, par);
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	for (i = 0; i < 25; i++)
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		VGAwCR(i, reg->CRTC[i], par);
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	for (i = 0; i < 9; i++)
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		VGAwGR(i, reg->Graphics[i], par);
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	VGAenablePalette(par);
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	for (i = 0; i < 21; i++)
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		VGAwATTR(i, reg->Attribute[i], par);
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	VGAdisablePalette(par);
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}

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static void vgaHWInit(struct fb_var_screeninfo *var,
		      struct savagefb_par            *par,
		      struct xtimings                *timings,
		      struct savage_reg              *reg)
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{
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	reg->MiscOutReg = 0x23;
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	if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
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		reg->MiscOutReg |= 0x40;
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	if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
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		reg->MiscOutReg |= 0x80;
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	/*
	 * Time Sequencer
	 */
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	reg->Sequencer[0x00] = 0x00;
	reg->Sequencer[0x01] = 0x01;
	reg->Sequencer[0x02] = 0x0F;
	reg->Sequencer[0x03] = 0x00;          /* Font select */
	reg->Sequencer[0x04] = 0x0E;          /* Misc */
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	/*
	 * CRTC Controller
	 */
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	reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
	reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
	reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
	reg->CRTC[0x03] = (((timings->HSyncEnd >> 3)  - 1) & 0x1f) | 0x80;
	reg->CRTC[0x04] = (timings->HSyncStart >> 3);
	reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
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		(((timings->HSyncEnd >> 3)) & 0x1f);
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	reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
	reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
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		(((timings->VDisplay - 1) & 0x100) >> 7) |
		((timings->VSyncStart & 0x100) >> 6) |
		(((timings->VSyncStart - 1) & 0x100) >> 5) |
		0x10 |
		(((timings->VTotal - 2) & 0x200) >> 4) |
		(((timings->VDisplay - 1) & 0x200) >> 3) |
		((timings->VSyncStart & 0x200) >> 2);
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	reg->CRTC[0x08] = 0x00;
	reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
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	if (timings->dblscan)
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		reg->CRTC[0x09] |= 0x80;

	reg->CRTC[0x0a] = 0x00;
	reg->CRTC[0x0b] = 0x00;
	reg->CRTC[0x0c] = 0x00;
	reg->CRTC[0x0d] = 0x00;
	reg->CRTC[0x0e] = 0x00;
	reg->CRTC[0x0f] = 0x00;
	reg->CRTC[0x10] = timings->VSyncStart & 0xff;
	reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
	reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
	reg->CRTC[0x13] = var->xres_virtual >> 4;
	reg->CRTC[0x14] = 0x00;
	reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
	reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
	reg->CRTC[0x17] = 0xc3;
	reg->CRTC[0x18] = 0xff;
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	/*
	 * are these unnecessary?
	 * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
	 * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
	 */

	/*
	 * Graphics Display Controller
	 */
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	reg->Graphics[0x00] = 0x00;
	reg->Graphics[0x01] = 0x00;
	reg->Graphics[0x02] = 0x00;
	reg->Graphics[0x03] = 0x00;
	reg->Graphics[0x04] = 0x00;
	reg->Graphics[0x05] = 0x40;
	reg->Graphics[0x06] = 0x05;   /* only map 64k VGA memory !!!! */
	reg->Graphics[0x07] = 0x0F;
	reg->Graphics[0x08] = 0xFF;


	reg->Attribute[0x00]  = 0x00; /* standard colormap translation */
	reg->Attribute[0x01]  = 0x01;
	reg->Attribute[0x02]  = 0x02;
	reg->Attribute[0x03]  = 0x03;
	reg->Attribute[0x04]  = 0x04;
	reg->Attribute[0x05]  = 0x05;
	reg->Attribute[0x06]  = 0x06;
	reg->Attribute[0x07]  = 0x07;
	reg->Attribute[0x08]  = 0x08;
	reg->Attribute[0x09]  = 0x09;
	reg->Attribute[0x0a] = 0x0A;
	reg->Attribute[0x0b] = 0x0B;
	reg->Attribute[0x0c] = 0x0C;
	reg->Attribute[0x0d] = 0x0D;
	reg->Attribute[0x0e] = 0x0E;
	reg->Attribute[0x0f] = 0x0F;
	reg->Attribute[0x10] = 0x41;
	reg->Attribute[0x11] = 0xFF;
	reg->Attribute[0x12] = 0x0F;
	reg->Attribute[0x13] = 0x00;
	reg->Attribute[0x14] = 0x00;
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}

/* -------------------- Hardware specific routines ------------------------- */

/*
 * Hardware Acceleration for SavageFB
 */

/* Wait for fifo space */
static void
savage3D_waitfifo(struct savagefb_par *par, int space)
{
	int slots = MAXFIFO - space;

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	while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots);
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}

static void
savage4_waitfifo(struct savagefb_par *par, int space)
{
	int slots = MAXFIFO - space;

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	while ((savage_in32(0x48C60, par) & 0x001fffff) > slots);
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}

static void
savage2000_waitfifo(struct savagefb_par *par, int space)
{
	int slots = MAXFIFO - space;

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	while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots);
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}

/* Wait for idle accelerator */
static void
savage3D_waitidle(struct savagefb_par *par)
{
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	while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000);
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}

static void
savage4_waitidle(struct savagefb_par *par)
{
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	while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000);
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}

static void
savage2000_waitidle(struct savagefb_par *par)
{
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	while ((savage_in32(0x48C60, par) & 0x009fffff));
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}

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#ifdef CONFIG_FB_SAVAGE_ACCEL
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static void
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SavageSetup2DEngine(struct savagefb_par  *par)
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{
	unsigned long GlobalBitmapDescriptor;

	GlobalBitmapDescriptor = 1 | 8 | BCI_BD_BW_DISABLE;
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	BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth);
	BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth);
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	switch(par->chip) {
	case S3_SAVAGE3D:
	case S3_SAVAGE_MX:
		/* Disable BCI */
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		savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
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		/* Setup BCI command overflow buffer */
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		savage_out32(0x48C14,
			     (par->cob_offset >> 11) | (par->cob_index << 29),
			     par);
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		/* Program shadow status update. */
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		savage_out32(0x48C10, 0x78207220, par);
		savage_out32(0x48C0C, 0, par);
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		/* Enable BCI and command overflow buffer */
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		savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
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		break;
	case S3_SAVAGE4:
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	case S3_TWISTER:
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	case S3_PROSAVAGE:
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	case S3_PROSAVAGEDDR:
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	case S3_SUPERSAVAGE:
		/* Disable BCI */
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		savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
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		/* Program shadow status update */
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		savage_out32(0x48C10, 0x00700040, par);
		savage_out32(0x48C0C, 0, par);
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		/* Enable BCI without the COB */
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		savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
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		break;
	case S3_SAVAGE2000:
		/* Disable BCI */
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		savage_out32(0x48C18, 0, par);
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		/* Setup BCI command overflow buffer */
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		savage_out32(0x48C18,
			     (par->cob_offset >> 7) | (par->cob_index),
			     par);
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		/* Disable shadow status update */
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		savage_out32(0x48A30, 0, par);
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		/* Enable BCI and command overflow buffer */
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		savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
			     par);
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		break;
	    default:
		break;
	}
	/* Turn on 16-bit register access. */
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	vga_out8(0x3d4, 0x31, par);
	vga_out8(0x3d5, 0x0c, par);
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	/* Set stride to use GBD. */
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	vga_out8(0x3d4, 0x50, par);
	vga_out8(0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
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	/* Enable 2D engine. */
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	vga_out8(0x3d4, 0x40, par);
	vga_out8(0x3d5, 0x01, par);
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	savage_out32(MONO_PAT_0, ~0, par);
	savage_out32(MONO_PAT_1, ~0, par);
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	/* Setup plane masks */
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	savage_out32(0x8128, ~0, par); /* enable all write planes */
	savage_out32(0x812C, ~0, par); /* enable all read planes */
	savage_out16(0x8134, 0x27, par);
	savage_out16(0x8136, 0x07, par);
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	/* Now set the GBD */
	par->bci_ptr = 0;
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	par->SavageWaitFifo(par, 4);
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	BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
	BCI_SEND(0);
	BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
	BCI_SEND(GlobalBitmapDescriptor);
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	/*
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	 * I don't know why, sending this twice fixes the initial black screen,
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	 * prevents X from crashing at least in Toshiba laptops with SavageIX.
	 * --Tony
	 */
	par->bci_ptr = 0;
	par->SavageWaitFifo(par, 4);

	BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
	BCI_SEND(0);
	BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
	BCI_SEND(GlobalBitmapDescriptor);
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}

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static void savagefb_set_clip(struct fb_info *info)
{
	struct savagefb_par *par = info->par;
	int cmd;

	cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
	par->bci_ptr = 0;
	par->SavageWaitFifo(par,3);
	BCI_SEND(cmd);
	BCI_SEND(BCI_CLIP_TL(0, 0));
	BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
}
#else
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static void SavageSetup2DEngine(struct savagefb_par  *par) {}
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#endif
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static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1,
			    int min_n2, int max_n2, long freq_min,
			    long freq_max, unsigned int *mdiv,
			    unsigned int *ndiv, unsigned int *r)
{
	long diff, best_diff;
	unsigned int m;
	unsigned char n1, n2, best_n1=16+2, best_n2=2, best_m=125+2;

	if (freq < freq_min / (1 << max_n2)) {
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		printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
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		freq = freq_min / (1 << max_n2);
	}
	if (freq > freq_max / (1 << min_n2)) {
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		printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
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		freq = freq_max / (1 << min_n2);
	}

	/* work out suitable timings */
	best_diff = freq;

	for (n2=min_n2; n2<=max_n2; n2++) {
		for (n1=min_n1+2; n1<=max_n1+2; n1++) {
			m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
				BASE_FREQ;
			if (m < min_m+2 || m > 127+2)
				continue;
			if ((m * BASE_FREQ >= freq_min * n1) &&
			    (m * BASE_FREQ <= freq_max * n1)) {
				diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
				if (diff < 0)
					diff = -diff;
				if (diff < best_diff) {
					best_diff = diff;
					best_m = m;
					best_n1 = n1;
					best_n2 = n2;
				}
			}
		}
	}

	*ndiv = best_n1 - 2;
	*r = best_n2;
	*mdiv = best_m - 2;
}

static int common_calc_clock(long freq, int min_m, int min_n1, int max_n1,
			     int min_n2, int max_n2, long freq_min,
			     long freq_max, unsigned char *mdiv,
			     unsigned char *ndiv)
{
	long diff, best_diff;
	unsigned int m;
	unsigned char n1, n2;
	unsigned char best_n1 = 16+2, best_n2 = 2, best_m = 125+2;

	best_diff = freq;

	for (n2 = min_n2; n2 <= max_n2; n2++) {
		for (n1 = min_n1+2; n1 <= max_n1+2; n1++) {
			m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
				BASE_FREQ;
			if (m < min_m + 2 || m > 127+2)
				continue;
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			if ((m * BASE_FREQ >= freq_min * n1) &&
			    (m * BASE_FREQ <= freq_max * n1)) {
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				diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
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				if (diff < 0)
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					diff = -diff;
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				if (diff < best_diff) {
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					best_diff = diff;
					best_m = m;
					best_n1 = n1;
					best_n2 = n2;
				}
			}
		}
	}

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	if (max_n1 == 63)
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		*ndiv = (best_n1 - 2) | (best_n2 << 6);
	else
		*ndiv = (best_n1 - 2) | (best_n2 << 5);

	*mdiv = best_m - 2;

	return 0;
}

#ifdef SAVAGEFB_DEBUG
/* This function is used to debug, it prints out the contents of s3 regs */

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static void SavagePrintRegs(struct savagefb_par *par)
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{
	unsigned char i;
	int vgaCRIndex = 0x3d4;
	int vgaCRReg = 0x3d5;

	printk(KERN_DEBUG "SR    x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE "
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	       "xF");
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	for (i = 0; i < 0x70; i++) {
		if (!(i % 16))
			printk(KERN_DEBUG "\nSR%xx ", i >> 4);
		vga_out8(0x3c4, i, par);
		printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par));
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	}

	printk(KERN_DEBUG "\n\nCR    x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
529
	       "xD xE xF");
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531 532 533 534 535
	for (i = 0; i < 0xB7; i++) {
		if (!(i % 16))
			printk(KERN_DEBUG "\nCR%xx ", i >> 4);
		vga_out8(vgaCRIndex, i, par);
		printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par));
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	}

	printk(KERN_DEBUG "\n\n");
}
#endif

/* --------------------------------------------------------------------- */

544
static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
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{
	unsigned char cr3a, cr53, cr66;

548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570
	vga_out16(0x3d4, 0x4838, par);
	vga_out16(0x3d4, 0xa039, par);
	vga_out16(0x3c4, 0x0608, par);

	vga_out8(0x3d4, 0x66, par);
	cr66 = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr66 | 0x80, par);
	vga_out8(0x3d4, 0x3a, par);
	cr3a = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr3a | 0x80, par);
	vga_out8(0x3d4, 0x53, par);
	cr53 = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr53 & 0x7f, par);

	vga_out8(0x3d4, 0x66, par);
	vga_out8(0x3d5, cr66, par);
	vga_out8(0x3d4, 0x3a, par);
	vga_out8(0x3d5, cr3a, par);

	vga_out8(0x3d4, 0x66, par);
	vga_out8(0x3d5, cr66, par);
	vga_out8(0x3d4, 0x3a, par);
	vga_out8(0x3d5, cr3a, par);
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	/* unlock extended seq regs */
573 574 575
	vga_out8(0x3c4, 0x08, par);
	reg->SR08 = vga_in8(0x3c5, par);
	vga_out8(0x3c5, 0x06, par);
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	/* now save all the extended regs we need */
578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626
	vga_out8(0x3d4, 0x31, par);
	reg->CR31 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x32, par);
	reg->CR32 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x34, par);
	reg->CR34 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x36, par);
	reg->CR36 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x3a, par);
	reg->CR3A = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x40, par);
	reg->CR40 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x42, par);
	reg->CR42 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x45, par);
	reg->CR45 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x50, par);
	reg->CR50 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x51, par);
	reg->CR51 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x53, par);
	reg->CR53 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x58, par);
	reg->CR58 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x60, par);
	reg->CR60 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x66, par);
	reg->CR66 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x67, par);
	reg->CR67 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x68, par);
	reg->CR68 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x69, par);
	reg->CR69 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x6f, par);
	reg->CR6F = vga_in8(0x3d5, par);

	vga_out8(0x3d4, 0x33, par);
	reg->CR33 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x86, par);
	reg->CR86 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x88, par);
	reg->CR88 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x90, par);
	reg->CR90 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x91, par);
	reg->CR91 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0xb0, par);
	reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
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	/* extended mode timing regs */
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	vga_out8(0x3d4, 0x3b, par);
	reg->CR3B = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x3c, par);
	reg->CR3C = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x43, par);
	reg->CR43 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x5d, par);
	reg->CR5D = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x5e, par);
	reg->CR5E = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x65, par);
	reg->CR65 = vga_in8(0x3d5, par);
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	/* save seq extended regs for DCLK PLL programming */
643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663
	vga_out8(0x3c4, 0x0e, par);
	reg->SR0E = vga_in8(0x3c5, par);
	vga_out8(0x3c4, 0x0f, par);
	reg->SR0F = vga_in8(0x3c5, par);
	vga_out8(0x3c4, 0x10, par);
	reg->SR10 = vga_in8(0x3c5, par);
	vga_out8(0x3c4, 0x11, par);
	reg->SR11 = vga_in8(0x3c5, par);
	vga_out8(0x3c4, 0x12, par);
	reg->SR12 = vga_in8(0x3c5, par);
	vga_out8(0x3c4, 0x13, par);
	reg->SR13 = vga_in8(0x3c5, par);
	vga_out8(0x3c4, 0x29, par);
	reg->SR29 = vga_in8(0x3c5, par);

	vga_out8(0x3c4, 0x15, par);
	reg->SR15 = vga_in8(0x3c5, par);
	vga_out8(0x3c4, 0x30, par);
	reg->SR30 = vga_in8(0x3c5, par);
	vga_out8(0x3c4, 0x18, par);
	reg->SR18 = vga_in8(0x3c5, par);
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	/* Save flat panel expansion regsters. */
	if (par->chip == S3_SAVAGE_MX) {
		int i;

		for (i = 0; i < 8; i++) {
670 671
			vga_out8(0x3c4, 0x54+i, par);
			reg->SR54[i] = vga_in8(0x3c5, par);
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		}
	}

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	vga_out8(0x3d4, 0x66, par);
	cr66 = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr66 | 0x80, par);
	vga_out8(0x3d4, 0x3a, par);
	cr3a = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr3a | 0x80, par);
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	/* now save MIU regs */
	if (par->chip != S3_SAVAGE_MX) {
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		reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
		reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
		reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
		reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
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	}

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	vga_out8(0x3d4, 0x3a, par);
	vga_out8(0x3d5, cr3a, par);
	vga_out8(0x3d4, 0x66, par);
	vga_out8(0x3d5, cr66, par);
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}

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static void savage_set_default_par(struct savagefb_par *par,
				struct savage_reg *reg)
{
	unsigned char cr3a, cr53, cr66;

	vga_out16(0x3d4, 0x4838, par);
	vga_out16(0x3d4, 0xa039, par);
	vga_out16(0x3c4, 0x0608, par);

	vga_out8(0x3d4, 0x66, par);
	cr66 = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr66 | 0x80, par);
	vga_out8(0x3d4, 0x3a, par);
	cr3a = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr3a | 0x80, par);
	vga_out8(0x3d4, 0x53, par);
	cr53 = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr53 & 0x7f, par);

	vga_out8(0x3d4, 0x66, par);
	vga_out8(0x3d5, cr66, par);
	vga_out8(0x3d4, 0x3a, par);
	vga_out8(0x3d5, cr3a, par);

	vga_out8(0x3d4, 0x66, par);
	vga_out8(0x3d5, cr66, par);
	vga_out8(0x3d4, 0x3a, par);
	vga_out8(0x3d5, cr3a, par);

	/* unlock extended seq regs */
	vga_out8(0x3c4, 0x08, par);
	vga_out8(0x3c5, reg->SR08, par);
	vga_out8(0x3c5, 0x06, par);

	/* now restore all the extended regs we need */
	vga_out8(0x3d4, 0x31, par);
	vga_out8(0x3d5, reg->CR31, par);
	vga_out8(0x3d4, 0x32, par);
	vga_out8(0x3d5, reg->CR32, par);
	vga_out8(0x3d4, 0x34, par);
	vga_out8(0x3d5, reg->CR34, par);
	vga_out8(0x3d4, 0x36, par);
	vga_out8(0x3d5,reg->CR36, par);
	vga_out8(0x3d4, 0x3a, par);
	vga_out8(0x3d5, reg->CR3A, par);
	vga_out8(0x3d4, 0x40, par);
	vga_out8(0x3d5, reg->CR40, par);
	vga_out8(0x3d4, 0x42, par);
	vga_out8(0x3d5, reg->CR42, par);
	vga_out8(0x3d4, 0x45, par);
	vga_out8(0x3d5, reg->CR45, par);
	vga_out8(0x3d4, 0x50, par);
	vga_out8(0x3d5, reg->CR50, par);
	vga_out8(0x3d4, 0x51, par);
	vga_out8(0x3d5, reg->CR51, par);
	vga_out8(0x3d4, 0x53, par);
	vga_out8(0x3d5, reg->CR53, par);
	vga_out8(0x3d4, 0x58, par);
	vga_out8(0x3d5, reg->CR58, par);
	vga_out8(0x3d4, 0x60, par);
	vga_out8(0x3d5, reg->CR60, par);
	vga_out8(0x3d4, 0x66, par);
	vga_out8(0x3d5, reg->CR66, par);
	vga_out8(0x3d4, 0x67, par);
	vga_out8(0x3d5, reg->CR67, par);
	vga_out8(0x3d4, 0x68, par);
	vga_out8(0x3d5, reg->CR68, par);
	vga_out8(0x3d4, 0x69, par);
	vga_out8(0x3d5, reg->CR69, par);
	vga_out8(0x3d4, 0x6f, par);
	vga_out8(0x3d5, reg->CR6F, par);

	vga_out8(0x3d4, 0x33, par);
	vga_out8(0x3d5, reg->CR33, par);
	vga_out8(0x3d4, 0x86, par);
	vga_out8(0x3d5, reg->CR86, par);
	vga_out8(0x3d4, 0x88, par);
	vga_out8(0x3d5, reg->CR88, par);
	vga_out8(0x3d4, 0x90, par);
	vga_out8(0x3d5, reg->CR90, par);
	vga_out8(0x3d4, 0x91, par);
	vga_out8(0x3d5, reg->CR91, par);
	vga_out8(0x3d4, 0xb0, par);
	vga_out8(0x3d5, reg->CRB0, par);

	/* extended mode timing regs */
	vga_out8(0x3d4, 0x3b, par);
	vga_out8(0x3d5, reg->CR3B, par);
	vga_out8(0x3d4, 0x3c, par);
	vga_out8(0x3d5, reg->CR3C, par);
	vga_out8(0x3d4, 0x43, par);
	vga_out8(0x3d5, reg->CR43, par);
	vga_out8(0x3d4, 0x5d, par);
	vga_out8(0x3d5, reg->CR5D, par);
	vga_out8(0x3d4, 0x5e, par);
	vga_out8(0x3d5, reg->CR5E, par);
	vga_out8(0x3d4, 0x65, par);
	vga_out8(0x3d5, reg->CR65, par);

	/* save seq extended regs for DCLK PLL programming */
	vga_out8(0x3c4, 0x0e, par);
	vga_out8(0x3c5, reg->SR0E, par);
	vga_out8(0x3c4, 0x0f, par);
	vga_out8(0x3c5, reg->SR0F, par);
	vga_out8(0x3c4, 0x10, par);
	vga_out8(0x3c5, reg->SR10, par);
	vga_out8(0x3c4, 0x11, par);
	vga_out8(0x3c5, reg->SR11, par);
	vga_out8(0x3c4, 0x12, par);
	vga_out8(0x3c5, reg->SR12, par);
	vga_out8(0x3c4, 0x13, par);
	vga_out8(0x3c5, reg->SR13, par);
	vga_out8(0x3c4, 0x29, par);
	vga_out8(0x3c5, reg->SR29, par);

	vga_out8(0x3c4, 0x15, par);
	vga_out8(0x3c5, reg->SR15, par);
	vga_out8(0x3c4, 0x30, par);
	vga_out8(0x3c5, reg->SR30, par);
	vga_out8(0x3c4, 0x18, par);
	vga_out8(0x3c5, reg->SR18, par);

	/* Save flat panel expansion regsters. */
	if (par->chip == S3_SAVAGE_MX) {
		int i;

		for (i = 0; i < 8; i++) {
			vga_out8(0x3c4, 0x54+i, par);
			vga_out8(0x3c5, reg->SR54[i], par);
		}
	}

	vga_out8(0x3d4, 0x66, par);
	cr66 = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr66 | 0x80, par);
	vga_out8(0x3d4, 0x3a, par);
	cr3a = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr3a | 0x80, par);

	/* now save MIU regs */
	if (par->chip != S3_SAVAGE_MX) {
		savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
		savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
		savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
		savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
	}

	vga_out8(0x3d4, 0x3a, par);
	vga_out8(0x3d5, cr3a, par);
	vga_out8(0x3d4, 0x66, par);
	vga_out8(0x3d5, cr66, par);
}

849 850
static void savage_update_var(struct fb_var_screeninfo *var,
			      const struct fb_videomode *modedb)
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{
	var->xres = var->xres_virtual = modedb->xres;
	var->yres = modedb->yres;
        if (var->yres_virtual < var->yres)
	    var->yres_virtual = var->yres;
        var->xoffset = var->yoffset = 0;
        var->pixclock = modedb->pixclock;
        var->left_margin = modedb->left_margin;
        var->right_margin = modedb->right_margin;
        var->upper_margin = modedb->upper_margin;
        var->lower_margin = modedb->lower_margin;
        var->hsync_len = modedb->hsync_len;
        var->vsync_len = modedb->vsync_len;
        var->sync = modedb->sync;
        var->vmode = modedb->vmode;
}

868 869
static int savagefb_check_var(struct fb_var_screeninfo   *var,
			      struct fb_info *info)
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{
871
	struct savagefb_par *par = info->par;
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	int memlen, vramlen, mode_valid = 0;

	DBG("savagefb_check_var");

	var->transp.offset = 0;
	var->transp.length = 0;
	switch (var->bits_per_pixel) {
	case 8:
		var->red.offset = var->green.offset =
			var->blue.offset = 0;
		var->red.length = var->green.length =
			var->blue.length = var->bits_per_pixel;
		break;
	case 16:
		var->red.offset = 11;
		var->red.length = 5;
		var->green.offset = 5;
		var->green.length = 6;
		var->blue.offset = 0;
		var->blue.length = 5;
		break;
	case 32:
		var->transp.offset = 24;
		var->transp.length = 8;
		var->red.offset = 16;
		var->red.length = 8;
		var->green.offset = 8;
		var->green.length = 8;
		var->blue.offset = 0;
		var->blue.length = 8;
		break;

	default:
		return -EINVAL;
	}

	if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
	    !info->monspecs.dclkmax || !fb_validate_mode(var, info))
		mode_valid = 1;

	/* calculate modeline if supported by monitor */
	if (!mode_valid && info->monspecs.gtf) {
		if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
			mode_valid = 1;
	}

	if (!mode_valid) {
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		const struct fb_videomode *mode;
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		mode = fb_find_best_mode(var, &info->modelist);
		if (mode) {
			savage_update_var(var, mode);
			mode_valid = 1;
		}
	}

	if (!mode_valid && info->monspecs.modedb_len)
		return -EINVAL;

	/* Is the mode larger than the LCD panel? */
	if (par->SavagePanelWidth &&
	    (var->xres > par->SavagePanelWidth ||
	     var->yres > par->SavagePanelHeight)) {
935 936 937 938
		printk(KERN_INFO "Mode (%dx%d) larger than the LCD panel "
		       "(%dx%d)\n", var->xres,  var->yres,
		       par->SavagePanelWidth,
		       par->SavagePanelHeight);
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		return -1;
	}

	if (var->yres_virtual < var->yres)
		var->yres_virtual = var->yres;
	if (var->xres_virtual < var->xres)
		var->xres_virtual = var->xres;

	vramlen = info->fix.smem_len;

	memlen = var->xres_virtual * var->bits_per_pixel *
		var->yres_virtual / 8;
	if (memlen > vramlen) {
		var->yres_virtual = vramlen * 8 /
			(var->xres_virtual * var->bits_per_pixel);
		memlen = var->xres_virtual * var->bits_per_pixel *
			var->yres_virtual / 8;
	}

	/* we must round yres/xres down, we already rounded y/xres_virtual up
	   if it was possible. We should return -EINVAL, but I disagree */
	if (var->yres_virtual < var->yres)
		var->yres = var->yres_virtual;
	if (var->xres_virtual < var->xres)
		var->xres = var->xres_virtual;
	if (var->xoffset + var->xres > var->xres_virtual)
		var->xoffset = var->xres_virtual - var->xres;
	if (var->yoffset + var->yres > var->yres_virtual)
		var->yoffset = var->yres_virtual - var->yres;

	return 0;
}


973 974 975
static int savagefb_decode_var(struct fb_var_screeninfo   *var,
			       struct savagefb_par        *par,
			       struct savage_reg          *reg)
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{
	struct xtimings timings;
	int width, dclk, i, j; /*, refresh; */
	unsigned int m, n, r;
	unsigned char tmp = 0;
	unsigned int pixclock = var->pixclock;

	DBG("savagefb_decode_var");

985
	memset(&timings, 0, sizeof(timings));
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	if (!pixclock) pixclock = 10000;	/* 10ns = 100MHz */
	timings.Clock = 1000000000 / pixclock;
	if (timings.Clock < 1) timings.Clock = 1;
	timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
	timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
	timings.HDisplay = var->xres;
	timings.HSyncStart = timings.HDisplay + var->right_margin;
	timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
	timings.HTotal = timings.HSyncEnd + var->left_margin;
	timings.VDisplay = var->yres;
	timings.VSyncStart = timings.VDisplay + var->lower_margin;
	timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
	timings.VTotal = timings.VSyncEnd + var->upper_margin;
	timings.sync = var->sync;


	par->depth  = var->bits_per_pixel;
	par->vwidth = var->xres_virtual;

	if (var->bits_per_pixel == 16  &&  par->chip == S3_SAVAGE3D) {
		timings.HDisplay *= 2;
		timings.HSyncStart *= 2;
		timings.HSyncEnd *= 2;
		timings.HTotal *= 2;
	}

	/*
	 * This will allocate the datastructure and initialize all of the
	 * generic VGA registers.
	 */
1017
	vgaHWInit(var, par, &timings, reg);
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	/* We need to set CR67 whether or not we use the BIOS. */

	dclk = timings.Clock;
1022
	reg->CR67 = 0x00;
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1024
	switch(var->bits_per_pixel) {
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	case 8:
1026
		if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
1027
			reg->CR67 = 0x10;	/* 8bpp, 2 pixels/clock */
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		else
1029
			reg->CR67 = 0x00;	/* 8bpp, 1 pixel/clock */
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		break;
	case 15:
1032 1033
		if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
		    ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1034
			reg->CR67 = 0x30;	/* 15bpp, 2 pixel/clock */
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		else
1036
			reg->CR67 = 0x20;	/* 15bpp, 1 pixels/clock */
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		break;
	case 16:
1039 1040
		if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
		   ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1041
			reg->CR67 = 0x50;	/* 16bpp, 2 pixel/clock */
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		else
1043
			reg->CR67 = 0x40;	/* 16bpp, 1 pixels/clock */
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		break;
	case 24:
1046
		reg->CR67 = 0x70;
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		break;
	case 32:
1049
		reg->CR67 = 0xd0;
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		break;
	}

	/*
	 * Either BIOS use is disabled, or we failed to find a suitable
	 * match.  Fall back to traditional register-crunching.
	 */

1058 1059
	vga_out8(0x3d4, 0x3a, par);
	tmp = vga_in8(0x3d5, par);
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	if (1 /*FIXME:psav->pci_burst*/)
1061
		reg->CR3A = (tmp & 0x7f) | 0x15;
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1062
	else
1063
		reg->CR3A = tmp | 0x95;
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1064

1065 1066 1067
	reg->CR53 = 0x00;
	reg->CR31 = 0x8c;
	reg->CR66 = 0x89;
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1069 1070
	vga_out8(0x3d4, 0x58, par);
	reg->CR58 = vga_in8(0x3d5, par) & 0x80;
1071
	reg->CR58 |= 0x13;
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1072

1073 1074 1075
	reg->SR15 = 0x03 | 0x80;
	reg->SR18 = 0x00;
	reg->CR43 = reg->CR45 = reg->CR65 = 0x00;
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1077 1078
	vga_out8(0x3d4, 0x40, par);
	reg->CR40 = vga_in8(0x3d5, par) & ~0x01;
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1080 1081 1082 1083
	reg->MMPR0 = 0x010400;
	reg->MMPR1 = 0x00;
	reg->MMPR2 = 0x0808;
	reg->MMPR3 = 0x08080810;
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1085
	SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
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	/* m = 107; n = 4; r = 2; */

	if (par->MCLK <= 0) {
1089 1090
		reg->SR10 = 255;
		reg->SR11 = 255;
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	} else {
1092
		common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
1093 1094 1095
				   &reg->SR11, &reg->SR10);
		/*      reg->SR10 = 80; // MCLK == 286000 */
		/*      reg->SR11 = 125; */
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	}

1098 1099 1100
	reg->SR12 = (r << 6) | (n & 0x3f);
	reg->SR13 = m & 0xff;
	reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
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	if (var->bits_per_pixel < 24)
1103
		reg->MMPR0 -= 0x8000;
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1104
	else
1105
		reg->MMPR0 -= 0x4000;
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	if (timings.interlaced)
1108
		reg->CR42 = 0x20;
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1109
	else
1110
		reg->CR42 = 0x00;
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1111

1112
	reg->CR34 = 0x10; /* display fifo */
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1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123

	i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) |
		((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) |
		((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) |
		((timings.HSyncStart & 0x800) >> 7);

	if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64)
		i |= 0x08;
	if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32)
		i |= 0x20;

1124 1125
	j = (reg->CRTC[0] + ((i & 0x01) << 8) +
	     reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
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1127 1128 1129 1130
	if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) {
		if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <=
		    reg->CRTC[0] + ((i & 0x01) << 8))
			j = reg->CRTC[4] + ((i & 0x10) << 4) + 4;
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		else
1132
			j = reg->CRTC[0] + ((i & 0x01) << 8) + 1;
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1133 1134
	}

1135
	reg->CR3B = j & 0xff;
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	i |= (j & 0x100) >> 2;
1137 1138 1139
	reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2;
	reg->CR5D = i;
	reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
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		(((timings.VDisplay - 1) & 0x400) >> 9) |
		(((timings.VSyncStart) & 0x400) >> 8) |
		(((timings.VSyncStart) & 0x400) >> 6) | 0x40;
	width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3;
1144 1145 1146 1147
	reg->CR91 = reg->CRTC[19] = 0xff & width;
	reg->CR51 = (0x300 & width) >> 4;
	reg->CR90 = 0x80 | (width >> 8);
	reg->MiscOutReg |= 0x0c;
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	/* Set frame buffer description. */

	if (var->bits_per_pixel <= 8)
1152
		reg->CR50 = 0;
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	else if (var->bits_per_pixel <= 16)
1154
		reg->CR50 = 0x10;
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1155
	else
1156
		reg->CR50 = 0x30;
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	if (var->xres_virtual <= 640)
1159
		reg->CR50 |= 0x40;
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	else if (var->xres_virtual == 800)
1161
		reg->CR50 |= 0x80;
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	else if (var->xres_virtual == 1024)
1163
		reg->CR50 |= 0x00;
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	else if (var->xres_virtual == 1152)
1165
		reg->CR50 |= 0x01;
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	else if (var->xres_virtual == 1280)
1167
		reg->CR50 |= 0xc0;
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1168
	else if (var->xres_virtual == 1600)
1169
		reg->CR50 |= 0x81;
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1170
	else
1171
		reg->CR50 |= 0xc1;	/* Use GBD */
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1172

1173
	if (par->chip == S3_SAVAGE2000)
1174
		reg->CR33 = 0x08;
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1175
	else
1176
		reg->CR33 = 0x20;
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1177

1178
	reg->CRTC[0x17] = 0xeb;
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1179

1180
	reg->CR67 |= 1;
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1182
	vga_out8(0x3d4, 0x36, par);
1183 1184 1185
	reg->CR36 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x68, par);
	reg->CR68 = vga_in8(0x3d5, par);
1186
	reg->CR69 = 0;
1187 1188 1189 1190 1191 1192 1193 1194
	vga_out8(0x3d4, 0x6f, par);
	reg->CR6F = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x86, par);
	reg->CR86 = vga_in8(0x3d5, par);
	vga_out8(0x3d4, 0x88, par);
	reg->CR88 = vga_in8(0x3d5, par) | 0x08;
	vga_out8(0x3d4, 0xb0, par);
	reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
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	return 0;
}

/* --------------------------------------------------------------------- */

/*
 *    Set a single color register. Return != 0 for invalid regno.
 */
static int savagefb_setcolreg(unsigned        regno,
			      unsigned        red,
			      unsigned        green,
			      unsigned        blue,
			      unsigned        transp,
			      struct fb_info *info)
{
1211
	struct savagefb_par *par = info->par;
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	if (regno >= NR_PALETTE)
		return -EINVAL;

	par->palette[regno].red    = red;
	par->palette[regno].green  = green;
	par->palette[regno].blue   = blue;
	par->palette[regno].transp = transp;

	switch (info->var.bits_per_pixel) {
	case 8:
1223
		vga_out8(0x3c8, regno, par);
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1225 1226 1227
		vga_out8(0x3c9, red   >> 10, par);
		vga_out8(0x3c9, green >> 10, par);
		vga_out8(0x3c9, blue  >> 10, par);
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		break;

	case 16:
		if (regno < 16)
			((u32 *)info->pseudo_palette)[regno] =
				((red   & 0xf800)      ) |
				((green & 0xfc00) >>  5) |
				((blue  & 0xf800) >> 11);
		break;

	case 24:
		if (regno < 16)
			((u32 *)info->pseudo_palette)[regno] =
				((red    & 0xff00) <<  8) |
				((green  & 0xff00)      ) |
				((blue   & 0xff00) >>  8);
		break;
	case 32:
		if (regno < 16)
			((u32 *)info->pseudo_palette)[regno] =
				((transp & 0xff00) << 16) |
				((red    & 0xff00) <<  8) |
				((green  & 0xff00)      ) |
				((blue   & 0xff00) >>  8);
		break;

	default:
		return 1;
	}

	return 0;
}

1261
static void savagefb_set_par_int(struct savagefb_par  *par, struct savage_reg *reg)
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{
	unsigned char tmp, cr3a, cr66, cr67;

1265
	DBG("savagefb_set_par_int");
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1266

1267
	par->SavageWaitIdle(par);
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1268

1269
	vga_out8(0x3c2, 0x23, par);
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1271 1272 1273
	vga_out16(0x3d4, 0x4838, par);
	vga_out16(0x3d4, 0xa539, par);
	vga_out16(0x3c4, 0x0608, par);
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1275
	vgaHWProtect(par, 1);
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	/*
	 * Some Savage/MX and /IX systems go nuts when trying to exit the
	 * server after WindowMaker has displayed a gradient background.  I
	 * haven't been able to find what causes it, but a non-destructive
	 * switch to mode 3 here seems to eliminate the issue.
	 */

1284
	VerticalRetraceWait(par);
1285 1286 1287
	vga_out8(0x3d4, 0x67, par);
	cr67 = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
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1289 1290 1291 1292
	vga_out8(0x3d4, 0x23, par);
	vga_out8(0x3d5, 0x00, par);
	vga_out8(0x3d4, 0x26, par);
	vga_out8(0x3d5, 0x00, par);
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	/* restore extended regs */
1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308
	vga_out8(0x3d4, 0x66, par);
	vga_out8(0x3d5, reg->CR66, par);
	vga_out8(0x3d4, 0x3a, par);
	vga_out8(0x3d5, reg->CR3A, par);
	vga_out8(0x3d4, 0x31, par);
	vga_out8(0x3d5, reg->CR31, par);
	vga_out8(0x3d4, 0x32, par);
	vga_out8(0x3d5, reg->CR32, par);
	vga_out8(0x3d4, 0x58, par);
	vga_out8(0x3d5, reg->CR58, par);
	vga_out8(0x3d4, 0x53, par);
	vga_out8(0x3d5, reg->CR53 & 0x7f, par);

	vga_out16(0x3c4, 0x0608, par);
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	/* Restore DCLK registers. */

1312 1313 1314 1315 1316 1317 1318 1319
	vga_out8(0x3c4, 0x0e, par);
	vga_out8(0x3c5, reg->SR0E, par);
	vga_out8(0x3c4, 0x0f, par);
	vga_out8(0x3c5, reg->SR0F, par);
	vga_out8(0x3c4, 0x29, par);
	vga_out8(0x3c5, reg->SR29, par);
	vga_out8(0x3c4, 0x15, par);
	vga_out8(0x3c5, reg->SR15, par);
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1320 1321

	/* Restore flat panel expansion regsters. */
1322
	if (par->chip == S3_SAVAGE_MX) {
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		int i;

1325 1326 1327
		for (i = 0; i < 8; i++) {
			vga_out8(0x3c4, 0x54+i, par);
			vga_out8(0x3c5, reg->SR54[i], par);
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1328 1329 1330
		}
	}

1331
	vgaHWRestore (par, reg);
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1332 1333

	/* extended mode timing registers */
1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347
	vga_out8(0x3d4, 0x53, par);
	vga_out8(0x3d5, reg->CR53, par);
	vga_out8(0x3d4, 0x5d, par);
	vga_out8(0x3d5, reg->CR5D, par);
	vga_out8(0x3d4, 0x5e, par);
	vga_out8(0x3d5, reg->CR5E, par);
	vga_out8(0x3d4, 0x3b, par);
	vga_out8(0x3d5, reg->CR3B, par);
	vga_out8(0x3d4, 0x3c, par);
	vga_out8(0x3d5, reg->CR3C, par);
	vga_out8(0x3d4, 0x43, par);
	vga_out8(0x3d5, reg->CR43, par);
	vga_out8(0x3d4, 0x65, par);
	vga_out8(0x3d5, reg->CR65, par);
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1348 1349

	/* restore the desired video mode with cr67 */
1350
	vga_out8(0x3d4, 0x67, par);
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1351
	/* following part not present in X11 driver */
1352 1353
	cr67 = vga_in8(0x3d5, par) & 0xf;
	vga_out8(0x3d5, 0x50 | cr67, par);
1354
	mdelay(10);
1355
	vga_out8(0x3d4, 0x67, par);
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1356
	/* end of part */
1357
	vga_out8(0x3d5, reg->CR67 & ~0x0c, par);
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1358 1359

	/* other mode timing and extended regs */
1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371
	vga_out8(0x3d4, 0x34, par);
	vga_out8(0x3d5, reg->CR34, par);
	vga_out8(0x3d4, 0x40, par);
	vga_out8(0x3d5, reg->CR40, par);
	vga_out8(0x3d4, 0x42, par);
	vga_out8(0x3d5, reg->CR42, par);
	vga_out8(0x3d4, 0x45, par);
	vga_out8(0x3d5, reg->CR45, par);
	vga_out8(0x3d4, 0x50, par);
	vga_out8(0x3d5, reg->CR50, par);
	vga_out8(0x3d4, 0x51, par);
	vga_out8(0x3d5, reg->CR51, par);
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	/* memory timings */
1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394
	vga_out8(0x3d4, 0x36, par);
	vga_out8(0x3d5, reg->CR36, par);
	vga_out8(0x3d4, 0x60, par);
	vga_out8(0x3d5, reg->CR60, par);
	vga_out8(0x3d4, 0x68, par);
	vga_out8(0x3d5, reg->CR68, par);
	vga_out8(0x3d4, 0x69, par);
	vga_out8(0x3d5, reg->CR69, par);
	vga_out8(0x3d4, 0x6f, par);
	vga_out8(0x3d5, reg->CR6F, par);

	vga_out8(0x3d4, 0x33, par);
	vga_out8(0x3d5, reg->CR33, par);
	vga_out8(0x3d4, 0x86, par);
	vga_out8(0x3d5, reg->CR86, par);
	vga_out8(0x3d4, 0x88, par);
	vga_out8(0x3d5, reg->CR88, par);
	vga_out8(0x3d4, 0x90, par);
	vga_out8(0x3d5, reg->CR90, par);
	vga_out8(0x3d4, 0x91, par);
	vga_out8(0x3d5, reg->CR91, par);
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	if (par->chip == S3_SAVAGE4) {
1397 1398
		vga_out8(0x3d4, 0xb0, par);
		vga_out8(0x3d5, reg->CRB0, par);
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	}

1401 1402
	vga_out8(0x3d4, 0x32, par);
	vga_out8(0x3d5, reg->CR32, par);
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	/* unlock extended seq regs */
1405 1406
	vga_out8(0x3c4, 0x08, par);
	vga_out8(0x3c5, 0x06, par);
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	/* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
	 * that we should leave the default SR10 and SR11 values there.
	 */
1411
	if (reg->SR10 != 255) {
1412 1413 1414 1415
		vga_out8(0x3c4, 0x10, par);
		vga_out8(0x3c5, reg->SR10, par);
		vga_out8(0x3c4, 0x11, par);
		vga_out8(0x3c5, reg->SR11, par);
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	}

	/* restore extended seq regs for dclk */
1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430
	vga_out8(0x3c4, 0x0e, par);
	vga_out8(0x3c5, reg->SR0E, par);
	vga_out8(0x3c4, 0x0f, par);
	vga_out8(0x3c5, reg->SR0F, par);
	vga_out8(0x3c4, 0x12, par);
	vga_out8(0x3c5, reg->SR12, par);
	vga_out8(0x3c4, 0x13, par);
	vga_out8(0x3c5, reg->SR13, par);
	vga_out8(0x3c4, 0x29, par);
	vga_out8(0x3c5, reg->SR29, par);
	vga_out8(0x3c4, 0x18, par);
	vga_out8(0x3c5, reg->SR18, par);
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	/* load new m, n pll values for dclk & mclk */
1433 1434
	vga_out8(0x3c4, 0x15, par);
	tmp = vga_in8(0x3c5, par) & ~0x21;
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1436 1437 1438 1439 1440
	vga_out8(0x3c5, tmp | 0x03, par);
	vga_out8(0x3c5, tmp | 0x23, par);
	vga_out8(0x3c5, tmp | 0x03, par);
	vga_out8(0x3c5, reg->SR15, par);
	udelay(100);
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1442 1443 1444 1445
	vga_out8(0x3c4, 0x30, par);
	vga_out8(0x3c5, reg->SR30, par);
	vga_out8(0x3c4, 0x08, par);
	vga_out8(0x3c5, reg->SR08, par);
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	/* now write out cr67 in full, possibly starting STREAMS */
1448
	VerticalRetraceWait(par);
1449 1450
	vga_out8(0x3d4, 0x67, par);
	vga_out8(0x3d5, reg->CR67, par);
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1452 1453 1454 1455 1456 1457
	vga_out8(0x3d4, 0x66, par);
	cr66 = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr66 | 0x80, par);
	vga_out8(0x3d4, 0x3a, par);
	cr3a = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr3a | 0x80, par);
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	if (par->chip != S3_SAVAGE_MX) {
1460
		VerticalRetraceWait(par);
1461 1462 1463 1464 1465 1466 1467
		savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
		par->SavageWaitIdle(par);
		savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
		par->SavageWaitIdle(par);
		savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
		par->SavageWaitIdle(par);
		savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
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	}

1470 1471 1472 1473
	vga_out8(0x3d4, 0x66, par);
	vga_out8(0x3d5, cr66, par);
	vga_out8(0x3d4, 0x3a, par);
	vga_out8(0x3d5, cr3a, par);
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1475 1476
	SavageSetup2DEngine(par);
	vgaHWProtect(par, 0);
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}

1479
static void savagefb_update_start(struct savagefb_par *par, int base)
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{
1481
	/* program the start address registers */
1482 1483
	vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
	vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
1484 1485
	vga_out8(0x3d4, 0x69, par);
	vga_out8(0x3d5, (base & 0x7f0000) >> 16, par);
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}


static void savagefb_set_fix(struct fb_info *info)
{
	info->fix.line_length = info->var.xres_virtual *
		info->var.bits_per_pixel / 8;

1494
	if (info->var.bits_per_pixel == 8) {
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		info->fix.visual      = FB_VISUAL_PSEUDOCOLOR;
1496 1497
		info->fix.xpanstep    = 4;
	} else {
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		info->fix.visual      = FB_VISUAL_TRUECOLOR;
1499 1500 1501
		info->fix.xpanstep    = 2;
	}

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}

1504
static int savagefb_set_par(struct fb_info *info)
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{
1506
	struct savagefb_par *par = info->par;
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	struct fb_var_screeninfo *var = &info->var;
	int err;

	DBG("savagefb_set_par");
1511
	err = savagefb_decode_var(var, par, &par->state);
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	if (err)
		return err;

	if (par->dacSpeedBpp <= 0) {
		if (var->bits_per_pixel > 24)
			par->dacSpeedBpp = par->clock[3];
		else if (var->bits_per_pixel >= 24)
			par->dacSpeedBpp = par->clock[2];
		else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24))
			par->dacSpeedBpp = par->clock[1];
		else if (var->bits_per_pixel <= 8)
			par->dacSpeedBpp = par->clock[0];
	}

	/* Set ramdac limits */
	par->maxClock = par->dacSpeedBpp;
	par->minClock = 10000;

1530 1531
	savagefb_set_par_int(par, &par->state);
	fb_set_cmap(&info->cmap, info);
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	savagefb_set_fix(info);
	savagefb_set_clip(info);

1535
	SavagePrintRegs(par);
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	return 0;
}

/*
 *    Pan or Wrap the Display
 */
1542 1543
static int savagefb_pan_display(struct fb_var_screeninfo *var,
				struct fb_info           *info)
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{
1545
	struct savagefb_par *par = info->par;
1546 1547 1548 1549
	int base;

	base = (var->yoffset * info->fix.line_length
	     + (var->xoffset & ~1) * ((info->var.bits_per_pixel+7) / 8)) >> 2;
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1551
	savagefb_update_start(par, base);
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	return 0;
}

1555 1556 1557 1558 1559 1560
static int savagefb_blank(int blank, struct fb_info *info)
{
	struct savagefb_par *par = info->par;
	u8 sr8 = 0, srd = 0;

	if (par->display_type == DISP_CRT) {
1561 1562
		vga_out8(0x3c4, 0x08, par);
		sr8 = vga_in8(0x3c5, par);
1563
		sr8 |= 0x06;
1564 1565 1566
		vga_out8(0x3c5, sr8, par);
		vga_out8(0x3c4, 0x0d, par);
		srd = vga_in8(0x3c5, par);
1567
		srd &= 0x50;
1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583

		switch (blank) {
		case FB_BLANK_UNBLANK:
		case FB_BLANK_NORMAL:
			break;
		case FB_BLANK_VSYNC_SUSPEND:
			srd |= 0x10;
			break;
		case FB_BLANK_HSYNC_SUSPEND:
			srd |= 0x40;
			break;
		case FB_BLANK_POWERDOWN:
			srd |= 0x50;
			break;
		}

1584 1585
		vga_out8(0x3c4, 0x0d, par);
		vga_out8(0x3c5, srd, par);
1586 1587 1588 1589 1590 1591 1592
	}

	if (par->display_type == DISP_LCD ||
	    par->display_type == DISP_DFP) {
		switch(blank) {
		case FB_BLANK_UNBLANK:
		case FB_BLANK_NORMAL:
1593 1594
			vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
			vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par);
1595 1596 1597 1598
			break;
		case FB_BLANK_VSYNC_SUSPEND:
		case FB_BLANK_HSYNC_SUSPEND:
		case FB_BLANK_POWERDOWN:
1599 1600
			vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
			vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par);
1601 1602 1603 1604 1605 1606
			break;
		}
	}

	return (blank == FB_BLANK_NORMAL) ? 1 : 0;
}
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1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643
static int savagefb_open(struct fb_info *info, int user)
{
	struct savagefb_par *par = info->par;

	mutex_lock(&par->open_lock);

	if (!par->open_count) {
		memset(&par->vgastate, 0, sizeof(par->vgastate));
		par->vgastate.flags = VGA_SAVE_CMAP | VGA_SAVE_FONTS |
			VGA_SAVE_MODE;
		par->vgastate.vgabase = par->mmio.vbase + 0x8000;
		save_vga(&par->vgastate);
		savage_get_default_par(par, &par->initial);
	}

	par->open_count++;
	mutex_unlock(&par->open_lock);
	return 0;
}

static int savagefb_release(struct fb_info *info, int user)
{
	struct savagefb_par *par = info->par;

	mutex_lock(&par->open_lock);

	if (par->open_count == 1) {
		savage_set_default_par(par, &par->initial);
		restore_vga(&par->vgastate);
	}

	par->open_count--;
	mutex_unlock(&par->open_lock);
	return 0;
}

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static struct fb_ops savagefb_ops = {
	.owner          = THIS_MODULE,
1646 1647
	.fb_open        = savagefb_open,
	.fb_release     = savagefb_release,
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	.fb_check_var   = savagefb_check_var,
	.fb_set_par     = savagefb_set_par,
	.fb_setcolreg   = savagefb_setcolreg,
	.fb_pan_display = savagefb_pan_display,
1652
	.fb_blank       = savagefb_blank,
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#if defined(CONFIG_FB_SAVAGE_ACCEL)
	.fb_fillrect    = savagefb_fillrect,
	.fb_copyarea    = savagefb_copyarea,
	.fb_imageblit   = savagefb_imageblit,
	.fb_sync        = savagefb_sync,
#else
	.fb_fillrect    = cfb_fillrect,
	.fb_copyarea    = cfb_copyarea,
	.fb_imageblit   = cfb_imageblit,
#endif
};

/* --------------------------------------------------------------------- */

static struct fb_var_screeninfo __devinitdata savagefb_var800x600x8 = {
	.accel_flags =	FB_ACCELF_TEXT,
	.xres =		800,
	.yres =		600,
	.xres_virtual =  800,
	.yres_virtual =  600,
	.bits_per_pixel = 8,
	.pixclock =	25000,
	.left_margin =	88,
	.right_margin =	40,
	.upper_margin =	23,
	.lower_margin =	1,
	.hsync_len =	128,
	.vsync_len =	4,
	.sync =		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	.vmode =	FB_VMODE_NONINTERLACED
};

1685
static void savage_enable_mmio(struct savagefb_par *par)
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{
	unsigned char val;

1689
	DBG("savage_enable_mmio\n");
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1691 1692 1693 1694
	val = vga_in8(0x3c3, par);
	vga_out8(0x3c3, val | 0x01, par);
	val = vga_in8(0x3cc, par);
	vga_out8(0x3c2, val | 0x01, par);
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	if (par->chip >= S3_SAVAGE4) {
1697 1698 1699
		vga_out8(0x3d4, 0x40, par);
		val = vga_in8(0x3d5, par);
		vga_out8(0x3d5, val | 1, par);
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	}
}


1704
static void savage_disable_mmio(struct savagefb_par *par)
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{
	unsigned char val;

1708
	DBG("savage_disable_mmio\n");
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1710 1711 1712 1713
	if (par->chip >= S3_SAVAGE4) {
		vga_out8(0x3d4, 0x40, par);
		val = vga_in8(0x3d5, par);
		vga_out8(0x3d5, val | 1, par);
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	}
}


1718
static int __devinit savage_map_mmio(struct fb_info *info)
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{
1720
	struct savagefb_par *par = info->par;
1721
	DBG("savage_map_mmio");
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1723 1724
	if (S3_SAVAGE3D_SERIES(par->chip))
		par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
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			SAVAGE_NEWMMIO_REGBASE_S3;
	else
1727
		par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
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			SAVAGE_NEWMMIO_REGBASE_S4;

	par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;

1732
	par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len);
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	if (!par->mmio.vbase) {
1734
		printk("savagefb: unable to map memory mapped IO\n");
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		return -ENOMEM;
	} else
1737
		printk(KERN_INFO "savagefb: mapped io at %p\n",
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			par->mmio.vbase);

	info->fix.mmio_start = par->mmio.pbase;
	info->fix.mmio_len   = par->mmio.len;

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	par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
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	par->bci_ptr  = 0;

1746
	savage_enable_mmio(par);
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	return 0;
}

1751
static void savage_unmap_mmio(struct fb_info *info)
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{
1753
	struct savagefb_par *par = info->par;
1754
	DBG("savage_unmap_mmio");
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	savage_disable_mmio(par);

	if (par->mmio.vbase) {
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		iounmap(par->mmio.vbase);
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		par->mmio.vbase = NULL;
	}
}

1764 1765
static int __devinit savage_map_video(struct fb_info *info,
				      int video_len)
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{
1767
	struct savagefb_par *par = info->par;
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	int resource;

	DBG("savage_map_video");

1772
	if (S3_SAVAGE3D_SERIES(par->chip))
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		resource = 0;
	else
		resource = 1;

1777
	par->video.pbase = pci_resource_start(par->pcidev, resource);
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	par->video.len   = video_len;
1779
	par->video.vbase = ioremap(par->video.pbase, par->video.len);
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	if (!par->video.vbase) {
1782
		printk("savagefb: unable to map screen memory\n");
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		return -ENOMEM;
	} else
1785 1786
		printk(KERN_INFO "savagefb: mapped framebuffer at %p, "
		       "pbase == %x\n", par->video.vbase, par->video.pbase);
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	info->fix.smem_start = par->video.pbase;
	info->fix.smem_len   = par->video.len - par->cob_size;
	info->screen_base    = par->video.vbase;

#ifdef CONFIG_MTRR
1793 1794
	par->video.mtrr = mtrr_add(par->video.pbase, video_len,
				   MTRR_TYPE_WRCOMB, 1);
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#endif

	/* Clear framebuffer, it's all white in memory after boot */
1798
	memset_io(par->video.vbase, 0, par->video.len);
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	return 0;
}

1803
static void savage_unmap_video(struct fb_info *info)
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{
1805
	struct savagefb_par *par = info->par;
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	DBG("savage_unmap_video");

	if (par->video.vbase) {
#ifdef CONFIG_MTRR
1811
		mtrr_del(par->video.mtrr, par->video.pbase, par->video.len);
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#endif

1814
		iounmap(par->video.vbase);
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		par->video.vbase = NULL;
		info->screen_base = NULL;
	}
}

1820
static int savage_init_hw(struct savagefb_par *par)
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{
	unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp;

	static unsigned char RamSavage3D[] = { 8, 4, 4, 2 };
	static unsigned char RamSavage4[] =  { 2, 4, 8, 12, 16, 32, 64, 32 };
	static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 };
	static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 };
1828
	int videoRam, videoRambytes, dvi;
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	DBG("savage_init_hw");

	/* unprotect CRTC[0-7] */
1833 1834 1835
	vga_out8(0x3d4, 0x11, par);
	tmp = vga_in8(0x3d5, par);
	vga_out8(0x3d5, tmp & 0x7f, par);
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	/* unlock extended regs */
1838 1839 1840
	vga_out16(0x3d4, 0x4838, par);
	vga_out16(0x3d4, 0xa039, par);
	vga_out16(0x3c4, 0x0608, par);
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1842 1843 1844
	vga_out8(0x3d4, 0x40, par);
	tmp = vga_in8(0x3d5, par);
	vga_out8(0x3d5, tmp & ~0x01, par);
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	/* unlock sys regs */
1847 1848
	vga_out8(0x3d4, 0x38, par);
	vga_out8(0x3d5, 0x48, par);
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	/* Unlock system registers. */
1851
	vga_out16(0x3d4, 0x4838, par);
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	/* Next go on to detect amount of installed ram */

1855 1856
	vga_out8(0x3d4, 0x36, par);            /* for register CR36 (CONFG_REG1), */
	config1 = vga_in8(0x3d5, par);    /* get amount of vram installed */
L
Linus Torvalds 已提交
1857 1858 1859 1860 1861

	/* Compute the amount of video memory and offscreen memory. */

	switch  (par->chip) {
	case S3_SAVAGE3D:
1862
		videoRam = RamSavage3D[(config1 & 0xC0) >> 6 ] * 1024;
L
Linus Torvalds 已提交
1863 1864 1865 1866 1867 1868 1869 1870 1871
		break;

	case S3_SAVAGE4:
		/*
		 * The Savage4 has one ugly special case to consider.  On
		 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB
		 * when it really means 8MB.  Why do it the same when you
		 * can do it different...
		 */
1872
		vga_out8(0x3d4, 0x68, par);	/* memory control 1 */
1873
		if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6))
L
Linus Torvalds 已提交
1874 1875 1876 1877 1878
			RamSavage4[1] = 8;

		/*FALLTHROUGH*/

	case S3_SAVAGE2000:
1879
		videoRam = RamSavage4[(config1 & 0xE0) >> 5] * 1024;
L
Linus Torvalds 已提交
1880 1881 1882 1883
		break;

	case S3_SAVAGE_MX:
	case S3_SUPERSAVAGE:
1884
		videoRam = RamSavageMX[(config1 & 0x0E) >> 1] * 1024;
L
Linus Torvalds 已提交
1885 1886 1887
		break;

	case S3_PROSAVAGE:
1888 1889
	case S3_PROSAVAGEDDR:
	case S3_TWISTER:
1890
		videoRam = RamSavageNB[(config1 & 0xE0) >> 5] * 1024;
L
Linus Torvalds 已提交
1891 1892 1893 1894 1895 1896 1897 1898 1899 1900
		break;

	default:
		/* How did we get here? */
		videoRam = 0;
		break;
	}

	videoRambytes = videoRam * 1024;

1901
	printk(KERN_INFO "savagefb: probed videoram:  %dk\n", videoRam);
L
Linus Torvalds 已提交
1902 1903

	/* reset graphics engine to avoid memory corruption */
1904 1905 1906
	vga_out8(0x3d4, 0x66, par);
	cr66 = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr66 | 0x02, par);
1907
	mdelay(10);
L
Linus Torvalds 已提交
1908

1909 1910
	vga_out8(0x3d4, 0x66, par);
	vga_out8(0x3d5, cr66 & ~0x02, par);	/* clear reset flag */
1911
	mdelay(10);
L
Linus Torvalds 已提交
1912 1913 1914 1915 1916 1917


	/*
	 * reset memory interface, 3D engine, AGP master, PCI master,
	 * master engine unit, motion compensation/LPB
	 */
1918 1919 1920
	vga_out8(0x3d4, 0x3f, par);
	cr3f = vga_in8(0x3d5, par);
	vga_out8(0x3d5, cr3f | 0x08, par);
1921
	mdelay(10);
L
Linus Torvalds 已提交
1922

1923 1924
	vga_out8(0x3d4, 0x3f, par);
	vga_out8(0x3d5, cr3f & ~0x08, par);	/* clear reset flags */
1925
	mdelay(10);
L
Linus Torvalds 已提交
1926 1927 1928 1929 1930 1931 1932 1933 1934

	/* Savage ramdac speeds */
	par->numClocks = 4;
	par->clock[0] = 250000;
	par->clock[1] = 250000;
	par->clock[2] = 220000;
	par->clock[3] = 220000;

	/* detect current mclk */
1935 1936 1937 1938 1939 1940 1941 1942 1943
	vga_out8(0x3c4, 0x08, par);
	sr8 = vga_in8(0x3c5, par);
	vga_out8(0x3c5, 0x06, par);
	vga_out8(0x3c4, 0x10, par);
	n = vga_in8(0x3c5, par);
	vga_out8(0x3c4, 0x11, par);
	m = vga_in8(0x3c5, par);
	vga_out8(0x3c4, 0x08, par);
	vga_out8(0x3c5, sr8, par);
L
Linus Torvalds 已提交
1944 1945 1946 1947
	m &= 0x7f;
	n1 = n & 0x1f;
	n2 = (n >> 5) & 0x03;
	par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
1948
	printk(KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
L
Linus Torvalds 已提交
1949 1950
		par->MCLK);

1951 1952 1953 1954 1955 1956
	/* check for DVI/flat panel */
	dvi = 0;

	if (par->chip == S3_SAVAGE4) {
		unsigned char sr30 = 0x00;

1957
		vga_out8(0x3c4, 0x30, par);
1958
		/* clear bit 1 */
1959 1960
		vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par);
		sr30 = vga_in8(0x3c5, par);
1961 1962 1963 1964 1965 1966
		if (sr30 & 0x02 /*0x04 */) {
			dvi = 1;
			printk("savagefb: Digital Flat Panel Detected\n");
		}
	}

1967 1968
	if ((S3_SAVAGE_MOBILE_SERIES(par->chip) ||
	     S3_MOBILE_TWISTER_SERIES(par->chip)) && !par->crtonly)
1969 1970 1971 1972 1973 1974
		par->display_type = DISP_LCD;
	else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
		par->display_type = DISP_DFP;
	else
		par->display_type = DISP_CRT;

L
Linus Torvalds 已提交
1975 1976
	/* Check LCD panel parrmation */

1977
	if (par->display_type == DISP_LCD) {
1978
		unsigned char cr6b = VGArCR(0x6b, par);
L
Linus Torvalds 已提交
1979

1980 1981 1982 1983
		int panelX = (VGArSEQ(0x61, par) +
			      ((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8;
		int panelY = (VGArSEQ(0x69, par) +
			      ((VGArSEQ(0x6e, par) & 0x70) << 4) + 1);
L
Linus Torvalds 已提交
1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004

		char * sTechnology = "Unknown";

		/* OK, I admit it.  I don't know how to limit the max dot clock
		 * for LCD panels of various sizes.  I thought I copied the
		 * formula from the BIOS, but many users have parrmed me of
		 * my folly.
		 *
		 * Instead, I'll abandon any attempt to automatically limit the
		 * clock, and add an LCDClock option to XF86Config.  Some day,
		 * I should come back to this.
		 */

		enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */
			ActiveCRT = 0x01,
			ActiveLCD = 0x02,
			ActiveTV = 0x04,
			ActiveCRT2 = 0x20,
			ActiveDUO = 0x80
		};

2005
		if ((VGArSEQ(0x39, par) & 0x03) == 0) {
L
Linus Torvalds 已提交
2006
			sTechnology = "TFT";
2007
		} else if ((VGArSEQ(0x30, par) & 0x01) == 0) {
L
Linus Torvalds 已提交
2008 2009 2010 2011 2012
			sTechnology = "DSTN";
		} else 	{
			sTechnology = "STN";
		}

2013 2014 2015
		printk(KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n",
		       panelX, panelY, sTechnology,
		       cr6b & ActiveLCD ? "and active" : "but not active");
L
Linus Torvalds 已提交
2016

2017
		if (cr6b & ActiveLCD) 	{
L
Linus Torvalds 已提交
2018 2019 2020 2021 2022
			/*
			 * If the LCD is active and panel expansion is enabled,
			 * we probably want to kill the HW cursor.
			 */

2023 2024
			printk(KERN_INFO "savagefb: Limiting video mode to "
				"%dx%d\n", panelX, panelY);
L
Linus Torvalds 已提交
2025 2026 2027 2028

			par->SavagePanelWidth = panelX;
			par->SavagePanelHeight = panelY;

2029 2030
		} else
			par->display_type = DISP_CRT;
L
Linus Torvalds 已提交
2031 2032
	}

2033
	savage_get_default_par(par, &par->state);
2034
	par->save = par->state;
L
Linus Torvalds 已提交
2035

2036
	if (S3_SAVAGE4_SERIES(par->chip)) {
L
Linus Torvalds 已提交
2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054
		/*
		 * The Savage4 and ProSavage have COB coherency bugs which
		 * render the buffer useless.  We disable it.
		 */
		par->cob_index = 2;
		par->cob_size = 0x8000 << par->cob_index;
		par->cob_offset = videoRambytes;
	} else {
		/* We use 128kB for the COB on all chips. */

		par->cob_index  = 7;
		par->cob_size   = 0x400 << par->cob_index;
		par->cob_offset = videoRambytes - par->cob_size;
	}

	return videoRambytes;
}

2055 2056 2057
static int __devinit savage_init_fb_info(struct fb_info *info,
					 struct pci_dev *dev,
					 const struct pci_device_id *id)
L
Linus Torvalds 已提交
2058
{
2059
	struct savagefb_par *par = info->par;
L
Linus Torvalds 已提交
2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072
	int err = 0;

	par->pcidev  = dev;

	info->fix.type	   = FB_TYPE_PACKED_PIXELS;
	info->fix.type_aux	   = 0;
	info->fix.ypanstep	   = 1;
	info->fix.ywrapstep   = 0;
	info->fix.accel       = id->driver_data;

	switch (info->fix.accel) {
	case FB_ACCEL_SUPERSAVAGE:
		par->chip = S3_SUPERSAVAGE;
2073
		snprintf(info->fix.id, 16, "SuperSavage");
L
Linus Torvalds 已提交
2074 2075 2076
		break;
	case FB_ACCEL_SAVAGE4:
		par->chip = S3_SAVAGE4;
2077
		snprintf(info->fix.id, 16, "Savage4");
L
Linus Torvalds 已提交
2078 2079 2080
		break;
	case FB_ACCEL_SAVAGE3D:
		par->chip = S3_SAVAGE3D;
2081
		snprintf(info->fix.id, 16, "Savage3D");
L
Linus Torvalds 已提交
2082 2083 2084
		break;
	case FB_ACCEL_SAVAGE3D_MV:
		par->chip = S3_SAVAGE3D;
2085
		snprintf(info->fix.id, 16, "Savage3D-MV");
L
Linus Torvalds 已提交
2086 2087 2088
		break;
	case FB_ACCEL_SAVAGE2000:
		par->chip = S3_SAVAGE2000;
2089
		snprintf(info->fix.id, 16, "Savage2000");
L
Linus Torvalds 已提交
2090 2091 2092
		break;
	case FB_ACCEL_SAVAGE_MX_MV:
		par->chip = S3_SAVAGE_MX;
2093
		snprintf(info->fix.id, 16, "Savage/MX-MV");
L
Linus Torvalds 已提交
2094 2095 2096
		break;
	case FB_ACCEL_SAVAGE_MX:
		par->chip = S3_SAVAGE_MX;
2097
		snprintf(info->fix.id, 16, "Savage/MX");
L
Linus Torvalds 已提交
2098 2099 2100
		break;
	case FB_ACCEL_SAVAGE_IX_MV:
		par->chip = S3_SAVAGE_MX;
2101
		snprintf(info->fix.id, 16, "Savage/IX-MV");
L
Linus Torvalds 已提交
2102 2103 2104
		break;
	case FB_ACCEL_SAVAGE_IX:
		par->chip = S3_SAVAGE_MX;
2105
		snprintf(info->fix.id, 16, "Savage/IX");
L
Linus Torvalds 已提交
2106 2107 2108
		break;
	case FB_ACCEL_PROSAVAGE_PM:
		par->chip = S3_PROSAVAGE;
2109
		snprintf(info->fix.id, 16, "ProSavagePM");
L
Linus Torvalds 已提交
2110 2111 2112
		break;
	case FB_ACCEL_PROSAVAGE_KM:
		par->chip = S3_PROSAVAGE;
2113
		snprintf(info->fix.id, 16, "ProSavageKM");
L
Linus Torvalds 已提交
2114 2115
		break;
	case FB_ACCEL_S3TWISTER_P:
2116
		par->chip = S3_TWISTER;
2117
		snprintf(info->fix.id, 16, "TwisterP");
L
Linus Torvalds 已提交
2118 2119
		break;
	case FB_ACCEL_S3TWISTER_K:
2120
		par->chip = S3_TWISTER;
2121
		snprintf(info->fix.id, 16, "TwisterK");
L
Linus Torvalds 已提交
2122 2123
		break;
	case FB_ACCEL_PROSAVAGE_DDR:
2124
		par->chip = S3_PROSAVAGEDDR;
2125
		snprintf(info->fix.id, 16, "ProSavageDDR");
L
Linus Torvalds 已提交
2126 2127
		break;
	case FB_ACCEL_PROSAVAGE_DDRK:
2128
		par->chip = S3_PROSAVAGEDDR;
2129
		snprintf(info->fix.id, 16, "ProSavage8");
L
Linus Torvalds 已提交
2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159
		break;
	}

	if (S3_SAVAGE3D_SERIES(par->chip)) {
		par->SavageWaitIdle = savage3D_waitidle;
		par->SavageWaitFifo = savage3D_waitfifo;
	} else if (S3_SAVAGE4_SERIES(par->chip) ||
		   S3_SUPERSAVAGE == par->chip) {
		par->SavageWaitIdle = savage4_waitidle;
		par->SavageWaitFifo = savage4_waitfifo;
	} else {
		par->SavageWaitIdle = savage2000_waitidle;
		par->SavageWaitFifo = savage2000_waitfifo;
	}

	info->var.nonstd      = 0;
	info->var.activate    = FB_ACTIVATE_NOW;
	info->var.width       = -1;
	info->var.height      = -1;
	info->var.accel_flags = 0;

	info->fbops          = &savagefb_ops;
	info->flags          = FBINFO_DEFAULT |
		               FBINFO_HWACCEL_YPAN |
		               FBINFO_HWACCEL_XPAN;

	info->pseudo_palette = par->pseudo_palette;

#if defined(CONFIG_FB_SAVAGE_ACCEL)
	/* FIFO size + padding for commands */
2160
	info->pixmap.addr = kcalloc(8, 1024, GFP_KERNEL);
L
Linus Torvalds 已提交
2161 2162 2163 2164 2165 2166

	err = -ENOMEM;
	if (info->pixmap.addr) {
		info->pixmap.size = 8*1024;
		info->pixmap.scan_align = 4;
		info->pixmap.buf_align = 4;
2167
		info->pixmap.access_align = 32;
L
Linus Torvalds 已提交
2168

2169
		err = fb_alloc_cmap(&info->cmap, NR_PALETTE, 0);
2170
		if (!err)
L
Linus Torvalds 已提交
2171 2172 2173 2174 2175 2176 2177 2178 2179 2180
		info->flags |= FBINFO_HWACCEL_COPYAREA |
	                       FBINFO_HWACCEL_FILLRECT |
		               FBINFO_HWACCEL_IMAGEBLIT;
	}
#endif
	return err;
}

/* --------------------------------------------------------------------- */

2181 2182
static int __devinit savagefb_probe(struct pci_dev* dev,
				    const struct pci_device_id* id)
L
Linus Torvalds 已提交
2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195
{
	struct fb_info *info;
	struct savagefb_par *par;
	u_int h_sync, v_sync;
	int err, lpitch;
	int video_len;

	DBG("savagefb_probe");

	info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev);
	if (!info)
		return -ENOMEM;
	par = info->par;
2196
	mutex_init(&par->open_lock);
L
Linus Torvalds 已提交
2197 2198 2199 2200
	err = pci_enable_device(dev);
	if (err)
		goto failed_enable;

2201
	if ((err = pci_request_regions(dev, "savagefb"))) {
L
Linus Torvalds 已提交
2202 2203 2204 2205 2206 2207
		printk(KERN_ERR "cannot request PCI regions\n");
		goto failed_enable;
	}

	err = -ENOMEM;

2208
	if ((err = savage_init_fb_info(info, dev, id)))
L
Linus Torvalds 已提交
2209 2210 2211 2212 2213 2214 2215
		goto failed_init;

	err = savage_map_mmio(info);
	if (err)
		goto failed_mmio;

	video_len = savage_init_hw(par);
L
Lucas De Marchi 已提交
2216
	/* FIXME: can't be negative */
L
Linus Torvalds 已提交
2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228
	if (video_len < 0) {
		err = video_len;
		goto failed_mmio;
	}

	err = savage_map_video(info, video_len);
	if (err)
		goto failed_video;

	INIT_LIST_HEAD(&info->modelist);
#if defined(CONFIG_FB_SAVAGE_I2C)
	savagefb_create_i2c_busses(info);
2229
	savagefb_probe_i2c_connector(info, &par->edid);
L
Linus Torvalds 已提交
2230
	fb_edid_to_monspecs(par->edid, &info->monspecs);
2231
	kfree(par->edid);
L
Linus Torvalds 已提交
2232 2233 2234 2235 2236
	fb_videomode_to_modelist(info->monspecs.modedb,
				 info->monspecs.modedb_len,
				 &info->modelist);
#endif
	info->var = savagefb_var800x600x8;
2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252
	/* if a panel was detected, default to a CVT mode instead */
	if (par->SavagePanelWidth) {
		struct fb_videomode cvt_mode;

		memset(&cvt_mode, 0, sizeof(cvt_mode));
		cvt_mode.xres = par->SavagePanelWidth;
		cvt_mode.yres = par->SavagePanelHeight;
		cvt_mode.refresh = 60;
		/* FIXME: if we know there is only the panel
		 * we can enable reduced blanking as well */
		if (fb_find_mode_cvt(&cvt_mode, 0, 0))
			printk(KERN_WARNING "No CVT mode found for panel\n");
		else if (fb_find_mode(&info->var, info, NULL, NULL, 0,
				      &cvt_mode, 0) != 3)
			info->var = savagefb_var800x600x8;
	}
L
Linus Torvalds 已提交
2253 2254 2255 2256 2257 2258

	if (mode_option) {
		fb_find_mode(&info->var, info, mode_option,
			     info->monspecs.modedb, info->monspecs.modedb_len,
			     NULL, 8);
	} else if (info->monspecs.modedb != NULL) {
2259
		const struct fb_videomode *mode;
L
Linus Torvalds 已提交
2260

2261 2262
		mode = fb_find_best_display(&info->monspecs, &info->modelist);
		savage_update_var(&info->var, mode);
L
Linus Torvalds 已提交
2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308
	}

	/* maximize virtual vertical length */
	lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3);
	info->var.yres_virtual = info->fix.smem_len/lpitch;

	if (info->var.yres_virtual < info->var.yres)
		goto failed;

#if defined(CONFIG_FB_SAVAGE_ACCEL)
	/*
	 * The clipping coordinates are masked with 0xFFF, so limit our
	 * virtual resolutions to these sizes.
	 */
	if (info->var.yres_virtual > 0x1000)
		info->var.yres_virtual = 0x1000;

	if (info->var.xres_virtual > 0x1000)
		info->var.xres_virtual = 0x1000;
#endif
	savagefb_check_var(&info->var, info);
	savagefb_set_fix(info);

	/*
	 * Calculate the hsync and vsync frequencies.  Note that
	 * we split the 1e12 constant up so that we can preserve
	 * the precision and fit the results into 32-bit registers.
	 *  (1953125000 * 512 = 1e12)
	 */
	h_sync = 1953125000 / info->var.pixclock;
	h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin +
				 info->var.right_margin +
				 info->var.hsync_len);
	v_sync = h_sync / (info->var.yres + info->var.upper_margin +
			   info->var.lower_margin + info->var.vsync_len);

	printk(KERN_INFO "savagefb v" SAVAGEFB_VERSION ": "
	       "%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
	       info->fix.smem_len >> 10,
	       info->var.xres, info->var.yres,
	       h_sync / 1000, h_sync % 1000, v_sync);


	fb_destroy_modedb(info->monspecs.modedb);
	info->monspecs.modedb = NULL;

2309
	err = register_framebuffer(info);
L
Linus Torvalds 已提交
2310 2311 2312
	if (err < 0)
		goto failed;

2313 2314
	printk(KERN_INFO "fb: S3 %s frame buffer device\n",
	       info->fix.id);
L
Linus Torvalds 已提交
2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326

	/*
	 * Our driver data
	 */
	pci_set_drvdata(dev, info);

	return 0;

 failed:
#ifdef CONFIG_FB_SAVAGE_I2C
	savagefb_delete_i2c_busses(info);
#endif
2327
	fb_alloc_cmap(&info->cmap, 0, 0);
L
Linus Torvalds 已提交
2328 2329
	savage_unmap_video(info);
 failed_video:
2330
	savage_unmap_mmio(info);
L
Linus Torvalds 已提交
2331 2332 2333 2334 2335 2336 2337 2338 2339 2340
 failed_mmio:
	kfree(info->pixmap.addr);
 failed_init:
	pci_release_regions(dev);
 failed_enable:
	framebuffer_release(info);

	return err;
}

2341
static void __devexit savagefb_remove(struct pci_dev *dev)
L
Linus Torvalds 已提交
2342
{
2343
	struct fb_info *info = pci_get_drvdata(dev);
L
Linus Torvalds 已提交
2344 2345 2346 2347 2348 2349 2350 2351 2352

	DBG("savagefb_remove");

	if (info) {
		/*
		 * If unregister_framebuffer fails, then
		 * we will be leaving hooks that could cause
		 * oopsen laying around.
		 */
2353 2354 2355
		if (unregister_framebuffer(info))
			printk(KERN_WARNING "savagefb: danger danger! "
			       "Oopsen imminent!\n");
L
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#ifdef CONFIG_FB_SAVAGE_I2C
		savagefb_delete_i2c_busses(info);
#endif
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		fb_alloc_cmap(&info->cmap, 0, 0);
		savage_unmap_video(info);
		savage_unmap_mmio(info);
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		kfree(info->pixmap.addr);
		pci_release_regions(dev);
		framebuffer_release(info);

		/*
		 * Ensure that the driver data is no longer
		 * valid.
		 */
		pci_set_drvdata(dev, NULL);
	}
}

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static int savagefb_suspend(struct pci_dev *dev, pm_message_t mesg)
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{
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	struct fb_info *info = pci_get_drvdata(dev);
	struct savagefb_par *par = info->par;
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	DBG("savagefb_suspend");

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	if (mesg.event == PM_EVENT_PRETHAW)
		mesg.event = PM_EVENT_FREEZE;
	par->pm_state = mesg.event;
	dev->dev.power.power_state = mesg;
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	/*
	 * For PM_EVENT_FREEZE, do not power down so the console
	 * can remain active.
	 */
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	if (mesg.event == PM_EVENT_FREEZE)
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		return 0;

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	console_lock();
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	fb_set_suspend(info, 1);
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	if (info->fbops->fb_sync)
		info->fbops->fb_sync(info);

	savagefb_blank(FB_BLANK_POWERDOWN, info);
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	savage_set_default_par(par, &par->save);
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	savage_disable_mmio(par);
	pci_save_state(dev);
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	pci_disable_device(dev);
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	pci_set_power_state(dev, pci_choose_state(dev, mesg));
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	console_unlock();
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	return 0;
}

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static int savagefb_resume(struct pci_dev* dev)
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{
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	struct fb_info *info = pci_get_drvdata(dev);
	struct savagefb_par *par = info->par;
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	int cur_state = par->pm_state;
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	DBG("savage_resume");

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	par->pm_state = PM_EVENT_ON;
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	/*
	 * The adapter was not powered down coming back from a
	 * PM_EVENT_FREEZE.
	 */
	if (cur_state == PM_EVENT_FREEZE) {
		pci_set_power_state(dev, PCI_D0);
		return 0;
	}
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	console_lock();
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	pci_set_power_state(dev, PCI_D0);
	pci_restore_state(dev);

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	if (pci_enable_device(dev))
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		DBG("err");

	pci_set_master(dev);
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	savage_enable_mmio(par);
	savage_init_hw(par);
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	savagefb_set_par(info);
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	fb_set_suspend(info, 0);
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	savagefb_blank(FB_BLANK_UNBLANK, info);
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	console_unlock();
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	return 0;
}


static struct pci_device_id savagefb_devices[] __devinitdata = {
	{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX128,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64C,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128SDR,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128DDR,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64SDR,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64DDR,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCSDR,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCDDR,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE4,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE4},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D_MV,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D_MV},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE2000,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE2000},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX_MV,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX_MV},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX_MV,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX_MV},

	{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX},

	{PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_PM,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_PM},

	{PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_KM,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_KM},

	{PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_P,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_P},

	{PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_K,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_K},

	{PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDR,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDR},

	{PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDRK,
	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDRK},

	{0, 0, 0, 0, 0, 0, 0}
};

MODULE_DEVICE_TABLE(pci, savagefb_devices);

static struct pci_driver savagefb_driver = {
	.name =     "savagefb",
	.id_table = savagefb_devices,
	.probe =    savagefb_probe,
	.suspend =  savagefb_suspend,
	.resume =   savagefb_resume,
	.remove =   __devexit_p(savagefb_remove)
};

/* **************************** exit-time only **************************** */

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static void __exit savage_done(void)
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{
	DBG("savage_done");
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	pci_unregister_driver(&savagefb_driver);
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}


/* ************************* init in-kernel code ************************** */

static int __init savagefb_setup(char *options)
{
#ifndef MODULE
	char *this_opt;

	if (!options || !*options)
		return 0;

	while ((this_opt = strsep(&options, ",")) != NULL) {
		mode_option = this_opt;
	}
#endif /* !MODULE */
	return 0;
}

static int __init savagefb_init(void)
{
	char *option;

	DBG("savagefb_init");

	if (fb_get_options("savagefb", &option))
		return -ENODEV;

	savagefb_setup(option);
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	return pci_register_driver(&savagefb_driver);
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}

module_init(savagefb_init);
module_exit(savage_done);
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module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Specify initial video mode");