acp-pcm-dma.c 35.3 KB
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/*
 * AMD ALSA SoC PCM Driver for ACP 2.x
 *
 * Copyright 2014-2015 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/module.h>
#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <linux/pm_runtime.h>
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#include <sound/soc.h>
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#include <drm/amd_asic_type.h>
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#include "acp.h"

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#define DRV_NAME "acp_audio_dma"

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#define PLAYBACK_MIN_NUM_PERIODS    2
#define PLAYBACK_MAX_NUM_PERIODS    2
#define PLAYBACK_MAX_PERIOD_SIZE    16384
#define PLAYBACK_MIN_PERIOD_SIZE    1024
#define CAPTURE_MIN_NUM_PERIODS     2
#define CAPTURE_MAX_NUM_PERIODS     2
#define CAPTURE_MAX_PERIOD_SIZE     16384
#define CAPTURE_MIN_PERIOD_SIZE     1024

#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
#define MIN_BUFFER MAX_BUFFER

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#define ST_PLAYBACK_MAX_PERIOD_SIZE 8192
#define ST_CAPTURE_MAX_PERIOD_SIZE  ST_PLAYBACK_MAX_PERIOD_SIZE
#define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
#define ST_MIN_BUFFER ST_MAX_BUFFER

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#define DRV_NAME "acp_audio_dma"

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static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
	.info = SNDRV_PCM_INFO_INTERLEAVED |
		SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
		SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
		SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
	.formats = SNDRV_PCM_FMTBIT_S16_LE |
		SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
	.channels_min = 1,
	.channels_max = 8,
	.rates = SNDRV_PCM_RATE_8000_96000,
	.rate_min = 8000,
	.rate_max = 96000,
	.buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
	.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
	.period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
	.periods_min = PLAYBACK_MIN_NUM_PERIODS,
	.periods_max = PLAYBACK_MAX_NUM_PERIODS,
};

static const struct snd_pcm_hardware acp_pcm_hardware_capture = {
	.info = SNDRV_PCM_INFO_INTERLEAVED |
		SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
		SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
	    SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
	.formats = SNDRV_PCM_FMTBIT_S16_LE |
		SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
	.channels_min = 1,
	.channels_max = 2,
	.rates = SNDRV_PCM_RATE_8000_48000,
	.rate_min = 8000,
	.rate_max = 48000,
	.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
	.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
	.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
	.periods_min = CAPTURE_MIN_NUM_PERIODS,
	.periods_max = CAPTURE_MAX_NUM_PERIODS,
};

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static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {
	.info = SNDRV_PCM_INFO_INTERLEAVED |
		SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
		SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
		SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
	.formats = SNDRV_PCM_FMTBIT_S16_LE |
		SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
	.channels_min = 1,
	.channels_max = 8,
	.rates = SNDRV_PCM_RATE_8000_96000,
	.rate_min = 8000,
	.rate_max = 96000,
	.buffer_bytes_max = ST_MAX_BUFFER,
	.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
	.period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,
	.periods_min = PLAYBACK_MIN_NUM_PERIODS,
	.periods_max = PLAYBACK_MAX_NUM_PERIODS,
};

static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {
	.info = SNDRV_PCM_INFO_INTERLEAVED |
		SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
		SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
		SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
	.formats = SNDRV_PCM_FMTBIT_S16_LE |
		SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
	.channels_min = 1,
	.channels_max = 2,
	.rates = SNDRV_PCM_RATE_8000_48000,
	.rate_min = 8000,
	.rate_max = 48000,
	.buffer_bytes_max = ST_MAX_BUFFER,
	.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
	.period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,
	.periods_min = CAPTURE_MIN_NUM_PERIODS,
	.periods_max = CAPTURE_MAX_NUM_PERIODS,
};

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static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
{
	return readl(acp_mmio + (reg * 4));
}

static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)
{
	writel(val, acp_mmio + (reg * 4));
}

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/*
 * Configure a given dma channel parameters - enable/disable,
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 * number of descriptors, priority
 */
static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
				   u16 dscr_strt_idx, u16 num_dscrs,
				   enum acp_dma_priority_level priority_level)
{
	u32 dma_ctrl;

	/* disable the channel run field */
	dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
	dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
	acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);

	/* program a DMA channel with first descriptor to be processed. */
	acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK
			& dscr_strt_idx),
			acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);

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	/*
	 * program a DMA channel with the number of descriptors to be
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	 * processed in the transfer
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	 */
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	acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,
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		      acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);
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	/* set DMA channel priority */
	acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
}

/* Initialize a dma descriptor in SRAM based on descritor information passed */
static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
					  u16 descr_idx,
					  acp_dma_dscr_transfer_t *descr_info)
{
	u32 sram_offset;

	sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t));

	/* program the source base address. */
	acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
	acp_reg_write(descr_info->src,	acp_mmio, mmACP_SRBM_Targ_Idx_Data);
	/* program the destination base address. */
	acp_reg_write(sram_offset + 4,	acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
	acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);

	/* program the number of bytes to be transferred for this descriptor. */
	acp_reg_write(sram_offset + 8,	acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
	acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
}

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/*
 * Initialize the DMA descriptor information for transfer between
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 * system memory <-> ACP SRAM
 */
static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
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					   u32 size, int direction,
					   u32 pte_offset, u16 ch,
					   u32 sram_bank, u16 dma_dscr_idx,
					   u32 asic_type)
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{
	u16 i;
	acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];

	for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
		dmadscr[i].xfer_val = 0;
		if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
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			dma_dscr_idx = dma_dscr_idx + i;
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			dmadscr[i].dest = sram_bank + (i * (size / 2));
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			dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
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				+ (pte_offset * SZ_4K) + (i * (size / 2));
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			switch (asic_type) {
			case CHIP_STONEY:
				dmadscr[i].xfer_val |=
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				(ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM  << 16) |
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				(size / 2);
				break;
			default:
				dmadscr[i].xfer_val |=
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				(ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM  << 16) |
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				(size / 2);
			}
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		} else {
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			dma_dscr_idx = dma_dscr_idx + i;
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			dmadscr[i].src = sram_bank + (i * (size / 2));
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			dmadscr[i].dest =
			ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
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			(pte_offset * SZ_4K) + (i * (size / 2));
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			switch (asic_type) {
			case CHIP_STONEY:
				dmadscr[i].xfer_val |=
				BIT(22) |
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				(ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) |
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				(size / 2);
				break;
			default:
				dmadscr[i].xfer_val |=
				BIT(22) |
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				(ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) |
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				(size / 2);
			}
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		}
		config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
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					      &dmadscr[i]);
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	}
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	config_acp_dma_channel(acp_mmio, ch,
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			       dma_dscr_idx - 1,
			       NUM_DSCRS_PER_CHANNEL,
			       ACP_DMA_PRIORITY_LEVEL_NORMAL);
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}

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/*
 * Initialize the DMA descriptor information for transfer between
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 * ACP SRAM <-> I2S
 */
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static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
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					   int direction, u32 sram_bank,
					   u16 destination, u16 ch,
					   u16 dma_dscr_idx, u32 asic_type)
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{
	u16 i;
	acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];

	for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
		dmadscr[i].xfer_val = 0;
		if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
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			dma_dscr_idx = dma_dscr_idx + i;
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			dmadscr[i].src = sram_bank  + (i * (size / 2));
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			/* dmadscr[i].dest is unused by hardware. */
			dmadscr[i].dest = 0;
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			dmadscr[i].xfer_val |= BIT(22) | (destination << 16) |
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						(size / 2);
		} else {
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			dma_dscr_idx = dma_dscr_idx + i;
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			/* dmadscr[i].src is unused by hardware. */
			dmadscr[i].src = 0;
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			dmadscr[i].dest =
				 sram_bank + (i * (size / 2));
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			dmadscr[i].xfer_val |= BIT(22) |
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				(destination << 16) | (size / 2);
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		}
		config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
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					      &dmadscr[i]);
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	}
	/* Configure the DMA channel with the above descriptore */
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	config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
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			       NUM_DSCRS_PER_CHANNEL,
			       ACP_DMA_PRIORITY_LEVEL_NORMAL);
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}

/* Create page table entries in ACP SRAM for the allocated memory */
static void acp_pte_config(void __iomem *acp_mmio, struct page *pg,
			   u16 num_of_pages, u32 pte_offset)
{
	u16 page_idx;
	u64 addr;
	u32 low;
	u32 high;
	u32 offset;

	offset	= ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8);
	for (page_idx = 0; page_idx < (num_of_pages); page_idx++) {
		/* Load the low address of page int ACP SRAM through SRBM */
		acp_reg_write((offset + (page_idx * 8)),
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			      acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
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		addr = page_to_phys(pg);

		low = lower_32_bits(addr);
		high = upper_32_bits(addr);

		acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);

		/* Load the High address of page int ACP SRAM through SRBM */
		acp_reg_write((offset + (page_idx * 8) + 4),
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			      acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
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		/* page enable in ACP */
		high |= BIT(31);
		acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);

		/* Move to next physically contiguos page */
		pg++;
	}
}

static void config_acp_dma(void __iomem *acp_mmio,
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			   struct audio_substream_data *rtd,
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			   u32 asic_type)
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{
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	u32 pte_offset, sram_bank;
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	if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
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		pte_offset = ACP_PLAYBACK_PTE_OFFSET;
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		sram_bank = ACP_SHARED_RAM_BANK_1_ADDRESS;
	} else {
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		pte_offset = ACP_CAPTURE_PTE_OFFSET;
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		switch (asic_type) {
		case CHIP_STONEY:
			sram_bank = ACP_SHARED_RAM_BANK_3_ADDRESS;
			break;
		default:
			sram_bank = ACP_SHARED_RAM_BANK_5_ADDRESS;
		}
	}
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	acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages,
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		       pte_offset);
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	/* Configure System memory <-> ACP SRAM DMA descriptors */
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	set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
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				       rtd->direction, pte_offset,
				       rtd->ch1, sram_bank,
				       rtd->dma_dscr_idx_1, asic_type);
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	/* Configure ACP SRAM <-> I2S DMA descriptors */
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	set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,
				       rtd->direction, sram_bank,
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				       rtd->destination, rtd->ch2,
				       rtd->dma_dscr_idx_2, asic_type);
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}

/* Start a given DMA channel transfer */
static void acp_dma_start(void __iomem *acp_mmio,
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			  u16 ch_num, bool is_circular)
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{
	u32 dma_ctrl;

	/* read the dma control register and disable the channel run field */
	dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);

	/* Invalidating the DAGB cache */
	acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);

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	/*
	 * configure the DMA channel and start the DMA transfer
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	 * set dmachrun bit to start the transfer and enable the
	 * interrupt on completion of the dma transfer
	 */
	dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK;

	switch (ch_num) {
	case ACP_TO_I2S_DMA_CH_NUM:
	case ACP_TO_SYSRAM_CH_NUM:
	case I2S_TO_ACP_DMA_CH_NUM:
		dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
		break;
	default:
		dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
		break;
	}

	/* enable  for ACP SRAM to/from I2S DMA channel */
	if (is_circular == true)
		dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
	else
		dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK;

	acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
}

/* Stop a given DMA channel transfer */
static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)
{
	u32 dma_ctrl;
	u32 dma_ch_sts;
	u32 count = ACP_DMA_RESET_TIME;

	dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);

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	/*
	 * clear the dma control register fields before writing zero
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	 * in reset bit
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	 */
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	dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
	dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;

	acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
	dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);

	if (dma_ch_sts & BIT(ch_num)) {
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		/*
		 * set the reset bit for this channel to stop the dma
		 *  transfer
		 */
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		dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;
		acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
	}

	/* check the channel status bit for some time and return the status */
	while (true) {
		dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
		if (!(dma_ch_sts & BIT(ch_num))) {
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			/*
			 * clear the reset flag after successfully stopping
			 * the dma transfer and break from the loop
			 */
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			dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;

			acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0
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				      + ch_num);
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			break;
		}
		if (--count == 0) {
			pr_err("Failed to stop ACP DMA channel : %d\n", ch_num);
			return -ETIMEDOUT;
		}
		udelay(100);
	}
	return 0;
}

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static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,
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				    bool power_on)
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{
	u32 val, req_reg, sts_reg, sts_reg_mask;
	u32 loops = 1000;

	if (bank < 32) {
		req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO;
		sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO;
		sts_reg_mask = 0xFFFFFFFF;

	} else {
		bank -= 32;
		req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI;
		sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI;
		sts_reg_mask = 0x0000FFFF;
	}

	val = acp_reg_read(acp_mmio, req_reg);
	if (val & (1 << bank)) {
		/* bank is in off state */
		if (power_on == true)
			/* request to on */
			val &= ~(1 << bank);
		else
			/* request to off */
			return;
	} else {
		/* bank is in on state */
		if (power_on == false)
			/* request to off */
			val |= 1 << bank;
		else
			/* request to on */
			return;
	}
	acp_reg_write(val, acp_mmio, req_reg);

	while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {
		if (!loops--) {
			pr_err("ACP SRAM bank %d state change failed\n", bank);
			break;
		}
		cpu_relax();
	}
}

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/* Initialize and bring ACP hardware to default state. */
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static int acp_init(void __iomem *acp_mmio, u32 asic_type)
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{
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	u16 bank;
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	u32 val, count, sram_pte_offset;

	/* Assert Soft reset of ACP */
	val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);

	val |= ACP_SOFT_RESET__SoftResetAud_MASK;
	acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);

	count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
	while (true) {
		val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
		if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
		    (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
			break;
		if (--count == 0) {
			pr_err("Failed to reset ACP\n");
			return -ETIMEDOUT;
		}
		udelay(100);
	}

	/* Enable clock to ACP and wait until the clock is enabled */
	val = acp_reg_read(acp_mmio, mmACP_CONTROL);
	val = val | ACP_CONTROL__ClkEn_MASK;
	acp_reg_write(val, acp_mmio, mmACP_CONTROL);

	count = ACP_CLOCK_EN_TIME_OUT_VALUE;

	while (true) {
		val = acp_reg_read(acp_mmio, mmACP_STATUS);
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		if (val & (u32)0x1)
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			break;
		if (--count == 0) {
			pr_err("Failed to reset ACP\n");
			return -ETIMEDOUT;
		}
		udelay(100);
	}

	/* Deassert the SOFT RESET flags */
	val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
	val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
	acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);

	/* initiailize Onion control DAGB register */
	acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
539
		      mmACP_AXI2DAGB_ONION_CNTL);
540 541 542

	/* initiailize Garlic control DAGB registers */
	acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
543
		      mmACP_AXI2DAGB_GARLIC_CNTL);
544 545 546 547 548 549 550

	sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS |
			ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK |
			ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK |
			ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK;
	acp_reg_write(sram_pte_offset,  acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);
	acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,
551
		      mmACP_DAGB_PAGE_SIZE_GRP_1);
552 553

	acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
554
		      mmACP_DMA_DESC_BASE_ADDR);
555 556 557 558

	/* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */
	acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
	acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
559
		      acp_mmio, mmACP_EXTERNAL_INTR_CNTL);
560

561 562
       /*
	* When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
563 564
	* Now, turn off all of them. This can't be done in 'poweron' of
	* ACP pm domain, as this requires ACP to be initialized.
565 566 567
	* For Stoney, Memory gating is disabled,i.e SRAM Banks
	* won't be turned off. The default state for SRAM banks is ON.
	* Setting SRAM bank state code skipped for STONEY platform.
568
	*/
569 570 571 572
	if (asic_type != CHIP_STONEY) {
		for (bank = 1; bank < 48; bank++)
			acp_set_sram_bank_state(acp_mmio, bank, false);
	}
573 574 575
	return 0;
}

576
/* Deinitialize ACP */
577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599
static int acp_deinit(void __iomem *acp_mmio)
{
	u32 val;
	u32 count;

	/* Assert Soft reset of ACP */
	val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);

	val |= ACP_SOFT_RESET__SoftResetAud_MASK;
	acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);

	count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
	while (true) {
		val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
		if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
		    (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
			break;
		if (--count == 0) {
			pr_err("Failed to reset ACP\n");
			return -ETIMEDOUT;
		}
		udelay(100);
	}
600
	/* Disable ACP clock */
601 602 603 604 605 606 607 608
	val = acp_reg_read(acp_mmio, mmACP_CONTROL);
	val &= ~ACP_CONTROL__ClkEn_MASK;
	acp_reg_write(val, acp_mmio, mmACP_CONTROL);

	count = ACP_CLOCK_EN_TIME_OUT_VALUE;

	while (true) {
		val = acp_reg_read(acp_mmio, mmACP_STATUS);
609
		if (!(val & (u32)0x1))
610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642
			break;
		if (--count == 0) {
			pr_err("Failed to reset ACP\n");
			return -ETIMEDOUT;
		}
		udelay(100);
	}
	return 0;
}

/* ACP DMA irq handler routine for playback, capture usecases */
static irqreturn_t dma_irq_handler(int irq, void *arg)
{
	u16 dscr_idx;
	u32 intr_flag, ext_intr_status;
	struct audio_drv_data *irq_data;
	void __iomem *acp_mmio;
	struct device *dev = arg;
	bool valid_irq = false;

	irq_data = dev_get_drvdata(dev);
	acp_mmio = irq_data->acp_mmio;

	ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);
	intr_flag = (((ext_intr_status &
		      ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >>
		     ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT));

	if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) {
		valid_irq = true;
		if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_13) ==
				PLAYBACK_START_DMA_DESCR_CH13)
			dscr_idx = PLAYBACK_END_DMA_DESCR_CH12;
643 644
		else
			dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
645 646 647 648
		config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, dscr_idx,
				       1, 0);
		acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false);

649
		snd_pcm_period_elapsed(irq_data->play_i2ssp_stream);
650 651

		acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
652
			      acp_mmio, mmACP_EXTERNAL_INTR_STAT);
653 654 655 656 657 658 659 660 661 662 663 664 665 666
	}

	if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
		valid_irq = true;
		if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_15) ==
				CAPTURE_START_DMA_DESCR_CH15)
			dscr_idx = CAPTURE_END_DMA_DESCR_CH14;
		else
			dscr_idx = CAPTURE_START_DMA_DESCR_CH14;
		config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx,
				       1, 0);
		acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false);

		acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
667
			      acp_mmio, mmACP_EXTERNAL_INTR_STAT);
668 669 670 671
	}

	if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) {
		valid_irq = true;
672
		snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
673
		acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16,
674
			      acp_mmio, mmACP_EXTERNAL_INTR_STAT);
675 676 677 678 679 680 681 682 683 684
	}

	if (valid_irq)
		return IRQ_HANDLED;
	else
		return IRQ_NONE;
}

static int acp_dma_open(struct snd_pcm_substream *substream)
{
685
	u16 bank;
686 687 688
	int ret = 0;
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct snd_soc_pcm_runtime *prtd = substream->private_data;
689 690
	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
								    DRV_NAME);
691
	struct audio_drv_data *intr_data = dev_get_drvdata(component->dev);
692 693
	struct audio_substream_data *adata =
		kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);
694
	if (!adata)
695 696
		return -ENOMEM;

697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		switch (intr_data->asic_type) {
		case CHIP_STONEY:
			runtime->hw = acp_st_pcm_hardware_playback;
			break;
		default:
			runtime->hw = acp_pcm_hardware_playback;
		}
	} else {
		switch (intr_data->asic_type) {
		case CHIP_STONEY:
			runtime->hw = acp_st_pcm_hardware_capture;
			break;
		default:
			runtime->hw = acp_pcm_hardware_capture;
		}
	}
714 715 716 717

	ret = snd_pcm_hw_constraint_integer(runtime,
					    SNDRV_PCM_HW_PARAM_PERIODS);
	if (ret < 0) {
718
		dev_err(component->dev, "set integer constraint failed\n");
D
Dan Carpenter 已提交
719
		kfree(adata);
720 721 722 723 724 725
		return ret;
	}

	adata->acp_mmio = intr_data->acp_mmio;
	runtime->private_data = adata;

726 727
	/*
	 * Enable ACP irq, when neither playback or capture streams are
728 729 730
	 * active by the time when a new stream is being opened.
	 * This enablement is not required for another stream, if current
	 * stream is not closed
731
	 */
732
	if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream)
733 734
		acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);

735
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
736
		intr_data->play_i2ssp_stream = substream;
737 738
		/*
		 * For Stoney, Memory gating is disabled,i.e SRAM Banks
739 740 741 742 743 744 745 746
		 * won't be turned off. The default state for SRAM banks is ON.
		 * Setting SRAM bank state code skipped for STONEY platform.
		 */
		if (intr_data->asic_type != CHIP_STONEY) {
			for (bank = 1; bank <= 4; bank++)
				acp_set_sram_bank_state(intr_data->acp_mmio,
							bank, true);
		}
747
	} else {
748
		intr_data->capture_i2ssp_stream = substream;
749 750 751 752 753
		if (intr_data->asic_type != CHIP_STONEY) {
			for (bank = 5; bank <= 8; bank++)
				acp_set_sram_bank_state(intr_data->acp_mmio,
							bank, true);
		}
754
	}
755 756 757 758 759 760 761 762 763

	return 0;
}

static int acp_dma_hw_params(struct snd_pcm_substream *substream,
			     struct snd_pcm_hw_params *params)
{
	int status;
	uint64_t size;
764
	u32 val = 0;
765 766 767
	struct page *pg;
	struct snd_pcm_runtime *runtime;
	struct audio_substream_data *rtd;
768
	struct snd_soc_pcm_runtime *prtd = substream->private_data;
769 770
	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
								    DRV_NAME);
771
	struct audio_drv_data *adata = dev_get_drvdata(component->dev);
772 773 774 775 776 777 778

	runtime = substream->runtime;
	rtd = runtime->private_data;

	if (WARN_ON(!rtd))
		return -EINVAL;

779
	if (adata->asic_type == CHIP_STONEY) {
780 781
		val = acp_reg_read(adata->acp_mmio,
				   mmACP_I2S_16BIT_RESOLUTION_EN);
782 783 784 785
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			val |= ACP_I2S_SP_16BIT_RESOLUTION_EN;
		else
			val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN;
786 787
		acp_reg_write(val, adata->acp_mmio,
			      mmACP_I2S_16BIT_RESOLUTION_EN);
788
	}
789 790 791 792 793 794 795 796 797 798 799 800 801 802 803

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;
		rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;
		rtd->destination = TO_ACP_I2S_1;
		rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12;
		rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13;
	} else {
		rtd->ch1 = ACP_TO_SYSRAM_CH_NUM;
		rtd->ch2 = I2S_TO_ACP_DMA_CH_NUM;
		rtd->destination = FROM_ACP_I2S_1;
		rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14;
		rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15;
	}

804 805 806 807 808 809 810 811
	size = params_buffer_bytes(params);
	status = snd_pcm_lib_malloc_pages(substream, size);
	if (status < 0)
		return status;

	memset(substream->runtime->dma_area, 0, params_buffer_bytes(params));
	pg = virt_to_page(substream->dma_buffer.area);

812
	if (pg) {
813
		acp_set_sram_bank_state(rtd->acp_mmio, 0, true);
814 815 816 817 818 819 820 821 822 823
		/* Save for runtime private data */
		rtd->pg = pg;
		rtd->order = get_order(size);

		/* Fill the page table entries in ACP SRAM */
		rtd->pg = pg;
		rtd->size = size;
		rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
		rtd->direction = substream->stream;

824
		config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type);
825 826 827 828 829 830 831 832 833 834 835 836
		status = 0;
	} else {
		status = -ENOMEM;
	}
	return status;
}

static int acp_dma_hw_free(struct snd_pcm_substream *substream)
{
	return snd_pcm_lib_free_pages(substream);
}

837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858
static u64 acp_get_byte_count(void __iomem *acp_mmio, int stream)
{
	union acp_dma_count playback_dma_count;
	union acp_dma_count capture_dma_count;
	u64 bytescount = 0;

	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		playback_dma_count.bcount.high = acp_reg_read(acp_mmio,
					mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH);
		playback_dma_count.bcount.low  = acp_reg_read(acp_mmio,
					mmACP_I2S_TRANSMIT_BYTE_CNT_LOW);
		bytescount = playback_dma_count.bytescount;
	} else {
		capture_dma_count.bcount.high = acp_reg_read(acp_mmio,
					mmACP_I2S_RECEIVED_BYTE_CNT_HIGH);
		capture_dma_count.bcount.low  = acp_reg_read(acp_mmio,
					mmACP_I2S_RECEIVED_BYTE_CNT_LOW);
		bytescount = capture_dma_count.bytescount;
	}
	return bytescount;
}

859 860
static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream)
{
861
	u32 buffersize;
862
	u32 pos = 0;
863
	u64 bytescount = 0;
864 865 866 867

	struct snd_pcm_runtime *runtime = substream->runtime;
	struct audio_substream_data *rtd = runtime->private_data;

868 869 870
	if (!rtd)
		return -EINVAL;

871 872
	buffersize = frames_to_bytes(runtime, runtime->buffer_size);
	bytescount = acp_get_byte_count(rtd->acp_mmio, substream->stream);
873

874
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
875 876
		if (bytescount > rtd->i2ssp_renderbytescount)
			bytescount = bytescount - rtd->i2ssp_renderbytescount;
877
	} else {
878 879
		if (bytescount > rtd->i2ssp_capturebytescount)
			bytescount = bytescount - rtd->i2ssp_capturebytescount;
880
	}
881
	pos = do_div(bytescount, buffersize);
882 883 884 885 886 887 888 889 890 891 892 893 894 895
	return bytes_to_frames(runtime, pos);
}

static int acp_dma_mmap(struct snd_pcm_substream *substream,
			struct vm_area_struct *vma)
{
	return snd_pcm_lib_default_mmap(substream, vma);
}

static int acp_dma_prepare(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct audio_substream_data *rtd = runtime->private_data;

896 897
	if (!rtd)
		return -EINVAL;
898 899 900 901 902 903 904 905 906

	config_acp_dma_channel(rtd->acp_mmio,
			       rtd->ch1,
			       rtd->dma_dscr_idx_1,
			       NUM_DSCRS_PER_CHANNEL, 0);
	config_acp_dma_channel(rtd->acp_mmio,
			       rtd->ch2,
			       rtd->dma_dscr_idx_2,
			       NUM_DSCRS_PER_CHANNEL, 0);
907 908 909 910 911 912
	return 0;
}

static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
{
	int ret;
913
	u32 loops = 4000;
914
	u64 bytescount = 0;
915 916 917 918

	struct snd_pcm_runtime *runtime = substream->runtime;
	struct snd_soc_pcm_runtime *prtd = substream->private_data;
	struct audio_substream_data *rtd = runtime->private_data;
919 920
	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
								    DRV_NAME);
921 922 923 924 925 926 927

	if (!rtd)
		return -EINVAL;
	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
928 929
		bytescount = acp_get_byte_count(rtd->acp_mmio,
						substream->stream);
930
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
931 932
			if (rtd->i2ssp_renderbytescount == 0)
				rtd->i2ssp_renderbytescount = bytescount;
933
			acp_dma_start(rtd->acp_mmio, rtd->ch1, false);
934
			while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) &
935
				BIT(rtd->ch1)) {
936
				if (!loops--) {
937
					dev_err(component->dev,
938 939 940 941 942 943
						"acp dma start timeout\n");
					return -ETIMEDOUT;
				}
				cpu_relax();
			}
		} else {
944 945
			if (rtd->i2ssp_capturebytescount == 0)
				rtd->i2ssp_capturebytescount = bytescount;
946
		}
947
		acp_dma_start(rtd->acp_mmio, rtd->ch2, true);
948 949 950 951 952
		ret = 0;
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	case SNDRV_PCM_TRIGGER_SUSPEND:
953 954 955 956 957 958 959
		/* For playback, non circular dma should be stopped first
		 * i.e Sysram to acp dma transfer channel(rtd->ch1) should be
		 * stopped before stopping cirular dma which is acp sram to i2s
		 * fifo dma transfer channel(rtd->ch2). Where as in Capture
		 * scenario, i2s fifo to acp sram dma channel(rtd->ch2) stopped
		 * first before stopping acp sram to sysram which is circular
		 * dma(rtd->ch1).
960
		 */
961
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
962 963
			acp_dma_stop(rtd->acp_mmio, rtd->ch1);
			ret =  acp_dma_stop(rtd->acp_mmio, rtd->ch2);
964
			rtd->i2ssp_renderbytescount = 0;
965
		} else {
966 967
			acp_dma_stop(rtd->acp_mmio, rtd->ch2);
			ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);
968
			rtd->i2ssp_capturebytescount = 0;
969
		}
970 971 972 973 974 975 976 977 978
		break;
	default:
		ret = -EINVAL;
	}
	return ret;
}

static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
{
979
	int ret;
980 981
	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd,
								    DRV_NAME);
982
	struct audio_drv_data *adata = dev_get_drvdata(component->dev);
983 984 985 986

	switch (adata->asic_type) {
	case CHIP_STONEY:
		ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
987 988 989
							    SNDRV_DMA_TYPE_DEV,
							    NULL, ST_MIN_BUFFER,
							    ST_MAX_BUFFER);
990 991 992
		break;
	default:
		ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
993 994 995
							    SNDRV_DMA_TYPE_DEV,
							    NULL, MIN_BUFFER,
							    MAX_BUFFER);
996 997 998
		break;
	}
	if (ret < 0)
999
		dev_err(component->dev,
1000
			"buffer preallocation failure error:%d\n", ret);
1001
	return ret;
1002 1003 1004 1005
}

static int acp_dma_close(struct snd_pcm_substream *substream)
{
1006
	u16 bank;
1007 1008 1009
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct audio_substream_data *rtd = runtime->private_data;
	struct snd_soc_pcm_runtime *prtd = substream->private_data;
1010 1011
	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
								    DRV_NAME);
1012
	struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1013 1014 1015

	kfree(rtd);

1016
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1017
		adata->play_i2ssp_stream = NULL;
1018 1019
		/*
		 * For Stoney, Memory gating is disabled,i.e SRAM Banks
1020 1021 1022 1023 1024 1025 1026
		 * won't be turned off. The default state for SRAM banks is ON.
		 * Setting SRAM bank state code skipped for STONEY platform.
		 * added condition checks for Carrizo platform only
		 */
		if (adata->asic_type != CHIP_STONEY) {
			for (bank = 1; bank <= 4; bank++)
				acp_set_sram_bank_state(adata->acp_mmio, bank,
1027
							false);
1028 1029
		}
	} else  {
1030
		adata->capture_i2ssp_stream = NULL;
1031 1032 1033
		if (adata->asic_type != CHIP_STONEY) {
			for (bank = 5; bank <= 8; bank++)
				acp_set_sram_bank_state(adata->acp_mmio, bank,
1034
							false);
1035
		}
1036
	}
1037

1038 1039
	/*
	 * Disable ACP irq, when the current stream is being closed and
1040
	 * another stream is also not active.
1041
	 */
1042
	if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream)
1043 1044 1045 1046 1047
		acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);

	return 0;
}

1048
static const struct snd_pcm_ops acp_dma_ops = {
1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059
	.open = acp_dma_open,
	.close = acp_dma_close,
	.ioctl = snd_pcm_lib_ioctl,
	.hw_params = acp_dma_hw_params,
	.hw_free = acp_dma_hw_free,
	.trigger = acp_dma_trigger,
	.pointer = acp_dma_pointer,
	.mmap = acp_dma_mmap,
	.prepare = acp_dma_prepare,
};

1060
static const struct snd_soc_component_driver acp_asoc_platform = {
1061
	.name = DRV_NAME,
1062 1063 1064 1065 1066 1067 1068 1069 1070
	.ops = &acp_dma_ops,
	.pcm_new = acp_dma_new,
};

static int acp_audio_probe(struct platform_device *pdev)
{
	int status;
	struct audio_drv_data *audio_drv_data;
	struct resource *res;
1071
	const u32 *pdata = pdev->dev.platform_data;
1072

1073 1074 1075 1076 1077
	if (!pdata) {
		dev_err(&pdev->dev, "Missing platform data\n");
		return -ENODEV;
	}

1078
	audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),
1079 1080
				      GFP_KERNEL);
	if (!audio_drv_data)
1081 1082 1083 1084
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res);
1085 1086
	if (IS_ERR(audio_drv_data->acp_mmio))
		return PTR_ERR(audio_drv_data->acp_mmio);
1087

1088 1089
	/*
	 * The following members gets populated in device 'open'
1090 1091 1092 1093
	 * function. Till then interrupts are disabled in 'acp_init'
	 * and device doesn't generate any interrupts.
	 */

1094 1095 1096
	audio_drv_data->play_i2ssp_stream = NULL;
	audio_drv_data->capture_i2ssp_stream = NULL;

1097
	audio_drv_data->asic_type =  *pdata;
1098 1099 1100 1101 1102 1103 1104 1105

	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res) {
		dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
		return -ENODEV;
	}

	status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler,
1106
				  0, "ACP_IRQ", &pdev->dev);
1107 1108 1109 1110 1111 1112 1113 1114
	if (status) {
		dev_err(&pdev->dev, "ACP IRQ request failed\n");
		return status;
	}

	dev_set_drvdata(&pdev->dev, audio_drv_data);

	/* Initialize the ACP */
1115 1116 1117 1118 1119
	status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);
	if (status) {
		dev_err(&pdev->dev, "ACP Init failed status:%d\n", status);
		return status;
	}
1120

1121
	status = devm_snd_soc_register_component(&pdev->dev,
1122
						 &acp_asoc_platform, NULL, 0);
1123 1124 1125 1126 1127
	if (status != 0) {
		dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
		return status;
	}

1128 1129 1130 1131
	pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_enable(&pdev->dev);

1132 1133 1134 1135 1136
	return status;
}

static int acp_audio_remove(struct platform_device *pdev)
{
1137
	int status;
1138 1139
	struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev);

1140 1141 1142
	status = acp_deinit(adata->acp_mmio);
	if (status)
		dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status);
1143
	pm_runtime_disable(&pdev->dev);
1144 1145 1146 1147

	return 0;
}

1148 1149
static int acp_pcm_resume(struct device *dev)
{
1150
	u16 bank;
1151
	int status;
1152 1153
	struct audio_drv_data *adata = dev_get_drvdata(dev);

1154 1155 1156 1157 1158
	status = acp_init(adata->acp_mmio, adata->asic_type);
	if (status) {
		dev_err(dev, "ACP Init failed status:%d\n", status);
		return status;
	}
1159

1160
	if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) {
1161 1162
		/*
		 * For Stoney, Memory gating is disabled,i.e SRAM Banks
1163 1164 1165 1166 1167 1168
		 * won't be turned off. The default state for SRAM banks is ON.
		 * Setting SRAM bank state code skipped for STONEY platform.
		 */
		if (adata->asic_type != CHIP_STONEY) {
			for (bank = 1; bank <= 4; bank++)
				acp_set_sram_bank_state(adata->acp_mmio, bank,
1169
							true);
1170
		}
1171
		config_acp_dma(adata->acp_mmio,
1172 1173
			       adata->play_i2ssp_stream->runtime->private_data,
			       adata->asic_type);
1174
	}
1175 1176
	if (adata->capture_i2ssp_stream &&
	    adata->capture_i2ssp_stream->runtime) {
1177 1178 1179
		if (adata->asic_type != CHIP_STONEY) {
			for (bank = 5; bank <= 8; bank++)
				acp_set_sram_bank_state(adata->acp_mmio, bank,
1180
							true);
1181
		}
1182
		config_acp_dma(adata->acp_mmio,
1183 1184
			       adata->capture_i2ssp_stream->runtime->private_data,
			       adata->asic_type);
1185
	}
1186 1187 1188 1189 1190 1191
	acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
	return 0;
}

static int acp_pcm_runtime_suspend(struct device *dev)
{
1192
	int status;
1193 1194
	struct audio_drv_data *adata = dev_get_drvdata(dev);

1195 1196 1197
	status = acp_deinit(adata->acp_mmio);
	if (status)
		dev_err(dev, "ACP Deinit failed status:%d\n", status);
1198 1199 1200 1201 1202 1203
	acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
	return 0;
}

static int acp_pcm_runtime_resume(struct device *dev)
{
1204
	int status;
1205 1206
	struct audio_drv_data *adata = dev_get_drvdata(dev);

1207 1208 1209 1210 1211
	status = acp_init(adata->acp_mmio, adata->asic_type);
	if (status) {
		dev_err(dev, "ACP Init failed status:%d\n", status);
		return status;
	}
1212 1213 1214 1215 1216 1217 1218 1219 1220 1221
	acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
	return 0;
}

static const struct dev_pm_ops acp_pm_ops = {
	.resume = acp_pcm_resume,
	.runtime_suspend = acp_pcm_runtime_suspend,
	.runtime_resume = acp_pcm_runtime_resume,
};

1222 1223 1224 1225
static struct platform_driver acp_dma_driver = {
	.probe = acp_audio_probe,
	.remove = acp_audio_remove,
	.driver = {
1226
		.name = DRV_NAME,
1227
		.pm = &acp_pm_ops,
1228 1229 1230 1231 1232
	},
};

module_platform_driver(acp_dma_driver);

1233
MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
1234 1235 1236
MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
MODULE_DESCRIPTION("AMD ACP PCM Driver");
MODULE_LICENSE("GPL v2");
1237
MODULE_ALIAS("platform:"DRV_NAME);