sata_sil24.c 37.4 KB
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/*
 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
 *
 * Copyright 2005  Tejun Heo
 *
 * Based on preview driver from Silicon Image.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2, or (at your option) any
 * later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <scsi/scsi_cmnd.h>
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#include <linux/libata.h>

#define DRV_NAME	"sata_sil24"
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#define DRV_VERSION	"1.1"
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/*
 * Port request block (PRB) 32 bytes
 */
struct sil24_prb {
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	__le16	ctrl;
	__le16	prot;
	__le32	rx_cnt;
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	u8	fis[6 * 4];
};

/*
 * Scatter gather entry (SGE) 16 bytes
 */
struct sil24_sge {
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	__le64	addr;
	__le32	cnt;
	__le32	flags;
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};

/*
 * Port multiplier
 */
struct sil24_port_multiplier {
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	__le32	diag;
	__le32	sactive;
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};

enum {
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	SIL24_HOST_BAR		= 0,
	SIL24_PORT_BAR		= 2,

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	/* sil24 fetches in chunks of 64bytes.  The first block
	 * contains the PRB and two SGEs.  From the second block, it's
	 * consisted of four SGEs and called SGT.  Calculate the
	 * number of SGTs that fit into one page.
	 */
	SIL24_PRB_SZ		= sizeof(struct sil24_prb)
				  + 2 * sizeof(struct sil24_sge),
	SIL24_MAX_SGT		= (PAGE_SIZE - SIL24_PRB_SZ)
				  / (4 * sizeof(struct sil24_sge)),

	/* This will give us one unused SGEs for ATA.  This extra SGE
	 * will be used to store CDB for ATAPI devices.
	 */
	SIL24_MAX_SGE		= 4 * SIL24_MAX_SGT + 1,

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	/*
	 * Global controller registers (128 bytes @ BAR0)
	 */
		/* 32 bit regs */
	HOST_SLOT_STAT		= 0x00, /* 32 bit slot stat * 4 */
	HOST_CTRL		= 0x40,
	HOST_IRQ_STAT		= 0x44,
	HOST_PHY_CFG		= 0x48,
	HOST_BIST_CTRL		= 0x50,
	HOST_BIST_PTRN		= 0x54,
	HOST_BIST_STAT		= 0x58,
	HOST_MEM_BIST_STAT	= 0x5c,
	HOST_FLASH_CMD		= 0x70,
		/* 8 bit regs */
	HOST_FLASH_DATA		= 0x74,
	HOST_TRANSITION_DETECT	= 0x75,
	HOST_GPIO_CTRL		= 0x76,
	HOST_I2C_ADDR		= 0x78, /* 32 bit */
	HOST_I2C_DATA		= 0x7c,
	HOST_I2C_XFER_CNT	= 0x7e,
	HOST_I2C_CTRL		= 0x7f,

	/* HOST_SLOT_STAT bits */
	HOST_SSTAT_ATTN		= (1 << 31),

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	/* HOST_CTRL bits */
	HOST_CTRL_M66EN		= (1 << 16), /* M66EN PCI bus signal */
	HOST_CTRL_TRDY		= (1 << 17), /* latched PCI TRDY */
	HOST_CTRL_STOP		= (1 << 18), /* latched PCI STOP */
	HOST_CTRL_DEVSEL	= (1 << 19), /* latched PCI DEVSEL */
	HOST_CTRL_REQ64		= (1 << 20), /* latched PCI REQ64 */
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	HOST_CTRL_GLOBAL_RST	= (1 << 31), /* global reset */
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	/*
	 * Port registers
	 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
	 */
	PORT_REGS_SIZE		= 0x2000,
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	PORT_LRAM		= 0x0000, /* 31 LRAM slots and PMP regs */
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	PORT_LRAM_SLOT_SZ	= 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
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	PORT_PMP		= 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
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	PORT_PMP_STATUS		= 0x0000, /* port device status offset */
	PORT_PMP_QACTIVE	= 0x0004, /* port device QActive offset */
	PORT_PMP_SIZE		= 0x0008, /* 8 bytes per PMP */

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		/* 32 bit regs */
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	PORT_CTRL_STAT		= 0x1000, /* write: ctrl-set, read: stat */
	PORT_CTRL_CLR		= 0x1004, /* write: ctrl-clear */
	PORT_IRQ_STAT		= 0x1008, /* high: status, low: interrupt */
	PORT_IRQ_ENABLE_SET	= 0x1010, /* write: enable-set */
	PORT_IRQ_ENABLE_CLR	= 0x1014, /* write: enable-clear */
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	PORT_ACTIVATE_UPPER_ADDR= 0x101c,
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	PORT_EXEC_FIFO		= 0x1020, /* command execution fifo */
	PORT_CMD_ERR		= 0x1024, /* command error number */
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	PORT_FIS_CFG		= 0x1028,
	PORT_FIFO_THRES		= 0x102c,
		/* 16 bit regs */
	PORT_DECODE_ERR_CNT	= 0x1040,
	PORT_DECODE_ERR_THRESH	= 0x1042,
	PORT_CRC_ERR_CNT	= 0x1044,
	PORT_CRC_ERR_THRESH	= 0x1046,
	PORT_HSHK_ERR_CNT	= 0x1048,
	PORT_HSHK_ERR_THRESH	= 0x104a,
		/* 32 bit regs */
	PORT_PHY_CFG		= 0x1050,
	PORT_SLOT_STAT		= 0x1800,
	PORT_CMD_ACTIVATE	= 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
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	PORT_CONTEXT		= 0x1e04,
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	PORT_EXEC_DIAG		= 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
	PORT_PSD_DIAG		= 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
	PORT_SCONTROL		= 0x1f00,
	PORT_SSTATUS		= 0x1f04,
	PORT_SERROR		= 0x1f08,
	PORT_SACTIVE		= 0x1f0c,

	/* PORT_CTRL_STAT bits */
	PORT_CS_PORT_RST	= (1 << 0), /* port reset */
	PORT_CS_DEV_RST		= (1 << 1), /* device reset */
	PORT_CS_INIT		= (1 << 2), /* port initialize */
	PORT_CS_IRQ_WOC		= (1 << 3), /* interrupt write one to clear */
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	PORT_CS_CDB16		= (1 << 5), /* 0=12b cdb, 1=16b cdb */
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	PORT_CS_PMP_RESUME	= (1 << 6), /* PMP resume */
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	PORT_CS_32BIT_ACTV	= (1 << 10), /* 32-bit activation */
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	PORT_CS_PMP_EN		= (1 << 13), /* port multiplier enable */
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	PORT_CS_RDY		= (1 << 31), /* port ready to accept commands */
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	/* PORT_IRQ_STAT/ENABLE_SET/CLR */
	/* bits[11:0] are masked */
	PORT_IRQ_COMPLETE	= (1 << 0), /* command(s) completed */
	PORT_IRQ_ERROR		= (1 << 1), /* command execution error */
	PORT_IRQ_PORTRDY_CHG	= (1 << 2), /* port ready change */
	PORT_IRQ_PWR_CHG	= (1 << 3), /* power management change */
	PORT_IRQ_PHYRDY_CHG	= (1 << 4), /* PHY ready change */
	PORT_IRQ_COMWAKE	= (1 << 5), /* COMWAKE received */
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	PORT_IRQ_UNK_FIS	= (1 << 6), /* unknown FIS received */
	PORT_IRQ_DEV_XCHG	= (1 << 7), /* device exchanged */
	PORT_IRQ_8B10B		= (1 << 8), /* 8b/10b decode error threshold */
	PORT_IRQ_CRC		= (1 << 9), /* CRC error threshold */
	PORT_IRQ_HANDSHAKE	= (1 << 10), /* handshake error threshold */
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	PORT_IRQ_SDB_NOTIFY	= (1 << 11), /* SDB notify received */
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	DEF_PORT_IRQ		= PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
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				  PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
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				  PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
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	/* bits[27:16] are unmasked (raw) */
	PORT_IRQ_RAW_SHIFT	= 16,
	PORT_IRQ_MASKED_MASK	= 0x7ff,
	PORT_IRQ_RAW_MASK	= (0x7ff << PORT_IRQ_RAW_SHIFT),

	/* ENABLE_SET/CLR specific, intr steering - 2 bit field */
	PORT_IRQ_STEER_SHIFT	= 30,
	PORT_IRQ_STEER_MASK	= (3 << PORT_IRQ_STEER_SHIFT),

	/* PORT_CMD_ERR constants */
	PORT_CERR_DEV		= 1, /* Error bit in D2H Register FIS */
	PORT_CERR_SDB		= 2, /* Error bit in SDB FIS */
	PORT_CERR_DATA		= 3, /* Error in data FIS not detected by dev */
	PORT_CERR_SEND		= 4, /* Initial cmd FIS transmission failure */
	PORT_CERR_INCONSISTENT	= 5, /* Protocol mismatch */
	PORT_CERR_DIRECTION	= 6, /* Data direction mismatch */
	PORT_CERR_UNDERRUN	= 7, /* Ran out of SGEs while writing */
	PORT_CERR_OVERRUN	= 8, /* Ran out of SGEs while reading */
	PORT_CERR_PKT_PROT	= 11, /* DIR invalid in 1st PIO setup of ATAPI */
	PORT_CERR_SGT_BOUNDARY	= 16, /* PLD ecode 00 - SGT not on qword boundary */
	PORT_CERR_SGT_TGTABRT	= 17, /* PLD ecode 01 - target abort */
	PORT_CERR_SGT_MSTABRT	= 18, /* PLD ecode 10 - master abort */
	PORT_CERR_SGT_PCIPERR	= 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
	PORT_CERR_CMD_BOUNDARY	= 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
	PORT_CERR_CMD_TGTABRT	= 25, /* ctrl[15:13] 010 - target abort */
	PORT_CERR_CMD_MSTABRT	= 26, /* ctrl[15:13] 100 - master abort */
	PORT_CERR_CMD_PCIPERR	= 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
	PORT_CERR_XFR_UNDEF	= 32, /* PSD ecode 00 - undefined */
	PORT_CERR_XFR_TGTABRT	= 33, /* PSD ecode 01 - target abort */
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	PORT_CERR_XFR_MSTABRT	= 34, /* PSD ecode 10 - master abort */
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	PORT_CERR_XFR_PCIPERR	= 35, /* PSD ecode 11 - PCI prity err during transfer */
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	PORT_CERR_SENDSERVICE	= 36, /* FIS received while sending service */
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	/* bits of PRB control field */
	PRB_CTRL_PROTOCOL	= (1 << 0), /* override def. ATA protocol */
	PRB_CTRL_PACKET_READ	= (1 << 4), /* PACKET cmd read */
	PRB_CTRL_PACKET_WRITE	= (1 << 5), /* PACKET cmd write */
	PRB_CTRL_NIEN		= (1 << 6), /* Mask completion irq */
	PRB_CTRL_SRST		= (1 << 7), /* Soft reset request (ign BSY?) */

	/* PRB protocol field */
	PRB_PROT_PACKET		= (1 << 0),
	PRB_PROT_TCQ		= (1 << 1),
	PRB_PROT_NCQ		= (1 << 2),
	PRB_PROT_READ		= (1 << 3),
	PRB_PROT_WRITE		= (1 << 4),
	PRB_PROT_TRANSPARENT	= (1 << 5),

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	/*
	 * Other constants
	 */
	SGE_TRM			= (1 << 31), /* Last SGE in chain */
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	SGE_LNK			= (1 << 30), /* linked list
						Points to SGT, not SGE */
	SGE_DRD			= (1 << 29), /* discard data read (/dev/null)
						data address ignored */
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	SIL24_MAX_CMDS		= 31,

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	/* board id */
	BID_SIL3124		= 0,
	BID_SIL3132		= 1,
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	BID_SIL3131		= 2,
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	/* host flags */
	SIL24_COMMON_FLAGS	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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				  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
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				  ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
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				  ATA_FLAG_AN | ATA_FLAG_PMP,
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	SIL24_FLAG_PCIX_IRQ_WOC	= (1 << 24), /* IRQ loss errata on PCI-X */
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	IRQ_STAT_4PORTS		= 0xf,
};

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struct sil24_ata_block {
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	struct sil24_prb prb;
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	struct sil24_sge sge[SIL24_MAX_SGE];
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};

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struct sil24_atapi_block {
	struct sil24_prb prb;
	u8 cdb[16];
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	struct sil24_sge sge[SIL24_MAX_SGE];
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};

union sil24_cmd_block {
	struct sil24_ata_block ata;
	struct sil24_atapi_block atapi;
};

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static struct sil24_cerr_info {
	unsigned int err_mask, action;
	const char *desc;
} sil24_cerr_db[] = {
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	[0]			= { AC_ERR_DEV, 0,
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				    "device error" },
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	[PORT_CERR_DEV]		= { AC_ERR_DEV, 0,
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				    "device error via D2H FIS" },
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	[PORT_CERR_SDB]		= { AC_ERR_DEV, 0,
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				    "device error via SDB FIS" },
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	[PORT_CERR_DATA]	= { AC_ERR_ATA_BUS, ATA_EH_RESET,
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				    "error in data FIS" },
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	[PORT_CERR_SEND]	= { AC_ERR_ATA_BUS, ATA_EH_RESET,
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				    "failed to transmit command FIS" },
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	[PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
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				     "protocol mismatch" },
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	[PORT_CERR_DIRECTION]	= { AC_ERR_HSM, ATA_EH_RESET,
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				    "data directon mismatch" },
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	[PORT_CERR_UNDERRUN]	= { AC_ERR_HSM, ATA_EH_RESET,
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				    "ran out of SGEs while writing" },
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	[PORT_CERR_OVERRUN]	= { AC_ERR_HSM, ATA_EH_RESET,
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				    "ran out of SGEs while reading" },
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	[PORT_CERR_PKT_PROT]	= { AC_ERR_HSM, ATA_EH_RESET,
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				    "invalid data directon for ATAPI CDB" },
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	[PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
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				     "SGT not on qword boundary" },
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	[PORT_CERR_SGT_TGTABRT]	= { AC_ERR_HOST_BUS, ATA_EH_RESET,
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				    "PCI target abort while fetching SGT" },
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	[PORT_CERR_SGT_MSTABRT]	= { AC_ERR_HOST_BUS, ATA_EH_RESET,
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				    "PCI master abort while fetching SGT" },
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	[PORT_CERR_SGT_PCIPERR]	= { AC_ERR_HOST_BUS, ATA_EH_RESET,
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				    "PCI parity error while fetching SGT" },
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	[PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
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				     "PRB not on qword boundary" },
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	[PORT_CERR_CMD_TGTABRT]	= { AC_ERR_HOST_BUS, ATA_EH_RESET,
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				    "PCI target abort while fetching PRB" },
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	[PORT_CERR_CMD_MSTABRT]	= { AC_ERR_HOST_BUS, ATA_EH_RESET,
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				    "PCI master abort while fetching PRB" },
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	[PORT_CERR_CMD_PCIPERR]	= { AC_ERR_HOST_BUS, ATA_EH_RESET,
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				    "PCI parity error while fetching PRB" },
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	[PORT_CERR_XFR_UNDEF]	= { AC_ERR_HOST_BUS, ATA_EH_RESET,
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				    "undefined error while transferring data" },
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	[PORT_CERR_XFR_TGTABRT]	= { AC_ERR_HOST_BUS, ATA_EH_RESET,
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				    "PCI target abort while transferring data" },
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	[PORT_CERR_XFR_MSTABRT]	= { AC_ERR_HOST_BUS, ATA_EH_RESET,
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				    "PCI master abort while transferring data" },
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	[PORT_CERR_XFR_PCIPERR]	= { AC_ERR_HOST_BUS, ATA_EH_RESET,
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				    "PCI parity error while transferring data" },
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	[PORT_CERR_SENDSERVICE]	= { AC_ERR_HSM, ATA_EH_RESET,
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				    "FIS received while sending service FIS" },
};

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/*
 * ap->private_data
 *
 * The preview driver always returned 0 for status.  We emulate it
 * here from the previous interrupt.
 */
struct sil24_port_priv {
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	union sil24_cmd_block *cmd_block;	/* 32 cmd blocks */
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	dma_addr_t cmd_block_dma;		/* DMA base addr for them */
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	int do_port_rst;
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};

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static void sil24_dev_config(struct ata_device *dev);
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static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
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static int sil24_qc_defer(struct ata_queued_cmd *qc);
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static void sil24_qc_prep(struct ata_queued_cmd *qc);
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static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
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static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
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static void sil24_pmp_attach(struct ata_port *ap);
static void sil24_pmp_detach(struct ata_port *ap);
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static void sil24_freeze(struct ata_port *ap);
static void sil24_thaw(struct ata_port *ap);
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static int sil24_softreset(struct ata_link *link, unsigned int *class,
			   unsigned long deadline);
static int sil24_hardreset(struct ata_link *link, unsigned int *class,
			   unsigned long deadline);
static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
			       unsigned long deadline);
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static void sil24_error_handler(struct ata_port *ap);
static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
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static int sil24_port_start(struct ata_port *ap);
static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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#ifdef CONFIG_PM
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static int sil24_pci_device_resume(struct pci_dev *pdev);
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static int sil24_port_resume(struct ata_port *ap);
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#endif
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static const struct pci_device_id sil24_pci_tbl[] = {
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	{ PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
	{ PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
	{ PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
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	{ PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
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	{ PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
	{ PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },

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	{ } /* terminate list */
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};

static struct pci_driver sil24_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= sil24_pci_tbl,
	.probe			= sil24_init_one,
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	.remove			= ata_pci_remove_one,
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#ifdef CONFIG_PM
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	.suspend		= ata_pci_device_suspend,
	.resume			= sil24_pci_device_resume,
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#endif
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};

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static struct scsi_host_template sil24_sht = {
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	ATA_NCQ_SHT(DRV_NAME),
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	.can_queue		= SIL24_MAX_CMDS,
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	.sg_tablesize		= SIL24_MAX_SGE,
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	.dma_boundary		= ATA_DMA_BOUNDARY,
};

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static struct ata_port_operations sil24_ops = {
	.inherits		= &sata_pmp_port_ops,
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	.qc_defer		= sil24_qc_defer,
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	.qc_prep		= sil24_qc_prep,
	.qc_issue		= sil24_qc_issue,
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	.qc_fill_rtf		= sil24_qc_fill_rtf,
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405 406
	.freeze			= sil24_freeze,
	.thaw			= sil24_thaw,
407 408
	.softreset		= sil24_softreset,
	.hardreset		= sil24_hardreset,
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	.pmp_softreset		= sil24_softreset,
410
	.pmp_hardreset		= sil24_pmp_hardreset,
411 412 413
	.error_handler		= sil24_error_handler,
	.post_internal_cmd	= sil24_post_internal_cmd,
	.dev_config		= sil24_dev_config,
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	.scr_read		= sil24_scr_read,
	.scr_write		= sil24_scr_write,
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	.pmp_attach		= sil24_pmp_attach,
	.pmp_detach		= sil24_pmp_detach,

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	.port_start		= sil24_port_start,
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#ifdef CONFIG_PM
	.port_resume		= sil24_port_resume,
#endif
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};

426
/*
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 * Use bits 30-31 of port_flags to encode available port numbers.
428 429 430 431 432
 * Current maxium is 4.
 */
#define SIL24_NPORTS2FLAG(nports)	((((unsigned)(nports) - 1) & 0x3) << 30)
#define SIL24_FLAG2NPORTS(flag)		((((flag) >> 30) & 0x3) + 1)

433
static const struct ata_port_info sil24_port_info[] = {
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	/* sil_3124 */
	{
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		.flags		= SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
437
				  SIL24_FLAG_PCIX_IRQ_WOC,
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		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
440
		.udma_mask	= ATA_UDMA5,		/* udma0-5 */
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		.port_ops	= &sil24_ops,
	},
443
	/* sil_3132 */
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	{
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		.flags		= SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
446 447
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
448
		.udma_mask	= ATA_UDMA5,		/* udma0-5 */
449 450 451 452
		.port_ops	= &sil24_ops,
	},
	/* sil_3131/sil_3531 */
	{
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		.flags		= SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
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		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
456
		.udma_mask	= ATA_UDMA5,		/* udma0-5 */
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		.port_ops	= &sil24_ops,
	},
};

461 462 463 464 465 466 467
static int sil24_tag(int tag)
{
	if (unlikely(ata_tag_internal(tag)))
		return 0;
	return tag;
}

468 469 470 471 472 473 474 475 476 477
static unsigned long sil24_port_offset(struct ata_port *ap)
{
	return ap->port_no * PORT_REGS_SIZE;
}

static void __iomem *sil24_port_base(struct ata_port *ap)
{
	return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap);
}

478
static void sil24_dev_config(struct ata_device *dev)
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{
480
	void __iomem *port = sil24_port_base(dev->link->ap);
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482
	if (dev->cdb_len == 16)
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		writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
	else
		writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
}

488
static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
489
{
490
	void __iomem *port = sil24_port_base(ap);
491
	struct sil24_prb __iomem *prb;
492
	u8 fis[6 * 4];
493

494 495 496
	prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
	memcpy_fromio(fis, prb->fis, sizeof(fis));
	ata_tf_from_fis(fis, tf);
497 498
}

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static int sil24_scr_map[] = {
	[SCR_CONTROL]	= 0,
	[SCR_STATUS]	= 1,
	[SCR_ERROR]	= 2,
	[SCR_ACTIVE]	= 3,
};

506
static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
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{
508
	void __iomem *scr_addr = sil24_port_base(ap) + PORT_SCONTROL;
509

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	if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
511
		void __iomem *addr;
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		addr = scr_addr + sil24_scr_map[sc_reg] * 4;
513 514
		*val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
		return 0;
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	}
516
	return -EINVAL;
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}

519
static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
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{
521
	void __iomem *scr_addr = sil24_port_base(ap) + PORT_SCONTROL;
522

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	if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
524
		void __iomem *addr;
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		addr = scr_addr + sil24_scr_map[sc_reg] * 4;
		writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
527
		return 0;
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	}
529
	return -EINVAL;
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}

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static void sil24_config_port(struct ata_port *ap)
{
534
	void __iomem *port = sil24_port_base(ap);
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	/* configure IRQ WoC */
	if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
		writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
	else
		writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);

	/* zero error counters. */
	writel(0x8000, port + PORT_DECODE_ERR_THRESH);
	writel(0x8000, port + PORT_CRC_ERR_THRESH);
	writel(0x8000, port + PORT_HSHK_ERR_THRESH);
	writel(0x0000, port + PORT_DECODE_ERR_CNT);
	writel(0x0000, port + PORT_CRC_ERR_CNT);
	writel(0x0000, port + PORT_HSHK_ERR_CNT);

	/* always use 64bit activation */
	writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);

	/* clear port multiplier enable and resume bits */
	writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
}

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static void sil24_config_pmp(struct ata_port *ap, int attached)
{
559
	void __iomem *port = sil24_port_base(ap);
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	if (attached)
		writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
	else
		writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
}

static void sil24_clear_pmp(struct ata_port *ap)
{
569
	void __iomem *port = sil24_port_base(ap);
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	int i;

	writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);

	for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
		void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;

		writel(0, pmp_base + PORT_PMP_STATUS);
		writel(0, pmp_base + PORT_PMP_QACTIVE);
	}
}

582 583
static int sil24_init_port(struct ata_port *ap)
{
584
	void __iomem *port = sil24_port_base(ap);
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	struct sil24_port_priv *pp = ap->private_data;
586 587
	u32 tmp;

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	/* clear PMP error status */
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	if (sata_pmp_attached(ap))
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		sil24_clear_pmp(ap);

592 593 594 595 596 597
	writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
	ata_wait_register(port + PORT_CTRL_STAT,
			  PORT_CS_INIT, PORT_CS_INIT, 10, 100);
	tmp = ata_wait_register(port + PORT_CTRL_STAT,
				PORT_CS_RDY, 0, 10, 100);

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	if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
		pp->do_port_rst = 1;
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		ap->link.eh_context.i.action |= ATA_EH_RESET;
601
		return -EIO;
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	}

604 605 606
	return 0;
}

607 608 609 610
static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
				 const struct ata_taskfile *tf,
				 int is_cmd, u32 ctrl,
				 unsigned long timeout_msec)
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{
612
	void __iomem *port = sil24_port_base(ap);
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	struct sil24_port_priv *pp = ap->private_data;
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	struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
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	dma_addr_t paddr = pp->cmd_block_dma;
616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653
	u32 irq_enabled, irq_mask, irq_stat;
	int rc;

	prb->ctrl = cpu_to_le16(ctrl);
	ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);

	/* temporarily plug completion and error interrupts */
	irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
	writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);

	writel((u32)paddr, port + PORT_CMD_ACTIVATE);
	writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);

	irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
	irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
				     10, timeout_msec);

	writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
	irq_stat >>= PORT_IRQ_RAW_SHIFT;

	if (irq_stat & PORT_IRQ_COMPLETE)
		rc = 0;
	else {
		/* force port into known state */
		sil24_init_port(ap);

		if (irq_stat & PORT_IRQ_ERROR)
			rc = -EIO;
		else
			rc = -EBUSY;
	}

	/* restore IRQ enabled */
	writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);

	return rc;
}

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static int sil24_softreset(struct ata_link *link, unsigned int *class,
			   unsigned long deadline)
656
{
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	struct ata_port *ap = link->ap;
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	int pmp = sata_srst_pmp(link);
659
	unsigned long timeout_msec = 0;
660
	struct ata_taskfile tf;
661
	const char *reason;
662
	int rc;
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664 665
	DPRINTK("ENTER\n");

666 667
	/* put the port into known state */
	if (sil24_init_port(ap)) {
668
		reason = "port not ready";
669 670 671
		goto err;
	}

672
	/* do SRST */
673 674
	if (time_after(deadline, jiffies))
		timeout_msec = jiffies_to_msecs(deadline - jiffies);
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	ata_tf_init(link->device, &tf);	/* doesn't really matter */
677 678
	rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
				   timeout_msec);
679 680 681 682 683
	if (rc == -EBUSY) {
		reason = "timeout";
		goto err;
	} else if (rc) {
		reason = "SRST command error";
684
		goto err;
685
	}
686

687 688
	sil24_read_tf(ap, 0, &tf);
	*class = ata_dev_classify(&tf);
689

690
	DPRINTK("EXIT, class=%u\n", *class);
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	return 0;
692 693

 err:
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	ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
695
	return -EIO;
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}

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static int sil24_hardreset(struct ata_link *link, unsigned int *class,
699
			   unsigned long deadline)
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700
{
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701
	struct ata_port *ap = link->ap;
702
	void __iomem *port = sil24_port_base(ap);
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	struct sil24_port_priv *pp = ap->private_data;
	int did_port_rst = 0;
705
	const char *reason;
706
	int tout_msec, rc;
707 708
	u32 tmp;

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 retry:
	/* Sometimes, DEV_RST is not enough to recover the controller.
	 * This happens often after PM DMA CS errata.
	 */
	if (pp->do_port_rst) {
		ata_port_printk(ap, KERN_WARNING, "controller in dubious "
				"state, performing PORT_RST\n");

		writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
		msleep(10);
		writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
		ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
				  10, 5000);

		/* restore port configuration */
		sil24_config_port(ap);
		sil24_config_pmp(ap, ap->nr_pmp_links);

		pp->do_port_rst = 0;
		did_port_rst = 1;
	}

731
	/* sil24 does the right thing(tm) without any protection */
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	sata_set_spd(link);
733 734

	tout_msec = 100;
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	if (ata_link_online(link))
736 737 738 739
		tout_msec = 5000;

	writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
	tmp = ata_wait_register(port + PORT_CTRL_STAT,
740 741
				PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
				tout_msec);
742

743 744
	/* SStatus oscillates between zero and valid status after
	 * DEV_RST, debounce it.
745
	 */
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	rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
747 748 749 750
	if (rc) {
		reason = "PHY debouncing failed";
		goto err;
	}
751 752

	if (tmp & PORT_CS_DEV_RST) {
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		if (ata_link_offline(link))
754 755 756 757 758
			return 0;
		reason = "link not ready";
		goto err;
	}

759 760 761 762 763
	/* Sil24 doesn't store signature FIS after hardreset, so we
	 * can't wait for BSY to clear.  Some devices take a long time
	 * to get ready and those devices will choke if we don't wait
	 * for BSY clearance here.  Tell libata to perform follow-up
	 * softreset.
764
	 */
765
	return -EAGAIN;
766 767

 err:
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	if (!did_port_rst) {
		pp->do_port_rst = 1;
		goto retry;
	}

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	ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
774
	return -EIO;
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}

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static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
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				 struct sil24_sge *sge)
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{
780
	struct scatterlist *sg;
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	struct sil24_sge *last_sge = NULL;
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	unsigned int si;
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	for_each_sg(qc->sg, sg, qc->n_elem, si) {
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		sge->addr = cpu_to_le64(sg_dma_address(sg));
		sge->cnt = cpu_to_le32(sg_dma_len(sg));
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787 788 789
		sge->flags = 0;

		last_sge = sge;
790
		sge++;
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	}
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	last_sge->flags = cpu_to_le32(SGE_TRM);
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}

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static int sil24_qc_defer(struct ata_queued_cmd *qc)
{
	struct ata_link *link = qc->dev->link;
	struct ata_port *ap = link->ap;
	u8 prot = qc->tf.protocol;
801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820

	/*
	 * There is a bug in the chip:
	 * Port LRAM Causes the PRB/SGT Data to be Corrupted
	 * If the host issues a read request for LRAM and SActive registers
	 * while active commands are available in the port, PRB/SGT data in
	 * the LRAM can become corrupted. This issue applies only when
	 * reading from, but not writing to, the LRAM.
	 *
	 * Therefore, reading LRAM when there is no particular error [and
	 * other commands may be outstanding] is prohibited.
	 *
	 * To avoid this bug there are two situations where a command must run
	 * exclusive of any other commands on the port:
	 *
	 * - ATAPI commands which check the sense data
	 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
	 *   set.
	 *
 	 */
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	int is_excl = (ata_is_atapi(prot) ||
822 823
		       (qc->flags & ATA_QCFLAG_RESULT_TF));

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	if (unlikely(ap->excl_link)) {
		if (link == ap->excl_link) {
			if (ap->nr_active_links)
				return ATA_DEFER_PORT;
			qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
		} else
			return ATA_DEFER_PORT;
831
	} else if (unlikely(is_excl)) {
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		ap->excl_link = link;
		if (ap->nr_active_links)
			return ATA_DEFER_PORT;
		qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
	}

	return ata_std_qc_defer(qc);
}

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static void sil24_qc_prep(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct sil24_port_priv *pp = ap->private_data;
845
	union sil24_cmd_block *cb;
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	struct sil24_prb *prb;
	struct sil24_sge *sge;
848
	u16 ctrl = 0;
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849

850 851
	cb = &pp->cmd_block[sil24_tag(qc->tag)];

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852
	if (!ata_is_atapi(qc->tf.protocol)) {
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		prb = &cb->ata.prb;
		sge = cb->ata.sge;
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	} else {
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		prb = &cb->atapi.prb;
		sge = cb->atapi.sge;
		memset(cb->atapi.cdb, 0, 32);
859
		memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
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861
		if (ata_is_data(qc->tf.protocol)) {
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862
			if (qc->tf.flags & ATA_TFLAG_WRITE)
863
				ctrl = PRB_CTRL_PACKET_WRITE;
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			else
865 866
				ctrl = PRB_CTRL_PACKET_READ;
		}
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	}

869
	prb->ctrl = cpu_to_le16(ctrl);
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	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
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	if (qc->flags & ATA_QCFLAG_DMAMAP)
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		sil24_fill_sg(qc, sge);
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}

876
static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
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{
	struct ata_port *ap = qc->ap;
	struct sil24_port_priv *pp = ap->private_data;
880
	void __iomem *port = sil24_port_base(ap);
881 882 883
	unsigned int tag = sil24_tag(qc->tag);
	dma_addr_t paddr;
	void __iomem *activate;
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884

885 886 887 888 889
	paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
	activate = port + PORT_CMD_ACTIVATE + tag * 8;

	writel((u32)paddr, activate);
	writel((u64)paddr >> 32, activate + 4);
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	return 0;
}

894 895 896 897 898 899
static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
{
	sil24_read_tf(qc->ap, qc->tag, &qc->result_tf);
	return true;
}

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static void sil24_pmp_attach(struct ata_port *ap)
{
902 903
	u32 *gscr = ap->link.device->gscr;

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904 905
	sil24_config_pmp(ap, 1);
	sil24_init_port(ap);
906 907 908 909 910 911 912

	if (sata_pmp_gscr_vendor(gscr) == 0x11ab &&
	    sata_pmp_gscr_devid(gscr) == 0x4140) {
		ata_port_printk(ap, KERN_INFO,
			"disabling NCQ support due to sil24-mv4140 quirk\n");
		ap->flags &= ~ATA_FLAG_NCQ;
	}
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}

static void sil24_pmp_detach(struct ata_port *ap)
{
	sil24_init_port(ap);
	sil24_config_pmp(ap, 0);
919 920

	ap->flags |= ATA_FLAG_NCQ;
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}

static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
			       unsigned long deadline)
{
	int rc;

	rc = sil24_init_port(link->ap);
	if (rc) {
		ata_link_printk(link, KERN_ERR,
				"hardreset failed (port not ready)\n");
		return rc;
	}

935
	return sata_std_hardreset(link, class, deadline);
T
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}

938
static void sil24_freeze(struct ata_port *ap)
939
{
940
	void __iomem *port = sil24_port_base(ap);
941

942 943 944 945
	/* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
	 * PORT_IRQ_ENABLE instead.
	 */
	writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
946 947
}

948
static void sil24_thaw(struct ata_port *ap)
T
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949
{
950
	void __iomem *port = sil24_port_base(ap);
T
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951 952
	u32 tmp;

953 954 955
	/* clear IRQ */
	tmp = readl(port + PORT_IRQ_STAT);
	writel(tmp, port + PORT_IRQ_STAT);
T
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957 958
	/* turn IRQ back on */
	writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
T
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959 960
}

961
static void sil24_error_intr(struct ata_port *ap)
962
{
963
	void __iomem *port = sil24_port_base(ap);
964
	struct sil24_port_priv *pp = ap->private_data;
T
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965 966 967 968
	struct ata_queued_cmd *qc = NULL;
	struct ata_link *link;
	struct ata_eh_info *ehi;
	int abort = 0, freeze = 0;
969
	u32 irq_stat;
970

971
	/* on error, we need to clear IRQ explicitly */
972
	irq_stat = readl(port + PORT_IRQ_STAT);
973
	writel(irq_stat, port + PORT_IRQ_STAT);
974

975
	/* first, analyze and record host port events */
T
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	link = &ap->link;
	ehi = &link->eh_info;
978
	ata_ehi_clear_desc(ehi);
979

980
	ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
981

T
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982 983
	if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
		ata_ehi_push_desc(ehi, "SDB notify");
984
		sata_async_notification(ap);
T
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985 986
	}

987 988
	if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
		ata_ehi_hotplugged(ehi);
T
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989 990 991
		ata_ehi_push_desc(ehi, "%s",
				  irq_stat & PORT_IRQ_PHYRDY_CHG ?
				  "PHY RDY changed" : "device exchanged");
992
		freeze = 1;
993 994
	}

995 996
	if (irq_stat & PORT_IRQ_UNK_FIS) {
		ehi->err_mask |= AC_ERR_HSM;
T
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		ehi->action |= ATA_EH_RESET;
T
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		ata_ehi_push_desc(ehi, "unknown FIS");
999 1000 1001 1002 1003 1004 1005
		freeze = 1;
	}

	/* deal with command error */
	if (irq_stat & PORT_IRQ_ERROR) {
		struct sil24_cerr_info *ci = NULL;
		unsigned int err_mask = 0, action = 0;
T
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		u32 context, cerr;
		int pmp;

		abort = 1;

		/* DMA Context Switch Failure in Port Multiplier Mode
		 * errata.  If we have active commands to 3 or more
		 * devices, any error condition on active devices can
		 * corrupt DMA context switching.
		 */
		if (ap->nr_active_links >= 3) {
			ehi->err_mask |= AC_ERR_OTHER;
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1018
			ehi->action |= ATA_EH_RESET;
T
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1019
			ata_ehi_push_desc(ehi, "PMP DMA CS errata");
T
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1020
			pp->do_port_rst = 1;
T
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1021 1022 1023 1024
			freeze = 1;
		}

		/* find out the offending link and qc */
T
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1025
		if (sata_pmp_attached(ap)) {
T
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1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038
			context = readl(port + PORT_CONTEXT);
			pmp = (context >> 5) & 0xf;

			if (pmp < ap->nr_pmp_links) {
				link = &ap->pmp_link[pmp];
				ehi = &link->eh_info;
				qc = ata_qc_from_tag(ap, link->active_tag);

				ata_ehi_clear_desc(ehi);
				ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
						  irq_stat);
			} else {
				err_mask |= AC_ERR_HSM;
T
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1039
				action |= ATA_EH_RESET;
T
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1040 1041 1042 1043
				freeze = 1;
			}
		} else
			qc = ata_qc_from_tag(ap, link->active_tag);
1044 1045 1046 1047 1048 1049 1050 1051 1052

		/* analyze CMD_ERR */
		cerr = readl(port + PORT_CMD_ERR);
		if (cerr < ARRAY_SIZE(sil24_cerr_db))
			ci = &sil24_cerr_db[cerr];

		if (ci && ci->desc) {
			err_mask |= ci->err_mask;
			action |= ci->action;
T
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1053
			if (action & ATA_EH_RESET)
1054
				freeze = 1;
T
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1055
			ata_ehi_push_desc(ehi, "%s", ci->desc);
1056 1057
		} else {
			err_mask |= AC_ERR_OTHER;
T
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1058
			action |= ATA_EH_RESET;
1059
			freeze = 1;
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1060
			ata_ehi_push_desc(ehi, "unknown command error %d",
1061 1062 1063 1064
					  cerr);
		}

		/* record error info */
1065
		if (qc)
1066
			qc->err_mask |= err_mask;
1067
		else
1068 1069 1070
			ehi->err_mask |= err_mask;

		ehi->action |= action;
T
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1071 1072

		/* if PMP, resume */
T
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1073
		if (sata_pmp_attached(ap))
T
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1074
			writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1075
	}
1076 1077 1078 1079

	/* freeze or abort */
	if (freeze)
		ata_port_freeze(ap);
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1080 1081 1082 1083 1084 1085
	else if (abort) {
		if (qc)
			ata_link_abort(qc->dev->link);
		else
			ata_port_abort(ap);
	}
1086 1087
}

T
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1088 1089
static inline void sil24_host_intr(struct ata_port *ap)
{
1090
	void __iomem *port = sil24_port_base(ap);
1091 1092
	u32 slot_stat, qc_active;
	int rc;
T
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1093

1094 1095 1096 1097 1098 1099 1100 1101 1102 1103
	/* If PCIX_IRQ_WOC, there's an inherent race window between
	 * clearing IRQ pending status and reading PORT_SLOT_STAT
	 * which may cause spurious interrupts afterwards.  This is
	 * unavoidable and much better than losing interrupts which
	 * happens if IRQ pending is cleared after reading
	 * PORT_SLOT_STAT.
	 */
	if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
		writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);

T
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1104
	slot_stat = readl(port + PORT_SLOT_STAT);
1105

1106 1107 1108 1109 1110
	if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
		sil24_error_intr(ap);
		return;
	}

1111
	qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1112
	rc = ata_qc_complete_multiple(ap, qc_active);
1113 1114 1115
	if (rc > 0)
		return;
	if (rc < 0) {
T
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1116
		struct ata_eh_info *ehi = &ap->link.eh_info;
1117
		ehi->err_mask |= AC_ERR_HSM;
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		ehi->action |= ATA_EH_RESET;
1119
		ata_port_freeze(ap);
1120 1121 1122
		return;
	}

1123 1124
	/* spurious interrupts are expected if PCIX_IRQ_WOC */
	if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1125
		ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1126
			"(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
T
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1127
			slot_stat, ap->link.active_tag, ap->link.sactive);
T
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}

1130
static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
T
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1131
{
J
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1132
	struct ata_host *host = dev_instance;
T
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1133
	void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
T
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1134 1135 1136 1137
	unsigned handled = 0;
	u32 status;
	int i;

T
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1138
	status = readl(host_base + HOST_IRQ_STAT);
T
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1139

1140 1141 1142 1143 1144 1145
	if (status == 0xffffffff) {
		printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
		       "PCI fault or device removal?\n");
		goto out;
	}

T
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1146 1147 1148
	if (!(status & IRQ_STAT_4PORTS))
		goto out;

J
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1149
	spin_lock(&host->lock);
T
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1150

J
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1151
	for (i = 0; i < host->n_ports; i++)
T
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1152
		if (status & (1 << i)) {
J
Jeff Garzik 已提交
1153
			struct ata_port *ap = host->ports[i];
1154
			if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
1155
				sil24_host_intr(ap);
1156 1157 1158 1159
				handled++;
			} else
				printk(KERN_ERR DRV_NAME
				       ": interrupt from disabled port %d\n", i);
T
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1160 1161
		}

J
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1162
	spin_unlock(&host->lock);
T
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1163 1164 1165 1166
 out:
	return IRQ_RETVAL(handled);
}

1167 1168
static void sil24_error_handler(struct ata_port *ap)
{
T
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1169 1170
	struct sil24_port_priv *pp = ap->private_data;

T
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1171
	if (sil24_init_port(ap))
1172 1173
		ata_eh_freeze_port(ap);

1174
	sata_pmp_error_handler(ap);
T
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1175 1176

	pp->do_port_rst = 0;
1177 1178 1179 1180 1181 1182 1183
}

static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;

	/* make DMA engine forget about the failed command */
T
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1184 1185
	if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
		ata_eh_freeze_port(ap);
1186 1187
}

T
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1188 1189
static int sil24_port_start(struct ata_port *ap)
{
J
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1190
	struct device *dev = ap->host->dev;
T
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1191
	struct sil24_port_priv *pp;
T
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1192
	union sil24_cmd_block *cb;
1193
	size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
T
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1194 1195
	dma_addr_t cb_dma;

1196
	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
T
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1197
	if (!pp)
1198
		return -ENOMEM;
T
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1199

1200
	cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1201
	if (!cb)
1202
		return -ENOMEM;
T
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1203 1204 1205 1206 1207 1208 1209
	memset(cb, 0, cb_size);

	pp->cmd_block = cb;
	pp->cmd_block_dma = cb_dma;

	ap->private_data = pp;

1210 1211 1212
	ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
	ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port");

T
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1213 1214 1215
	return 0;
}

1216
static void sil24_init_controller(struct ata_host *host)
1217
{
1218
	void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1219 1220 1221 1222 1223 1224 1225 1226 1227 1228
	u32 tmp;
	int i;

	/* GPIO off */
	writel(0, host_base + HOST_FLASH_CMD);

	/* clear global reset & mask interrupts during initialization */
	writel(0, host_base + HOST_CTRL);

	/* init ports */
1229
	for (i = 0; i < host->n_ports; i++) {
T
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1230
		struct ata_port *ap = host->ports[i];
1231 1232
		void __iomem *port = sil24_port_base(ap);

1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244

		/* Initial PHY setting */
		writel(0x20c, port + PORT_PHY_CFG);

		/* Clear port RST */
		tmp = readl(port + PORT_CTRL_STAT);
		if (tmp & PORT_CS_PORT_RST) {
			writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
			tmp = ata_wait_register(port + PORT_CTRL_STAT,
						PORT_CS_PORT_RST,
						PORT_CS_PORT_RST, 10, 100);
			if (tmp & PORT_CS_PORT_RST)
1245
				dev_printk(KERN_ERR, host->dev,
1246
					   "failed to clear port RST\n");
1247 1248
		}

T
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1249 1250
		/* configure port */
		sil24_config_port(ap);
1251 1252 1253 1254 1255 1256
	}

	/* Turn on interrupts */
	writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
}

T
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1257 1258
static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
T
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1259
	extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
1260
	static int printed_version;
1261 1262 1263 1264
	struct ata_port_info pi = sil24_port_info[ent->driver_data];
	const struct ata_port_info *ppi[] = { &pi, NULL };
	void __iomem * const *iomap;
	struct ata_host *host;
1265
	int rc;
1266
	u32 tmp;
T
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1267

T
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1268 1269 1270 1271
	/* cause link error if sil24_cmd_block is sized wrongly */
	if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
		__MARKER__sil24_cmd_block_is_sized_wrongly = 1;

T
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1272
	if (!printed_version++)
1273
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
T
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1274

1275
	/* acquire resources */
1276
	rc = pcim_enable_device(pdev);
T
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1277 1278 1279
	if (rc)
		return rc;

T
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1280 1281 1282
	rc = pcim_iomap_regions(pdev,
				(1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
				DRV_NAME);
T
Tejun Heo 已提交
1283
	if (rc)
1284
		return rc;
1285
	iomap = pcim_iomap_table(pdev);
T
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1286

1287 1288 1289 1290 1291 1292 1293 1294 1295 1296
	/* apply workaround for completion IRQ loss on PCI-X errata */
	if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
		tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
		if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
			dev_printk(KERN_INFO, &pdev->dev,
				   "Applying completion IRQ loss on PCI-X "
				   "errata fix\n");
		else
			pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
	}
T
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1298 1299 1300 1301 1302 1303
	/* allocate and fill host */
	host = ata_host_alloc_pinfo(&pdev->dev, ppi,
				    SIL24_FLAG2NPORTS(ppi[0]->flags));
	if (!host)
		return -ENOMEM;
	host->iomap = iomap;
T
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1304

1305
	/* configure and activate the device */
T
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1306 1307 1308 1309 1310 1311 1312
	if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
		rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
		if (rc) {
			rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
			if (rc) {
				dev_printk(KERN_ERR, &pdev->dev,
					   "64-bit DMA enable failed\n");
1313
				return rc;
T
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1314 1315 1316 1317 1318 1319 1320
			}
		}
	} else {
		rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
		if (rc) {
			dev_printk(KERN_ERR, &pdev->dev,
				   "32-bit DMA enable failed\n");
1321
			return rc;
T
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1322 1323 1324 1325 1326
		}
		rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
		if (rc) {
			dev_printk(KERN_ERR, &pdev->dev,
				   "32-bit consistent DMA enable failed\n");
1327
			return rc;
T
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1328
		}
T
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1329 1330
	}

1331
	sil24_init_controller(host);
T
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1332 1333

	pci_set_master(pdev);
1334 1335
	return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
				 &sil24_sht);
T
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1336 1337
}

1338
#ifdef CONFIG_PM
1339 1340
static int sil24_pci_device_resume(struct pci_dev *pdev)
{
J
Jeff Garzik 已提交
1341
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
T
Tejun Heo 已提交
1342
	void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1343
	int rc;
1344

1345 1346 1347
	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;
1348 1349

	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
T
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1350
		writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1351

1352
	sil24_init_controller(host);
1353

J
Jeff Garzik 已提交
1354
	ata_host_resume(host);
1355 1356 1357

	return 0;
}
T
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1358 1359 1360 1361 1362 1363

static int sil24_port_resume(struct ata_port *ap)
{
	sil24_config_pmp(ap, ap->nr_pmp_links);
	return 0;
}
1364
#endif
1365

T
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1366 1367
static int __init sil24_init(void)
{
1368
	return pci_register_driver(&sil24_pci_driver);
T
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1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382
}

static void __exit sil24_exit(void)
{
	pci_unregister_driver(&sil24_pci_driver);
}

MODULE_AUTHOR("Tejun Heo");
MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);

module_init(sil24_init);
module_exit(sil24_exit);