pxa_camera.c 67.3 KB
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/*
 * V4L2 Driver for PXA camera host
 *
 * Copyright (C) 2006, Sascha Hauer, Pengutronix
 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
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 * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr>
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/init.h>
#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/moduleparam.h>
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#include <linux/of.h>
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#include <linux/time.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/dma/pxa-dma.h>
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#include <media/v4l2-async.h>
#include <media/v4l2-clk.h>
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#include <media/v4l2-common.h>
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#include <media/v4l2-device.h>
#include <media/v4l2-ioctl.h>
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#include <media/v4l2-of.h>
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#include <media/videobuf2-dma-sg.h>

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#include <linux/videodev2.h>

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#include <linux/platform_data/media/camera-pxa.h>
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#define PXA_CAM_VERSION "0.0.6"
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#define PXA_CAM_DRV_NAME "pxa27x-camera"

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#define DEFAULT_WIDTH	640
#define DEFAULT_HEIGHT	480

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/* Camera Interface */
#define CICR0		0x0000
#define CICR1		0x0004
#define CICR2		0x0008
#define CICR3		0x000C
#define CICR4		0x0010
#define CISR		0x0014
#define CIFR		0x0018
#define CITOR		0x001C
#define CIBR0		0x0028
#define CIBR1		0x0030
#define CIBR2		0x0038

#define CICR0_DMAEN	(1 << 31)	/* DMA request enable */
#define CICR0_PAR_EN	(1 << 30)	/* Parity enable */
#define CICR0_SL_CAP_EN	(1 << 29)	/* Capture enable for slave mode */
#define CICR0_ENB	(1 << 28)	/* Camera interface enable */
#define CICR0_DIS	(1 << 27)	/* Camera interface disable */
#define CICR0_SIM	(0x7 << 24)	/* Sensor interface mode mask */
#define CICR0_TOM	(1 << 9)	/* Time-out mask */
#define CICR0_RDAVM	(1 << 8)	/* Receive-data-available mask */
#define CICR0_FEM	(1 << 7)	/* FIFO-empty mask */
#define CICR0_EOLM	(1 << 6)	/* End-of-line mask */
#define CICR0_PERRM	(1 << 5)	/* Parity-error mask */
#define CICR0_QDM	(1 << 4)	/* Quick-disable mask */
#define CICR0_CDM	(1 << 3)	/* Disable-done mask */
#define CICR0_SOFM	(1 << 2)	/* Start-of-frame mask */
#define CICR0_EOFM	(1 << 1)	/* End-of-frame mask */
#define CICR0_FOM	(1 << 0)	/* FIFO-overrun mask */

#define CICR1_TBIT	(1 << 31)	/* Transparency bit */
#define CICR1_RGBT_CONV	(0x3 << 29)	/* RGBT conversion mask */
#define CICR1_PPL	(0x7ff << 15)	/* Pixels per line mask */
#define CICR1_RGB_CONV	(0x7 << 12)	/* RGB conversion mask */
#define CICR1_RGB_F	(1 << 11)	/* RGB format */
#define CICR1_YCBCR_F	(1 << 10)	/* YCbCr format */
#define CICR1_RGB_BPP	(0x7 << 7)	/* RGB bis per pixel mask */
#define CICR1_RAW_BPP	(0x3 << 5)	/* Raw bis per pixel mask */
#define CICR1_COLOR_SP	(0x3 << 3)	/* Color space mask */
#define CICR1_DW	(0x7 << 0)	/* Data width mask */

#define CICR2_BLW	(0xff << 24)	/* Beginning-of-line pixel clock
					   wait count mask */
#define CICR2_ELW	(0xff << 16)	/* End-of-line pixel clock
					   wait count mask */
#define CICR2_HSW	(0x3f << 10)	/* Horizontal sync pulse width mask */
#define CICR2_BFPW	(0x3f << 3)	/* Beginning-of-frame pixel clock
					   wait count mask */
#define CICR2_FSW	(0x7 << 0)	/* Frame stabilization
					   wait count mask */

#define CICR3_BFW	(0xff << 24)	/* Beginning-of-frame line clock
					   wait count mask */
#define CICR3_EFW	(0xff << 16)	/* End-of-frame line clock
					   wait count mask */
#define CICR3_VSW	(0x3f << 10)	/* Vertical sync pulse width mask */
#define CICR3_BFPW	(0x3f << 3)	/* Beginning-of-frame pixel clock
					   wait count mask */
#define CICR3_LPF	(0x7ff << 0)	/* Lines per frame mask */

#define CICR4_MCLK_DLY	(0x3 << 24)	/* MCLK Data Capture Delay mask */
#define CICR4_PCLK_EN	(1 << 23)	/* Pixel clock enable */
#define CICR4_PCP	(1 << 22)	/* Pixel clock polarity */
#define CICR4_HSP	(1 << 21)	/* Horizontal sync polarity */
#define CICR4_VSP	(1 << 20)	/* Vertical sync polarity */
#define CICR4_MCLK_EN	(1 << 19)	/* MCLK enable */
#define CICR4_FR_RATE	(0x7 << 8)	/* Frame rate mask */
#define CICR4_DIV	(0xff << 0)	/* Clock divisor mask */

#define CISR_FTO	(1 << 15)	/* FIFO time-out */
#define CISR_RDAV_2	(1 << 14)	/* Channel 2 receive data available */
#define CISR_RDAV_1	(1 << 13)	/* Channel 1 receive data available */
#define CISR_RDAV_0	(1 << 12)	/* Channel 0 receive data available */
#define CISR_FEMPTY_2	(1 << 11)	/* Channel 2 FIFO empty */
#define CISR_FEMPTY_1	(1 << 10)	/* Channel 1 FIFO empty */
#define CISR_FEMPTY_0	(1 << 9)	/* Channel 0 FIFO empty */
#define CISR_EOL	(1 << 8)	/* End of line */
#define CISR_PAR_ERR	(1 << 7)	/* Parity error */
#define CISR_CQD	(1 << 6)	/* Camera interface quick disable */
#define CISR_CDD	(1 << 5)	/* Camera interface disable done */
#define CISR_SOF	(1 << 4)	/* Start of frame */
#define CISR_EOF	(1 << 3)	/* End of frame */
#define CISR_IFO_2	(1 << 2)	/* FIFO overrun for Channel 2 */
#define CISR_IFO_1	(1 << 1)	/* FIFO overrun for Channel 1 */
#define CISR_IFO_0	(1 << 0)	/* FIFO overrun for Channel 0 */

#define CIFR_FLVL2	(0x7f << 23)	/* FIFO 2 level mask */
#define CIFR_FLVL1	(0x7f << 16)	/* FIFO 1 level mask */
#define CIFR_FLVL0	(0xff << 8)	/* FIFO 0 level mask */
#define CIFR_THL_0	(0x3 << 4)	/* Threshold Level for Channel 0 FIFO */
#define CIFR_RESET_F	(1 << 3)	/* Reset input FIFOs */
#define CIFR_FEN2	(1 << 2)	/* FIFO enable for channel 2 */
#define CIFR_FEN1	(1 << 1)	/* FIFO enable for channel 1 */
#define CIFR_FEN0	(1 << 0)	/* FIFO enable for channel 0 */

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#define CICR0_SIM_MP	(0 << 24)
#define CICR0_SIM_SP	(1 << 24)
#define CICR0_SIM_MS	(2 << 24)
#define CICR0_SIM_EP	(3 << 24)
#define CICR0_SIM_ES	(4 << 24)

#define CICR1_DW_VAL(x)   ((x) & CICR1_DW)	    /* Data bus width */
#define CICR1_PPL_VAL(x)  (((x) << 15) & CICR1_PPL) /* Pixels per line */
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#define CICR1_COLOR_SP_VAL(x)	(((x) << 3) & CICR1_COLOR_SP)	/* color space */
#define CICR1_RGB_BPP_VAL(x)	(((x) << 7) & CICR1_RGB_BPP)	/* bpp for rgb */
#define CICR1_RGBT_CONV_VAL(x)	(((x) << 29) & CICR1_RGBT_CONV)	/* rgbt conv */
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#define CICR2_BLW_VAL(x)  (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
#define CICR2_ELW_VAL(x)  (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
#define CICR2_HSW_VAL(x)  (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
#define CICR2_FSW_VAL(x)  (((x) << 0) & CICR2_FSW)  /* Frame stabilization wait count */

#define CICR3_BFW_VAL(x)  (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count  */
#define CICR3_EFW_VAL(x)  (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
#define CICR3_VSW_VAL(x)  (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
#define CICR3_LPF_VAL(x)  (((x) << 0) & CICR3_LPF)  /* Lines per frame */

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#define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
			CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
			CICR0_EOFM | CICR0_FOM)

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#define sensor_call(cam, o, f, args...) \
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	v4l2_subdev_call(cam->sensor, o, f, ##args)

/*
 * Format handling
 */
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/**
 * enum pxa_mbus_packing - data packing types on the media-bus
 * @PXA_MBUS_PACKING_NONE:	no packing, bit-for-bit transfer to RAM, one
 *				sample represents one pixel
 * @PXA_MBUS_PACKING_2X8_PADHI:	16 bits transferred in 2 8-bit samples, in the
 *				possibly incomplete byte high bits are padding
 * @PXA_MBUS_PACKING_EXTEND16:	sample width (e.g., 10 bits) has to be extended
 *				to 16 bits
 */
enum pxa_mbus_packing {
	PXA_MBUS_PACKING_NONE,
	PXA_MBUS_PACKING_2X8_PADHI,
	PXA_MBUS_PACKING_EXTEND16,
};

/**
 * enum pxa_mbus_order - sample order on the media bus
 * @PXA_MBUS_ORDER_LE:		least significant sample first
 * @PXA_MBUS_ORDER_BE:		most significant sample first
 */
enum pxa_mbus_order {
	PXA_MBUS_ORDER_LE,
	PXA_MBUS_ORDER_BE,
};

/**
 * enum pxa_mbus_layout - planes layout in memory
 * @PXA_MBUS_LAYOUT_PACKED:		color components packed
 * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V:	YUV components stored in 3 planes (4:2:2)
 * @PXA_MBUS_LAYOUT_PLANAR_2Y_C:	YUV components stored in a luma and a
 *					chroma plane (C plane is half the size
 *					of Y plane)
 * @PXA_MBUS_LAYOUT_PLANAR_Y_C:		YUV components stored in a luma and a
 *					chroma plane (C plane is the same size
 *					as Y plane)
 */
enum pxa_mbus_layout {
	PXA_MBUS_LAYOUT_PACKED = 0,
	PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
	PXA_MBUS_LAYOUT_PLANAR_2Y_C,
	PXA_MBUS_LAYOUT_PLANAR_Y_C,
};

/**
 * struct pxa_mbus_pixelfmt - Data format on the media bus
 * @name:		Name of the format
 * @fourcc:		Fourcc code, that will be obtained if the data is
 *			stored in memory in the following way:
 * @packing:		Type of sample-packing, that has to be used
 * @order:		Sample order when storing in memory
 * @bits_per_sample:	How many bits the bridge has to sample
 */
struct pxa_mbus_pixelfmt {
	const char		*name;
	u32			fourcc;
	enum pxa_mbus_packing	packing;
	enum pxa_mbus_order	order;
	enum pxa_mbus_layout	layout;
	u8			bits_per_sample;
};

/**
 * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
 * @code:	mediabus pixel-code
 * @fmt:	pixel format description
 */
struct pxa_mbus_lookup {
	u32	code;
	struct pxa_mbus_pixelfmt	fmt;
};

static const struct pxa_mbus_lookup mbus_fmt[] = {
{
	.code = MEDIA_BUS_FMT_YUYV8_2X8,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_YUYV,
		.name			= "YUYV",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_YVYU8_2X8,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_YVYU,
		.name			= "YVYU",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_UYVY8_2X8,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_UYVY,
		.name			= "UYVY",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_VYUY8_2X8,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_VYUY,
		.name			= "VYUY",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_RGB555,
		.name			= "RGB555",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_RGB555X,
		.name			= "RGB555X",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
		.order			= PXA_MBUS_ORDER_BE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_RGB565_2X8_LE,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_RGB565,
		.name			= "RGB565",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_RGB565_2X8_BE,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_RGB565X,
		.name			= "RGB565X",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
		.order			= PXA_MBUS_ORDER_BE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_SBGGR8_1X8,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_SBGGR8,
		.name			= "Bayer 8 BGGR",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_NONE,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_SBGGR10_1X10,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_SBGGR10,
		.name			= "Bayer 10 BGGR",
		.bits_per_sample	= 10,
		.packing		= PXA_MBUS_PACKING_EXTEND16,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_Y8_1X8,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_GREY,
		.name			= "Grey",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_NONE,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_Y10_1X10,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_Y10,
		.name			= "Grey 10bit",
		.bits_per_sample	= 10,
		.packing		= PXA_MBUS_PACKING_EXTEND16,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_SBGGR10,
		.name			= "Bayer 10 BGGR",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_SBGGR10,
		.name			= "Bayer 10 BGGR",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
		.order			= PXA_MBUS_ORDER_BE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_RGB444,
		.name			= "RGB444",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
		.order			= PXA_MBUS_ORDER_BE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_UYVY8_1X16,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_UYVY,
		.name			= "UYVY 16bit",
		.bits_per_sample	= 16,
		.packing		= PXA_MBUS_PACKING_EXTEND16,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_VYUY8_1X16,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_VYUY,
		.name			= "VYUY 16bit",
		.bits_per_sample	= 16,
		.packing		= PXA_MBUS_PACKING_EXTEND16,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_YUYV8_1X16,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_YUYV,
		.name			= "YUYV 16bit",
		.bits_per_sample	= 16,
		.packing		= PXA_MBUS_PACKING_EXTEND16,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_YVYU8_1X16,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_YVYU,
		.name			= "YVYU 16bit",
		.bits_per_sample	= 16,
		.packing		= PXA_MBUS_PACKING_EXTEND16,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_SGRBG8_1X8,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_SGRBG8,
		.name			= "Bayer 8 GRBG",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_NONE,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_SGRBG10DPCM8,
		.name			= "Bayer 10 BGGR DPCM 8",
		.bits_per_sample	= 8,
		.packing		= PXA_MBUS_PACKING_NONE,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_SGBRG10_1X10,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_SGBRG10,
		.name			= "Bayer 10 GBRG",
		.bits_per_sample	= 10,
		.packing		= PXA_MBUS_PACKING_EXTEND16,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_SGRBG10_1X10,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_SGRBG10,
		.name			= "Bayer 10 GRBG",
		.bits_per_sample	= 10,
		.packing		= PXA_MBUS_PACKING_EXTEND16,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_SRGGB10_1X10,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_SRGGB10,
		.name			= "Bayer 10 RGGB",
		.bits_per_sample	= 10,
		.packing		= PXA_MBUS_PACKING_EXTEND16,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_SBGGR12_1X12,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_SBGGR12,
		.name			= "Bayer 12 BGGR",
		.bits_per_sample	= 12,
		.packing		= PXA_MBUS_PACKING_EXTEND16,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_SGBRG12_1X12,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_SGBRG12,
		.name			= "Bayer 12 GBRG",
		.bits_per_sample	= 12,
		.packing		= PXA_MBUS_PACKING_EXTEND16,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_SGRBG12_1X12,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_SGRBG12,
		.name			= "Bayer 12 GRBG",
		.bits_per_sample	= 12,
		.packing		= PXA_MBUS_PACKING_EXTEND16,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
}, {
	.code = MEDIA_BUS_FMT_SRGGB12_1X12,
	.fmt = {
		.fourcc			= V4L2_PIX_FMT_SRGGB12,
		.name			= "Bayer 12 RGGB",
		.bits_per_sample	= 12,
		.packing		= PXA_MBUS_PACKING_EXTEND16,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PACKED,
	},
},
};

static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
{
	if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
		return width * mf->bits_per_sample / 8;

	switch (mf->packing) {
	case PXA_MBUS_PACKING_NONE:
		return width * mf->bits_per_sample / 8;
	case PXA_MBUS_PACKING_2X8_PADHI:
	case PXA_MBUS_PACKING_EXTEND16:
		return width * 2;
	}
	return -EINVAL;
}

static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
			u32 bytes_per_line, u32 height)
{
	switch (mf->packing) {
	case PXA_MBUS_PACKING_2X8_PADHI:
		return bytes_per_line * height * 2;
	default:
		return -EINVAL;
	}
}

static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
	u32 code,
	const struct pxa_mbus_lookup *lookup,
	int n)
{
	int i;

	for (i = 0; i < n; i++)
		if (lookup[i].code == code)
			return &lookup[i].fmt;

	return NULL;
}

static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
	u32 code)
{
	return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
}

static unsigned int pxa_mbus_config_compatible(const struct v4l2_mbus_config *cfg,
					unsigned int flags)
{
	unsigned long common_flags;
	bool hsync = true, vsync = true, pclk, data, mode;
	bool mipi_lanes, mipi_clock;

	common_flags = cfg->flags & flags;

	switch (cfg->type) {
	case V4L2_MBUS_PARALLEL:
		hsync = common_flags & (V4L2_MBUS_HSYNC_ACTIVE_HIGH |
					V4L2_MBUS_HSYNC_ACTIVE_LOW);
		vsync = common_flags & (V4L2_MBUS_VSYNC_ACTIVE_HIGH |
					V4L2_MBUS_VSYNC_ACTIVE_LOW);
		/* fall through */
	case V4L2_MBUS_BT656:
		pclk = common_flags & (V4L2_MBUS_PCLK_SAMPLE_RISING |
				       V4L2_MBUS_PCLK_SAMPLE_FALLING);
		data = common_flags & (V4L2_MBUS_DATA_ACTIVE_HIGH |
				       V4L2_MBUS_DATA_ACTIVE_LOW);
		mode = common_flags & (V4L2_MBUS_MASTER | V4L2_MBUS_SLAVE);
		return (!hsync || !vsync || !pclk || !data || !mode) ?
			0 : common_flags;
	case V4L2_MBUS_CSI2:
		mipi_lanes = common_flags & V4L2_MBUS_CSI2_LANES;
		mipi_clock = common_flags & (V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
					     V4L2_MBUS_CSI2_CONTINUOUS_CLOCK);
		return (!mipi_lanes || !mipi_clock) ? 0 : common_flags;
	}
	return 0;
}

619 620 621 622 623 624 625 626 627 628 629 630
/**
 * struct soc_camera_format_xlate - match between host and sensor formats
 * @code: code of a sensor provided format
 * @host_fmt: host format after host translation from code
 *
 * Host and sensor translation structure. Used in table of host and sensor
 * formats matchings in soc_camera_device. A host can override the generic list
 * generation by implementing get_formats(), and use it for format checks and
 * format setup.
 */
struct soc_camera_format_xlate {
	u32 code;
631
	const struct pxa_mbus_pixelfmt *host_fmt;
632
};
633

634 635 636
/*
 * Structures
 */
637 638 639 640 641 642
enum pxa_camera_active_dma {
	DMA_Y = 0x1,
	DMA_U = 0x2,
	DMA_V = 0x4,
};

643 644 645
/* buffer for one video frame */
struct pxa_buffer {
	/* common v4l buffer stuff -- must be first */
646 647
	struct vb2_v4l2_buffer		vbuf;
	struct list_head		queue;
648
	u32	code;
649
	int				nb_planes;
650
	/* our descriptor lists for Y, U and V channels */
651 652 653 654
	struct dma_async_tx_descriptor	*descs[3];
	dma_cookie_t			cookie[3];
	struct scatterlist		*sg[3];
	int				sg_len[3];
655
	size_t				plane_sizes[3];
656 657
	int				inwork;
	enum pxa_camera_active_dma	active_dma;
658 659 660
};

struct pxa_camera_dev {
661 662 663 664 665 666 667 668 669 670 671 672
	struct v4l2_device	v4l2_dev;
	struct video_device	vdev;
	struct v4l2_async_notifier notifier;
	struct vb2_queue	vb2_vq;
	struct v4l2_subdev	*sensor;
	struct soc_camera_format_xlate *user_formats;
	const struct soc_camera_format_xlate *current_fmt;
	struct v4l2_pix_format	current_pix;

	struct v4l2_async_subdev asd;
	struct v4l2_async_subdev *asds[1];

673 674
	/*
	 * PXA27x is only supposed to handle one camera on its Quick Capture
675
	 * interface. If anyone ever builds hardware to enable more than
676 677
	 * one camera, they will have to modify this driver too
	 */
678 679 680 681
	struct clk		*clk;

	unsigned int		irq;
	void __iomem		*base;
682

683
	int			channels;
684
	struct dma_chan		*dma_chans[3];
685 686 687 688

	struct pxacamera_platform_data *pdata;
	struct resource		*res;
	unsigned long		platform_flags;
689 690 691
	unsigned long		ciclk;
	unsigned long		mclk;
	u32			mclk_divisor;
692
	struct v4l2_clk		*mclk_clk;
693
	u16			width_flags;	/* max 10 bits */
694 695 696 697

	struct list_head	capture;

	spinlock_t		lock;
698
	struct mutex		mlock;
699
	unsigned int		buf_sequence;
700 701

	struct pxa_buffer	*active;
702
	struct tasklet_struct	task_eof;
703 704

	u32			save_cicr[5];
705 706
};

707 708 709 710
struct pxa_cam {
	unsigned long flags;
};

711 712
static const char *pxa_cam_driver_description = "PXA_Camera";

713 714 715
/*
 * Format translation functions
 */
716
static const struct soc_camera_format_xlate
717
*pxa_mbus_xlate_by_fourcc(struct soc_camera_format_xlate *user_formats,
718
			  unsigned int fourcc)
719 720 721 722 723 724 725 726 727
{
	unsigned int i;

	for (i = 0; user_formats[i].code; i++)
		if (user_formats[i].host_fmt->fourcc == fourcc)
			return user_formats + i;
	return NULL;
}

728
static struct soc_camera_format_xlate *pxa_mbus_build_fmts_xlate(
729 730 731
	struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
	int (*get_formats)(struct v4l2_device *, unsigned int,
			   struct soc_camera_format_xlate *xlate))
732
{
733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757
	unsigned int i, fmts = 0, raw_fmts = 0;
	int ret;
	struct v4l2_subdev_mbus_code_enum code = {
		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
	};
	struct soc_camera_format_xlate *user_formats;

	while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
		raw_fmts++;
		code.index++;
	}

	/*
	 * First pass - only count formats this host-sensor
	 * configuration can provide
	 */
	for (i = 0; i < raw_fmts; i++) {
		ret = get_formats(v4l2_dev, i, NULL);
		if (ret < 0)
			return ERR_PTR(ret);
		fmts += ret;
	}

	if (!fmts)
		return ERR_PTR(-ENXIO);
758

759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776
	user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
	if (!user_formats)
		return ERR_PTR(-ENOMEM);

	/* Second pass - actually fill data formats */
	fmts = 0;
	for (i = 0; i < raw_fmts; i++) {
		ret = get_formats(v4l2_dev, i, user_formats + fmts);
		if (ret < 0)
			goto egfmt;
		fmts += ret;
	}
	user_formats[fmts].code = 0;

	return user_formats;
egfmt:
	kfree(user_formats);
	return ERR_PTR(ret);
777 778
}

779 780 781
/*
 *  Videobuf operations
 */
782
static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
783
{
784
	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
785

786
	return container_of(vbuf, struct pxa_buffer, vbuf);
787 788
}

789
static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
790
{
791 792 793 794 795 796
	return pcdev->v4l2_dev.dev;
}

static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
{
	return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
797 798
}

799
static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
800 801
			       enum pxa_camera_active_dma act_dma);

802
static void pxa_camera_dma_irq_y(void *data)
803 804 805
{
	struct pxa_camera_dev *pcdev = data;

806
	pxa_camera_dma_irq(pcdev, DMA_Y);
807 808
}

809
static void pxa_camera_dma_irq_u(void *data)
810 811 812
{
	struct pxa_camera_dev *pcdev = data;

813
	pxa_camera_dma_irq(pcdev, DMA_U);
814 815
}

816
static void pxa_camera_dma_irq_v(void *data)
817 818 819
{
	struct pxa_camera_dev *pcdev = data;

820
	pxa_camera_dma_irq(pcdev, DMA_V);
821 822
}

823 824 825
/**
 * pxa_init_dma_channel - init dma descriptors
 * @pcdev: pxa camera device
826
 * @vb: videobuffer2 buffer
827 828 829 830 831 832
 * @dma: dma video buffer
 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
 * @cibr: camera Receive Buffer Register
 *
 * Prepares the pxa dma descriptors to transfer one camera channel.
 *
833
 * Returns 0 if success or -ENOMEM if no memory is available
834
 */
835
static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
836 837
				struct pxa_buffer *buf, int channel,
				struct scatterlist *sg, int sglen)
838
{
839 840 841 842 843 844
	struct dma_chan *dma_chan = pcdev->dma_chans[channel];
	struct dma_async_tx_descriptor *tx;

	tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
				     DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
	if (!tx) {
845
		dev_err(pcdev_to_dev(pcdev),
846 847
			"dmaengine_prep_slave_sg failed\n");
		goto fail;
848 849
	}

850 851 852 853 854 855 856 857 858 859 860
	tx->callback_param = pcdev;
	switch (channel) {
	case 0:
		tx->callback = pxa_camera_dma_irq_y;
		break;
	case 1:
		tx->callback = pxa_camera_dma_irq_u;
		break;
	case 2:
		tx->callback = pxa_camera_dma_irq_v;
		break;
861 862
	}

863
	buf->descs[channel] = tx;
864
	return 0;
865
fail:
866 867 868
	dev_dbg(pcdev_to_dev(pcdev),
		"%s (vb=%p) dma_tx=%p\n",
		__func__, buf, tx);
869 870

	return -ENOMEM;
871 872
}

873 874 875 876
static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
				    struct pxa_buffer *buf)
{
	buf->active_dma = DMA_Y;
877
	if (buf->nb_planes == 3)
878 879 880 881 882 883 884 885 886 887 888 889 890 891 892
		buf->active_dma |= DMA_U | DMA_V;
}

/**
 * pxa_dma_start_channels - start DMA channel for active buffer
 * @pcdev: pxa camera device
 *
 * Initialize DMA channels to the beginning of the active video buffer, and
 * start these channels.
 */
static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
{
	int i;

	for (i = 0; i < pcdev->channels; i++) {
893
		dev_dbg(pcdev_to_dev(pcdev),
894 895
			"%s (channel=%d)\n", __func__, i);
		dma_async_issue_pending(pcdev->dma_chans[i]);
896 897 898 899 900 901 902 903
	}
}

static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
{
	int i;

	for (i = 0; i < pcdev->channels; i++) {
904
		dev_dbg(pcdev_to_dev(pcdev),
905
			"%s (channel=%d)\n", __func__, i);
906
		dmaengine_terminate_all(pcdev->dma_chans[i]);
907 908 909 910 911 912 913 914 915
	}
}

static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
				 struct pxa_buffer *buf)
{
	int i;

	for (i = 0; i < pcdev->channels; i++) {
916
		buf->cookie[i] = dmaengine_submit(buf->descs[i]);
917
		dev_dbg(pcdev_to_dev(pcdev),
918 919
			"%s (channel=%d) : submit vb=%p cookie=%d\n",
			__func__, i, buf, buf->descs[i]->cookie);
920
	}
921 922 923 924 925 926 927 928 929 930 931 932
}

/**
 * pxa_camera_start_capture - start video capturing
 * @pcdev: camera device
 *
 * Launch capturing. DMA channels should not be active yet. They should get
 * activated at the end of frame interrupt, to capture only whole frames, and
 * never begin the capture of a partial frame.
 */
static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
{
933
	unsigned long cicr0;
934

935
	dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
936
	__raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
937 938 939 940 941 942 943 944 945 946 947 948 949 950 951
	/* Enable End-Of-Frame Interrupt */
	cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
	cicr0 &= ~CICR0_EOFM;
	__raw_writel(cicr0, pcdev->base + CICR0);
}

static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
{
	unsigned long cicr0;

	pxa_dma_stop_channels(pcdev);

	cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
	__raw_writel(cicr0, pcdev->base + CICR0);

952
	pcdev->active = NULL;
953
	dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
954 955
}

956
static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
957 958
			      struct pxa_buffer *buf,
			      enum vb2_buffer_state state)
959
{
960
	struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
961
	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
962

963
	/* _init is used to debug races, see comment in pxa_camera_reqbufs() */
964 965
	list_del_init(&buf->queue);
	vb->timestamp = ktime_get_ns();
966 967
	vbuf->sequence = pcdev->buf_sequence++;
	vbuf->field = V4L2_FIELD_NONE;
968
	vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
969
	dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n",
970
		__func__, buf);
971 972

	if (list_empty(&pcdev->capture)) {
973
		pxa_camera_stop_capture(pcdev);
974 975 976 977
		return;
	}

	pcdev->active = list_entry(pcdev->capture.next,
978
				   struct pxa_buffer, queue);
979 980
}

981 982 983 984 985 986
/**
 * pxa_camera_check_link_miss - check missed DMA linking
 * @pcdev: camera device
 *
 * The DMA chaining is done with DMA running. This means a tiny temporal window
 * remains, where a buffer is queued on the chain, while the chain is already
L
Lucas De Marchi 已提交
987
 * stopped. This means the tailed buffer would never be transferred by DMA.
988 989 990 991 992 993 994 995 996
 * This function restarts the capture for this corner case, where :
 *  - DADR() == DADDR_STOP
 *  - a videobuffer is queued on the pcdev->capture list
 *
 * Please check the "DMA hot chaining timeslice issue" in
 *   Documentation/video4linux/pxa_camera.txt
 *
 * Context: should only be called within the dma irq handler
 */
997 998 999
static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
				       dma_cookie_t last_submitted,
				       dma_cookie_t last_issued)
1000
{
1001
	bool is_dma_stopped = last_submitted != last_issued;
1002

1003
	dev_dbg(pcdev_to_dev(pcdev),
1004
		"%s : top queued buffer=%p, is_dma_stopped=%d\n",
1005
		__func__, pcdev->active, is_dma_stopped);
1006

1007 1008 1009 1010
	if (pcdev->active && is_dma_stopped)
		pxa_camera_start_capture(pcdev);
}

1011
static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
1012
			       enum pxa_camera_active_dma act_dma)
1013
{
1014
	struct pxa_buffer *buf, *last_buf;
1015
	unsigned long flags;
1016 1017 1018 1019
	u32 camera_status, overrun;
	int chan;
	enum dma_status last_status;
	dma_cookie_t last_issued;
1020 1021 1022

	spin_lock_irqsave(&pcdev->lock, flags);

1023
	camera_status = __raw_readl(pcdev->base + CISR);
1024
	dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
1025
		camera_status, act_dma);
1026 1027 1028
	overrun = CISR_IFO_0;
	if (pcdev->channels == 3)
		overrun |= CISR_IFO_1 | CISR_IFO_2;
1029

1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042
	/*
	 * pcdev->active should not be NULL in DMA irq handler.
	 *
	 * But there is one corner case : if capture was stopped due to an
	 * overrun of channel 1, and at that same channel 2 was completed.
	 *
	 * When handling the overrun in DMA irq for channel 1, we'll stop the
	 * capture and restart it (and thus set pcdev->active to NULL). But the
	 * DMA irq handler will already be pending for channel 2. So on entering
	 * the DMA irq handler for channel 2 there will be no active buffer, yet
	 * that is normal.
	 */
	if (!pcdev->active)
1043 1044
		goto out;

1045 1046
	buf = pcdev->active;
	WARN_ON(buf->inwork || list_empty(&buf->queue));
1047

1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063
	/*
	 * It's normal if the last frame creates an overrun, as there
	 * are no more DMA descriptors to fetch from QCI fifos
	 */
	switch (act_dma) {
	case DMA_U:
		chan = 1;
		break;
	case DMA_V:
		chan = 2;
		break;
	default:
		chan = 0;
		break;
	}
	last_buf = list_entry(pcdev->capture.prev,
1064
			      struct pxa_buffer, queue);
1065 1066 1067 1068 1069
	last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
					       last_buf->cookie[chan],
					       NULL, &last_issued);
	if (camera_status & overrun &&
	    last_status != DMA_COMPLETE) {
1070
		dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
1071 1072
			camera_status);
		pxa_camera_stop_capture(pcdev);
1073
		list_for_each_entry(buf, &pcdev->capture, queue)
1074 1075 1076 1077 1078 1079
			pxa_dma_add_tail_buf(pcdev, buf);
		pxa_camera_start_capture(pcdev);
		goto out;
	}
	buf->active_dma &= ~act_dma;
	if (!buf->active_dma) {
1080
		pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
1081 1082
		pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
					   last_issued);
1083
	}
1084 1085 1086 1087 1088

out:
	spin_unlock_irqrestore(&pcdev->lock, flags);
}

1089 1090
static u32 mclk_get_divisor(struct platform_device *pdev,
			    struct pxa_camera_dev *pcdev)
1091
{
1092 1093
	unsigned long mclk = pcdev->mclk;
	u32 div;
1094 1095
	unsigned long lcdclk;

1096 1097
	lcdclk = clk_get_rate(pcdev->clk);
	pcdev->ciclk = lcdclk;
1098

1099 1100 1101
	/* mclk <= ciclk / 4 (27.4.2) */
	if (mclk > lcdclk / 4) {
		mclk = lcdclk / 4;
1102 1103
		dev_warn(pcdev_to_dev(pcdev),
			 "Limiting master clock to %lu\n", mclk);
1104 1105 1106 1107
	}

	/* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
	div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
1108

1109 1110 1111
	/* If we're not supplying MCLK, leave it at 0 */
	if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
		pcdev->mclk = lcdclk / (2 * (div + 1));
1112

1113
	dev_dbg(pcdev_to_dev(pcdev), "LCD clock %luHz, target freq %luHz, divisor %u\n",
1114
		lcdclk, mclk, div);
1115 1116 1117 1118

	return div;
}

1119 1120 1121 1122 1123 1124 1125 1126 1127
static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
				     unsigned long pclk)
{
	/* We want a timeout > 1 pixel time, not ">=" */
	u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;

	__raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
}

1128
static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
1129 1130 1131
{
	u32 cicr4 = 0;

1132 1133
	/* disable all interrupts */
	__raw_writel(0x3ff, pcdev->base + CICR0);
1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145

	if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
		cicr4 |= CICR4_PCLK_EN;
	if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
		cicr4 |= CICR4_MCLK_EN;
	if (pcdev->platform_flags & PXA_CAMERA_PCP)
		cicr4 |= CICR4_PCP;
	if (pcdev->platform_flags & PXA_CAMERA_HSP)
		cicr4 |= CICR4_HSP;
	if (pcdev->platform_flags & PXA_CAMERA_VSP)
		cicr4 |= CICR4_VSP;

1146 1147 1148 1149 1150 1151 1152 1153
	__raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);

	if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
		/* Initialise the timeout under the assumption pclk = mclk */
		recalculate_fifo_timeout(pcdev, pcdev->mclk);
	else
		/* "Safe default" - 13MHz */
		recalculate_fifo_timeout(pcdev, 13000000);
1154

1155
	clk_prepare_enable(pcdev->clk);
1156 1157
}

1158
static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
1159
{
1160
	clk_disable_unprepare(pcdev->clk);
1161 1162
}

1163
static void pxa_camera_eof(unsigned long arg)
1164
{
1165 1166
	struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg;
	unsigned long cifr;
1167
	struct pxa_buffer *buf;
1168

1169
	dev_dbg(pcdev_to_dev(pcdev),
1170 1171 1172 1173 1174 1175 1176 1177
		"Camera interrupt status 0x%x\n",
		__raw_readl(pcdev->base + CISR));

	/* Reset the FIFOs */
	cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
	__raw_writel(cifr, pcdev->base + CIFR);

	pcdev->active = list_first_entry(&pcdev->capture,
1178 1179
					 struct pxa_buffer, queue);
	buf = pcdev->active;
1180 1181 1182 1183 1184 1185 1186 1187 1188 1189
	pxa_videobuf_set_actdma(pcdev, buf);

	pxa_dma_start_channels(pcdev);
}

static irqreturn_t pxa_camera_irq(int irq, void *data)
{
	struct pxa_camera_dev *pcdev = data;
	unsigned long status, cicr0;

1190
	status = __raw_readl(pcdev->base + CISR);
1191
	dev_dbg(pcdev_to_dev(pcdev),
1192
		"Camera interrupt status 0x%lx\n", status);
1193

1194 1195 1196
	if (!status)
		return IRQ_NONE;

1197
	__raw_writel(status, pcdev->base + CISR);
1198 1199

	if (status & CISR_EOF) {
1200 1201
		cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
		__raw_writel(cicr0, pcdev->base + CICR0);
1202
		tasklet_schedule(&pcdev->task_eof);
1203 1204
	}

1205 1206 1207
	return IRQ_HANDLED;
}

1208 1209
static int test_platform_param(struct pxa_camera_dev *pcdev,
			       unsigned char buswidth, unsigned long *flags)
1210
{
1211 1212 1213 1214 1215 1216
	/*
	 * Platform specified synchronization and pixel clock polarities are
	 * only a recommendation and are only used during probing. The PXA270
	 * quick capture interface supports both.
	 */
	*flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1217 1218 1219 1220 1221 1222 1223 1224
		  V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
		V4L2_MBUS_HSYNC_ACTIVE_HIGH |
		V4L2_MBUS_HSYNC_ACTIVE_LOW |
		V4L2_MBUS_VSYNC_ACTIVE_HIGH |
		V4L2_MBUS_VSYNC_ACTIVE_LOW |
		V4L2_MBUS_DATA_ACTIVE_HIGH |
		V4L2_MBUS_PCLK_SAMPLE_RISING |
		V4L2_MBUS_PCLK_SAMPLE_FALLING;
1225 1226

	/* If requested data width is supported by the platform, use it */
1227 1228
	if ((1 << (buswidth - 1)) & pcdev->width_flags)
		return 0;
1229

1230
	return -EINVAL;
1231 1232
}

1233
static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
1234
				  unsigned long flags, __u32 pixfmt)
1235
{
1236
	unsigned long dw, bpp;
1237
	u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1238
	int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
1239 1240 1241

	if (ret < 0)
		y_skip_top = 0;
1242

1243 1244 1245 1246
	/*
	 * Datawidth is now guaranteed to be equal to one of the three values.
	 * We fix bit-per-pixel equal to data-width...
	 */
1247
	switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
1248
	case 10:
1249 1250 1251
		dw = 4;
		bpp = 0x40;
		break;
1252
	case 9:
1253 1254 1255 1256
		dw = 3;
		bpp = 0x20;
		break;
	default:
1257 1258 1259 1260
		/*
		 * Actually it can only be 8 now,
		 * default is just to silence compiler warnings
		 */
1261
	case 8:
1262 1263 1264 1265 1266 1267 1268 1269
		dw = 2;
		bpp = 0;
	}

	if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
		cicr4 |= CICR4_PCLK_EN;
	if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
		cicr4 |= CICR4_MCLK_EN;
1270
	if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1271
		cicr4 |= CICR4_PCP;
1272
	if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1273
		cicr4 |= CICR4_HSP;
1274
	if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1275 1276
		cicr4 |= CICR4_VSP;

1277
	cicr0 = __raw_readl(pcdev->base + CICR0);
1278
	if (cicr0 & CICR0_ENB)
1279
		__raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1280

1281
	cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
1282 1283 1284

	switch (pixfmt) {
	case V4L2_PIX_FMT_YUV422P:
1285
		pcdev->channels = 3;
1286
		cicr1 |= CICR1_YCBCR_F;
1287 1288 1289 1290 1291 1292 1293 1294 1295
		/*
		 * Normally, pxa bus wants as input UYVY format. We allow all
		 * reorderings of the YUV422 format, as no processing is done,
		 * and the YUV stream is just passed through without any
		 * transformation. Note that UYVY is the only format that
		 * should be used if pxa framebuffer Overlay2 is used.
		 */
	case V4L2_PIX_FMT_UYVY:
	case V4L2_PIX_FMT_VYUY:
1296
	case V4L2_PIX_FMT_YUYV:
1297
	case V4L2_PIX_FMT_YVYU:
1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308
		cicr1 |= CICR1_COLOR_SP_VAL(2);
		break;
	case V4L2_PIX_FMT_RGB555:
		cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
			CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
		break;
	case V4L2_PIX_FMT_RGB565:
		cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
		break;
	}

1309
	cicr2 = 0;
1310
	cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
1311
		CICR3_BFW_VAL(min((u32)255, y_skip_top));
1312
	cicr4 |= pcdev->mclk_divisor;
1313 1314 1315 1316 1317

	__raw_writel(cicr1, pcdev->base + CICR1);
	__raw_writel(cicr2, pcdev->base + CICR2);
	__raw_writel(cicr3, pcdev->base + CICR3);
	__raw_writel(cicr4, pcdev->base + CICR4);
1318 1319

	/* CIF interrupts are not used, only DMA */
1320 1321 1322 1323
	cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
		CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
	cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
	__raw_writel(cicr0, pcdev->base + CICR0);
1324 1325
}

1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426
/*
 * Videobuf2 section
 */
static void pxa_buffer_cleanup(struct pxa_buffer *buf)
{
	int i;

	for (i = 0; i < 3 && buf->descs[i]; i++) {
		dmaengine_desc_free(buf->descs[i]);
		kfree(buf->sg[i]);
		buf->descs[i] = NULL;
		buf->sg[i] = NULL;
		buf->sg_len[i] = 0;
		buf->plane_sizes[i] = 0;
	}
	buf->nb_planes = 0;
}

static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
			   struct pxa_buffer *buf)
{
	struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
	struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
	int nb_channels = pcdev->channels;
	int i, ret = 0;
	unsigned long size = vb2_plane_size(vb, 0);

	switch (nb_channels) {
	case 1:
		buf->plane_sizes[0] = size;
		break;
	case 3:
		buf->plane_sizes[0] = size / 2;
		buf->plane_sizes[1] = size / 4;
		buf->plane_sizes[2] = size / 4;
		break;
	default:
		return -EINVAL;
	};
	buf->nb_planes = nb_channels;

	ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
		       buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
	if (ret < 0) {
		dev_err(pcdev_to_dev(pcdev),
			"sg_split failed: %d\n", ret);
		return ret;
	}
	for (i = 0; i < nb_channels; i++) {
		ret = pxa_init_dma_channel(pcdev, buf, i,
					   buf->sg[i], buf->sg_len[i]);
		if (ret) {
			pxa_buffer_cleanup(buf);
			return ret;
		}
	}
	INIT_LIST_HEAD(&buf->queue);

	return ret;
}

static void pxac_vb2_cleanup(struct vb2_buffer *vb)
{
	struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);

	dev_dbg(pcdev_to_dev(pcdev),
		 "%s(vb=%p)\n", __func__, vb);
	pxa_buffer_cleanup(buf);
}

static void pxac_vb2_queue(struct vb2_buffer *vb)
{
	struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);

	dev_dbg(pcdev_to_dev(pcdev),
		 "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
		__func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
		pcdev->active);

	list_add_tail(&buf->queue, &pcdev->capture);

	pxa_dma_add_tail_buf(pcdev, buf);
}

/*
 * Please check the DMA prepared buffer structure in :
 *   Documentation/video4linux/pxa_camera.txt
 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
 * modification while DMA chain is running will work anyway.
 */
static int pxac_vb2_prepare(struct vb2_buffer *vb)
{
	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
	struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
	int ret = 0;

	switch (pcdev->channels) {
	case 1:
	case 3:
1427
		vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
1428 1429 1430 1431 1432 1433 1434 1435 1436
		break;
	default:
		return -EINVAL;
	}

	dev_dbg(pcdev_to_dev(pcdev),
		 "%s (vb=%p) nb_channels=%d size=%lu\n",
		__func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));

1437
	WARN_ON(!pcdev->current_fmt);
1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476

#ifdef DEBUG
	/*
	 * This can be useful if you want to see if we actually fill
	 * the buffer with something
	 */
	for (i = 0; i < vb->num_planes; i++)
		memset((void *)vb2_plane_vaddr(vb, i),
		       0xaa, vb2_get_plane_payload(vb, i));
#endif

	/*
	 * I think, in buf_prepare you only have to protect global data,
	 * the actual buffer is yours
	 */
	buf->inwork = 0;
	pxa_videobuf_set_actdma(pcdev, buf);

	return ret;
}

static int pxac_vb2_init(struct vb2_buffer *vb)
{
	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
	struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);

	dev_dbg(pcdev_to_dev(pcdev),
		 "%s(nb_channels=%d)\n",
		__func__, pcdev->channels);

	return pxa_buffer_init(pcdev, buf);
}

static int pxac_vb2_queue_setup(struct vb2_queue *vq,
				unsigned int *nbufs,
				unsigned int *num_planes, unsigned int sizes[],
				struct device *alloc_devs[])
{
	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1477
	int size = pcdev->current_pix.sizeimage;
1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512

	dev_dbg(pcdev_to_dev(pcdev),
		 "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
		__func__, vq, *nbufs, *num_planes, size);
	/*
	 * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
	 * format, even if there are 3 planes Y, U and V, we reply there is only
	 * one plane, containing Y, U and V data, one after the other.
	 */
	if (*num_planes)
		return sizes[0] < size ? -EINVAL : 0;

	*num_planes = 1;
	switch (pcdev->channels) {
	case 1:
	case 3:
		sizes[0] = size;
		break;
	default:
		return -EINVAL;
	}

	if (!*nbufs)
		*nbufs = 1;

	return 0;
}

static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
{
	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);

	dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
		__func__, count, pcdev->active);

1513
	pcdev->buf_sequence = 0;
1514 1515 1516 1517 1518 1519 1520 1521
	if (!pcdev->active)
		pxa_camera_start_capture(pcdev);

	return 0;
}

static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
{
1522 1523 1524 1525 1526 1527 1528 1529 1530
	struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
	struct pxa_buffer *buf, *tmp;

	dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
		__func__, pcdev->active);
	pxa_camera_stop_capture(pcdev);

	list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
		pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544
}

static struct vb2_ops pxac_vb2_ops = {
	.queue_setup		= pxac_vb2_queue_setup,
	.buf_init		= pxac_vb2_init,
	.buf_prepare		= pxac_vb2_prepare,
	.buf_queue		= pxac_vb2_queue,
	.buf_cleanup		= pxac_vb2_cleanup,
	.start_streaming	= pxac_vb2_start_streaming,
	.stop_streaming		= pxac_vb2_stop_streaming,
	.wait_prepare		= vb2_ops_wait_prepare,
	.wait_finish		= vb2_ops_wait_finish,
};

1545
static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
1546 1547
{
	int ret;
1548
	struct vb2_queue *vq = &pcdev->vb2_vq;
1549

1550
	memset(vq, 0, sizeof(*vq));
1551 1552 1553 1554 1555
	vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
	vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
	vq->drv_priv = pcdev;
	vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
	vq->buf_struct_size = sizeof(struct pxa_buffer);
1556
	vq->dev = pcdev->v4l2_dev.dev;
1557 1558 1559

	vq->ops = &pxac_vb2_ops;
	vq->mem_ops = &vb2_dma_sg_memops;
1560
	vq->lock = &pcdev->mlock;
1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571

	ret = vb2_queue_init(vq);
	dev_dbg(pcdev_to_dev(pcdev),
		 "vb2_queue_init(vq=%p): %d\n", vq, ret);

	return ret;
}

/*
 * Video ioctls section
 */
1572
static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
1573
{
1574
	struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1575
	u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
1576
	unsigned long bus_flags, common_flags;
1577
	int ret;
1578

1579 1580
	ret = test_platform_param(pcdev,
				  pcdev->current_fmt->host_fmt->bits_per_sample,
1581
				  &bus_flags);
1582 1583 1584
	if (ret < 0)
		return ret;

1585
	ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1586
	if (!ret) {
1587
		common_flags = pxa_mbus_config_compatible(&cfg,
1588 1589
							  bus_flags);
		if (!common_flags) {
1590
			dev_warn(pcdev_to_dev(pcdev),
1591 1592 1593 1594 1595 1596 1597 1598 1599
				 "Flags incompatible: camera 0x%x, host 0x%lx\n",
				 cfg.flags, bus_flags);
			return -EINVAL;
		}
	} else if (ret != -ENOIOCTLCMD) {
		return ret;
	} else {
		common_flags = bus_flags;
	}
1600 1601 1602 1603

	pcdev->channels = 1;

	/* Make choises, based on platform preferences */
1604 1605
	if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
	    (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1606
		if (pcdev->platform_flags & PXA_CAMERA_HSP)
1607
			common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1608
		else
1609
			common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1610 1611
	}

1612 1613
	if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
	    (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1614
		if (pcdev->platform_flags & PXA_CAMERA_VSP)
1615
			common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1616
		else
1617
			common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1618 1619
	}

1620 1621
	if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
	    (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1622
		if (pcdev->platform_flags & PXA_CAMERA_PCP)
1623
			common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1624
		else
1625
			common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1626 1627
	}

1628
	cfg.flags = common_flags;
1629
	ret = sensor_call(pcdev, video, s_mbus_config, &cfg);
1630
	if (ret < 0 && ret != -ENOIOCTLCMD) {
1631 1632
		dev_dbg(pcdev_to_dev(pcdev),
			"camera s_mbus_config(0x%lx) returned %d\n",
1633
			common_flags, ret);
1634
		return ret;
1635 1636
	}

1637
	pxa_camera_setup_cicr(pcdev, common_flags, pixfmt);
1638 1639 1640 1641

	return 0;
}

1642
static int pxa_camera_try_bus_param(struct pxa_camera_dev *pcdev,
1643
				    unsigned char buswidth)
1644
{
1645 1646
	struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
	unsigned long bus_flags, common_flags;
1647
	int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1648 1649 1650 1651

	if (ret < 0)
		return ret;

1652
	ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1653
	if (!ret) {
1654
		common_flags = pxa_mbus_config_compatible(&cfg,
1655 1656
							  bus_flags);
		if (!common_flags) {
1657
			dev_warn(pcdev_to_dev(pcdev),
1658 1659 1660 1661 1662 1663 1664
				 "Flags incompatible: camera 0x%x, host 0x%lx\n",
				 cfg.flags, bus_flags);
			return -EINVAL;
		}
	} else if (ret == -ENOIOCTLCMD) {
		ret = 0;
	}
1665

1666
	return ret;
1667 1668
}

1669
static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
1670
	{
1671 1672 1673
		.fourcc			= V4L2_PIX_FMT_YUV422P,
		.name			= "Planar YUV422 16 bit",
		.bits_per_sample	= 8,
1674 1675 1676
		.packing		= PXA_MBUS_PACKING_2X8_PADHI,
		.order			= PXA_MBUS_ORDER_LE,
		.layout			= PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
1677 1678 1679
	},
};

1680
/* This will be corrected as we get more formats */
1681
static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
1682
{
1683
	return	fmt->packing == PXA_MBUS_PACKING_NONE ||
1684
		(fmt->bits_per_sample == 8 &&
1685
		 fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
1686
		(fmt->bits_per_sample > 8 &&
1687
		 fmt->packing == PXA_MBUS_PACKING_EXTEND16);
1688 1689
}

1690 1691
static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
				  unsigned int idx,
1692 1693
				  struct soc_camera_format_xlate *xlate)
{
1694
	struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
1695
	int formats = 0, ret;
1696 1697 1698 1699
	struct v4l2_subdev_mbus_code_enum code = {
		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
		.index = idx,
	};
1700
	const struct pxa_mbus_pixelfmt *fmt;
1701

1702
	ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1703 1704 1705
	if (ret < 0)
		/* No more formats */
		return 0;
1706

1707
	fmt = pxa_mbus_get_fmtdesc(code.code);
1708
	if (!fmt) {
1709 1710
		dev_err(pcdev_to_dev(pcdev),
			"Invalid format code #%u: %d\n", idx, code.code);
1711
		return 0;
1712
	}
1713

1714
	/* This also checks support for the requested bits-per-sample */
1715
	ret = pxa_camera_try_bus_param(pcdev, fmt->bits_per_sample);
1716 1717 1718
	if (ret < 0)
		return 0;

1719
	switch (code.code) {
1720
	case MEDIA_BUS_FMT_UYVY8_2X8:
1721 1722
		formats++;
		if (xlate) {
1723
			xlate->host_fmt	= &pxa_camera_formats[0];
1724
			xlate->code	= code.code;
1725
			xlate++;
1726 1727
			dev_dbg(pcdev_to_dev(pcdev),
				"Providing format %s using code %d\n",
1728
				pxa_camera_formats[0].name, code.code);
1729
		}
1730
	/* fall through */
1731 1732 1733 1734 1735
	case MEDIA_BUS_FMT_VYUY8_2X8:
	case MEDIA_BUS_FMT_YUYV8_2X8:
	case MEDIA_BUS_FMT_YVYU8_2X8:
	case MEDIA_BUS_FMT_RGB565_2X8_LE:
	case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1736
		if (xlate)
1737 1738
			dev_dbg(pcdev_to_dev(pcdev),
				"Providing format %s packed\n",
1739
				fmt->name);
1740 1741
		break;
	default:
1742 1743 1744
		if (!pxa_camera_packing_supported(fmt))
			return 0;
		if (xlate)
1745
			dev_dbg(pcdev_to_dev(pcdev),
1746
				"Providing format %s in pass-through mode\n",
1747
				fmt->name);
1748
		break;
1749 1750 1751 1752 1753 1754
	}

	/* Generic pass-through */
	formats++;
	if (xlate) {
		xlate->host_fmt	= fmt;
1755
		xlate->code	= code.code;
1756
		xlate++;
1757 1758 1759 1760 1761
	}

	return formats;
}

1762 1763 1764 1765
static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
{
	struct soc_camera_format_xlate *xlate;

1766
	xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
1767 1768 1769 1770 1771 1772 1773 1774 1775
					  pxa_camera_get_formats);
	if (IS_ERR(xlate))
		return PTR_ERR(xlate);

	pcdev->user_formats = xlate;
	return 0;
}

static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
1776
{
1777
	kfree(pcdev->user_formats);
1778 1779
}

1780
static int pxa_camera_check_frame(u32 width, u32 height)
1781 1782
{
	/* limit to pxa hardware capabilities */
1783 1784
	return height < 32 || height > 2048 || width < 48 || width > 2048 ||
		(width & 0x01);
1785 1786
}

1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int pxac_vidioc_g_register(struct file *file, void *priv,
				  struct v4l2_dbg_register *reg)
{
	struct pxa_camera_dev *pcdev = video_drvdata(file);

	if (reg->reg > CIBR2)
		return -ERANGE;

	reg->val = __raw_readl(pcdev->base + reg->reg);
	reg->size = sizeof(__u32);
	return 0;
}

static int pxac_vidioc_s_register(struct file *file, void *priv,
				  const struct v4l2_dbg_register *reg)
{
	struct pxa_camera_dev *pcdev = video_drvdata(file);

	if (reg->reg > CIBR2)
		return -ERANGE;
	if (reg->size != sizeof(__u32))
		return -EINVAL;
	__raw_writel(reg->val, pcdev->base + reg->reg);
	return 0;
}
#endif

1815 1816
static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void  *priv,
					struct v4l2_fmtdesc *f)
1817
{
1818
	struct pxa_camera_dev *pcdev = video_drvdata(filp);
1819
	const struct pxa_mbus_pixelfmt *format;
1820
	unsigned int idx;
1821

1822 1823
	for (idx = 0; pcdev->user_formats[idx].code; idx++);
	if (f->index >= idx)
1824
		return -EINVAL;
1825

1826 1827 1828 1829
	format = pcdev->user_formats[f->index].host_fmt;
	f->pixelformat = format->fourcc;
	return 0;
}
1830

1831 1832 1833 1834 1835
static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
				    struct v4l2_format *f)
{
	struct pxa_camera_dev *pcdev = video_drvdata(filp);
	struct v4l2_pix_format *pix = &f->fmt.pix;
1836

1837 1838 1839 1840 1841 1842 1843 1844 1845 1846
	pix->width		= pcdev->current_pix.width;
	pix->height		= pcdev->current_pix.height;
	pix->bytesperline	= pcdev->current_pix.bytesperline;
	pix->sizeimage		= pcdev->current_pix.sizeimage;
	pix->field		= pcdev->current_pix.field;
	pix->pixelformat	= pcdev->current_fmt->host_fmt->fourcc;
	pix->colorspace		= pcdev->current_pix.colorspace;
	dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
		pcdev->current_fmt->host_fmt->fourcc);
	return 0;
1847 1848
}

1849 1850
static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
				      struct v4l2_format *f)
1851
{
1852
	struct pxa_camera_dev *pcdev = video_drvdata(filp);
1853 1854
	const struct soc_camera_format_xlate *xlate;
	struct v4l2_pix_format *pix = &f->fmt.pix;
1855 1856 1857 1858 1859
	struct v4l2_subdev_pad_config pad_cfg;
	struct v4l2_subdev_format format = {
		.which = V4L2_SUBDEV_FORMAT_TRY,
	};
	struct v4l2_mbus_framefmt *mf = &format.format;
1860
	__u32 pixfmt = pix->pixelformat;
1861
	int ret;
1862

1863
	xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
1864
	if (!xlate) {
1865
		dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1866
		return -EINVAL;
1867
	}
1868

1869
	/*
1870 1871 1872 1873
	 * Limit to pxa hardware capabilities.  YUV422P planar format requires
	 * images size to be a multiple of 16 bytes.  If not, zeros will be
	 * inserted between Y and U planes, and U and V planes, which violates
	 * the YUV422P standard.
1874
	 */
1875 1876
	v4l_bound_align_image(&pix->width, 48, 2048, 1,
			      &pix->height, 32, 2048, 0,
1877
			      pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1878

1879
	v4l2_fill_mbus_format(mf, pix, xlate->code);
1880
	ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format);
1881 1882
	if (ret < 0)
		return ret;
1883

1884
	v4l2_fill_pix_format(pix, mf);
1885

1886
	/* Only progressive video supported so far */
1887
	switch (mf->field) {
1888 1889
	case V4L2_FIELD_ANY:
	case V4L2_FIELD_NONE:
1890
		pix->field = V4L2_FIELD_NONE;
1891 1892 1893
		break;
	default:
		/* TODO: support interlaced at least in pass-through mode */
1894
		dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1895
			mf->field);
1896 1897 1898
		return -EINVAL;
	}

1899
	ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
1900 1901 1902 1903
	if (ret < 0)
		return ret;

	pix->bytesperline = ret;
1904
	ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
1905 1906 1907 1908 1909 1910
				  pix->height);
	if (ret < 0)
		return ret;

	pix->sizeimage = ret;
	return 0;
1911 1912
}

1913 1914
static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
				    struct v4l2_format *f)
1915
{
1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939
	struct pxa_camera_dev *pcdev = video_drvdata(filp);
	const struct soc_camera_format_xlate *xlate;
	struct v4l2_pix_format *pix = &f->fmt.pix;
	struct v4l2_subdev_format format = {
		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
	};
	unsigned long flags;
	int ret, is_busy;

	dev_dbg(pcdev_to_dev(pcdev),
		"s_fmt_vid_cap(pix=%dx%d:%x)\n",
		pix->width, pix->height, pix->pixelformat);

	spin_lock_irqsave(&pcdev->lock, flags);
	is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
	spin_unlock_irqrestore(&pcdev->lock, flags);

	if (is_busy)
		return -EBUSY;

	ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
	if (ret)
		return ret;

1940
	xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956
					 pix->pixelformat);
	v4l2_fill_mbus_format(&format.format, pix, xlate->code);
	ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
	if (ret < 0) {
		dev_warn(pcdev_to_dev(pcdev),
			 "Failed to configure for format %x\n",
			 pix->pixelformat);
	} else if (pxa_camera_check_frame(pix->width, pix->height)) {
		dev_warn(pcdev_to_dev(pcdev),
			 "Camera driver produced an unsupported frame %dx%d\n",
			 pix->width, pix->height);
		return -EINVAL;
	}

	pcdev->current_fmt = xlate;
	pcdev->current_pix = *pix;
1957

1958 1959
	ret = pxa_camera_set_bus_param(pcdev);
	return ret;
1960 1961
}

1962 1963
static int pxac_vidioc_querycap(struct file *file, void *priv,
				struct v4l2_capability *cap)
1964
{
1965 1966
	strlcpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
	strlcpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
1967
	strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1968 1969
	cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
	cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1970 1971 1972 1973

	return 0;
}

1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064
static int pxac_vidioc_enum_input(struct file *file, void *priv,
				  struct v4l2_input *i)
{
	if (i->index > 0)
		return -EINVAL;

	i->type = V4L2_INPUT_TYPE_CAMERA;
	strlcpy(i->name, "Camera", sizeof(i->name));

	return 0;
}

static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
{
	*i = 0;

	return 0;
}

static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
{
	if (i > 0)
		return -EINVAL;

	return 0;
}

static int pxac_fops_camera_open(struct file *filp)
{
	struct pxa_camera_dev *pcdev = video_drvdata(filp);
	int ret;

	mutex_lock(&pcdev->mlock);
	ret = v4l2_fh_open(filp);
	if (ret < 0)
		goto out;

	ret = sensor_call(pcdev, core, s_power, 1);
	if (ret)
		v4l2_fh_release(filp);
out:
	mutex_unlock(&pcdev->mlock);
	return ret;
}

static int pxac_fops_camera_release(struct file *filp)
{
	struct pxa_camera_dev *pcdev = video_drvdata(filp);
	int ret;

	ret = vb2_fop_release(filp);
	if (ret < 0)
		return ret;

	mutex_lock(&pcdev->mlock);
	ret = sensor_call(pcdev, core, s_power, 0);
	mutex_unlock(&pcdev->mlock);

	return ret;
}

static const struct v4l2_file_operations pxa_camera_fops = {
	.owner		= THIS_MODULE,
	.open		= pxac_fops_camera_open,
	.release	= pxac_fops_camera_release,
	.read		= vb2_fop_read,
	.poll		= vb2_fop_poll,
	.mmap		= vb2_fop_mmap,
	.unlocked_ioctl = video_ioctl2,
};

static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
	.vidioc_querycap		= pxac_vidioc_querycap,

	.vidioc_enum_input		= pxac_vidioc_enum_input,
	.vidioc_g_input			= pxac_vidioc_g_input,
	.vidioc_s_input			= pxac_vidioc_s_input,

	.vidioc_enum_fmt_vid_cap	= pxac_vidioc_enum_fmt_vid_cap,
	.vidioc_g_fmt_vid_cap		= pxac_vidioc_g_fmt_vid_cap,
	.vidioc_s_fmt_vid_cap		= pxac_vidioc_s_fmt_vid_cap,
	.vidioc_try_fmt_vid_cap		= pxac_vidioc_try_fmt_vid_cap,

	.vidioc_reqbufs			= vb2_ioctl_reqbufs,
	.vidioc_create_bufs		= vb2_ioctl_create_bufs,
	.vidioc_querybuf		= vb2_ioctl_querybuf,
	.vidioc_qbuf			= vb2_ioctl_qbuf,
	.vidioc_dqbuf			= vb2_ioctl_dqbuf,
	.vidioc_expbuf			= vb2_ioctl_expbuf,
	.vidioc_streamon		= vb2_ioctl_streamon,
	.vidioc_streamoff		= vb2_ioctl_streamoff,
2065 2066 2067 2068
#ifdef CONFIG_VIDEO_ADV_DEBUG
	.vidioc_g_register		= pxac_vidioc_g_register,
	.vidioc_s_register		= pxac_vidioc_s_register,
#endif
2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120
};

static struct v4l2_clk_ops pxa_camera_mclk_ops = {
};

static const struct video_device pxa_camera_videodev_template = {
	.name = "pxa-camera",
	.minor = -1,
	.fops = &pxa_camera_fops,
	.ioctl_ops = &pxa_camera_ioctl_ops,
	.release = video_device_release_empty,
	.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
};

static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
		     struct v4l2_subdev *subdev,
		     struct v4l2_async_subdev *asd)
{
	int err;
	struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
	struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
	struct video_device *vdev = &pcdev->vdev;
	struct v4l2_pix_format *pix = &pcdev->current_pix;
	struct v4l2_subdev_format format = {
		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
	};
	struct v4l2_mbus_framefmt *mf = &format.format;

	dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
		 __func__);
	mutex_lock(&pcdev->mlock);
	*vdev = pxa_camera_videodev_template;
	vdev->v4l2_dev = v4l2_dev;
	vdev->lock = &pcdev->mlock;
	pcdev->sensor = subdev;
	pcdev->vdev.queue = &pcdev->vb2_vq;
	pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
	pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
	video_set_drvdata(&pcdev->vdev, pcdev);

	err = pxa_camera_build_formats(pcdev);
	if (err) {
		dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
			err);
		goto out;
	}

	pcdev->current_fmt = pcdev->user_formats;
	pix->field = V4L2_FIELD_NONE;
	pix->width = DEFAULT_WIDTH;
	pix->height = DEFAULT_HEIGHT;
	pix->bytesperline =
2121
		pxa_mbus_bytes_per_line(pix->width,
2122 2123
					pcdev->current_fmt->host_fmt);
	pix->sizeimage =
2124
		pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177
				    pix->bytesperline, pix->height);
	pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
	v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
	err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
	if (err)
		goto out;

	v4l2_fill_pix_format(pix, mf);
	pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
		__func__, pix->colorspace, pix->pixelformat);

	err = pxa_camera_init_videobuf2(pcdev);
	if (err)
		goto out;

	err = video_register_device(&pcdev->vdev, VFL_TYPE_GRABBER, -1);
	if (err) {
		v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
		pcdev->sensor = NULL;
	} else {
		dev_info(pcdev_to_dev(pcdev),
			 "PXA Camera driver attached to camera %s\n",
			 subdev->name);
	}
out:
	mutex_unlock(&pcdev->mlock);
	return err;
}

static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
		     struct v4l2_subdev *subdev,
		     struct v4l2_async_subdev *asd)
{
	struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);

	mutex_lock(&pcdev->mlock);
	dev_info(pcdev_to_dev(pcdev),
		 "PXA Camera driver detached from camera %s\n",
		 subdev->name);

	/* disable capture, disable interrupts */
	__raw_writel(0x3ff, pcdev->base + CICR0);

	/* Stop DMA engine */
	pxa_dma_stop_channels(pcdev);

	pxa_camera_destroy_formats(pcdev);
	video_unregister_device(&pcdev->vdev);
	pcdev->sensor = NULL;

	mutex_unlock(&pcdev->mlock);
}

2178 2179 2180
/*
 * Driver probe, remove, suspend and resume operations
 */
2181
static int pxa_camera_suspend(struct device *dev)
2182
{
2183
	struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2184 2185
	int i = 0, ret = 0;

2186 2187 2188 2189 2190
	pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
	pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
	pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
	pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
	pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
2191

2192
	if (pcdev->sensor) {
2193
		ret = sensor_call(pcdev, core, s_power, 0);
2194 2195 2196
		if (ret == -ENOIOCTLCMD)
			ret = 0;
	}
2197 2198 2199 2200

	return ret;
}

2201
static int pxa_camera_resume(struct device *dev)
2202
{
2203
	struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2204 2205
	int i = 0, ret = 0;

2206 2207 2208 2209 2210
	__raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
	__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
	__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
	__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
	__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
2211

2212
	if (pcdev->sensor) {
2213
		ret = sensor_call(pcdev, core, s_power, 1);
2214 2215 2216
		if (ret == -ENOIOCTLCMD)
			ret = 0;
	}
2217 2218

	/* Restart frame capture if active buffer exists */
2219 2220
	if (!ret && pcdev->active)
		pxa_camera_start_capture(pcdev);
2221 2222 2223 2224

	return ret;
}

2225
static int pxa_camera_pdata_from_dt(struct device *dev,
2226 2227
				    struct pxa_camera_dev *pcdev,
				    struct v4l2_async_subdev *asd)
2228 2229
{
	u32 mclk_rate;
2230
	struct device_node *remote, *np = dev->of_node;
2231 2232 2233 2234 2235 2236 2237 2238 2239 2240
	struct v4l2_of_endpoint ep;
	int err = of_property_read_u32(np, "clock-frequency",
				       &mclk_rate);
	if (!err) {
		pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
		pcdev->mclk = mclk_rate;
	}

	np = of_graph_get_next_endpoint(np, NULL);
	if (!np) {
2241
		dev_err(dev, "could not find endpoint\n");
2242 2243 2244 2245 2246
		return -EINVAL;
	}

	err = v4l2_of_parse_endpoint(np, &ep);
	if (err) {
2247
		dev_err(dev, "could not parse endpoint\n");
2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268
		goto out;
	}

	switch (ep.bus.parallel.bus_width) {
	case 4:
		pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
		break;
	case 5:
		pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
		break;
	case 8:
		pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
		break;
	case 9:
		pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
		break;
	case 10:
		pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
		break;
	default:
		break;
2269
	}
2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281

	if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
		pcdev->platform_flags |= PXA_CAMERA_MASTER;
	if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
		pcdev->platform_flags |= PXA_CAMERA_HSP;
	if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
		pcdev->platform_flags |= PXA_CAMERA_VSP;
	if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
		pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
	if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
		pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;

2282 2283 2284 2285 2286 2287 2288 2289 2290
	asd->match_type = V4L2_ASYNC_MATCH_OF;
	remote = of_graph_get_remote_port(np);
	if (remote) {
		asd->match.of.node = remote;
		of_node_put(remote);
	} else {
		dev_notice(dev, "no remote for %s\n", of_node_full_name(np));
	}

2291 2292 2293 2294 2295 2296
out:
	of_node_put(np);

	return err;
}

2297
static int pxa_camera_probe(struct platform_device *pdev)
2298 2299 2300 2301
{
	struct pxa_camera_dev *pcdev;
	struct resource *res;
	void __iomem *base;
2302 2303 2304 2305 2306 2307 2308
	struct dma_slave_config config = {
		.src_addr_width = 0,
		.src_maxburst = 8,
		.direction = DMA_DEV_TO_MEM,
	};
	dma_cap_mask_t mask;
	struct pxad_param params;
2309
	char clk_name[V4L2_CLK_NAME_SIZE];
2310
	int irq;
2311
	int err = 0, i;
2312 2313 2314

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_irq(pdev, 0);
2315 2316
	if (!res || irq < 0)
		return -ENODEV;
2317

2318
	pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
2319
	if (!pcdev) {
2320
		dev_err(&pdev->dev, "Could not allocate pcdev\n");
2321
		return -ENOMEM;
2322 2323
	}

2324 2325 2326
	pcdev->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pcdev->clk))
		return PTR_ERR(pcdev->clk);
2327 2328 2329 2330

	pcdev->res = res;

	pcdev->pdata = pdev->dev.platform_data;
2331
	if (&pdev->dev.of_node && !pcdev->pdata) {
2332
		err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev, &pcdev->asd);
2333 2334 2335
	} else {
		pcdev->platform_flags = pcdev->pdata->flags;
		pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
2336 2337 2338 2339
		pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
		pcdev->asd.match.i2c.adapter_id =
			pcdev->pdata->sensor_i2c_adapter_id;
		pcdev->asd.match.i2c.address = pcdev->pdata->sensor_i2c_address;
2340 2341 2342 2343
	}
	if (err < 0)
		return err;

2344 2345
	if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
			PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
2346 2347 2348 2349
		/*
		 * Platform hasn't set available data widths. This is bad.
		 * Warn and use a default.
		 */
2350
		dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n");
2351 2352
		pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
	}
2353 2354 2355 2356 2357 2358
	if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
		pcdev->width_flags = 1 << 7;
	if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
		pcdev->width_flags |= 1 << 8;
	if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
		pcdev->width_flags |= 1 << 9;
2359
	if (!pcdev->mclk) {
2360
		dev_warn(&pdev->dev,
2361
			 "mclk == 0! Please, fix your platform data. Using default 20MHz\n");
2362
		pcdev->mclk = 20000000;
2363 2364
	}

2365
	pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
2366

2367 2368
	INIT_LIST_HEAD(&pcdev->capture);
	spin_lock_init(&pcdev->lock);
2369
	mutex_init(&pcdev->mlock);
2370 2371 2372 2373

	/*
	 * Request the regions.
	 */
2374 2375 2376 2377
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

2378 2379 2380 2381
	pcdev->irq = irq;
	pcdev->base = base;

	/* request dma */
2382 2383 2384 2385 2386 2387 2388 2389 2390 2391
	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);
	dma_cap_set(DMA_PRIVATE, mask);

	params.prio = 0;
	params.drcmr = 68;
	pcdev->dma_chans[0] =
		dma_request_slave_channel_compat(mask, pxad_filter_fn,
						 &params, &pdev->dev, "CI_Y");
	if (!pcdev->dma_chans[0]) {
2392
		dev_err(&pdev->dev, "Can't request DMA for Y\n");
2393
		return -ENODEV;
2394
	}
2395

2396 2397 2398 2399 2400 2401
	params.drcmr = 69;
	pcdev->dma_chans[1] =
		dma_request_slave_channel_compat(mask, pxad_filter_fn,
						 &params, &pdev->dev, "CI_U");
	if (!pcdev->dma_chans[1]) {
		dev_err(&pdev->dev, "Can't request DMA for Y\n");
2402
		err = -ENODEV;
2403 2404 2405
		goto exit_free_dma_y;
	}

2406 2407 2408 2409 2410
	params.drcmr = 70;
	pcdev->dma_chans[2] =
		dma_request_slave_channel_compat(mask, pxad_filter_fn,
						 &params, &pdev->dev, "CI_V");
	if (!pcdev->dma_chans[2]) {
2411
		dev_err(&pdev->dev, "Can't request DMA for V\n");
2412
		err = -ENODEV;
2413 2414
		goto exit_free_dma_u;
	}
2415

2416 2417 2418 2419 2420 2421 2422 2423 2424
	for (i = 0; i < 3; i++) {
		config.src_addr = pcdev->res->start + CIBR0 + i * 8;
		err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
		if (err < 0) {
			dev_err(&pdev->dev, "dma slave config failed: %d\n",
				err);
			goto exit_free_dma;
		}
	}
2425 2426

	/* request irq */
2427 2428
	err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
			       PXA_CAM_DRV_NAME, pcdev);
2429
	if (err) {
2430
		dev_err(&pdev->dev, "Camera interrupt register failed\n");
2431 2432 2433
		goto exit_free_dma;
	}

2434
	tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev);
2435

2436 2437 2438 2439
	pxa_camera_activate(pcdev);

	dev_set_drvdata(&pdev->dev, pcdev);
	err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
2440
	if (err)
2441
		goto exit_free_dma;
2442

2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454
	pcdev->asds[0] = &pcdev->asd;
	pcdev->notifier.subdevs = pcdev->asds;
	pcdev->notifier.num_subdevs = 1;
	pcdev->notifier.bound = pxa_camera_sensor_bound;
	pcdev->notifier.unbind = pxa_camera_sensor_unbind;

	if (!of_have_populated_dt())
		pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;

	err = pxa_camera_init_videobuf2(pcdev);
	if (err)
		goto exit_free_v4l2dev;
2455

2456 2457 2458 2459 2460 2461 2462
	if (pcdev->mclk) {
		v4l2_clk_name_i2c(clk_name, sizeof(clk_name),
				  pcdev->asd.match.i2c.adapter_id,
				  pcdev->asd.match.i2c.address);

		pcdev->mclk_clk = v4l2_clk_register(&pxa_camera_mclk_ops,
						    clk_name, NULL);
2463 2464 2465 2466
		if (IS_ERR(pcdev->mclk_clk)) {
			err = PTR_ERR(pcdev->mclk_clk);
			goto exit_free_v4l2dev;
		}
2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477
	}

	err = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier);
	if (err)
		goto exit_free_clk;

	return 0;
exit_free_clk:
	v4l2_clk_unregister(pcdev->mclk_clk);
exit_free_v4l2dev:
	v4l2_device_unregister(&pcdev->v4l2_dev);
2478
exit_free_dma:
2479
	dma_release_channel(pcdev->dma_chans[2]);
2480
exit_free_dma_u:
2481
	dma_release_channel(pcdev->dma_chans[1]);
2482
exit_free_dma_y:
2483
	dma_release_channel(pcdev->dma_chans[0]);
2484 2485 2486
	return err;
}

2487
static int pxa_camera_remove(struct platform_device *pdev)
2488
{
2489
	struct pxa_camera_dev *pcdev = dev_get_drvdata(&pdev->dev);
2490

2491
	pxa_camera_deactivate(pcdev);
2492 2493 2494
	dma_release_channel(pcdev->dma_chans[0]);
	dma_release_channel(pcdev->dma_chans[1]);
	dma_release_channel(pcdev->dma_chans[2]);
2495

2496 2497
	v4l2_clk_unregister(pcdev->mclk_clk);
	v4l2_device_unregister(&pcdev->v4l2_dev);
2498

2499
	dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
2500 2501 2502 2503

	return 0;
}

2504
static const struct dev_pm_ops pxa_camera_pm = {
2505 2506 2507 2508
	.suspend	= pxa_camera_suspend,
	.resume		= pxa_camera_resume,
};

2509 2510 2511 2512 2513 2514
static const struct of_device_id pxa_camera_of_match[] = {
	{ .compatible = "marvell,pxa270-qci", },
	{},
};
MODULE_DEVICE_TABLE(of, pxa_camera_of_match);

2515
static struct platform_driver pxa_camera_driver = {
2516
	.driver		= {
2517
		.name	= PXA_CAM_DRV_NAME,
2518
		.pm	= &pxa_camera_pm,
2519
		.of_match_table = of_match_ptr(pxa_camera_of_match),
2520 2521
	},
	.probe		= pxa_camera_probe,
2522
	.remove		= pxa_camera_remove,
2523 2524
};

2525
module_platform_driver(pxa_camera_driver);
2526 2527 2528 2529

MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
MODULE_LICENSE("GPL");
2530
MODULE_VERSION(PXA_CAM_VERSION);
2531
MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);