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coh901318.c 80.2 KB
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/*
 * driver/dma/coh901318.c
 *
 * Copyright (C) 2007-2009 ST-Ericsson
 * License terms: GNU General Public License (GPL) version 2
 * DMA driver for COH 901 318
 * Author: Per Friden <per.friden@stericsson.com>
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h> /* printk() */
#include <linux/fs.h> /* everything... */
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#include <linux/scatterlist.h>
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#include <linux/slab.h> /* kmalloc() */
#include <linux/dmaengine.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/irqreturn.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/debugfs.h>
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#include <linux/platform_data/dma-coh901318.h>
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#include <linux/of_dma.h>
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#include "coh901318.h"
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#include "dmaengine.h"
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#define COH901318_MOD32_MASK					(0x1F)
#define COH901318_WORD_MASK					(0xFFFFFFFF)
/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
#define COH901318_INT_STATUS1					(0x0000)
#define COH901318_INT_STATUS2					(0x0004)
/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
#define COH901318_TC_INT_STATUS1				(0x0008)
#define COH901318_TC_INT_STATUS2				(0x000C)
/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
#define COH901318_TC_INT_CLEAR1					(0x0010)
#define COH901318_TC_INT_CLEAR2					(0x0014)
/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
#define COH901318_RAW_TC_INT_STATUS1				(0x0018)
#define COH901318_RAW_TC_INT_STATUS2				(0x001C)
/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
#define COH901318_BE_INT_STATUS1				(0x0020)
#define COH901318_BE_INT_STATUS2				(0x0024)
/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
#define COH901318_BE_INT_CLEAR1					(0x0028)
#define COH901318_BE_INT_CLEAR2					(0x002C)
/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
#define COH901318_RAW_BE_INT_STATUS1				(0x0030)
#define COH901318_RAW_BE_INT_STATUS2				(0x0034)

/*
 * CX_CFG - Channel Configuration Registers 32bit (R/W)
 */
#define COH901318_CX_CFG					(0x0100)
#define COH901318_CX_CFG_SPACING				(0x04)
/* Channel enable activates tha dma job */
#define COH901318_CX_CFG_CH_ENABLE				(0x00000001)
#define COH901318_CX_CFG_CH_DISABLE				(0x00000000)
/* Request Mode */
#define COH901318_CX_CFG_RM_MASK				(0x00000006)
#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY			(0x0 << 1)
#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY			(0x1 << 1)
#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY			(0x1 << 1)
#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY		(0x3 << 1)
#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY		(0x3 << 1)
/* Linked channel request field. RM must == 11 */
#define COH901318_CX_CFG_LCRF_SHIFT				3
#define COH901318_CX_CFG_LCRF_MASK				(0x000001F8)
#define COH901318_CX_CFG_LCR_DISABLE				(0x00000000)
/* Terminal Counter Interrupt Request Mask */
#define COH901318_CX_CFG_TC_IRQ_ENABLE				(0x00000200)
#define COH901318_CX_CFG_TC_IRQ_DISABLE				(0x00000000)
/* Bus Error interrupt Mask */
#define COH901318_CX_CFG_BE_IRQ_ENABLE				(0x00000400)
#define COH901318_CX_CFG_BE_IRQ_DISABLE				(0x00000000)

/*
 * CX_STAT - Channel Status Registers 32bit (R/-)
 */
#define COH901318_CX_STAT					(0x0200)
#define COH901318_CX_STAT_SPACING				(0x04)
#define COH901318_CX_STAT_RBE_IRQ_IND				(0x00000008)
#define COH901318_CX_STAT_RTC_IRQ_IND				(0x00000004)
#define COH901318_CX_STAT_ACTIVE				(0x00000002)
#define COH901318_CX_STAT_ENABLED				(0x00000001)

/*
 * CX_CTRL - Channel Control Registers 32bit (R/W)
 */
#define COH901318_CX_CTRL					(0x0400)
#define COH901318_CX_CTRL_SPACING				(0x10)
/* Transfer Count Enable */
#define COH901318_CX_CTRL_TC_ENABLE				(0x00001000)
#define COH901318_CX_CTRL_TC_DISABLE				(0x00000000)
/* Transfer Count Value 0 - 4095 */
#define COH901318_CX_CTRL_TC_VALUE_MASK				(0x00000FFF)
/* Burst count */
#define COH901318_CX_CTRL_BURST_COUNT_MASK			(0x0000E000)
#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES			(0x7 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES			(0x6 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES			(0x5 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES			(0x4 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES			(0x3 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES			(0x2 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES			(0x1 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE			(0x0 << 13)
/* Source bus size  */
#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK			(0x00030000)
#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS			(0x2 << 16)
#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS			(0x1 << 16)
#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS			(0x0 << 16)
/* Source address increment */
#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE			(0x00040000)
#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE			(0x00000000)
/* Destination Bus Size */
#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK			(0x00180000)
#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS			(0x2 << 19)
#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS			(0x1 << 19)
#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS			(0x0 << 19)
/* Destination address increment */
#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE			(0x00200000)
#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE			(0x00000000)
/* Master Mode (Master2 is only connected to MSL) */
#define COH901318_CX_CTRL_MASTER_MODE_MASK			(0x00C00000)
#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W			(0x3 << 22)
#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W			(0x2 << 22)
#define COH901318_CX_CTRL_MASTER_MODE_M2RW			(0x1 << 22)
#define COH901318_CX_CTRL_MASTER_MODE_M1RW			(0x0 << 22)
/* Terminal Count flag to PER enable */
#define COH901318_CX_CTRL_TCP_ENABLE				(0x01000000)
#define COH901318_CX_CTRL_TCP_DISABLE				(0x00000000)
/* Terminal Count flags to CPU enable */
#define COH901318_CX_CTRL_TC_IRQ_ENABLE				(0x02000000)
#define COH901318_CX_CTRL_TC_IRQ_DISABLE			(0x00000000)
/* Hand shake to peripheral */
#define COH901318_CX_CTRL_HSP_ENABLE				(0x04000000)
#define COH901318_CX_CTRL_HSP_DISABLE				(0x00000000)
#define COH901318_CX_CTRL_HSS_ENABLE				(0x08000000)
#define COH901318_CX_CTRL_HSS_DISABLE				(0x00000000)
/* DMA mode */
#define COH901318_CX_CTRL_DDMA_MASK				(0x30000000)
#define COH901318_CX_CTRL_DDMA_LEGACY				(0x0 << 28)
#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1			(0x1 << 28)
#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2			(0x2 << 28)
/* Primary Request Data Destination */
#define COH901318_CX_CTRL_PRDD_MASK				(0x40000000)
#define COH901318_CX_CTRL_PRDD_DEST				(0x1 << 30)
#define COH901318_CX_CTRL_PRDD_SOURCE				(0x0 << 30)

/*
 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
 */
#define COH901318_CX_SRC_ADDR					(0x0404)
#define COH901318_CX_SRC_ADDR_SPACING				(0x10)

/*
 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
 */
#define COH901318_CX_DST_ADDR					(0x0408)
#define COH901318_CX_DST_ADDR_SPACING				(0x10)

/*
 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
 */
#define COH901318_CX_LNK_ADDR					(0x040C)
#define COH901318_CX_LNK_ADDR_SPACING				(0x10)
#define COH901318_CX_LNK_LINK_IMMEDIATE				(0x00000001)

/**
 * struct coh901318_params - parameters for DMAC configuration
 * @config: DMA config register
 * @ctrl_lli_last: DMA control register for the last lli in the list
 * @ctrl_lli: DMA control register for an lli
 * @ctrl_lli_chained: DMA control register for a chained lli
 */
struct coh901318_params {
	u32 config;
	u32 ctrl_lli_last;
	u32 ctrl_lli;
	u32 ctrl_lli_chained;
};

/**
 * struct coh_dma_channel - dma channel base
 * @name: ascii name of dma channel
 * @number: channel id number
 * @desc_nbr_max: number of preallocated descriptors
 * @priority_high: prio of channel, 0 low otherwise high.
 * @param: configuration parameters
 */
struct coh_dma_channel {
	const char name[32];
	const int number;
	const int desc_nbr_max;
	const int priority_high;
	const struct coh901318_params param;
};

/**
 * struct powersave - DMA power save structure
 * @lock: lock protecting data in this struct
 * @started_channels: bit mask indicating active dma channels
 */
struct powersave {
	spinlock_t lock;
	u64 started_channels;
};

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/* points out all dma slave channels.
 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 * Select all channels from A to B, end of list is marked with -1,-1
 */
static int dma_slave_channels[] = {
	U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
	U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};

/* points out all dma memcpy channels. */
static int dma_memcpy_channels[] = {
	U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};

#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
			COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
			COH901318_CX_CFG_LCR_DISABLE | \
			COH901318_CX_CFG_TC_IRQ_ENABLE | \
			COH901318_CX_CFG_BE_IRQ_ENABLE)
#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
			COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
			COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
			COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
			COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
			COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
			COH901318_CX_CTRL_MASTER_MODE_M1RW | \
			COH901318_CX_CTRL_TCP_DISABLE | \
			COH901318_CX_CTRL_TC_IRQ_DISABLE | \
			COH901318_CX_CTRL_HSP_DISABLE | \
			COH901318_CX_CTRL_HSS_DISABLE | \
			COH901318_CX_CTRL_DDMA_LEGACY | \
			COH901318_CX_CTRL_PRDD_SOURCE)
#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
			COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
			COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
			COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
			COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
			COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
			COH901318_CX_CTRL_MASTER_MODE_M1RW | \
			COH901318_CX_CTRL_TCP_DISABLE | \
			COH901318_CX_CTRL_TC_IRQ_DISABLE | \
			COH901318_CX_CTRL_HSP_DISABLE | \
			COH901318_CX_CTRL_HSS_DISABLE | \
			COH901318_CX_CTRL_DDMA_LEGACY | \
			COH901318_CX_CTRL_PRDD_SOURCE)
#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
			COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
			COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
			COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
			COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
			COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
			COH901318_CX_CTRL_MASTER_MODE_M1RW | \
			COH901318_CX_CTRL_TCP_DISABLE | \
			COH901318_CX_CTRL_TC_IRQ_ENABLE | \
			COH901318_CX_CTRL_HSP_DISABLE | \
			COH901318_CX_CTRL_HSS_DISABLE | \
			COH901318_CX_CTRL_DDMA_LEGACY | \
			COH901318_CX_CTRL_PRDD_SOURCE)

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static const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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	{
		.number = U300_DMA_MSL_TX_0,
		.name = "MSL TX 0",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_MSL_TX_1,
		.name = "MSL TX 1",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
	},
	{
		.number = U300_DMA_MSL_TX_2,
		.name = "MSL TX 2",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.desc_nbr_max = 10,
	},
	{
		.number = U300_DMA_MSL_TX_3,
		.name = "MSL TX 3",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
	},
	{
		.number = U300_DMA_MSL_TX_4,
		.name = "MSL TX 4",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
	},
	{
		.number = U300_DMA_MSL_TX_5,
		.name = "MSL TX 5",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_MSL_TX_6,
		.name = "MSL TX 6",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_MSL_RX_0,
		.name = "MSL RX 0",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_MSL_RX_1,
		.name = "MSL RX 1",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_MSL_RX_2,
		.name = "MSL RX 2",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_MSL_RX_3,
		.name = "MSL RX 3",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_MSL_RX_4,
		.name = "MSL RX 4",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_MSL_RX_5,
		.name = "MSL RX 5",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_MSL_RX_6,
		.name = "MSL RX 6",
		.priority_high = 0,
	},
	/*
	 * Don't set up device address, burst count or size of src
	 * or dst bus for this peripheral - handled by PrimeCell
	 * DMA extension.
	 */
	{
		.number = U300_DMA_MMCSD_RX_TX,
		.name = "MMCSD RX TX",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,

	},
	{
		.number = U300_DMA_MSPRO_TX,
		.name = "MSPRO TX",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_MSPRO_RX,
		.name = "MSPRO RX",
		.priority_high = 0,
	},
	/*
	 * Don't set up device address, burst count or size of src
	 * or dst bus for this peripheral - handled by PrimeCell
	 * DMA extension.
	 */
	{
		.number = U300_DMA_UART0_TX,
		.name = "UART0 TX",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
	},
	{
		.number = U300_DMA_UART0_RX,
		.name = "UART0 RX",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
	},
	{
		.number = U300_DMA_APEX_TX,
		.name = "APEX TX",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_APEX_RX,
		.name = "APEX RX",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_PCM_I2S0_TX,
		.name = "PCM I2S0 TX",
		.priority_high = 1,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
	},
	{
		.number = U300_DMA_PCM_I2S0_RX,
		.name = "PCM I2S0 RX",
		.priority_high = 1,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_PCM_I2S1_TX,
		.name = "PCM I2S1 TX",
		.priority_high = 1,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
	},
	{
		.number = U300_DMA_PCM_I2S1_RX,
		.name = "PCM I2S1 RX",
		.priority_high = 1,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_XGAM_CDI,
		.name = "XGAM CDI",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_XGAM_PDI,
		.name = "XGAM PDI",
		.priority_high = 0,
	},
	/*
	 * Don't set up device address, burst count or size of src
	 * or dst bus for this peripheral - handled by PrimeCell
	 * DMA extension.
	 */
	{
		.number = U300_DMA_SPI_TX,
		.name = "SPI TX",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
	},
	{
		.number = U300_DMA_SPI_RX,
		.name = "SPI RX",
		.priority_high = 0,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,

	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_0,
		.name = "GENERAL 00",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_1,
		.name = "GENERAL 01",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_2,
		.name = "GENERAL 02",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_3,
		.name = "GENERAL 03",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_4,
		.name = "GENERAL 04",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_5,
		.name = "GENERAL 05",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_6,
		.name = "GENERAL 06",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_7,
		.name = "GENERAL 07",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_8,
		.name = "GENERAL 08",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_UART1_TX,
		.name = "UART1 TX",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_UART1_RX,
		.name = "UART1 RX",
		.priority_high = 0,
	}
};

1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272
#define COHC_2_DEV(cohc) (&cohc->chan.dev->device)

#ifdef VERBOSE_DEBUG
#define COH_DBG(x) ({ if (1) x; 0; })
#else
#define COH_DBG(x) ({ if (0) x; 0; })
#endif

struct coh901318_desc {
	struct dma_async_tx_descriptor desc;
	struct list_head node;
	struct scatterlist *sg;
	unsigned int sg_len;
1273
	struct coh901318_lli *lli;
1274
	enum dma_transfer_direction dir;
1275
	unsigned long flags;
1276 1277
	u32 head_config;
	u32 head_ctrl;
1278 1279 1280 1281 1282
};

struct coh901318_base {
	struct device *dev;
	void __iomem *virtbase;
1283
	unsigned int irq;
1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308
	struct coh901318_pool pool;
	struct powersave pm;
	struct dma_device dma_slave;
	struct dma_device dma_memcpy;
	struct coh901318_chan *chans;
};

struct coh901318_chan {
	spinlock_t lock;
	int allocated;
	int id;
	int stopped;

	struct work_struct free_work;
	struct dma_chan chan;

	struct tasklet_struct tasklet;

	struct list_head active;
	struct list_head queue;
	struct list_head free;

	unsigned long nbr_active_done;
	unsigned long busy;

1309 1310
	u32 addr;
	u32 ctrl;
1311

1312 1313 1314 1315 1316 1317
	struct coh901318_base *base;
};

static void coh901318_list_print(struct coh901318_chan *cohc,
				 struct coh901318_lli *lli)
{
1318
	struct coh901318_lli *l = lli;
1319 1320
	int i = 0;

1321
	while (l) {
1322 1323
		dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src %pad"
			 ", dst %pad, link %pad virt_link_addr 0x%p\n",
1324 1325
			 i, l, l->control, &l->src_addr, &l->dst_addr,
			 &l->link_addr, l->virt_link_addr);
1326
		i++;
1327
		l = l->virt_link_addr;
1328 1329 1330 1331 1332 1333 1334 1335 1336 1337
	}
}

#ifdef CONFIG_DEBUG_FS

#define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)

static struct coh901318_base *debugfs_dma_base;
static struct dentry *dma_dentry;

1338
static ssize_t coh901318_debugfs_read(struct file *file, char __user *buf,
1339 1340 1341 1342 1343 1344
				  size_t count, loff_t *f_pos)
{
	u64 started_channels = debugfs_dma_base->pm.started_channels;
	int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
	char *dev_buf;
	char *tmp;
1345 1346
	int ret;
	int i;
1347 1348 1349

	dev_buf = kmalloc(4*1024, GFP_KERNEL);
	if (dev_buf == NULL)
1350
		return -ENOMEM;
1351 1352
	tmp = dev_buf;

1353
	tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
1354

1355 1356
	for (i = 0; i < U300_DMA_CHANNELS; i++) {
		if (started_channels & (1ULL << i))
1357
			tmp += sprintf(tmp, "channel %d\n", i);
1358
	}
1359 1360 1361

	tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);

1362 1363
	ret = simple_read_from_buffer(buf, count, f_pos, dev_buf, 
					tmp - dev_buf);
1364 1365 1366 1367 1368
	kfree(dev_buf);
	return ret;
}

static const struct file_operations coh901318_debugfs_status_operations = {
1369
	.open		= simple_open,
1370
	.read		= coh901318_debugfs_read,
1371
	.llseek		= default_llseek,
1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407
};


static int __init init_coh901318_debugfs(void)
{

	dma_dentry = debugfs_create_dir("dma", NULL);

	(void) debugfs_create_file("status",
				   S_IFREG | S_IRUGO,
				   dma_dentry, NULL,
				   &coh901318_debugfs_status_operations);
	return 0;
}

static void __exit exit_coh901318_debugfs(void)
{
	debugfs_remove_recursive(dma_dentry);
}

module_init(init_coh901318_debugfs);
module_exit(exit_coh901318_debugfs);
#else

#define COH901318_DEBUGFS_ASSIGN(x, y)

#endif /* CONFIG_DEBUG_FS */

static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
{
	return container_of(chan, struct coh901318_chan, chan);
}

static inline const struct coh901318_params *
cohc_chan_param(struct coh901318_chan *cohc)
{
1408
	return &chan_config[cohc->id].param;
1409 1410 1411 1412 1413
}

static inline const struct coh_dma_channel *
cohc_chan_conf(struct coh901318_chan *cohc)
{
1414
	return &chan_config[cohc->id];
1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482
}

static void enable_powersave(struct coh901318_chan *cohc)
{
	unsigned long flags;
	struct powersave *pm = &cohc->base->pm;

	spin_lock_irqsave(&pm->lock, flags);

	pm->started_channels &= ~(1ULL << cohc->id);

	spin_unlock_irqrestore(&pm->lock, flags);
}
static void disable_powersave(struct coh901318_chan *cohc)
{
	unsigned long flags;
	struct powersave *pm = &cohc->base->pm;

	spin_lock_irqsave(&pm->lock, flags);

	pm->started_channels |= (1ULL << cohc->id);

	spin_unlock_irqrestore(&pm->lock, flags);
}

static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
{
	int channel = cohc->id;
	void __iomem *virtbase = cohc->base->virtbase;

	writel(control,
	       virtbase + COH901318_CX_CTRL +
	       COH901318_CX_CTRL_SPACING * channel);
	return 0;
}

static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
{
	int channel = cohc->id;
	void __iomem *virtbase = cohc->base->virtbase;

	writel(conf,
	       virtbase + COH901318_CX_CFG +
	       COH901318_CX_CFG_SPACING*channel);
	return 0;
}


static int coh901318_start(struct coh901318_chan *cohc)
{
	u32 val;
	int channel = cohc->id;
	void __iomem *virtbase = cohc->base->virtbase;

	disable_powersave(cohc);

	val = readl(virtbase + COH901318_CX_CFG +
		    COH901318_CX_CFG_SPACING * channel);

	/* Enable channel */
	val |= COH901318_CX_CFG_CH_ENABLE;
	writel(val, virtbase + COH901318_CX_CFG +
	       COH901318_CX_CFG_SPACING * channel);

	return 0;
}

static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
1483
				      struct coh901318_lli *lli)
1484 1485 1486 1487 1488 1489 1490 1491
{
	int channel = cohc->id;
	void __iomem *virtbase = cohc->base->virtbase;

	BUG_ON(readl(virtbase + COH901318_CX_STAT +
		     COH901318_CX_STAT_SPACING*channel) &
	       COH901318_CX_STAT_ACTIVE);

1492
	writel(lli->src_addr,
1493 1494 1495
	       virtbase + COH901318_CX_SRC_ADDR +
	       COH901318_CX_SRC_ADDR_SPACING * channel);

1496
	writel(lli->dst_addr, virtbase +
1497 1498 1499
	       COH901318_CX_DST_ADDR +
	       COH901318_CX_DST_ADDR_SPACING * channel);

1500
	writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
1501 1502
	       COH901318_CX_LNK_ADDR_SPACING * channel);

1503
	writel(lli->control, virtbase + COH901318_CX_CTRL +
1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518
	       COH901318_CX_CTRL_SPACING * channel);

	return 0;
}

static struct coh901318_desc *
coh901318_desc_get(struct coh901318_chan *cohc)
{
	struct coh901318_desc *desc;

	if (list_empty(&cohc->free)) {
		/* alloc new desc because we're out of used ones
		 * TODO: alloc a pile of descs instead of just one,
		 * avoid many small allocations.
		 */
1519
		desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
1520 1521 1522
		if (desc == NULL)
			goto out;
		INIT_LIST_HEAD(&desc->node);
1523
		dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
1524 1525 1526 1527 1528 1529
	} else {
		/* Reuse an old desc. */
		desc = list_first_entry(&cohc->free,
					struct coh901318_desc,
					node);
		list_del(&desc->node);
1530 1531 1532 1533 1534
		/* Initialize it a bit so it's not insane */
		desc->sg = NULL;
		desc->sg_len = 0;
		desc->desc.callback = NULL;
		desc->desc.callback_param = NULL;
1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556
	}

 out:
	return desc;
}

static void
coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
{
	list_add_tail(&cohd->node, &cohc->free);
}

/* call with irq lock held */
static void
coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
{
	list_add_tail(&desc->node, &cohc->active);
}

static struct coh901318_desc *
coh901318_first_active_get(struct coh901318_chan *cohc)
{
1557 1558
	return list_first_entry_or_null(&cohc->active, struct coh901318_desc,
					node);
1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575
}

static void
coh901318_desc_remove(struct coh901318_desc *cohd)
{
	list_del(&cohd->node);
}

static void
coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
{
	list_add_tail(&desc->node, &cohc->queue);
}

static struct coh901318_desc *
coh901318_first_queued(struct coh901318_chan *cohc)
{
1576 1577
	return list_first_entry_or_null(&cohc->queue, struct coh901318_desc,
					node);
1578 1579
}

1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591
static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
{
	struct coh901318_lli *lli = in_lli;
	u32 bytes = 0;

	while (lli) {
		bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
		lli = lli->virt_link_addr;
	}
	return bytes;
}

1592
/*
1593 1594 1595 1596
 * Get the number of bytes left to transfer on this channel,
 * it is unwise to call this before stopping the channel for
 * absolute measures, but for a rough guess you can still call
 * it.
1597
 */
1598
static u32 coh901318_get_bytes_left(struct dma_chan *chan)
1599 1600
{
	struct coh901318_chan *cohc = to_coh901318_chan(chan);
1601 1602 1603 1604 1605
	struct coh901318_desc *cohd;
	struct list_head *pos;
	unsigned long flags;
	u32 left = 0;
	int i = 0;
1606 1607 1608

	spin_lock_irqsave(&cohc->lock, flags);

1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669
	/*
	 * If there are many queued jobs, we iterate and add the
	 * size of them all. We take a special look on the first
	 * job though, since it is probably active.
	 */
	list_for_each(pos, &cohc->active) {
		/*
		 * The first job in the list will be working on the
		 * hardware. The job can be stopped but still active,
		 * so that the transfer counter is somewhere inside
		 * the buffer.
		 */
		cohd = list_entry(pos, struct coh901318_desc, node);

		if (i == 0) {
			struct coh901318_lli *lli;
			dma_addr_t ladd;

			/* Read current transfer count value */
			left = readl(cohc->base->virtbase +
				     COH901318_CX_CTRL +
				     COH901318_CX_CTRL_SPACING * cohc->id) &
				COH901318_CX_CTRL_TC_VALUE_MASK;

			/* See if the transfer is linked... */
			ladd = readl(cohc->base->virtbase +
				     COH901318_CX_LNK_ADDR +
				     COH901318_CX_LNK_ADDR_SPACING *
				     cohc->id) &
				~COH901318_CX_LNK_LINK_IMMEDIATE;
			/* Single transaction */
			if (!ladd)
				continue;

			/*
			 * Linked transaction, follow the lli, find the
			 * currently processing lli, and proceed to the next
			 */
			lli = cohd->lli;
			while (lli && lli->link_addr != ladd)
				lli = lli->virt_link_addr;

			if (lli)
				lli = lli->virt_link_addr;

			/*
			 * Follow remaining lli links around to count the total
			 * number of bytes left
			 */
			left += coh901318_get_bytes_in_lli(lli);
		} else {
			left += coh901318_get_bytes_in_lli(cohd->lli);
		}
		i++;
	}

	/* Also count bytes in the queued jobs */
	list_for_each(pos, &cohc->queue) {
		cohd = list_entry(pos, struct coh901318_desc, node);
		left += coh901318_get_bytes_in_lli(cohd->lli);
	}
1670 1671 1672

	spin_unlock_irqrestore(&cohc->lock, flags);

1673
	return left;
1674 1675
}

1676 1677 1678 1679
/*
 * Pauses a transfer without losing data. Enables power save.
 * Use this function in conjunction with coh901318_resume.
 */
1680
static int coh901318_pause(struct dma_chan *chan)
1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693
{
	u32 val;
	unsigned long flags;
	struct coh901318_chan *cohc = to_coh901318_chan(chan);
	int channel = cohc->id;
	void __iomem *virtbase = cohc->base->virtbase;

	spin_lock_irqsave(&cohc->lock, flags);

	/* Disable channel in HW */
	val = readl(virtbase + COH901318_CX_CFG +
		    COH901318_CX_CFG_SPACING * channel);

L
Lucas De Marchi 已提交
1694
	/* Stopping infinite transfer */
1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719
	if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
	    (val & COH901318_CX_CFG_CH_ENABLE))
		cohc->stopped = 1;


	val &= ~COH901318_CX_CFG_CH_ENABLE;
	/* Enable twice, HW bug work around */
	writel(val, virtbase + COH901318_CX_CFG +
	       COH901318_CX_CFG_SPACING * channel);
	writel(val, virtbase + COH901318_CX_CFG +
	       COH901318_CX_CFG_SPACING * channel);

	/* Spin-wait for it to actually go inactive */
	while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
		     channel) & COH901318_CX_STAT_ACTIVE)
		cpu_relax();

	/* Check if we stopped an active job */
	if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
		   channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
		cohc->stopped = 1;

	enable_powersave(cohc);

	spin_unlock_irqrestore(&cohc->lock, flags);
1720
	return 0;
1721 1722
}

1723
/* Resumes a transfer that has been stopped via 300_dma_stop(..).
1724 1725
   Power save is handled.
*/
1726
static int coh901318_resume(struct dma_chan *chan)
1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750
{
	u32 val;
	unsigned long flags;
	struct coh901318_chan *cohc = to_coh901318_chan(chan);
	int channel = cohc->id;

	spin_lock_irqsave(&cohc->lock, flags);

	disable_powersave(cohc);

	if (cohc->stopped) {
		/* Enable channel in HW */
		val = readl(cohc->base->virtbase + COH901318_CX_CFG +
			    COH901318_CX_CFG_SPACING * channel);

		val |= COH901318_CX_CFG_CH_ENABLE;

		writel(val, cohc->base->virtbase + COH901318_CX_CFG +
		       COH901318_CX_CFG_SPACING*channel);

		cohc->stopped = 0;
	}

	spin_unlock_irqrestore(&cohc->lock, flags);
1751
	return 0;
1752 1753 1754 1755
}

bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
{
1756
	unsigned long ch_nr = (unsigned long) chan_id;
1757 1758 1759 1760 1761 1762 1763 1764

	if (ch_nr == to_coh901318_chan(chan)->id)
		return true;

	return false;
}
EXPORT_SYMBOL(coh901318_filter_id);

1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793
struct coh901318_filter_args {
	struct coh901318_base *base;
	unsigned int ch_nr;
};

static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data)
{
	struct coh901318_filter_args *args = data;

	if (&args->base->dma_slave == chan->device &&
	    args->ch_nr == to_coh901318_chan(chan)->id)
		return true;

	return false;
}

static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec,
					struct of_dma *ofdma)
{
	struct coh901318_filter_args args = {
		.base = ofdma->of_dma_data,
		.ch_nr = dma_spec->args[0],
	};
	dma_cap_mask_t cap;
	dma_cap_zero(cap);
	dma_cap_set(DMA_SLAVE, cap);

	return dma_request_channel(cap, coh901318_filter_base_and_id, &args);
}
1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809
/*
 * DMA channel allocation
 */
static int coh901318_config(struct coh901318_chan *cohc,
			    struct coh901318_params *param)
{
	unsigned long flags;
	const struct coh901318_params *p;
	int channel = cohc->id;
	void __iomem *virtbase = cohc->base->virtbase;

	spin_lock_irqsave(&cohc->lock, flags);

	if (param)
		p = param;
	else
1810
		p = cohc_chan_param(cohc);
1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839

	/* Clear any pending BE or TC interrupt */
	if (channel < 32) {
		writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
		writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
	} else {
		writel(1 << (channel - 32), virtbase +
		       COH901318_BE_INT_CLEAR2);
		writel(1 << (channel - 32), virtbase +
		       COH901318_TC_INT_CLEAR2);
	}

	coh901318_set_conf(cohc, p->config);
	coh901318_set_ctrl(cohc, p->ctrl_lli_last);

	spin_unlock_irqrestore(&cohc->lock, flags);

	return 0;
}

/* must lock when calling this function
 * start queued jobs, if any
 * TODO: start all queued jobs in one go
 *
 * Returns descriptor if queued job is started otherwise NULL.
 * If the queue is empty NULL is returned.
 */
static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
{
1840
	struct coh901318_desc *cohd;
1841

1842 1843
	/*
	 * start queued jobs, if any
1844 1845
	 * TODO: transmit all queued jobs in one go
	 */
1846
	cohd = coh901318_first_queued(cohc);
1847

1848
	if (cohd != NULL) {
1849
		/* Remove from queue */
1850
		coh901318_desc_remove(cohd);
1851 1852 1853
		/* initiate DMA job */
		cohc->busy = 1;

1854
		coh901318_desc_submit(cohc, cohd);
1855

1856 1857 1858
		/* Program the transaction head */
		coh901318_set_conf(cohc, cohd->head_config);
		coh901318_set_ctrl(cohc, cohd->head_ctrl);
1859
		coh901318_prep_linked_list(cohc, cohd->lli);
1860

1861
		/* start dma job on this channel */
1862 1863 1864 1865
		coh901318_start(cohc);

	}

1866
	return cohd;
1867 1868
}

1869 1870 1871 1872
/*
 * This tasklet is called from the interrupt handler to
 * handle each descriptor (DMA job) that is sent to a channel.
 */
1873 1874 1875 1876 1877
static void dma_tasklet(unsigned long data)
{
	struct coh901318_chan *cohc = (struct coh901318_chan *) data;
	struct coh901318_desc *cohd_fin;
	unsigned long flags;
1878
	struct dmaengine_desc_callback cb;
1879

1880 1881 1882 1883
	dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
		 " nbr_active_done %ld\n", __func__,
		 cohc->id, cohc->nbr_active_done);

1884 1885
	spin_lock_irqsave(&cohc->lock, flags);

1886
	/* get first active descriptor entry from list */
1887 1888 1889 1890 1891
	cohd_fin = coh901318_first_active_get(cohc);

	if (cohd_fin == NULL)
		goto err;

1892
	/* locate callback to client */
1893
	dmaengine_desc_get_callback(&cohd_fin->desc, &cb);
1894

1895
	/* sign this job as completed on the channel */
1896
	dma_cookie_complete(&cohd_fin->desc);
1897

1898
	/* release the lli allocation and remove the descriptor */
1899
	coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
1900

1901 1902 1903
	/* return desc to free-list */
	coh901318_desc_remove(cohd_fin);
	coh901318_desc_free(cohc, cohd_fin);
1904

1905
	spin_unlock_irqrestore(&cohc->lock, flags);
1906

1907
	/* Call the callback when we're done */
1908
	dmaengine_desc_callback_invoke(&cb, NULL);
1909

1910
	spin_lock_irqsave(&cohc->lock, flags);
1911

1912 1913 1914 1915 1916 1917 1918
	/*
	 * If another interrupt fired while the tasklet was scheduling,
	 * we don't get called twice, so we have this number of active
	 * counter that keep track of the number of IRQs expected to
	 * be handled for this channel. If there happen to be more than
	 * one IRQ to be ack:ed, we simply schedule this tasklet again.
	 */
1919
	cohc->nbr_active_done--;
1920
	if (cohc->nbr_active_done) {
1921 1922
		dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
			"came in while we were scheduling this tasklet\n");
1923 1924 1925 1926 1927 1928
		if (cohc_chan_conf(cohc)->priority_high)
			tasklet_hi_schedule(&cohc->tasklet);
		else
			tasklet_schedule(&cohc->tasklet);
	}

1929
	spin_unlock_irqrestore(&cohc->lock, flags);
1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941

	return;

 err:
	spin_unlock_irqrestore(&cohc->lock, flags);
	dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
}


/* called from interrupt context */
static void dma_tc_handle(struct coh901318_chan *cohc)
{
1942 1943 1944 1945 1946 1947 1948
	/*
	 * If the channel is not allocated, then we shouldn't have
	 * any TC interrupts on it.
	 */
	if (!cohc->allocated) {
		dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
			"unallocated channel\n");
1949
		return;
1950
	}
1951

1952
	spin_lock(&cohc->lock);
1953

1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964
	/*
	 * When we reach this point, at least one queue item
	 * should have been moved over from cohc->queue to
	 * cohc->active and run to completion, that is why we're
	 * getting a terminal count interrupt is it not?
	 * If you get this BUG() the most probable cause is that
	 * the individual nodes in the lli chain have IRQ enabled,
	 * so check your platform config for lli chain ctrl.
	 */
	BUG_ON(list_empty(&cohc->active));

1965 1966
	cohc->nbr_active_done++;

1967 1968 1969 1970
	/*
	 * This attempt to take a job from cohc->queue, put it
	 * into cohc->active and start it.
	 */
1971
	if (coh901318_queue_start(cohc) == NULL)
1972 1973
		cohc->busy = 0;

1974 1975
	spin_unlock(&cohc->lock);

1976 1977 1978 1979
	/*
	 * This tasklet will remove items from cohc->active
	 * and thus terminates them.
	 */
1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044
	if (cohc_chan_conf(cohc)->priority_high)
		tasklet_hi_schedule(&cohc->tasklet);
	else
		tasklet_schedule(&cohc->tasklet);
}


static irqreturn_t dma_irq_handler(int irq, void *dev_id)
{
	u32 status1;
	u32 status2;
	int i;
	int ch;
	struct coh901318_base *base  = dev_id;
	struct coh901318_chan *cohc;
	void __iomem *virtbase = base->virtbase;

	status1 = readl(virtbase + COH901318_INT_STATUS1);
	status2 = readl(virtbase + COH901318_INT_STATUS2);

	if (unlikely(status1 == 0 && status2 == 0)) {
		dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
		return IRQ_HANDLED;
	}

	/* TODO: consider handle IRQ in tasklet here to
	 *       minimize interrupt latency */

	/* Check the first 32 DMA channels for IRQ */
	while (status1) {
		/* Find first bit set, return as a number. */
		i = ffs(status1) - 1;
		ch = i;

		cohc = &base->chans[ch];
		spin_lock(&cohc->lock);

		/* Mask off this bit */
		status1 &= ~(1 << i);
		/* Check the individual channel bits */
		if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
			dev_crit(COHC_2_DEV(cohc),
				 "DMA bus error on channel %d!\n", ch);
			BUG_ON(1);
			/* Clear BE interrupt */
			__set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
		} else {
			/* Caused by TC, really? */
			if (unlikely(!test_bit(i, virtbase +
					       COH901318_TC_INT_STATUS1))) {
				dev_warn(COHC_2_DEV(cohc),
					 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
				/* Clear TC interrupt */
				BUG_ON(1);
				__set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
			} else {
				/* Enable powersave if transfer has finished */
				if (!(readl(virtbase + COH901318_CX_STAT +
					    COH901318_CX_STAT_SPACING*ch) &
				      COH901318_CX_STAT_ENABLED)) {
					enable_powersave(cohc);
				}

				/* Must clear TC interrupt before calling
				 * dma_tc_handle
2045
				 * in case tc_handle initiate a new dma job
2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089
				 */
				__set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);

				dma_tc_handle(cohc);
			}
		}
		spin_unlock(&cohc->lock);
	}

	/* Check the remaining 32 DMA channels for IRQ */
	while (status2) {
		/* Find first bit set, return as a number. */
		i = ffs(status2) - 1;
		ch = i + 32;
		cohc = &base->chans[ch];
		spin_lock(&cohc->lock);

		/* Mask off this bit */
		status2 &= ~(1 << i);
		/* Check the individual channel bits */
		if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
			dev_crit(COHC_2_DEV(cohc),
				 "DMA bus error on channel %d!\n", ch);
			/* Clear BE interrupt */
			BUG_ON(1);
			__set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
		} else {
			/* Caused by TC, really? */
			if (unlikely(!test_bit(i, virtbase +
					       COH901318_TC_INT_STATUS2))) {
				dev_warn(COHC_2_DEV(cohc),
					 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
				/* Clear TC interrupt */
				__set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
				BUG_ON(1);
			} else {
				/* Enable powersave if transfer has finished */
				if (!(readl(virtbase + COH901318_CX_STAT +
					    COH901318_CX_STAT_SPACING*ch) &
				      COH901318_CX_STAT_ENABLED)) {
					enable_powersave(cohc);
				}
				/* Must clear TC interrupt before calling
				 * dma_tc_handle
2090
				 * in case tc_handle initiate a new dma job
2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102
				 */
				__set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);

				dma_tc_handle(cohc);
			}
		}
		spin_unlock(&cohc->lock);
	}

	return IRQ_HANDLED;
}

2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153
static int coh901318_terminate_all(struct dma_chan *chan)
{
	unsigned long flags;
	struct coh901318_chan *cohc = to_coh901318_chan(chan);
	struct coh901318_desc *cohd;
	void __iomem *virtbase = cohc->base->virtbase;

	/* The remainder of this function terminates the transfer */
	coh901318_pause(chan);
	spin_lock_irqsave(&cohc->lock, flags);

	/* Clear any pending BE or TC interrupt */
	if (cohc->id < 32) {
		writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
		writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
	} else {
		writel(1 << (cohc->id - 32), virtbase +
		       COH901318_BE_INT_CLEAR2);
		writel(1 << (cohc->id - 32), virtbase +
		       COH901318_TC_INT_CLEAR2);
	}

	enable_powersave(cohc);

	while ((cohd = coh901318_first_active_get(cohc))) {
		/* release the lli allocation*/
		coh901318_lli_free(&cohc->base->pool, &cohd->lli);

		/* return desc to free-list */
		coh901318_desc_remove(cohd);
		coh901318_desc_free(cohc, cohd);
	}

	while ((cohd = coh901318_first_queued(cohc))) {
		/* release the lli allocation*/
		coh901318_lli_free(&cohc->base->pool, &cohd->lli);

		/* return desc to free-list */
		coh901318_desc_remove(cohd);
		coh901318_desc_free(cohc, cohd);
	}


	cohc->nbr_active_done = 0;
	cohc->busy = 0;

	spin_unlock_irqrestore(&cohc->lock, flags);

	return 0;
}

2154 2155 2156
static int coh901318_alloc_chan_resources(struct dma_chan *chan)
{
	struct coh901318_chan	*cohc = to_coh901318_chan(chan);
2157
	unsigned long flags;
2158 2159 2160 2161 2162 2163 2164

	dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
		 __func__, cohc->id);

	if (chan->client_count > 1)
		return -EBUSY;

2165 2166
	spin_lock_irqsave(&cohc->lock, flags);

2167 2168 2169
	coh901318_config(cohc, NULL);

	cohc->allocated = 1;
2170
	dma_cookie_init(chan);
2171

2172 2173
	spin_unlock_irqrestore(&cohc->lock, flags);

2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195
	return 1;
}

static void
coh901318_free_chan_resources(struct dma_chan *chan)
{
	struct coh901318_chan	*cohc = to_coh901318_chan(chan);
	int channel = cohc->id;
	unsigned long flags;

	spin_lock_irqsave(&cohc->lock, flags);

	/* Disable HW */
	writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
	       COH901318_CX_CFG_SPACING*channel);
	writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
	       COH901318_CX_CTRL_SPACING*channel);

	cohc->allocated = 0;

	spin_unlock_irqrestore(&cohc->lock, flags);

2196
	coh901318_terminate_all(chan);
2197 2198 2199 2200 2201 2202 2203 2204 2205 2206
}


static dma_cookie_t
coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
{
	struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
						   desc);
	struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
	unsigned long flags;
2207
	dma_cookie_t cookie;
2208 2209

	spin_lock_irqsave(&cohc->lock, flags);
2210
	cookie = dma_cookie_assign(tx);
2211 2212 2213 2214 2215

	coh901318_desc_queue(cohc, cohd);

	spin_unlock_irqrestore(&cohc->lock, flags);

2216
	return cookie;
2217 2218 2219 2220 2221 2222
}

static struct dma_async_tx_descriptor *
coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
		      size_t size, unsigned long flags)
{
2223
	struct coh901318_lli *lli;
2224 2225 2226 2227 2228
	struct coh901318_desc *cohd;
	unsigned long flg;
	struct coh901318_chan *cohc = to_coh901318_chan(chan);
	int lli_len;
	u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
2229
	int ret;
2230 2231 2232 2233

	spin_lock_irqsave(&cohc->lock, flg);

	dev_vdbg(COHC_2_DEV(cohc),
2234
		 "[%s] channel %d src %pad dest %pad size %zu\n",
2235
		 __func__, cohc->id, &src, &dest, size);
2236 2237 2238 2239 2240 2241 2242 2243 2244

	if (flags & DMA_PREP_INTERRUPT)
		/* Trigger interrupt after last lli */
		ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;

	lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
	if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
		lli_len++;

2245
	lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
2246

2247
	if (lli == NULL)
2248 2249
		goto err;

2250
	ret = coh901318_lli_fill_memcpy(
2251
		&cohc->base->pool, lli, src, size, dest,
2252 2253 2254 2255
		cohc_chan_param(cohc)->ctrl_lli_chained,
		ctrl_last);
	if (ret)
		goto err;
2256

2257
	COH_DBG(coh901318_list_print(cohc, lli));
2258

2259 2260
	/* Pick a descriptor to handle this transfer */
	cohd = coh901318_desc_get(cohc);
2261
	cohd->lli = lli;
2262
	cohd->flags = flags;
2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274
	cohd->desc.tx_submit = coh901318_tx_submit;

	spin_unlock_irqrestore(&cohc->lock, flg);

	return &cohd->desc;
 err:
	spin_unlock_irqrestore(&cohc->lock, flg);
	return NULL;
}

static struct dma_async_tx_descriptor *
coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2275
			unsigned int sg_len, enum dma_transfer_direction direction,
2276
			unsigned long flags, void *context)
2277 2278
{
	struct coh901318_chan *cohc = to_coh901318_chan(chan);
2279
	struct coh901318_lli *lli;
2280
	struct coh901318_desc *cohd;
2281
	const struct coh901318_params *params;
2282 2283 2284 2285 2286 2287 2288
	struct scatterlist *sg;
	int len = 0;
	int size;
	int i;
	u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
	u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
	u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
2289
	u32 config;
2290
	unsigned long flg;
2291
	int ret;
2292 2293 2294

	if (!sgl)
		goto out;
2295
	if (sg_dma_len(sgl) == 0)
2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306
		goto out;

	spin_lock_irqsave(&cohc->lock, flg);

	dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
		 __func__, sg_len, direction);

	if (flags & DMA_PREP_INTERRUPT)
		/* Trigger interrupt after last lli */
		ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;

2307 2308
	params = cohc_chan_param(cohc);
	config = params->config;
2309 2310 2311 2312 2313
	/*
	 * Add runtime-specific control on top, make
	 * sure the bits you set per peripheral channel are
	 * cleared in the default config from the platform.
	 */
2314 2315 2316
	ctrl_chained |= cohc->ctrl;
	ctrl_last |= cohc->ctrl;
	ctrl |= cohc->ctrl;
2317

2318
	if (direction == DMA_MEM_TO_DEV) {
2319 2320 2321
		u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
			COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;

2322
		config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
2323 2324 2325
		ctrl_chained |= tx_flags;
		ctrl_last |= tx_flags;
		ctrl |= tx_flags;
2326
	} else if (direction == DMA_DEV_TO_MEM) {
2327 2328 2329
		u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
			COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;

2330
		config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356
		ctrl_chained |= rx_flags;
		ctrl_last |= rx_flags;
		ctrl |= rx_flags;
	} else
		goto err_direction;

	/* The dma only supports transmitting packages up to
	 * MAX_DMA_PACKET_SIZE. Calculate to total number of
	 * dma elemts required to send the entire sg list
	 */
	for_each_sg(sgl, sg, sg_len, i) {
		unsigned int factor;
		size = sg_dma_len(sg);

		if (size <= MAX_DMA_PACKET_SIZE) {
			len++;
			continue;
		}

		factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
		if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
			factor++;

		len += factor;
	}

2357
	pr_debug("Allocate %d lli:s for this transfer\n", len);
2358
	lli = coh901318_lli_alloc(&cohc->base->pool, len);
2359

2360
	if (lli == NULL)
2361 2362
		goto err_dma_alloc;

2363 2364
	/* initiate allocated lli list */
	ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
2365
				    cohc->addr,
2366 2367 2368 2369 2370 2371
				    ctrl_chained,
				    ctrl,
				    ctrl_last,
				    direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
	if (ret)
		goto err_lli_fill;
2372

2373

2374
	COH_DBG(coh901318_list_print(cohc, lli));
2375

2376 2377
	/* Pick a descriptor to handle this transfer */
	cohd = coh901318_desc_get(cohc);
2378 2379 2380 2381 2382 2383 2384
	cohd->head_config = config;
	/*
	 * Set the default head ctrl for the channel to the one from the
	 * lli, things may have changed due to odd buffer alignment
	 * etc.
	 */
	cohd->head_ctrl = lli->control;
2385 2386 2387
	cohd->dir = direction;
	cohd->flags = flags;
	cohd->desc.tx_submit = coh901318_tx_submit;
2388
	cohd->lli = lli;
2389

2390 2391 2392
	spin_unlock_irqrestore(&cohc->lock, flg);

	return &cohd->desc;
2393
 err_lli_fill:
2394 2395 2396 2397 2398 2399 2400 2401
 err_dma_alloc:
 err_direction:
	spin_unlock_irqrestore(&cohc->lock, flg);
 out:
	return NULL;
}

static enum dma_status
2402 2403
coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
		 struct dma_tx_state *txstate)
2404 2405
{
	struct coh901318_chan *cohc = to_coh901318_chan(chan);
2406
	enum dma_status ret;
2407

2408
	ret = dma_cookie_status(chan, cookie, txstate);
2409
	if (ret == DMA_COMPLETE || !txstate)
2410 2411
		return ret;

2412
	dma_set_residue(txstate, coh901318_get_bytes_left(chan));
2413

2414 2415
	if (ret == DMA_IN_PROGRESS && cohc->stopped)
		ret = DMA_PAUSED;
2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427

	return ret;
}

static void
coh901318_issue_pending(struct dma_chan *chan)
{
	struct coh901318_chan *cohc = to_coh901318_chan(chan);
	unsigned long flags;

	spin_lock_irqsave(&cohc->lock, flags);

2428 2429 2430 2431 2432 2433
	/*
	 * Busy means that pending jobs are already being processed,
	 * and then there is no point in starting the queue: the
	 * terminal count interrupt on the channel will take the next
	 * job on the queue and execute it anyway.
	 */
2434 2435 2436 2437 2438 2439
	if (!cohc->busy)
		coh901318_queue_start(cohc);

	spin_unlock_irqrestore(&cohc->lock, flags);
}

2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500
/*
 * Here we wrap in the runtime dma control interface
 */
struct burst_table {
	int burst_8bit;
	int burst_16bit;
	int burst_32bit;
	u32 reg;
};

static const struct burst_table burst_sizes[] = {
	{
		.burst_8bit = 64,
		.burst_16bit = 32,
		.burst_32bit = 16,
		.reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
	},
	{
		.burst_8bit = 48,
		.burst_16bit = 24,
		.burst_32bit = 12,
		.reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
	},
	{
		.burst_8bit = 32,
		.burst_16bit = 16,
		.burst_32bit = 8,
		.reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
	},
	{
		.burst_8bit = 16,
		.burst_16bit = 8,
		.burst_32bit = 4,
		.reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
	},
	{
		.burst_8bit = 8,
		.burst_16bit = 4,
		.burst_32bit = 2,
		.reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
	},
	{
		.burst_8bit = 4,
		.burst_16bit = 2,
		.burst_32bit = 1,
		.reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
	},
	{
		.burst_8bit = 2,
		.burst_16bit = 1,
		.burst_32bit = 0,
		.reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
	},
	{
		.burst_8bit = 1,
		.burst_16bit = 0,
		.burst_32bit = 0,
		.reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
	},
};

2501 2502
static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
					   struct dma_slave_config *config)
2503 2504 2505 2506 2507
{
	struct coh901318_chan *cohc = to_coh901318_chan(chan);
	dma_addr_t addr;
	enum dma_slave_buswidth addr_width;
	u32 maxburst;
2508
	u32 ctrl = 0;
2509 2510 2511
	int i = 0;

	/* We only support mem to per or per to mem transfers */
2512
	if (config->direction == DMA_DEV_TO_MEM) {
2513 2514 2515
		addr = config->src_addr;
		addr_width = config->src_addr_width;
		maxburst = config->src_maxburst;
2516
	} else if (config->direction == DMA_MEM_TO_DEV) {
2517 2518 2519 2520 2521
		addr = config->dst_addr;
		addr_width = config->dst_addr_width;
		maxburst = config->dst_maxburst;
	} else {
		dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
2522
		return -EINVAL;
2523 2524 2525 2526 2527 2528
	}

	dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
		addr_width);
	switch (addr_width)  {
	case DMA_SLAVE_BUSWIDTH_1_BYTE:
2529
		ctrl |=
2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540
			COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
			COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;

		while (i < ARRAY_SIZE(burst_sizes)) {
			if (burst_sizes[i].burst_8bit <= maxburst)
				break;
			i++;
		}

		break;
	case DMA_SLAVE_BUSWIDTH_2_BYTES:
2541
		ctrl |=
2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553
			COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
			COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;

		while (i < ARRAY_SIZE(burst_sizes)) {
			if (burst_sizes[i].burst_16bit <= maxburst)
				break;
			i++;
		}

		break;
	case DMA_SLAVE_BUSWIDTH_4_BYTES:
		/* Direction doesn't matter here, it's 32/32 bits */
2554
		ctrl |=
2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567
			COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
			COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;

		while (i < ARRAY_SIZE(burst_sizes)) {
			if (burst_sizes[i].burst_32bit <= maxburst)
				break;
			i++;
		}

		break;
	default:
		dev_err(COHC_2_DEV(cohc),
			"bad runtimeconfig: alien address width\n");
2568
		return -EINVAL;
2569 2570
	}

2571
	ctrl |= burst_sizes[i].reg;
2572 2573 2574 2575
	dev_dbg(COHC_2_DEV(cohc),
		"selected burst size %d bytes for address width %d bytes, maxburst %d\n",
		burst_sizes[i].burst_8bit, addr_width, maxburst);

2576 2577
	cohc->addr = addr;
	cohc->ctrl = ctrl;
2578 2579

	return 0;
2580 2581
}

2582 2583
static void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
				struct coh901318_base *base)
2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628
{
	int chans_i;
	int i = 0;
	struct coh901318_chan *cohc;

	INIT_LIST_HEAD(&dma->channels);

	for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
		for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
			cohc = &base->chans[i];

			cohc->base = base;
			cohc->chan.device = dma;
			cohc->id = i;

			/* TODO: do we really need this lock if only one
			 * client is connected to each channel?
			 */

			spin_lock_init(&cohc->lock);

			cohc->nbr_active_done = 0;
			cohc->busy = 0;
			INIT_LIST_HEAD(&cohc->free);
			INIT_LIST_HEAD(&cohc->active);
			INIT_LIST_HEAD(&cohc->queue);

			tasklet_init(&cohc->tasklet, dma_tasklet,
				     (unsigned long) cohc);

			list_add_tail(&cohc->chan.device_node,
				      &dma->channels);
		}
	}
}

static int __init coh901318_probe(struct platform_device *pdev)
{
	int err = 0;
	struct coh901318_base *base;
	int irq;
	struct resource *io;

	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!io)
2629
		return -ENODEV;
2630 2631

	/* Map DMA controller registers to virtual memory */
2632 2633 2634 2635 2636
	if (devm_request_mem_region(&pdev->dev,
				    io->start,
				    resource_size(io),
				    pdev->dev.driver->name) == NULL)
		return -ENOMEM;
2637

2638 2639
	base = devm_kzalloc(&pdev->dev,
			    ALIGN(sizeof(struct coh901318_base), 4) +
2640
			    U300_DMA_CHANNELS *
2641 2642
			    sizeof(struct coh901318_chan),
			    GFP_KERNEL);
2643
	if (!base)
2644
		return -ENOMEM;
2645 2646 2647

	base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);

2648 2649 2650
	base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io));
	if (!base->virtbase)
		return -ENOMEM;
2651 2652 2653 2654 2655 2656 2657 2658 2659

	base->dev = &pdev->dev;
	spin_lock_init(&base->pm.lock);
	base->pm.started_channels = 0;

	COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
2660 2661
		return irq;

2662
	err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, 0,
2663 2664 2665
			       "coh901318", base);
	if (err)
		return err;
2666

2667 2668
	base->irq = irq;

2669 2670 2671 2672
	err = coh901318_pool_create(&base->pool, &pdev->dev,
				    sizeof(struct coh901318_lli),
				    32);
	if (err)
2673
		return err;
2674 2675

	/* init channels for device transfers */
2676
	coh901318_base_init(&base->dma_slave, dma_slave_channels,
2677 2678 2679 2680 2681 2682 2683 2684
			    base);

	dma_cap_zero(base->dma_slave.cap_mask);
	dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);

	base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
	base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
	base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
2685
	base->dma_slave.device_tx_status = coh901318_tx_status;
2686
	base->dma_slave.device_issue_pending = coh901318_issue_pending;
2687 2688 2689 2690
	base->dma_slave.device_config = coh901318_dma_set_runtimeconfig;
	base->dma_slave.device_pause = coh901318_pause;
	base->dma_slave.device_resume = coh901318_resume;
	base->dma_slave.device_terminate_all = coh901318_terminate_all;
2691 2692 2693 2694 2695 2696 2697 2698
	base->dma_slave.dev = &pdev->dev;

	err = dma_async_device_register(&base->dma_slave);

	if (err)
		goto err_register_slave;

	/* init channels for memcpy */
2699
	coh901318_base_init(&base->dma_memcpy, dma_memcpy_channels,
2700 2701 2702 2703 2704 2705 2706 2707
			    base);

	dma_cap_zero(base->dma_memcpy.cap_mask);
	dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);

	base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
	base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
	base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
2708
	base->dma_memcpy.device_tx_status = coh901318_tx_status;
2709
	base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
2710 2711 2712 2713
	base->dma_memcpy.device_config = coh901318_dma_set_runtimeconfig;
	base->dma_memcpy.device_pause = coh901318_pause;
	base->dma_memcpy.device_resume = coh901318_resume;
	base->dma_memcpy.device_terminate_all = coh901318_terminate_all;
2714
	base->dma_memcpy.dev = &pdev->dev;
2715 2716 2717 2718
	/*
	 * This controller can only access address at even 32bit boundaries,
	 * i.e. 2^2
	 */
2719
	base->dma_memcpy.copy_align = DMAENGINE_ALIGN_4_BYTES;
2720 2721 2722 2723 2724
	err = dma_async_device_register(&base->dma_memcpy);

	if (err)
		goto err_register_memcpy;

2725 2726 2727 2728 2729
	err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate,
					 base);
	if (err)
		goto err_register_of_dma;

2730
	platform_set_drvdata(pdev, base);
2731 2732
	dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%p\n",
		base->virtbase);
2733 2734 2735

	return err;

2736 2737
 err_register_of_dma:
	dma_async_device_unregister(&base->dma_memcpy);
2738 2739 2740 2741 2742 2743
 err_register_memcpy:
	dma_async_device_unregister(&base->dma_slave);
 err_register_slave:
	coh901318_pool_destroy(&base->pool);
	return err;
}
2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758
static void coh901318_base_remove(struct coh901318_base *base, const int *pick_chans)
{
	int chans_i;
	int i = 0;
	struct coh901318_chan *cohc;

	for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
		for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
			cohc = &base->chans[i];

			tasklet_kill(&cohc->tasklet);
		}
	}

}
2759

2760
static int coh901318_remove(struct platform_device *pdev)
2761 2762 2763
{
	struct coh901318_base *base = platform_get_drvdata(pdev);

2764 2765
	devm_free_irq(&pdev->dev, base->irq, base);

2766 2767 2768
	coh901318_base_remove(base, dma_slave_channels);
	coh901318_base_remove(base, dma_memcpy_channels);

2769
	of_dma_controller_free(pdev->dev.of_node);
2770 2771 2772 2773 2774 2775
	dma_async_device_unregister(&base->dma_memcpy);
	dma_async_device_unregister(&base->dma_slave);
	coh901318_pool_destroy(&base->pool);
	return 0;
}

2776 2777 2778 2779
static const struct of_device_id coh901318_dt_match[] = {
	{ .compatible = "stericsson,coh901318" },
	{},
};
2780 2781

static struct platform_driver coh901318_driver = {
2782
	.remove = coh901318_remove,
2783 2784
	.driver = {
		.name	= "coh901318",
2785
		.of_match_table = coh901318_dt_match,
2786 2787 2788
	},
};

2789
static int __init coh901318_init(void)
2790 2791 2792
{
	return platform_driver_probe(&coh901318_driver, coh901318_probe);
}
2793
subsys_initcall(coh901318_init);
2794

2795
static void __exit coh901318_exit(void)
2796 2797 2798 2799 2800 2801 2802
{
	platform_driver_unregister(&coh901318_driver);
}
module_exit(coh901318_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Per Friden");
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