smsc-ircc2.c 77.3 KB
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/*********************************************************************
 *
 * Description:   Driver for the SMC Infrared Communications Controller
 * Status:        Experimental.
 * Author:        Daniele Peri (peri@csai.unipa.it)
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 * Created at:
 * Modified at:
 * Modified by:
 *
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 *     Copyright (c) 2002      Daniele Peri
 *     All Rights Reserved.
 *     Copyright (c) 2002      Jean Tourrilhes
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 *     Copyright (c) 2006      Linus Walleij
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 *
 *
 * Based on smc-ircc.c:
 *
 *     Copyright (c) 2001      Stefani Seibold
 *     Copyright (c) 1999-2001 Dag Brattli
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 *     Copyright (c) 1998-1999 Thomas Davis,
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 *
 *	and irport.c:
 *
 *     Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
 *
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 *
 *     This program is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of
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 *     the License, or (at your option) any later version.
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 *
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 *     This program is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 *     GNU General Public License for more details.
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 *
 *     You should have received a copy of the GNU General Public License
 *     along with this program; if not, write to the Free Software
 *     Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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 *     MA 02111-1307 USA
 *
 ********************************************************************/

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/rtnetlink.h>
#include <linux/serial_reg.h>
#include <linux/dma-mapping.h>
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#include <linux/pnp.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
#include <asm/dma.h>
#include <asm/byteorder.h>

#include <linux/spinlock.h>
#include <linux/pm.h>
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#ifdef CONFIG_PCI
#include <linux/pci.h>
#endif
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#include <net/irda/wrapper.h>
#include <net/irda/irda.h>
#include <net/irda/irda_device.h>

#include "smsc-ircc2.h"
#include "smsc-sio.h"

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MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
MODULE_LICENSE("GPL");

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static int smsc_nopnp = 1;
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module_param_named(nopnp, smsc_nopnp, bool, 0);
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MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
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#define DMA_INVAL 255
static int ircc_dma = DMA_INVAL;
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module_param(ircc_dma, int, 0);
MODULE_PARM_DESC(ircc_dma, "DMA channel");

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#define IRQ_INVAL 255
static int ircc_irq = IRQ_INVAL;
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module_param(ircc_irq, int, 0);
MODULE_PARM_DESC(ircc_irq, "IRQ line");

static int ircc_fir;
module_param(ircc_fir, int, 0);
MODULE_PARM_DESC(ircc_fir, "FIR Base Address");

static int ircc_sir;
module_param(ircc_sir, int, 0);
MODULE_PARM_DESC(ircc_sir, "SIR Base Address");

static int ircc_cfg;
module_param(ircc_cfg, int, 0);
MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");

static int ircc_transceiver;
module_param(ircc_transceiver, int, 0);
MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");

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/* Types */

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#ifdef CONFIG_PCI
struct smsc_ircc_subsystem_configuration {
	unsigned short vendor; /* PCI vendor ID */
	unsigned short device; /* PCI vendor ID */
	unsigned short subvendor; /* PCI subsystem vendor ID */
	unsigned short subdevice; /* PCI sybsystem device ID */
	unsigned short sir_io; /* I/O port for SIR */
	unsigned short fir_io; /* I/O port for FIR */
	unsigned char  fir_irq; /* FIR IRQ */
	unsigned char  fir_dma; /* FIR DMA */
	unsigned short cfg_base; /* I/O port for chip configuration */
	int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
	const char *name;	/* name shown as info */
};
#endif

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struct smsc_transceiver {
	char *name;
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	void (*set_for_speed)(int fir_base, u32 speed);
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	int  (*probe)(int fir_base);
};

struct smsc_chip {
	char *name;
	#if 0
	u8	type;
	#endif
	u16 flags;
	u8 devid;
	u8 rev;
};

struct smsc_chip_address {
	unsigned int cfg_base;
	unsigned int type;
};

/* Private data for each instance */
struct smsc_ircc_cb {
	struct net_device *netdev;     /* Yes! we are some kind of netdevice */
	struct net_device_stats stats;
	struct irlap_cb    *irlap; /* The link layer we are binded to */
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	chipio_t io;               /* IrDA controller information */
	iobuff_t tx_buff;          /* Transmit buffer */
	iobuff_t rx_buff;          /* Receive buffer */
	dma_addr_t tx_buff_dma;
	dma_addr_t rx_buff_dma;

	struct qos_info qos;       /* QoS capabilities for this device */

	spinlock_t lock;           /* For serializing operations */
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	__u32 new_speed;
	__u32 flags;               /* Interface flags */

	int tx_buff_offsets[10];   /* Offsets between frames in tx_buff */
	int tx_len;                /* Number of frames in tx_buff */

	int transceiver;
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	struct platform_device *pldev;
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};

/* Constants */

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#define SMSC_IRCC2_DRIVER_NAME			"smsc-ircc2"

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#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED	9600
#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER	1
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#define SMSC_IRCC2_C_NET_TIMEOUT		0
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#define SMSC_IRCC2_C_SIR_STOP			0

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static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;

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/* Prototypes */

static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
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static int  smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
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static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
static int  smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
static int  smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
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static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
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static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
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static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
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static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
#if SMSC_IRCC2_C_SIR_STOP
static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
#endif
static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
static int  smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
static int  smsc_ircc_net_open(struct net_device *dev);
static int  smsc_ircc_net_close(struct net_device *dev);
static int  smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
#if SMSC_IRCC2_C_NET_TIMEOUT
static void smsc_ircc_timeout(struct net_device *dev);
#endif
static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);

/* Probing */
static int __init smsc_ircc_look_for_chips(void);
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static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
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static int __init smsc_superio_fdc(unsigned short cfg_base);
static int __init smsc_superio_lpc(unsigned short cfg_base);
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#ifdef CONFIG_PCI
static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
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static void __init preconfigure_ali_port(struct pci_dev *dev,
					 unsigned short port);
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static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
						    unsigned short ircc_fir,
						    unsigned short ircc_sir,
						    unsigned char ircc_dma,
						    unsigned char ircc_irq);
#endif
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/* Transceivers specific functions */

static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
static int  smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
static int  smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
static int  smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);

/* Power Management */

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static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
static int smsc_ircc_resume(struct platform_device *dev);
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static struct platform_driver smsc_ircc_driver = {
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	.suspend	= smsc_ircc_suspend,
	.resume		= smsc_ircc_resume,
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	.driver		= {
		.name	= SMSC_IRCC2_DRIVER_NAME,
	},
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};
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/* Transceivers for SMSC-ircc */

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static struct smsc_transceiver smsc_transceivers[] =
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{
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	{ "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
	{ "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
	{ "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
	{ NULL, NULL }
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};
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#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
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/*  SMC SuperIO chipsets definitions */

#define	KEY55_1	0	/* SuperIO Configuration mode with Key <0x55> */
#define	KEY55_2	1	/* SuperIO Configuration mode with Key <0x55,0x55> */
#define	NoIRDA	2	/* SuperIO Chip has no IRDA Port */
#define	SIR	0	/* SuperIO Chip has only slow IRDA */
#define	FIR	4	/* SuperIO Chip has fast IRDA */
#define	SERx4	8	/* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */

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static struct smsc_chip __initdata fdc_chips_flat[] =
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{
	/* Base address 0x3f0 or 0x370 */
	{ "37C44",	KEY55_1|NoIRDA,		0x00, 0x00 }, /* This chip cannot be detected */
	{ "37C665GT",	KEY55_2|NoIRDA,		0x65, 0x01 },
	{ "37C665GT",	KEY55_2|NoIRDA,		0x66, 0x01 },
	{ "37C669",	KEY55_2|SIR|SERx4,	0x03, 0x02 },
	{ "37C669",	KEY55_2|SIR|SERx4,	0x04, 0x02 }, /* ID? */
	{ "37C78",	KEY55_2|NoIRDA,		0x78, 0x00 },
	{ "37N769",	KEY55_1|FIR|SERx4,	0x28, 0x00 },
	{ "37N869",	KEY55_1|FIR|SERx4,	0x29, 0x00 },
	{ NULL }
};

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static struct smsc_chip __initdata fdc_chips_paged[] =
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{
	/* Base address 0x3f0 or 0x370 */
	{ "37B72X",	KEY55_1|SIR|SERx4,	0x4c, 0x00 },
	{ "37B77X",	KEY55_1|SIR|SERx4,	0x43, 0x00 },
	{ "37B78X",	KEY55_1|SIR|SERx4,	0x44, 0x00 },
	{ "37B80X",	KEY55_1|SIR|SERx4,	0x42, 0x00 },
	{ "37C67X",	KEY55_1|FIR|SERx4,	0x40, 0x00 },
	{ "37C93X",	KEY55_2|SIR|SERx4,	0x02, 0x01 },
	{ "37C93XAPM",	KEY55_1|SIR|SERx4,	0x30, 0x01 },
	{ "37C93XFR",	KEY55_2|FIR|SERx4,	0x03, 0x01 },
	{ "37M707",	KEY55_1|SIR|SERx4,	0x42, 0x00 },
	{ "37M81X",	KEY55_1|SIR|SERx4,	0x4d, 0x00 },
	{ "37N958FR",	KEY55_1|FIR|SERx4,	0x09, 0x04 },
	{ "37N971",	KEY55_1|FIR|SERx4,	0x0a, 0x00 },
	{ "37N972",	KEY55_1|FIR|SERx4,	0x0b, 0x00 },
	{ NULL }
};

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static struct smsc_chip __initdata lpc_chips_flat[] =
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{
	/* Base address 0x2E or 0x4E */
	{ "47N227",	KEY55_1|FIR|SERx4,	0x5a, 0x00 },
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	{ "47N227",	KEY55_1|FIR|SERx4,	0x7a, 0x00 },
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	{ "47N267",	KEY55_1|FIR|SERx4,	0x5e, 0x00 },
	{ NULL }
};

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static struct smsc_chip __initdata lpc_chips_paged[] =
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{
	/* Base address 0x2E or 0x4E */
	{ "47B27X",	KEY55_1|SIR|SERx4,	0x51, 0x00 },
	{ "47B37X",	KEY55_1|SIR|SERx4,	0x52, 0x00 },
	{ "47M10X",	KEY55_1|SIR|SERx4,	0x59, 0x00 },
	{ "47M120",	KEY55_1|NoIRDA|SERx4,	0x5c, 0x00 },
	{ "47M13X",	KEY55_1|SIR|SERx4,	0x59, 0x00 },
	{ "47M14X",	KEY55_1|SIR|SERx4,	0x5f, 0x00 },
	{ "47N252",	KEY55_1|FIR|SERx4,	0x0e, 0x00 },
	{ "47S42X",	KEY55_1|SIR|SERx4,	0x57, 0x00 },
	{ NULL }
};

#define SMSCSIO_TYPE_FDC	1
#define SMSCSIO_TYPE_LPC	2
#define SMSCSIO_TYPE_FLAT	4
#define SMSCSIO_TYPE_PAGED	8

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static struct smsc_chip_address __initdata possible_addresses[] =
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{
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	{ 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
	{ 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
	{ 0xe0,  SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
	{ 0x2e,  SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
	{ 0x4e,  SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
	{ 0, 0 }
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};

/* Globals */

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static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
static unsigned short dev_count;
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static inline void register_bank(int iobase, int bank)
{
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        outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
               iobase + IRCC_MASTER);
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}

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/* PNP hotplug support */
static const struct pnp_device_id smsc_ircc_pnp_table[] = {
	{ .id = "SMCf010", .driver_data = 0 },
	/* and presumably others */
	{ }
};
MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
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static int pnp_driver_registered;

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#ifdef CONFIG_PNP
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static int __init smsc_ircc_pnp_probe(struct pnp_dev *dev,
				      const struct pnp_device_id *dev_id)
{
	unsigned int firbase, sirbase;
	u8 dma, irq;

	if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
	      pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
		return -EINVAL;

	sirbase = pnp_port_start(dev, 0);
	firbase = pnp_port_start(dev, 1);
	dma = pnp_dma(dev, 0);
	irq = pnp_irq(dev, 0);

	if (smsc_ircc_open(firbase, sirbase, dma, irq))
		return -ENODEV;

	return 0;
}

static struct pnp_driver smsc_ircc_pnp_driver = {
	.name		= "smsc-ircc2",
	.id_table	= smsc_ircc_pnp_table,
	.probe		= smsc_ircc_pnp_probe,
};
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#else /* CONFIG_PNP */
static struct pnp_driver smsc_ircc_pnp_driver;
#endif
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/*******************************************************************************
 *
 *
 * SMSC-ircc stuff
 *
 *
 *******************************************************************************/

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static int __init smsc_ircc_legacy_probe(void)
{
	int ret = 0;

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#ifdef CONFIG_PCI
	if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
		/* Ignore errors from preconfiguration */
		IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
	}
#endif

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	if (ircc_fir > 0 && ircc_sir > 0) {
		IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
		IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);

		if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
			ret = -ENODEV;
	} else {
		ret = -ENODEV;

		/* try user provided configuration register base address */
		if (ircc_cfg > 0) {
			IRDA_MESSAGE(" Overriding configuration address "
				     "0x%04x\n", ircc_cfg);
			if (!smsc_superio_fdc(ircc_cfg))
				ret = 0;
			if (!smsc_superio_lpc(ircc_cfg))
				ret = 0;
		}

		if (smsc_ircc_look_for_chips() > 0)
			ret = 0;
	}
	return ret;
}

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/*
 * Function smsc_ircc_init ()
 *
 *    Initialize chip. Just try to find out how many chips we are dealing with
 *    and where they are
 */
static int __init smsc_ircc_init(void)
{
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	int ret;
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	IRDA_DEBUG(1, "%s\n", __func__);
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	ret = platform_driver_register(&smsc_ircc_driver);
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	if (ret) {
		IRDA_ERROR("%s, Can't register driver!\n", driver_name);
		return ret;
	}

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	dev_count = 0;
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	if (smsc_nopnp || !pnp_platform_devices ||
	    ircc_cfg || ircc_fir || ircc_sir ||
	    ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
		ret = smsc_ircc_legacy_probe();
477
	} else {
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		if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
			pnp_driver_registered = 1;
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	}
481

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	if (ret) {
		if (pnp_driver_registered)
			pnp_unregister_driver(&smsc_ircc_pnp_driver);
485
		platform_driver_unregister(&smsc_ircc_driver);
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486
	}
487

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	return ret;
}

/*
 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
 *
 *    Try to open driver instance
 *
 */
static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
{
	struct smsc_ircc_cb *self;
	struct net_device *dev;
	int err;
502

503
	IRDA_DEBUG(1, "%s\n", __func__);
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	err = smsc_ircc_present(fir_base, sir_base);
506
	if (err)
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		goto err_out;
508

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	err = -ENOMEM;
510
	if (dev_count >= ARRAY_SIZE(dev_self)) {
511
	        IRDA_WARNING("%s(), too many devices!\n", __func__);
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		goto err_out1;
	}

	/*
	 *  Allocate new instance of the driver
	 */
	dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
	if (!dev) {
520
		IRDA_WARNING("%s() can't allocate net device\n", __func__);
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		goto err_out1;
	}

	dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
#if SMSC_IRCC2_C_NET_TIMEOUT
	dev->tx_timeout	     = smsc_ircc_timeout;
527
	dev->watchdog_timeo  = HZ * 2;  /* Allow enough time for speed change */
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#endif
	dev->open            = smsc_ircc_net_open;
	dev->stop            = smsc_ircc_net_close;
	dev->do_ioctl        = smsc_ircc_net_ioctl;
	dev->get_stats	     = smsc_ircc_net_get_stats;
533

534
	self = netdev_priv(dev);
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	self->netdev = dev;

	/* Make ifconfig display some details */
	dev->base_addr = self->io.fir_base = fir_base;
	dev->irq = self->io.irq = irq;

	/* Need to store self somewhere */
542
	dev_self[dev_count] = self;
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	spin_lock_init(&self->lock);

545
	self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
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	self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;

	self->rx_buff.head =
		dma_alloc_coherent(NULL, self->rx_buff.truesize,
				   &self->rx_buff_dma, GFP_KERNEL);
	if (self->rx_buff.head == NULL) {
		IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
			   driver_name);
		goto err_out2;
	}

	self->tx_buff.head =
		dma_alloc_coherent(NULL, self->tx_buff.truesize,
				   &self->tx_buff_dma, GFP_KERNEL);
	if (self->tx_buff.head == NULL) {
		IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
			   driver_name);
		goto err_out3;
	}

	memset(self->rx_buff.head, 0, self->rx_buff.truesize);
	memset(self->tx_buff.head, 0, self->tx_buff.truesize);

	self->rx_buff.in_frame = FALSE;
	self->rx_buff.state = OUTSIDE_FRAME;
	self->tx_buff.data = self->tx_buff.head;
	self->rx_buff.data = self->rx_buff.head;
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	smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
	smsc_ircc_setup_qos(self);
	smsc_ircc_init_chip(self);
577

578 579
	if (ircc_transceiver > 0  &&
	    ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
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		self->transceiver = ircc_transceiver;
	else
		smsc_ircc_probe_transceiver(self);

	err = register_netdev(self->netdev);
585
	if (err) {
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		IRDA_ERROR("%s, Network device registration failed!\n",
			   driver_name);
		goto err_out4;
	}

591 592 593 594 595 596
	self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
						      dev_count, NULL, 0);
	if (IS_ERR(self->pldev)) {
		err = PTR_ERR(self->pldev);
		goto err_out5;
	}
597
	platform_set_drvdata(self->pldev, self);
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	IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
600
	dev_count++;
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	return 0;
603

604 605 606
 err_out5:
	unregister_netdev(self->netdev);

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 err_out4:
	dma_free_coherent(NULL, self->tx_buff.truesize,
			  self->tx_buff.head, self->tx_buff_dma);
 err_out3:
	dma_free_coherent(NULL, self->rx_buff.truesize,
			  self->rx_buff.head, self->rx_buff_dma);
 err_out2:
	free_netdev(self->netdev);
615
	dev_self[dev_count] = NULL;
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 err_out1:
	release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
	release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
 err_out:
	return err;
}

/*
 * Function smsc_ircc_present(fir_base, sir_base)
 *
 *    Check the smsc-ircc chip presence
 *
 */
static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
{
	unsigned char low, high, chip, config, dma, irq, version;

	if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
			    driver_name)) {
		IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
636
			     __func__, fir_base);
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		goto out1;
	}

	if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
			    driver_name)) {
		IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
643
			     __func__, sir_base);
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		goto out2;
	}

	register_bank(fir_base, 3);

649 650 651 652 653
	high    = inb(fir_base + IRCC_ID_HIGH);
	low     = inb(fir_base + IRCC_ID_LOW);
	chip    = inb(fir_base + IRCC_CHIP_ID);
	version = inb(fir_base + IRCC_VERSION);
	config  = inb(fir_base + IRCC_INTERFACE);
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	dma     = config & IRCC_INTERFACE_DMA_MASK;
	irq     = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;

657
	if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
658
		IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
659
			     __func__, fir_base);
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		goto out3;
	}
	IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
		     "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
		     chip & 0x0f, version, fir_base, sir_base, dma, irq);

	return 0;
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 out3:
	release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
 out2:
	release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
 out1:
	return -ENODEV;
}

/*
 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
 *
 *    Setup I/O
 *
 */
682 683
static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
			       unsigned int fir_base, unsigned int sir_base,
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			       u8 dma, u8 irq)
{
	unsigned char config, chip_dma, chip_irq;

	register_bank(fir_base, 3);
689 690 691
	config = inb(fir_base + IRCC_INTERFACE);
	chip_dma = config & IRCC_INTERFACE_DMA_MASK;
	chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
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	self->io.fir_base  = fir_base;
	self->io.sir_base  = sir_base;
	self->io.fir_ext   = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
	self->io.sir_ext   = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
	self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
	self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;

700
	if (irq != IRQ_INVAL) {
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		if (irq != chip_irq)
			IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
				     driver_name, chip_irq, irq);
		self->io.irq = irq;
705
	} else
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		self->io.irq = chip_irq;
707

708
	if (dma != DMA_INVAL) {
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		if (dma != chip_dma)
			IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
				     driver_name, chip_dma, dma);
		self->io.dma = dma;
713
	} else
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		self->io.dma = chip_dma;

}

/*
 * Function smsc_ircc_setup_qos(self)
 *
 *    Setup qos
 *
 */
static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
{
	/* Initialize QoS for this device */
	irda_init_max_qos_capabilies(&self->qos);
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	self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
		IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);

	self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
	self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
	irda_qos_bits_to_value(&self->qos);
}

/*
 * Function smsc_ircc_init_chip(self)
 *
 *    Init chip
 *
 */
static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
{
745
	int iobase = self->io.fir_base;
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	register_bank(iobase, 0);
748 749
	outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
	outb(0x00, iobase + IRCC_MASTER);
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	register_bank(iobase, 1);
752
	outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
753
	     iobase + IRCC_SCE_CFGA);
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#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
756 757
	outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
	     iobase + IRCC_SCE_CFGB);
758
#else
759 760
	outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
	     iobase + IRCC_SCE_CFGB);
761
#endif
762 763
	(void) inb(iobase + IRCC_FIFO_THRESHOLD);
	outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
764

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	register_bank(iobase, 4);
766
	outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
767

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	register_bank(iobase, 0);
769
	outb(0, iobase + IRCC_LCR_A);
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	smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
772

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	/* Power on device */
774
	outb(0x00, iobase + IRCC_MASTER);
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}

/*
 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
 *
 *    Process IOCTL commands for this device
 *
 */
static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
	struct if_irda_req *irq = (struct if_irda_req *) rq;
	struct smsc_ircc_cb *self;
	unsigned long flags;
	int ret = 0;

	IRDA_ASSERT(dev != NULL, return -1;);

792
	self = netdev_priv(dev);
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	IRDA_ASSERT(self != NULL, return -1;);

796
	IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
797

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	switch (cmd) {
	case SIOCSBANDWIDTH: /* Set bandwidth */
		if (!capable(CAP_NET_ADMIN))
			ret = -EPERM;
                else {
			/* Make sure we are the only one touching
			 * self->io.speed and the hardware - Jean II */
			spin_lock_irqsave(&self->lock, flags);
			smsc_ircc_change_speed(self, irq->ifr_baudrate);
			spin_unlock_irqrestore(&self->lock, flags);
		}
		break;
	case SIOCSMEDIABUSY: /* Set media busy */
		if (!capable(CAP_NET_ADMIN)) {
			ret = -EPERM;
			break;
		}

		irda_device_set_media_busy(self->netdev, TRUE);
		break;
	case SIOCGRECEIVING: /* Check if we are receiving right now */
		irq->ifr_receiving = smsc_ircc_is_receiving(self);
		break;
	#if 0
	case SIOCSDTRRTS:
		if (!capable(CAP_NET_ADMIN)) {
			ret = -EPERM;
			break;
		}
		smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
		break;
	#endif
	default:
		ret = -EOPNOTSUPP;
	}
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	return ret;
}

static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
{
839
	struct smsc_ircc_cb *self = netdev_priv(dev);
840

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	return &self->stats;
}

#if SMSC_IRCC2_C_NET_TIMEOUT
/*
 * Function smsc_ircc_timeout (struct net_device *dev)
 *
 *    The networking timeout management.
 *
 */

static void smsc_ircc_timeout(struct net_device *dev)
{
854
	struct smsc_ircc_cb *self = netdev_priv(dev);
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	unsigned long flags;

	IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
		     dev->name, self->io.speed);
	spin_lock_irqsave(&self->lock, flags);
	smsc_ircc_sir_start(self);
	smsc_ircc_change_speed(self, self->io.speed);
	dev->trans_start = jiffies;
	netif_wake_queue(dev);
	spin_unlock_irqrestore(&self->lock, flags);
}
#endif

/*
 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
 *
 *    Transmits the current frame until FIFO is full, then
 *    waits until the next transmit interrupt, and continues until the
 *    frame is transmitted.
 */
int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
{
	struct smsc_ircc_cb *self;
	unsigned long flags;
	s32 speed;

881
	IRDA_DEBUG(1, "%s\n", __func__);
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	IRDA_ASSERT(dev != NULL, return 0;);
884

885
	self = netdev_priv(dev);
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	IRDA_ASSERT(self != NULL, return 0;);

	netif_stop_queue(dev);
889

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	/* Make sure test of self->io.speed & speed change are atomic */
	spin_lock_irqsave(&self->lock, flags);

	/* Check if we need to change the speed */
	speed = irda_get_next_speed(skb);
895
	if (speed != self->io.speed && speed != -1) {
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		/* Check for empty frame */
		if (!skb->len) {
			/*
			 * We send frames one by one in SIR mode (no
			 * pipelining), so at this point, if we were sending
			 * a previous frame, we just received the interrupt
			 * telling us it is finished (UART_IIR_THRI).
			 * Therefore, waiting for the transmitter to really
			 * finish draining the fifo won't take too long.
			 * And the interrupt handler is not expected to run.
			 * - Jean II */
			smsc_ircc_sir_wait_hw_transmitter_finish(self);
			smsc_ircc_change_speed(self, speed);
			spin_unlock_irqrestore(&self->lock, flags);
			dev_kfree_skb(skb);
			return 0;
		}
913
		self->new_speed = speed;
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	}

	/* Init tx buffer */
	self->tx_buff.data = self->tx_buff.head;

	/* Copy skb to tx_buff while wrapping, stuffing and making CRC */
920
	self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
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					   self->tx_buff.truesize);
922

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	self->stats.tx_bytes += self->tx_buff.len;

	/* Turn on transmit finished interrupt. Will fire immediately!  */
926
	outb(UART_IER_THRI, self->io.sir_base + UART_IER);
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	spin_unlock_irqrestore(&self->lock, flags);

	dev_kfree_skb(skb);
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	return 0;
}

/*
 * Function smsc_ircc_set_fir_speed (self, baud)
 *
 *    Change the speed of the device
 *
 */
static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
{
	int fir_base, ir_mode, ctrl, fast;

	IRDA_ASSERT(self != NULL, return;);
	fir_base = self->io.fir_base;

	self->io.speed = speed;

950
	switch (speed) {
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951
	default:
952
	case 576000:
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		ir_mode = IRCC_CFGA_IRDA_HDLC;
		ctrl = IRCC_CRC;
		fast = 0;
956
		IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__);
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		break;
	case 1152000:
		ir_mode = IRCC_CFGA_IRDA_HDLC;
		ctrl = IRCC_1152 | IRCC_CRC;
		fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
		IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
963
			   __func__);
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		break;
	case 4000000:
		ir_mode = IRCC_CFGA_IRDA_4PPM;
		ctrl = IRCC_CRC;
		fast = IRCC_LCR_A_FAST;
		IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
970
			   __func__);
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		break;
	}
	#if 0
	Now in tranceiver!
	/* This causes an interrupt */
	register_bank(fir_base, 0);
977
	outb((inb(fir_base + IRCC_LCR_A) &  0xbf) | fast, fir_base + IRCC_LCR_A);
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	#endif
979

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	register_bank(fir_base, 1);
981
	outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
982

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	register_bank(fir_base, 4);
984
	outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
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}

/*
 * Function smsc_ircc_fir_start(self)
 *
 *    Change the speed of the device
 *
 */
static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
{
	struct net_device *dev;
	int fir_base;

998
	IRDA_DEBUG(1, "%s\n", __func__);
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	IRDA_ASSERT(self != NULL, return;);
	dev = self->netdev;
	IRDA_ASSERT(dev != NULL, return;);

	fir_base = self->io.fir_base;

	/* Reset everything */

	/* Install FIR transmit handler */
1009
	dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
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	/* Clear FIFO */
1012
	outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
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	/* Enable interrupt */
1015
	/*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
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	register_bank(fir_base, 1);

1019
	/* Select the TX/RX interface */
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#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
1021 1022
	outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
	     fir_base + IRCC_SCE_CFGB);
1023
#else
1024 1025
	outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
	     fir_base + IRCC_SCE_CFGB);
1026
#endif
1027
	(void) inb(fir_base + IRCC_FIFO_THRESHOLD);
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	/* Enable SCE interrupts */
1030
	outb(0, fir_base + IRCC_MASTER);
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	register_bank(fir_base, 0);
1032 1033
	outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
	outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
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}

/*
 * Function smsc_ircc_fir_stop(self, baud)
 *
 *    Change the speed of the device
 *
 */
static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
{
	int fir_base;

1046
	IRDA_DEBUG(1, "%s\n", __func__);
1047

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	IRDA_ASSERT(self != NULL, return;);

	fir_base = self->io.fir_base;
	register_bank(fir_base, 0);
1052 1053
	/*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
	outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
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}


/*
 * Function smsc_ircc_change_speed(self, baud)
 *
 *    Change the speed of the device
 *
 * This function *must* be called with spinlock held, because it may
 * be called from the irq handler. - Jean II
 */
1065
static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
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{
	struct net_device *dev;
	int last_speed_was_sir;
1069

1070
	IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__, speed);
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	IRDA_ASSERT(self != NULL, return;);
	dev = self->netdev;

	last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;

	#if 0
	/* Temp Hack */
	speed= 1152000;
	self->io.speed = speed;
	last_speed_was_sir = 0;
1082
	smsc_ircc_fir_start(self);
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	#endif
1084

1085
	if (self->io.speed == 0)
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		smsc_ircc_sir_start(self);

	#if 0
1089
	if (!last_speed_was_sir) speed = self->io.speed;
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	#endif

1092 1093
	if (self->io.speed != speed)
		smsc_ircc_set_transceiver_for_speed(self, speed);
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	self->io.speed = speed;
1096

1097 1098
	if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
		if (!last_speed_was_sir) {
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			smsc_ircc_fir_stop(self);
			smsc_ircc_sir_start(self);
		}
1102
		smsc_ircc_set_sir_speed(self, speed);
1103 1104
	} else {
		if (last_speed_was_sir) {
1105
			#if SMSC_IRCC2_C_SIR_STOP
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			smsc_ircc_sir_stop(self);
			#endif
			smsc_ircc_fir_start(self);
		}
		smsc_ircc_set_fir_speed(self, speed);

		#if 0
		self->tx_buff.len = 10;
		self->tx_buff.data = self->tx_buff.head;
1115

1116
		smsc_ircc_dma_xmit(self, 4000);
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		#endif
		/* Be ready for incoming frames */
1119
		smsc_ircc_dma_receive(self);
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	}
1121

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	netif_wake_queue(dev);
}

/*
 * Function smsc_ircc_set_sir_speed (self, speed)
 *
 *    Set speed of IrDA port to specified baudrate
 *
 */
1131
void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
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{
1133
	int iobase;
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	int fcr;    /* FIFO control reg */
	int lcr;    /* Line control reg */
	int divisor;

1138
	IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__, speed);
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	IRDA_ASSERT(self != NULL, return;);
	iobase = self->io.sir_base;
1142

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	/* Update accounting for new speed */
	self->io.speed = speed;

	/* Turn off interrupts */
1147
	outb(0, iobase + UART_IER);
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1149
	divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1150

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	fcr = UART_FCR_ENABLE_FIFO;

1153
	/*
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	 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
	 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1156
	 * about this timeout since it will always be fast enough.
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	 */
1158 1159
	fcr |= self->io.speed < 38400 ?
		UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1160

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	/* IrDA ports use 8N1 */
	lcr = UART_LCR_WLEN8;
1163

1164 1165 1166 1167 1168
	outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
	outb(divisor & 0xff,      iobase + UART_DLL); /* Set speed */
	outb(divisor >> 8,	  iobase + UART_DLM);
	outb(lcr,		  iobase + UART_LCR); /* Set 8N1 */
	outb(fcr,		  iobase + UART_FCR); /* Enable FIFO's */
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	/* Turn on interrups */
1171
	outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
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1173
	IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__, speed);
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}


/*
 * Function smsc_ircc_hard_xmit_fir (skb, dev)
 *
 *    Transmit the frame!
 *
 */
static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
{
	struct smsc_ircc_cb *self;
	unsigned long flags;
	s32 speed;
	int mtt;

	IRDA_ASSERT(dev != NULL, return 0;);
1191
	self = netdev_priv(dev);
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	IRDA_ASSERT(self != NULL, return 0;);

	netif_stop_queue(dev);

	/* Make sure test of self->io.speed & speed change are atomic */
	spin_lock_irqsave(&self->lock, flags);

	/* Check if we need to change the speed after this frame */
	speed = irda_get_next_speed(skb);
1201
	if (speed != self->io.speed && speed != -1) {
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		/* Check for empty frame */
		if (!skb->len) {
			/* Note : you should make sure that speed changes
			 * are not going to corrupt any outgoing frame.
			 * Look at nsc-ircc for the gory details - Jean II */
1207
			smsc_ircc_change_speed(self, speed);
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			spin_unlock_irqrestore(&self->lock, flags);
			dev_kfree_skb(skb);
			return 0;
1211 1212 1213
		}

		self->new_speed = speed;
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	}
1215

1216
	skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
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	self->tx_buff.len = skb->len;
	self->tx_buff.data = self->tx_buff.head;
1220 1221

	mtt = irda_get_mtt(skb);
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	if (mtt) {
		int bofs;

1225
		/*
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		 * Compute how many BOFs (STA or PA's) we need to waste the
		 * min turn time given the speed of the link.
		 */
		bofs = mtt * (self->io.speed / 1000) / 8000;
		if (bofs > 4095)
			bofs = 4095;

1233
		smsc_ircc_dma_xmit(self, bofs);
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	} else {
		/* Transmit frame */
1236
		smsc_ircc_dma_xmit(self, 0);
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	}
1238

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	spin_unlock_irqrestore(&self->lock, flags);
	dev_kfree_skb(skb);

	return 0;
}

/*
1246
 * Function smsc_ircc_dma_xmit (self, bofs)
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 *
 *    Transmit data using DMA
 *
 */
1251
static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
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{
1253
	int iobase = self->io.fir_base;
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	u8 ctrl;

1256
	IRDA_DEBUG(3, "%s\n", __func__);
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#if 1
	/* Disable Rx */
	register_bank(iobase, 0);
1260
	outb(0x00, iobase + IRCC_LCR_B);
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#endif
	register_bank(iobase, 1);
1263 1264
	outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
	     iobase + IRCC_SCE_CFGB);
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	self->io.direction = IO_XMIT;

	/* Set BOF additional count for generating the min turn time */
	register_bank(iobase, 4);
1270 1271 1272
	outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
	ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
	outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
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	/* Set max Tx frame size */
1275 1276
	outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
	outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
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	/*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1279

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	/* Enable burst mode chip Tx DMA */
	register_bank(iobase, 1);
1282 1283
	outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
	     IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
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	/* Setup DMA controller (must be done after enabling chip DMA) */
	irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
		       DMA_TX_MODE);

	/* Enable interrupt */

	register_bank(iobase, 0);
1292 1293
	outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
	outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1294

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	/* Enable transmit */
1296
	outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
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}

/*
 * Function smsc_ircc_dma_xmit_complete (self)
 *
1302
 *    The transfer of a frame in finished. This function will only be called
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 *    by the interrupt handler
 *
 */
1306
static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
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{
1308 1309
	int iobase = self->io.fir_base;

1310
	IRDA_DEBUG(3, "%s\n", __func__);
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#if 0
	/* Disable Tx */
	register_bank(iobase, 0);
1314
	outb(0x00, iobase + IRCC_LCR_B);
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#endif
1316 1317 1318
	register_bank(iobase, 1);
	outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
	     iobase + IRCC_SCE_CFGB);
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	/* Check for underrun! */
	register_bank(iobase, 0);
1322
	if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
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		self->stats.tx_errors++;
		self->stats.tx_fifo_errors++;

		/* Reset error condition */
		register_bank(iobase, 0);
1328 1329
		outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
		outb(0x00, iobase + IRCC_MASTER);
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	} else {
		self->stats.tx_packets++;
1332
		self->stats.tx_bytes += self->tx_buff.len;
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	}

	/* Check if it's time to change the speed */
	if (self->new_speed) {
1337
		smsc_ircc_change_speed(self, self->new_speed);
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		self->new_speed = 0;
	}

	netif_wake_queue(self->netdev);
}

/*
 * Function smsc_ircc_dma_receive(self)
 *
 *    Get ready for receiving a frame. The device will initiate a DMA
 *    if it starts to receive a frame.
 *
 */
1351
static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
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{
1353
	int iobase = self->io.fir_base;
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#if 0
	/* Turn off chip DMA */
	register_bank(iobase, 1);
1357 1358
	outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
	     iobase + IRCC_SCE_CFGB);
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#endif
1360

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	/* Disable Tx */
	register_bank(iobase, 0);
1363
	outb(0x00, iobase + IRCC_LCR_B);
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	/* Turn off chip DMA */
	register_bank(iobase, 1);
1367 1368
	outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
	     iobase + IRCC_SCE_CFGB);
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	self->io.direction = IO_RECV;
	self->rx_buff.data = self->rx_buff.head;

	/* Set max Rx frame size */
	register_bank(iobase, 4);
1375 1376
	outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
	outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
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	/* Setup DMA controller */
	irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
		       DMA_RX_MODE);

	/* Enable burst mode chip Rx DMA */
	register_bank(iobase, 1);
1384 1385
	outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
	     IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
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	/* Enable interrupt */
	register_bank(iobase, 0);
1389 1390
	outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
	outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
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	/* Enable receiver */
	register_bank(iobase, 0);
1394
	outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1395
	     iobase + IRCC_LCR_B);
1396

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	return 0;
}

/*
1401
 * Function smsc_ircc_dma_receive_complete(self)
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 *
 *    Finished with receiving frames
 *
 */
1406
static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
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{
	struct sk_buff *skb;
	int len, msgcnt, lsr;
1410
	int iobase = self->io.fir_base;
1411

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	register_bank(iobase, 0);
1413

1414
	IRDA_DEBUG(3, "%s\n", __func__);
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#if 0
	/* Disable Rx */
	register_bank(iobase, 0);
1418
	outb(0x00, iobase + IRCC_LCR_B);
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#endif
	register_bank(iobase, 0);
1421 1422 1423
	outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
	lsr= inb(iobase + IRCC_LSR);
	msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
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1425
	IRDA_DEBUG(2, "%s: dma count = %d\n", __func__,
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		   get_dma_residue(self->io.dma));

	len = self->rx_buff.truesize - get_dma_residue(self->io.dma);

1430 1431
	/* Look for errors */
	if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
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		self->stats.rx_errors++;
1433 1434 1435 1436 1437 1438 1439 1440
		if (lsr & IRCC_LSR_FRAME_ERROR)
			self->stats.rx_frame_errors++;
		if (lsr & IRCC_LSR_CRC_ERROR)
			self->stats.rx_crc_errors++;
		if (lsr & IRCC_LSR_SIZE_ERROR)
			self->stats.rx_length_errors++;
		if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
			self->stats.rx_length_errors++;
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		return;
	}
1443

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	/* Remove CRC */
1445
	len -= self->io.speed < 4000000 ? 2 : 4;
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1447
	if (len < 2 || len > 2050) {
1448
		IRDA_WARNING("%s(), bogus len=%d\n", __func__, len);
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		return;
	}
1451
	IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len);
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1453 1454
	skb = dev_alloc_skb(len + 1);
	if (!skb) {
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		IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1456
			     __func__);
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		return;
1458
	}
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	/* Make sure IP header gets aligned */
1460
	skb_reserve(skb, 1);
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	memcpy(skb_put(skb, len), self->rx_buff.data, len);
	self->stats.rx_packets++;
	self->stats.rx_bytes += len;

	skb->dev = self->netdev;
1467
	skb_reset_mac_header(skb);
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	skb->protocol = htons(ETH_P_IRDA);
	netif_rx(skb);
}

/*
 * Function smsc_ircc_sir_receive (self)
 *
 *    Receive one frame from the infrared port
 *
 */
1478
static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
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{
	int boguscount = 0;
	int iobase;

	IRDA_ASSERT(self != NULL, return;);

	iobase = self->io.sir_base;

1487 1488 1489
	/*
	 * Receive all characters in Rx FIFO, unwrap and unstuff them.
         * async_unwrap_char will deliver all found frames
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	 */
	do {
1492
		async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1493
				  inb(iobase + UART_RX));
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		/* Make sure we don't stay here to long */
		if (boguscount++ > 32) {
1497
			IRDA_DEBUG(2, "%s(), breaking!\n", __func__);
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			break;
		}
1500
	} while (inb(iobase + UART_LSR) & UART_LSR_DR);
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}


/*
 * Function smsc_ircc_interrupt (irq, dev_id, regs)
 *
 *    An interrupt from the chip has arrived. Time to do some work
 *
 */
1510
static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
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{
1512 1513
	struct net_device *dev = dev_id;
	struct smsc_ircc_cb *self = netdev_priv(dev);
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	int iobase, iir, lcra, lsr;
	irqreturn_t ret = IRQ_NONE;

	/* Serialise the interrupt handler in various CPUs, stop Tx path */
1518
	spin_lock(&self->lock);
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	/* Check if we should use the SIR interrupt handler */
1521
	if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
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		ret = smsc_ircc_interrupt_sir(dev);
		goto irq_ret_unlock;
	}

	iobase = self->io.fir_base;

	register_bank(iobase, 0);
1529
	iir = inb(iobase + IRCC_IIR);
1530
	if (iir == 0)
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		goto irq_ret_unlock;
	ret = IRQ_HANDLED;

	/* Disable interrupts */
1535 1536 1537
	outb(0, iobase + IRCC_IER);
	lcra = inb(iobase + IRCC_LCR_A);
	lsr = inb(iobase + IRCC_LSR);
1538

1539
	IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__, iir);
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	if (iir & IRCC_IIR_EOM) {
		if (self->io.direction == IO_RECV)
1543
			smsc_ircc_dma_receive_complete(self);
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		else
1545
			smsc_ircc_dma_xmit_complete(self);
1546

1547
		smsc_ircc_dma_receive(self);
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	}

	if (iir & IRCC_IIR_ACTIVE_FRAME) {
1551
		/*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/
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	}

	/* Enable interrupts again */

	register_bank(iobase, 0);
1557
	outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
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 irq_ret_unlock:
	spin_unlock(&self->lock);
1561

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	return ret;
}

/*
1566
 * Function irport_interrupt_sir (irq, dev_id)
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 *
 *    Interrupt handler for SIR modes
 */
static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
{
1572
	struct smsc_ircc_cb *self = netdev_priv(dev);
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	int boguscount = 0;
	int iobase;
	int iir, lsr;

	/* Already locked comming here in smsc_ircc_interrupt() */
	/*spin_lock(&self->lock);*/

	iobase = self->io.sir_base;

1582
	iir = inb(iobase + UART_IIR) & UART_IIR_ID;
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	if (iir == 0)
		return IRQ_NONE;
	while (iir) {
		/* Clear interrupt */
1587
		lsr = inb(iobase + UART_LSR);
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1589
		IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1590
			    __func__, iir, lsr, iobase);
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		switch (iir) {
		case UART_IIR_RLSI:
1594
			IRDA_DEBUG(2, "%s(), RLSI\n", __func__);
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			break;
		case UART_IIR_RDI:
			/* Receive interrupt */
			smsc_ircc_sir_receive(self);
			break;
		case UART_IIR_THRI:
			if (lsr & UART_LSR_THRE)
				/* Transmitter ready for data */
				smsc_ircc_sir_write_wakeup(self);
			break;
		default:
			IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1607
				   __func__, iir);
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			break;
1609 1610
		}

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		/* Make sure we don't stay here to long */
		if (boguscount++ > 100)
			break;

1615
	        iir = inb(iobase + UART_IIR) & UART_IIR_ID;
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	}
	/*spin_unlock(&self->lock);*/
	return IRQ_HANDLED;
}


#if 0 /* unused */
/*
 * Function ircc_is_receiving (self)
 *
 *    Return TRUE is we are currently receiving a frame
 *
 */
static int ircc_is_receiving(struct smsc_ircc_cb *self)
{
	int status = FALSE;
	/* int iobase; */

1634
	IRDA_DEBUG(1, "%s\n", __func__);
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	IRDA_ASSERT(self != NULL, return FALSE;);

1638
	IRDA_DEBUG(0, "%s: dma count = %d\n", __func__,
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		   get_dma_residue(self->io.dma));

	status = (self->rx_buff.state != OUTSIDE_FRAME);
1642

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	return status;
}
#endif /* unused */

1647 1648 1649 1650 1651 1652 1653 1654
static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
{
	int error;

	error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
			    self->netdev->name, self->netdev);
	if (error)
		IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1655
			   __func__, self->io.irq, error);
1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686

	return error;
}

static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
{
	unsigned long flags;

	spin_lock_irqsave(&self->lock, flags);

	self->io.speed = 0;
	smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);

	spin_unlock_irqrestore(&self->lock, flags);
}

static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
{
	int iobase = self->io.fir_base;
	unsigned long flags;

	spin_lock_irqsave(&self->lock, flags);

	register_bank(iobase, 0);
	outb(0, iobase + IRCC_IER);
	outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
	outb(0x00, iobase + IRCC_MASTER);

	spin_unlock_irqrestore(&self->lock, flags);
}

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/*
 * Function smsc_ircc_net_open (dev)
 *
 *    Start the device
 *
 */
static int smsc_ircc_net_open(struct net_device *dev)
{
	struct smsc_ircc_cb *self;
	char hwname[16];

1699
	IRDA_DEBUG(1, "%s\n", __func__);
1700

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	IRDA_ASSERT(dev != NULL, return -1;);
1702
	self = netdev_priv(dev);
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	IRDA_ASSERT(self != NULL, return 0;);
1704

1705
	if (self->io.suspended) {
1706
		IRDA_DEBUG(0, "%s(), device is suspended\n", __func__);
1707 1708 1709
		return -EAGAIN;
	}

1710
	if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
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			(void *) dev)) {
		IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1713
			   __func__, self->io.irq);
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		return -EAGAIN;
	}

1717
	smsc_ircc_start_interrupts(self);
1718

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	/* Give self a hardware name */
	/* It would be cool to offer the chip revision here - Jean II */
	sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);

1723
	/*
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	 * Open new IrLAP layer instance, now that everything should be
1725
	 * initialized properly
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	 */
	self->irlap = irlap_open(dev, &self->qos, hwname);

	/*
	 * Always allocate the DMA channel after the IRQ,
	 * and clean up on failure.
	 */
	if (request_dma(self->io.dma, dev->name)) {
		smsc_ircc_net_close(dev);

		IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1737
			     __func__, self->io.dma);
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		return -EAGAIN;
	}
1740

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	netif_start_queue(dev);

	return 0;
}

/*
 * Function smsc_ircc_net_close (dev)
 *
 *    Stop the device
 *
 */
static int smsc_ircc_net_close(struct net_device *dev)
{
	struct smsc_ircc_cb *self;

1756
	IRDA_DEBUG(1, "%s\n", __func__);
1757

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	IRDA_ASSERT(dev != NULL, return -1;);
1759
	self = netdev_priv(dev);
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	IRDA_ASSERT(self != NULL, return 0;);
1761

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	/* Stop device */
	netif_stop_queue(dev);
1764

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	/* Stop and remove instance of IrLAP */
	if (self->irlap)
		irlap_close(self->irlap);
	self->irlap = NULL;

1770 1771 1772 1773 1774 1775
	smsc_ircc_stop_interrupts(self);

	/* if we are called from smsc_ircc_resume we don't have IRQ reserved */
	if (!self->io.suspended)
		free_irq(self->io.irq, dev);

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	disable_dma(self->io.dma);
	free_dma(self->io.dma);

	return 0;
}

1782
static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
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{
1784
	struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1785

1786
	if (!self->io.suspended) {
1787 1788 1789 1790 1791 1792 1793 1794 1795
		IRDA_DEBUG(1, "%s, Suspending\n", driver_name);

		rtnl_lock();
		if (netif_running(self->netdev)) {
			netif_device_detach(self->netdev);
			smsc_ircc_stop_interrupts(self);
			free_irq(self->io.irq, self->netdev);
			disable_dma(self->io.dma);
		}
1796
		self->io.suspended = 1;
1797
		rtnl_unlock();
1798
	}
1799 1800

	return 0;
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}

1803
static int smsc_ircc_resume(struct platform_device *dev)
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1804
{
1805
	struct smsc_ircc_cb *self = platform_get_drvdata(dev);
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1806

1807
	if (self->io.suspended) {
1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824
		IRDA_DEBUG(1, "%s, Waking up\n", driver_name);

		rtnl_lock();
		smsc_ircc_init_chip(self);
		if (netif_running(self->netdev)) {
			if (smsc_ircc_request_irq(self)) {
				/*
				 * Don't fail resume process, just kill this
				 * network interface
				 */
				unregister_netdevice(self->netdev);
			} else {
				enable_dma(self->io.dma);
				smsc_ircc_start_interrupts(self);
				netif_device_attach(self->netdev);
			}
		}
1825
		self->io.suspended = 0;
1826
		rtnl_unlock();
1827
	}
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	return 0;
}

/*
 * Function smsc_ircc_close (self)
 *
 *    Close driver instance
 *
 */
static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
{
1839
	IRDA_DEBUG(1, "%s\n", __func__);
L
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	IRDA_ASSERT(self != NULL, return -1;);

1843
	platform_device_unregister(self->pldev);
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	/* Remove netdevice */
	unregister_netdev(self->netdev);

1848
	smsc_ircc_stop_interrupts(self);
L
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1849 1850

	/* Release the PORTS that this driver is using */
1851
	IRDA_DEBUG(0, "%s(), releasing 0x%03x\n",  __func__,
L
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1852 1853 1854 1855
		   self->io.fir_base);

	release_region(self->io.fir_base, self->io.fir_ext);

1856
	IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
L
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1857 1858 1859 1860 1861 1862 1863
		   self->io.sir_base);

	release_region(self->io.sir_base, self->io.sir_ext);

	if (self->tx_buff.head)
		dma_free_coherent(NULL, self->tx_buff.truesize,
				  self->tx_buff.head, self->tx_buff_dma);
1864

L
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	if (self->rx_buff.head)
		dma_free_coherent(NULL, self->rx_buff.truesize,
				  self->rx_buff.head, self->rx_buff_dma);

	free_netdev(self->netdev);

	return 0;
}

static void __exit smsc_ircc_cleanup(void)
{
	int i;

1878
	IRDA_DEBUG(1, "%s\n", __func__);
L
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1879

1880
	for (i = 0; i < 2; i++) {
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1881 1882 1883
		if (dev_self[i])
			smsc_ircc_close(dev_self[i]);
	}
1884

B
Bjorn Helgaas 已提交
1885 1886 1887
	if (pnp_driver_registered)
		pnp_unregister_driver(&smsc_ircc_pnp_driver);

1888
	platform_driver_unregister(&smsc_ircc_driver);
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}

/*
 *	Start SIR operations
 *
 * This function *must* be called with spinlock held, because it may
 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
 */
void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
{
	struct net_device *dev;
	int fir_base, sir_base;

1902
	IRDA_DEBUG(3, "%s\n", __func__);
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1904
	IRDA_ASSERT(self != NULL, return;);
1905
	dev = self->netdev;
1906
	IRDA_ASSERT(dev != NULL, return;);
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	dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;

	fir_base = self->io.fir_base;
	sir_base = self->io.sir_base;

	/* Reset everything */
1913
	outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
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	#if SMSC_IRCC2_C_SIR_STOP
	/*smsc_ircc_sir_stop(self);*/
	#endif

	register_bank(fir_base, 1);
1920
	outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
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	/* Initialize UART */
1923 1924
	outb(UART_LCR_WLEN8, sir_base + UART_LCR);  /* Reset DLAB */
	outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1925

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	/* Turn on interrups */
1927
	outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
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1928

1929
	IRDA_DEBUG(3, "%s() - exit\n", __func__);
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1930

1931
	outb(0x00, fir_base + IRCC_MASTER);
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1932 1933 1934 1935 1936 1937 1938
}

#if SMSC_IRCC2_C_SIR_STOP
void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
{
	int iobase;

1939
	IRDA_DEBUG(3, "%s\n", __func__);
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	iobase = self->io.sir_base;

	/* Reset UART */
1943
	outb(0, iobase + UART_MCR);
1944

L
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	/* Turn off interrupts */
1946
	outb(0, iobase + UART_IER);
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}
#endif

/*
 * Function smsc_sir_write_wakeup (self)
 *
 *    Called by the SIR interrupt handler when there's room for more data.
 *    If we have more packets to send, we send them here.
 *
 */
static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
{
	int actual = 0;
	int iobase;
	int fcr;

	IRDA_ASSERT(self != NULL, return;);

1965
	IRDA_DEBUG(4, "%s\n", __func__);
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	iobase = self->io.sir_base;

	/* Finished with frame?  */
	if (self->tx_buff.len > 0)  {
		/* Write data left in transmit buffer */
1972
		actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
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				      self->tx_buff.data, self->tx_buff.len);
		self->tx_buff.data += actual;
		self->tx_buff.len  -= actual;
	} else {
1977

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	/*if (self->tx_buff.len ==0)  {*/
1979 1980 1981

		/*
		 *  Now serial buffer is almost free & we can start
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		 *  transmission of another packet. But first we must check
		 *  if we need to change the speed of the hardware
		 */
		if (self->new_speed) {
			IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1987
				   __func__, self->new_speed);
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			smsc_ircc_sir_wait_hw_transmitter_finish(self);
			smsc_ircc_change_speed(self, self->new_speed);
			self->new_speed = 0;
		} else {
			/* Tell network layer that we want more frames */
			netif_wake_queue(self->netdev);
		}
		self->stats.tx_packets++;

1997 1998 1999 2000 2001 2002 2003 2004
		if (self->io.speed <= 115200) {
			/*
			 * Reset Rx FIFO to make sure that all reflected transmit data
			 * is discarded. This is needed for half duplex operation
			 */
			fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
			fcr |= self->io.speed < 38400 ?
					UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
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2006
			outb(fcr, iobase + UART_FCR);
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2008 2009
			/* Turn on receive interrupts */
			outb(UART_IER_RDI, iobase + UART_IER);
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		}
	}
}

/*
 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
 *
 *    Fill Tx FIFO with transmit data
 *
 */
static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
{
	int actual = 0;
2023

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	/* Tx FIFO should be empty! */
2025
	if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
2026
		IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__);
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2027 2028
		return 0;
	}
2029

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2030
	/* Fill FIFO with current frame */
2031
	while (fifo_size-- > 0 && actual < len) {
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2032
		/* Transmit next byte */
2033
		outb(buf[actual], iobase + UART_TX);
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2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059
		actual++;
	}
	return actual;
}

/*
 * Function smsc_ircc_is_receiving (self)
 *
 *    Returns true is we are currently receiving data
 *
 */
static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
{
	return (self->rx_buff.state != OUTSIDE_FRAME);
}


/*
 * Function smsc_ircc_probe_transceiver(self)
 *
 *    Tries to find the used Transceiver
 *
 */
static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
{
	unsigned int	i;
2060

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2061
	IRDA_ASSERT(self != NULL, return;);
2062

2063 2064
	for (i = 0; smsc_transceivers[i].name != NULL; i++)
		if (smsc_transceivers[i].probe(self->io.fir_base)) {
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2065 2066
			IRDA_MESSAGE(" %s transceiver found\n",
				     smsc_transceivers[i].name);
2067
			self->transceiver= i + 1;
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			return;
		}
2070

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	IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
		     smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
2073

2074
	self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
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}


/*
 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
 *
 *    Set the transceiver according to the speed
 *
 */
static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
{
	unsigned int trx;
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	trx = self->transceiver;
2089 2090
	if (trx > 0)
		smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
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}

/*
 * Function smsc_ircc_wait_hw_transmitter_finish ()
 *
 *    Wait for the real end of HW transmission
 *
 * The UART is a strict FIFO, and we get called only when we have finished
 * pushing data to the FIFO, so the maximum amount of time we must wait
 * is only for the FIFO to drain out.
 *
 * We use a simple calibrated loop. We may need to adjust the loop
 * delay (udelay) to balance I/O traffic and latency. And we also need to
 * adjust the maximum timeout.
 * It would probably be better to wait for the proper interrupt,
 * but it doesn't seem to be available.
 *
 * We can't use jiffies or kernel timers because :
 * 1) We are called from the interrupt handler, which disable softirqs,
 * so jiffies won't be increased
 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
 * want to wait that long to detect stuck hardware.
 * Jean II
 */

static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
{
2118
	int iobase = self->io.sir_base;
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	int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
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	/* Calibrated busy loop */
2122
	while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
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		udelay(1);

2125
	if (count == 0)
2126
		IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__);
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}


/* PROBING
 *
2132 2133
 * REVISIT we can be told about the device by PNP, and should use that info
 * instead of probing hardware and creating a platform_device ...
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2134 2135 2136 2137
 */

static int __init smsc_ircc_look_for_chips(void)
{
2138
	struct smsc_chip_address *address;
2139
	char *type;
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2140
	unsigned int cfg_base, found;
2141

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2142 2143
	found = 0;
	address = possible_addresses;
2144

2145
	while (address->cfg_base) {
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2146
		cfg_base = address->cfg_base;
2147

2148
		/*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/
2149

2150
		if (address->type & SMSCSIO_TYPE_FDC) {
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			type = "FDC";
2152 2153 2154 2155 2156 2157 2158
			if (address->type & SMSCSIO_TYPE_FLAT)
				if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
					found++;

			if (address->type & SMSCSIO_TYPE_PAGED)
				if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
					found++;
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2159
		}
2160
		if (address->type & SMSCSIO_TYPE_LPC) {
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			type = "LPC";
2162 2163 2164 2165 2166 2167 2168
			if (address->type & SMSCSIO_TYPE_FLAT)
				if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
					found++;

			if (address->type & SMSCSIO_TYPE_PAGED)
				if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
					found++;
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2169 2170 2171 2172
		}
		address++;
	}
	return found;
2173
}
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/*
 * Function smsc_superio_flat (chip, base, type)
 *
 *    Try to get configuration of a smc SuperIO chip with flat register model
 *
 */
2181
static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
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2182 2183 2184 2185 2186
{
	unsigned short firbase, sirbase;
	u8 mode, dma, irq;
	int ret = -ENODEV;

2187
	IRDA_DEBUG(1, "%s\n", __func__);
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2188

2189
	if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
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2190 2191 2192
		return ret;

	outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2193
	mode = inb(cfgbase + 1);
2194

2195
	/*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/
2196

2197
	if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2198
		IRDA_WARNING("%s(): IrDA not enabled\n", __func__);
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	outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2201
	sirbase = inb(cfgbase + 1) << 2;
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2203
	/* FIR iobase */
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2204
	outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2205
	firbase = inb(cfgbase + 1) << 3;
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2206 2207 2208

	/* DMA */
	outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2209
	dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2210

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2211 2212
	/* IRQ */
	outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2213
	irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
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2215
	IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__, firbase, sirbase, dma, irq, mode);
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2217 2218
	if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
		ret = 0;
2219

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	/* Exit configuration */
	outb(SMSCSIO_CFGEXITKEY, cfgbase);

	return ret;
}

/*
 * Function smsc_superio_paged (chip, base, type)
 *
 *    Try  to get configuration of a smc SuperIO chip with paged register model
 *
 */
2232
static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
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2233 2234 2235
{
	unsigned short fir_io, sir_io;
	int ret = -ENODEV;
2236

2237
	IRDA_DEBUG(1, "%s\n", __func__);
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2239
	if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
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2240
		return ret;
2241

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	/* Select logical device (UART2) */
	outb(0x07, cfg_base);
	outb(0x05, cfg_base + 1);
2245

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	/* SIR iobase */
	outb(0x60, cfg_base);
2248
	sir_io = inb(cfg_base + 1) << 8;
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	outb(0x61, cfg_base);
	sir_io |= inb(cfg_base + 1);
2251

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	/* Read FIR base */
	outb(0x62, cfg_base);
	fir_io = inb(cfg_base + 1) << 8;
	outb(0x63, cfg_base);
	fir_io |= inb(cfg_base + 1);
	outb(0x2b, cfg_base); /* ??? */

2259 2260
	if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
		ret = 0;
2261

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	/* Exit configuration */
	outb(SMSCSIO_CFGEXITKEY, cfg_base);

	return ret;
}


2269
static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
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2270
{
2271
	IRDA_DEBUG(1, "%s\n", __func__);
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2272 2273

	outb(reg, cfg_base);
2274
	return inb(cfg_base) != reg ? -1 : 0;
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}

2277
static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
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2278
{
2279
	u8 devid, xdevid, rev;
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2280

2281
	IRDA_DEBUG(1, "%s\n", __func__);
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2282 2283 2284 2285 2286 2287 2288 2289 2290 2291

	/* Leave configuration */

	outb(SMSCSIO_CFGEXITKEY, cfg_base);

	if (inb(cfg_base) == SMSCSIO_CFGEXITKEY)	/* not a smc superio chip */
		return NULL;

	outb(reg, cfg_base);

2292
	xdevid = inb(cfg_base + 1);
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2293 2294 2295 2296 2297 2298 2299 2300 2301

	/* Enter configuration */

	outb(SMSCSIO_CFGACCESSKEY, cfg_base);

	#if 0
	if (smsc_access(cfg_base,0x55))	/* send second key and check */
		return NULL;
	#endif
2302

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2303 2304
	/* probe device ID */

2305
	if (smsc_access(cfg_base, reg))
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2306 2307
		return NULL;

2308
	devid = inb(cfg_base + 1);
2309

2310
	if (devid == 0 || devid == 0xff)	/* typical values for unused port */
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2311 2312 2313 2314
		return NULL;

	/* probe revision ID */

2315
	if (smsc_access(cfg_base, reg + 1))
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2316 2317
		return NULL;

2318
	rev = inb(cfg_base + 1);
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2319

2320
	if (rev >= 128)			/* i think this will make no sense */
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2321 2322
		return NULL;

2323
	if (devid == xdevid)		/* protection against false positives */
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2324 2325 2326 2327
		return NULL;

	/* Check for expected device ID; are there others? */

2328
	while (chip->devid != devid) {
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2329 2330 2331

		chip++;

2332
		if (chip->name == NULL)
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2333 2334 2335
			return NULL;
	}

2336 2337
	IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
		     devid, rev, cfg_base, type, chip->name);
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2338

2339
	if (chip->rev > rev) {
2340
		IRDA_MESSAGE("Revision higher than expected\n");
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2341 2342
		return NULL;
	}
2343

2344
	if (chip->flags & NoIRDA)
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2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355
		IRDA_MESSAGE("chipset does not support IRDA\n");

	return chip;
}

static int __init smsc_superio_fdc(unsigned short cfg_base)
{
	int ret = -1;

	if (!request_region(cfg_base, 2, driver_name)) {
		IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2356
			     __func__, cfg_base);
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	} else {
2358 2359
		if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
		    !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
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2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373
			ret =  0;

		release_region(cfg_base, 2);
	}

	return ret;
}

static int __init smsc_superio_lpc(unsigned short cfg_base)
{
	int ret = -1;

	if (!request_region(cfg_base, 2, driver_name)) {
		IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2374
			     __func__, cfg_base);
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2375
	} else {
2376 2377
		if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
		    !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
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			ret = 0;
2379

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2380 2381 2382 2383 2384
		release_region(cfg_base, 2);
	}
	return ret;
}

2385 2386 2387 2388 2389
/*
 * Look for some specific subsystem setups that need
 * pre-configuration not properly done by the BIOS (especially laptops)
 * This code is based in part on smcinit.c, tosh1800-smcinit.c
 * and tosh2450-smcinit.c. The table lists the device entries
2390 2391 2392 2393 2394 2395 2396 2397
 * for ISA bridges with an LPC (Low Pin Count) controller which
 * handles the communication with the SMSC device. After the LPC
 * controller is initialized through PCI, the SMSC device is initialized
 * through a dedicated port in the ISA port-mapped I/O area, this latter
 * area is used to configure the SMSC device with default
 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
 * used different sets of parameters and different control port
 * addresses making a subsystem device table necessary.
2398 2399 2400 2401
 */
#ifdef CONFIG_PCI
#define PCIID_VENDOR_INTEL 0x8086
#define PCIID_VENDOR_ALI 0x10b9
2402
static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422
	/*
	 * Subsystems needing entries:
	 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
	 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
	 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
	 */
	{
		/* Guessed entry */
		.vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
		.device = 0x24cc,
		.subvendor = 0x103c,
		.subdevice = 0x08bc,
		.sir_io = 0x02f8,
		.fir_io = 0x0130,
		.fir_irq = 0x05,
		.fir_dma = 0x03,
		.cfg_base = 0x004e,
		.preconfigure = preconfigure_through_82801,
		.name = "HP nx5000 family",
	},
2423 2424 2425 2426 2427
	{
		.vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
		.device = 0x24cc,
		.subvendor = 0x103c,
		.subdevice = 0x088c,
2428 2429
		/* Quite certain these are the same for nc8000 as for nc6000 */
		.sir_io = 0x02f8,
2430
		.fir_io = 0x0130,
2431
		.fir_irq = 0x05,
2432 2433 2434
		.fir_dma = 0x03,
		.cfg_base = 0x004e,
		.preconfigure = preconfigure_through_82801,
2435
		.name = "HP nc8000 family",
2436 2437 2438 2439 2440 2441 2442 2443
	},
	{
		.vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
		.device = 0x24cc,
		.subvendor = 0x103c,
		.subdevice = 0x0890,
		.sir_io = 0x02f8,
		.fir_io = 0x0130,
2444
		.fir_irq = 0x05,
2445 2446 2447
		.fir_dma = 0x03,
		.cfg_base = 0x004e,
		.preconfigure = preconfigure_through_82801,
2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462
		.name = "HP nc6000 family",
	},
	{
		.vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
		.device = 0x24cc,
		.subvendor = 0x0e11,
		.subdevice = 0x0860,
		/* I assume these are the same for x1000 as for the others */
		.sir_io = 0x02e8,
		.fir_io = 0x02f8,
		.fir_irq = 0x07,
		.fir_dma = 0x03,
		.cfg_base = 0x002e,
		.preconfigure = preconfigure_through_82801,
		.name = "Compaq x1000 family",
2463 2464
	},
	{
2465 2466
		/* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
		.vendor = PCIID_VENDOR_INTEL,
2467 2468
		.device = 0x24c0,
		.subvendor = 0x1179,
2469
		.subdevice = 0xffff, /* 0xffff is "any" */
2470 2471 2472 2473 2474 2475
		.sir_io = 0x03f8,
		.fir_io = 0x0130,
		.fir_irq = 0x07,
		.fir_dma = 0x01,
		.cfg_base = 0x002e,
		.preconfigure = preconfigure_through_82801,
2476
		.name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2477 2478 2479
	},
	{
		.vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */
2480
		.device = 0x248c,
2481
		.subvendor = 0x1179,
2482
		.subdevice = 0xffff, /* 0xffff is "any" */
2483 2484 2485 2486 2487 2488
		.sir_io = 0x03f8,
		.fir_io = 0x0130,
		.fir_irq = 0x03,
		.fir_dma = 0x03,
		.cfg_base = 0x002e,
		.preconfigure = preconfigure_through_82801,
2489
		.name = "Toshiba laptop with Intel 82801CAM ISA bridge",
2490 2491
	},
	{
2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507
		/* 82801DBM (ICH4-M) LPC Interface Bridge */
		.vendor = PCIID_VENDOR_INTEL,
		.device = 0x24cc,
		.subvendor = 0x1179,
		.subdevice = 0xffff, /* 0xffff is "any" */
		.sir_io = 0x03f8,
		.fir_io = 0x0130,
		.fir_irq = 0x03,
		.fir_dma = 0x03,
		.cfg_base = 0x002e,
		.preconfigure = preconfigure_through_82801,
		.name = "Toshiba laptop with Intel 8281DBM LPC bridge",
	},
	{
		/* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
		.vendor = PCIID_VENDOR_ALI,
2508 2509
		.device = 0x1533,
		.subvendor = 0x1179,
2510
		.subdevice = 0xffff, /* 0xffff is "any" */
2511 2512 2513 2514 2515 2516
		.sir_io = 0x02e8,
		.fir_io = 0x02f8,
		.fir_irq = 0x07,
		.fir_dma = 0x03,
		.cfg_base = 0x002e,
		.preconfigure = preconfigure_through_ali,
2517
		.name = "Toshiba laptop with ALi ISA bridge",
2518 2519 2520 2521 2522 2523
	},
	{ } // Terminator
};


/*
2524 2525
 * This sets up the basic SMSC parameters
 * (FIR port, SIR port, FIR DMA, FIR IRQ)
2526 2527
 * through the chip configuration port.
 */
2528 2529 2530
static int __init preconfigure_smsc_chip(struct
					 smsc_ircc_subsystem_configuration
					 *conf)
2531 2532 2533 2534 2535 2536 2537
{
	unsigned short iobase = conf->cfg_base;
	unsigned char tmpbyte;

	outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
	outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
	tmpbyte = inb(iobase +1); // Read device ID
2538 2539 2540
	IRDA_DEBUG(0,
		   "Detected Chip id: 0x%02x, setting up registers...\n",
		   tmpbyte);
2541 2542 2543 2544 2545 2546 2547 2548 2549

	/* Disable UART1 and set up SIR I/O port */
	outb(0x24, iobase);  // select CR24 - UART1 base addr
	outb(0x00, iobase + 1); // disable UART1
	outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase);  // select CR25 - UART2 base addr
	outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
	tmpbyte = inb(iobase + 1);
	if (tmpbyte != (conf->sir_io >> 2) ) {
		IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2550
		IRDA_WARNING("Try to supply ircc_cfg argument.\n");
2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585
		return -ENXIO;
	}

	/* Set up FIR IRQ channel for UART2 */
	outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
	tmpbyte = inb(iobase + 1);
	tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
	tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
	outb(tmpbyte, iobase + 1);
	tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
	if (tmpbyte != conf->fir_irq) {
		IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
		return -ENXIO;
	}

	/* Set up FIR I/O port */
	outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase);  // CR2B - SCE (FIR) base addr
	outb((conf->fir_io >> 3), iobase + 1);
	tmpbyte = inb(iobase + 1);
	if (tmpbyte != (conf->fir_io >> 3) ) {
		IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
		return -ENXIO;
	}

	/* Set up FIR DMA channel */
	outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase);  // CR2C - SCE (FIR) DMA select
	outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
	tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
	if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
		IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
		return -ENXIO;
	}

	outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase);  // CR0C - UART mode
	tmpbyte = inb(iobase + 1);
2586 2587
	tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
		SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611
	outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed

	outb(LPC47N227_APMBOOTDRIVE_REG, iobase);  // CR07 - Auto Pwr Mgt/boot drive sel
	tmpbyte = inb(iobase + 1);
	outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down

	/* This one was not part of tosh1800 */
	outb(0x0a, iobase);  // CR0a - ecp fifo / ir mux
	tmpbyte = inb(iobase + 1);
	outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port

	outb(LPC47N227_UART12POWER_REG, iobase);  // CR02 - UART 1,2 power
	tmpbyte = inb(iobase + 1);
	outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down

	outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase);  // CR00 - FDC Power/valid config cycle
	tmpbyte = inb(iobase + 1);
	outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done

	outb(LPC47N227_CFGEXITKEY, iobase);  // Exit configuration

	return 0;
}

2612
/* 82801CAM generic registers */
2613 2614
#define VID 0x00
#define DID 0x02
2615 2616 2617
#define PIRQ_A_D_ROUT 0x60
#define SIRQ_CNTL 0x64
#define PIRQ_E_H_ROUT 0x68
2618
#define PCI_DMA_C 0x90
2619
/* LPC-specific registers */
2620
#define COM_DEC 0xe0
2621
#define GEN1_DEC 0xe4
2622 2623 2624
#define LPC_EN 0xe6
#define GEN2_DEC 0xec
/*
2625 2626 2627
 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
 * They all work the same way!
2628 2629
 */
static int __init preconfigure_through_82801(struct pci_dev *dev,
2630 2631 2632
					     struct
					     smsc_ircc_subsystem_configuration
					     *conf)
2633 2634
{
	unsigned short tmpword;
2635
	unsigned char tmpbyte;
2636

2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687
	IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
	/*
	 * Select the range for the COMA COM port (SIR)
	 * Register COM_DEC:
	 * Bit 7: reserved
	 * Bit 6-4, COMB decode range
	 * Bit 3: reserved
	 * Bit 2-0, COMA decode range
	 *
	 * Decode ranges:
	 *   000 = 0x3f8-0x3ff (COM1)
	 *   001 = 0x2f8-0x2ff (COM2)
	 *   010 = 0x220-0x227
	 *   011 = 0x228-0x22f
	 *   100 = 0x238-0x23f
	 *   101 = 0x2e8-0x2ef (COM4)
	 *   110 = 0x338-0x33f
	 *   111 = 0x3e8-0x3ef (COM3)
	 */
	pci_read_config_byte(dev, COM_DEC, &tmpbyte);
	tmpbyte &= 0xf8; /* mask COMA bits */
	switch(conf->sir_io) {
	case 0x3f8:
		tmpbyte |= 0x00;
		break;
	case 0x2f8:
		tmpbyte |= 0x01;
		break;
	case 0x220:
		tmpbyte |= 0x02;
		break;
	case 0x228:
		tmpbyte |= 0x03;
		break;
	case 0x238:
		tmpbyte |= 0x04;
		break;
	case 0x2e8:
		tmpbyte |= 0x05;
		break;
	case 0x338:
		tmpbyte |= 0x06;
		break;
	case 0x3e8:
		tmpbyte |= 0x07;
		break;
	default:
		tmpbyte |= 0x01; /* COM2 default */
	}
	IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
	pci_write_config_byte(dev, COM_DEC, tmpbyte);
2688

2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714
	/* Enable Low Pin Count interface */
	pci_read_config_word(dev, LPC_EN, &tmpword);
	/* These seem to be set up at all times,
	 * just make sure it is properly set.
	 */
	switch(conf->cfg_base) {
	case 0x04e:
		tmpword |= 0x2000;
		break;
	case 0x02e:
		tmpword |= 0x1000;
		break;
	case 0x062:
		tmpword |= 0x0800;
		break;
	case 0x060:
		tmpword |= 0x0400;
		break;
	default:
		IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
			     conf->cfg_base);
		break;
	}
	tmpword &= 0xfffd; /* disable LPC COMB */
	tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
	IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
2715 2716
	pci_write_config_word(dev, LPC_EN, tmpword);

2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771
	/*
	 * Configure LPC DMA channel
	 * PCI_DMA_C bits:
	 * Bit 15-14: DMA channel 7 select
	 * Bit 13-12: DMA channel 6 select
	 * Bit 11-10: DMA channel 5 select
	 * Bit 9-8:   Reserved
	 * Bit 7-6:   DMA channel 3 select
	 * Bit 5-4:   DMA channel 2 select
	 * Bit 3-2:   DMA channel 1 select
	 * Bit 1-0:   DMA channel 0 select
	 *  00 = Reserved value
	 *  01 = PC/PCI DMA
	 *  10 = Reserved value
	 *  11 = LPC I/F DMA
	 */
	pci_read_config_word(dev, PCI_DMA_C, &tmpword);
	switch(conf->fir_dma) {
	case 0x07:
		tmpword |= 0xc000;
		break;
	case 0x06:
		tmpword |= 0x3000;
		break;
	case 0x05:
		tmpword |= 0x0c00;
		break;
	case 0x03:
		tmpword |= 0x00c0;
		break;
	case 0x02:
		tmpword |= 0x0030;
		break;
	case 0x01:
		tmpword |= 0x000c;
		break;
	case 0x00:
		tmpword |= 0x0003;
		break;
	default:
		break; /* do not change settings */
	}
	IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
	pci_write_config_word(dev, PCI_DMA_C, tmpword);

	/*
	 * GEN2_DEC bits:
	 * Bit 15-4: Generic I/O range
	 * Bit 3-1: reserved (read as 0)
	 * Bit 0: enable GEN2 range on LPC I/F
	 */
	tmpword = conf->fir_io & 0xfff8;
	tmpword |= 0x0001;
	IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
	pci_write_config_word(dev, GEN2_DEC, tmpword);
2772 2773

	/* Pre-configure chip */
2774 2775
	return preconfigure_smsc_chip(conf);
}
2776

2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818
/*
 * Pre-configure a certain port on the ALi 1533 bridge.
 * This is based on reverse-engineering since ALi does not
 * provide any data sheet for the 1533 chip.
 */
static void __init preconfigure_ali_port(struct pci_dev *dev,
					 unsigned short port)
{
	unsigned char reg;
	/* These bits obviously control the different ports */
	unsigned char mask;
	unsigned char tmpbyte;

	switch(port) {
	case 0x0130:
	case 0x0178:
		reg = 0xb0;
		mask = 0x80;
		break;
	case 0x03f8:
		reg = 0xb4;
		mask = 0x80;
		break;
	case 0x02f8:
		reg = 0xb4;
		mask = 0x30;
		break;
	case 0x02e8:
		reg = 0xb4;
		mask = 0x08;
		break;
	default:
		IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
		return;
	}

	pci_read_config_byte(dev, reg, &tmpbyte);
	/* Turn on the right bits */
	tmpbyte |= mask;
	pci_write_config_byte(dev, reg, tmpbyte);
	IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
	return;
2819 2820 2821
}

static int __init preconfigure_through_ali(struct pci_dev *dev,
2822 2823 2824
					   struct
					   smsc_ircc_subsystem_configuration
					   *conf)
2825
{
2826 2827 2828 2829 2830 2831
	/* Configure the two ports on the ALi 1533 */
	preconfigure_ali_port(dev, conf->sir_io);
	preconfigure_ali_port(dev, conf->fir_io);

	/* Pre-configure chip */
	return preconfigure_smsc_chip(conf);
2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850
}

static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
						    unsigned short ircc_fir,
						    unsigned short ircc_sir,
						    unsigned char ircc_dma,
						    unsigned char ircc_irq)
{
	struct pci_dev *dev = NULL;
	unsigned short ss_vendor = 0x0000;
	unsigned short ss_device = 0x0000;
	int ret = 0;

	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);

	while (dev != NULL) {
		struct smsc_ircc_subsystem_configuration *conf;

		/*
2851 2852 2853 2854
		 * Cache the subsystem vendor/device:
		 * some manufacturers fail to set this for all components,
		 * so we save it in case there is just 0x0000 0x0000 on the
		 * device we want to check.
2855 2856 2857 2858 2859 2860 2861 2862 2863
		 */
		if (dev->subsystem_vendor != 0x0000U) {
			ss_vendor = dev->subsystem_vendor;
			ss_device = dev->subsystem_device;
		}
		conf = subsystem_configurations;
		for( ; conf->subvendor; conf++) {
			if(conf->vendor == dev->vendor &&
			   conf->device == dev->device &&
2864 2865 2866 2867 2868 2869
			   conf->subvendor == ss_vendor &&
			   /* Sometimes these are cached values */
			   (conf->subdevice == ss_device ||
			    conf->subdevice == 0xffff)) {
				struct smsc_ircc_subsystem_configuration
					tmpconf;
2870

2871 2872
				memcpy(&tmpconf, conf,
				       sizeof(struct smsc_ircc_subsystem_configuration));
2873

2874 2875 2876 2877
				/*
				 * Override the default values with anything
				 * passed in as parameter
				 */
2878 2879 2880 2881 2882 2883
				if (ircc_cfg != 0)
					tmpconf.cfg_base = ircc_cfg;
				if (ircc_fir != 0)
					tmpconf.fir_io = ircc_fir;
				if (ircc_sir != 0)
					tmpconf.sir_io = ircc_sir;
2884
				if (ircc_dma != DMA_INVAL)
2885
					tmpconf.fir_dma = ircc_dma;
2886
				if (ircc_irq != IRQ_INVAL)
2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902
					tmpconf.fir_irq = ircc_irq;

				IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
				if (conf->preconfigure)
					ret = conf->preconfigure(dev, &tmpconf);
				else
					ret = -ENODEV;
			}
		}
		dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	}

	return ret;
}
#endif // CONFIG_PCI

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/************************************************
 *
 * Transceivers specific functions
 *
 ************************************************/


/*
 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
 *
 *    Program transceiver through smsc-ircc ATC circuitry
 *
 */

static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
{
	unsigned long jiffies_now, jiffies_timeout;
2920
	u8 val;
2921

2922 2923
	jiffies_now = jiffies;
	jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2924

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	/* ATC */
	register_bank(fir_base, 4);
2927 2928 2929 2930 2931 2932 2933 2934
	outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
	     fir_base + IRCC_ATC);

	while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
		!time_after(jiffies, jiffies_timeout))
		/* empty */;

	if (val)
2935
		IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__,
2936
			     inb(fir_base + IRCC_ATC));
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}

/*
 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
 *
 *    Probe transceiver smsc-ircc ATC circuitry
 *
 */

static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
{
	return 0;
}

/*
 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
 *
2954
 *    Set transceiver
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 *
 */

static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
{
2960
	u8 fast_mode;
2961

2962 2963 2964
	switch (speed) {
	default:
	case 576000 :
2965
		fast_mode = 0;
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		break;
2967 2968
	case 1152000 :
	case 4000000 :
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		fast_mode = IRCC_LCR_A_FAST;
		break;
	}
	register_bank(fir_base, 0);
2973
	outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
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}

/*
 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
 *
2979
 *    Probe transceiver
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 *
 */

static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
{
	return 0;
}

/*
 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
 *
2991
 *    Set transceiver
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 *
 */

static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
{
2997
	u8 fast_mode;
2998

2999 3000 3001
	switch (speed) {
	default:
	case 576000 :
3002
		fast_mode = 0;
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		break;
3004 3005
	case 1152000 :
	case 4000000 :
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		fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
		break;
3008

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	}
	/* This causes an interrupt */
	register_bank(fir_base, 0);
3012
	outb((inb(fir_base + IRCC_LCR_A) &  0xbf) | fast_mode, fir_base + IRCC_LCR_A);
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}

/*
 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
 *
3018
 *    Probe transceiver
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 *
 */

static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
{
	return 0;
}


module_init(smsc_ircc_init);
module_exit(smsc_ircc_cleanup);