lapic.c 55.2 KB
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/*
 * Local APIC virtualization
 *
 * Copyright (C) 2006 Qumranet, Inc.
 * Copyright (C) 2007 Novell
 * Copyright (C) 2007 Intel
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 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
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 *
 * Authors:
 *   Dor Laor <dor.laor@qumranet.com>
 *   Gregory Haskins <ghaskins@novell.com>
 *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
 *
 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 */

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#include <linux/kvm_host.h>
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#include <linux/kvm.h>
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/smp.h>
#include <linux/hrtimer.h>
#include <linux/io.h>
#include <linux/module.h>
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#include <linux/math64.h>
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#include <linux/slab.h>
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#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/page.h>
#include <asm/current.h>
#include <asm/apicdef.h>
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#include <asm/delay.h>
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#include <linux/atomic.h>
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#include <linux/jump_label.h>
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#include "kvm_cache_regs.h"
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#include "irq.h"
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#include "trace.h"
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#include "x86.h"
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#include "cpuid.h"
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#include "hyperv.h"
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#ifndef CONFIG_X86_64
#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
#else
#define mod_64(x, y) ((x) % (y))
#endif

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#define PRId64 "d"
#define PRIx64 "llx"
#define PRIu64 "u"
#define PRIo64 "o"

#define APIC_BUS_CYCLE_NS 1

/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
#define apic_debug(fmt, arg...)

#define APIC_LVT_NUM			6
/* 14 is the version for Xeon and Pentium 8.4.8*/
#define APIC_VERSION			(0x14UL | ((APIC_LVT_NUM - 1) << 16))
#define LAPIC_MMIO_LENGTH		(1 << 12)
/* followed define is not in apicdef.h */
#define APIC_SHORT_MASK			0xc0000
#define APIC_DEST_NOSHORT		0x0
#define APIC_DEST_MASK			0x800
#define MAX_APIC_VECTOR			256
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#define APIC_VECTORS_PER_REG		32
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#define APIC_BROADCAST			0xFF
#define X2APIC_BROADCAST		0xFFFFFFFFul

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#define VEC_POS(v) ((v) & (32 - 1))
#define REG_POS(v) (((v) >> 5) << 4)
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static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
{
	*((u32 *) (apic->regs + reg_off)) = val;
}

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static inline int apic_test_vector(int vec, void *bitmap)
{
	return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

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bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
{
	struct kvm_lapic *apic = vcpu->arch.apic;

	return apic_test_vector(vector, apic->regs + APIC_ISR) ||
		apic_test_vector(vector, apic->regs + APIC_IRR);
}

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static inline void apic_set_vector(int vec, void *bitmap)
{
	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

static inline void apic_clear_vector(int vec, void *bitmap)
{
	clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

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static inline int __apic_test_and_set_vector(int vec, void *bitmap)
{
	return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
{
	return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

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struct static_key_deferred apic_hw_disabled __read_mostly;
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struct static_key_deferred apic_sw_disabled __read_mostly;

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static inline int apic_enabled(struct kvm_lapic *apic)
{
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	return kvm_apic_sw_enabled(apic) &&	kvm_apic_hw_enabled(apic);
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}

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#define LVT_MASK	\
	(APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)

#define LINT_MASK	\
	(LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
	 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)

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/* The logical map is definitely wrong if we have multiple
 * modes at the same time.  (Physical map is always right.)
 */
static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
{
	return !(map->mode & (map->mode - 1));
}

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static inline void
apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
{
	unsigned lid_bits;

	BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER !=  4);
	BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT    !=  8);
	BUILD_BUG_ON(KVM_APIC_MODE_X2APIC        != 16);
	lid_bits = map->mode;

	*cid = dest_id >> lid_bits;
	*lid = dest_id & ((1 << lid_bits) - 1);
}

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static void recalculate_apic_map(struct kvm *kvm)
{
	struct kvm_apic_map *new, *old = NULL;
	struct kvm_vcpu *vcpu;
	int i;

	new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);

	mutex_lock(&kvm->arch.apic_map_lock);

	if (!new)
		goto out;

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	kvm_for_each_vcpu(i, vcpu, kvm) {
		struct kvm_lapic *apic = vcpu->arch.apic;
		u16 cid, lid;
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		u32 ldr, aid;
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		if (!kvm_apic_present(vcpu))
			continue;

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		aid = kvm_apic_id(apic);
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		ldr = kvm_apic_get_reg(apic, APIC_LDR);

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		if (aid < ARRAY_SIZE(new->phys_map))
			new->phys_map[aid] = apic;
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		if (apic_x2apic_mode(apic)) {
			new->mode |= KVM_APIC_MODE_X2APIC;
		} else if (ldr) {
			ldr = GET_APIC_LOGICAL_ID(ldr);
			if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
				new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
			else
				new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
		}

		if (!kvm_apic_logical_map_valid(new))
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			continue;

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		apic_logical_id(new, ldr, &cid, &lid);

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		if (lid && cid < ARRAY_SIZE(new->logical_map))
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			new->logical_map[cid][ffs(lid) - 1] = apic;
	}
out:
	old = rcu_dereference_protected(kvm->arch.apic_map,
			lockdep_is_held(&kvm->arch.apic_map_lock));
	rcu_assign_pointer(kvm->arch.apic_map, new);
	mutex_unlock(&kvm->arch.apic_map_lock);

	if (old)
		kfree_rcu(old, rcu);
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	kvm_make_scan_ioapic_request(kvm);
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}

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static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
{
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	bool enabled = val & APIC_SPIV_APIC_ENABLED;
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	apic_set_reg(apic, APIC_SPIV, val);
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	if (enabled != apic->sw_enabled) {
		apic->sw_enabled = enabled;
		if (enabled) {
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			static_key_slow_dec_deferred(&apic_sw_disabled);
			recalculate_apic_map(apic->vcpu->kvm);
		} else
			static_key_slow_inc(&apic_sw_disabled.key);
	}
}

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static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
{
	apic_set_reg(apic, APIC_ID, id << 24);
	recalculate_apic_map(apic->vcpu->kvm);
}

static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
{
	apic_set_reg(apic, APIC_LDR, id);
	recalculate_apic_map(apic->vcpu->kvm);
}

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static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id)
{
	u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));

	apic_set_reg(apic, APIC_ID, id << 24);
	apic_set_reg(apic, APIC_LDR, ldr);
	recalculate_apic_map(apic->vcpu->kvm);
}

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static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
{
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	return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
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}

static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
{
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	return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
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}

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static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
{
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	return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
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}

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static inline int apic_lvtt_period(struct kvm_lapic *apic)
{
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	return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
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}

static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
{
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	return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
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}

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static inline int apic_lvt_nmi_mode(u32 lvt_val)
{
	return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
}

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void kvm_apic_set_version(struct kvm_vcpu *vcpu)
{
	struct kvm_lapic *apic = vcpu->arch.apic;
	struct kvm_cpuid_entry2 *feat;
	u32 v = APIC_VERSION;

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	if (!lapic_in_kernel(vcpu))
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		return;

	feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
	if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
		v |= APIC_LVR_DIRECTED_EOI;
	apic_set_reg(apic, APIC_LVR, v);
}

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static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
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	LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
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	LVT_MASK | APIC_MODE_MASK,	/* LVTTHMR */
	LVT_MASK | APIC_MODE_MASK,	/* LVTPC */
	LINT_MASK, LINT_MASK,	/* LVT0-1 */
	LVT_MASK		/* LVTERR */
};

static int find_highest_vector(void *bitmap)
{
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	int vec;
	u32 *reg;
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	for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
	     vec >= 0; vec -= APIC_VECTORS_PER_REG) {
		reg = bitmap + REG_POS(vec);
		if (*reg)
			return fls(*reg) - 1 + vec;
	}
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	return -1;
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}

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static u8 count_vectors(void *bitmap)
{
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	int vec;
	u32 *reg;
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	u8 count = 0;
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	for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
		reg = bitmap + REG_POS(vec);
		count += hweight32(*reg);
	}

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	return count;
}

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void __kvm_apic_update_irr(u32 *pir, void *regs)
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{
	u32 i, pir_val;

	for (i = 0; i <= 7; i++) {
		pir_val = xchg(&pir[i], 0);
		if (pir_val)
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			*((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
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	}
}
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EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);

void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
{
	struct kvm_lapic *apic = vcpu->arch.apic;

	__kvm_apic_update_irr(pir, apic->regs);
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	kvm_make_request(KVM_REQ_EVENT, vcpu);
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}
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EXPORT_SYMBOL_GPL(kvm_apic_update_irr);

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static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
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{
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	apic_set_vector(vec, apic->regs + APIC_IRR);
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	/*
	 * irr_pending must be true if any interrupt is pending; set it after
	 * APIC_IRR to avoid race with apic_clear_irr
	 */
	apic->irr_pending = true;
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}

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static inline int apic_search_irr(struct kvm_lapic *apic)
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{
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	return find_highest_vector(apic->regs + APIC_IRR);
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}

static inline int apic_find_highest_irr(struct kvm_lapic *apic)
{
	int result;

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	/*
	 * Note that irr_pending is just a hint. It will be always
	 * true with virtual interrupt delivery enabled.
	 */
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	if (!apic->irr_pending)
		return -1;

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	if (apic->vcpu->arch.apicv_active)
		kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
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	result = apic_search_irr(apic);
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	ASSERT(result == -1 || result >= 16);

	return result;
}

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static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
{
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	struct kvm_vcpu *vcpu;

	vcpu = apic->vcpu;

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	if (unlikely(vcpu->arch.apicv_active)) {
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		/* try to update RVI */
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		apic_clear_vector(vec, apic->regs + APIC_IRR);
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		kvm_make_request(KVM_REQ_EVENT, vcpu);
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	} else {
		apic->irr_pending = false;
		apic_clear_vector(vec, apic->regs + APIC_IRR);
		if (apic_search_irr(apic) != -1)
			apic->irr_pending = true;
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	}
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}

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static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
{
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	struct kvm_vcpu *vcpu;

	if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
		return;

	vcpu = apic->vcpu;
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	/*
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	 * With APIC virtualization enabled, all caching is disabled
	 * because the processor can modify ISR under the hood.  Instead
	 * just set SVI.
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	 */
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	if (unlikely(vcpu->arch.apicv_active))
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		kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
	else {
		++apic->isr_count;
		BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
		/*
		 * ISR (in service register) bit is set when injecting an interrupt.
		 * The highest vector is injected. Thus the latest bit set matches
		 * the highest bit in ISR.
		 */
		apic->highest_isr_cache = vec;
	}
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}

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static inline int apic_find_highest_isr(struct kvm_lapic *apic)
{
	int result;

	/*
	 * Note that isr_count is always 1, and highest_isr_cache
	 * is always -1, with APIC virtualization enabled.
	 */
	if (!apic->isr_count)
		return -1;
	if (likely(apic->highest_isr_cache != -1))
		return apic->highest_isr_cache;

	result = find_highest_vector(apic->regs + APIC_ISR);
	ASSERT(result == -1 || result >= 16);

	return result;
}

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static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
{
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	struct kvm_vcpu *vcpu;
	if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
		return;

	vcpu = apic->vcpu;

	/*
	 * We do get here for APIC virtualization enabled if the guest
	 * uses the Hyper-V APIC enlightenment.  In this case we may need
	 * to trigger a new interrupt delivery by writing the SVI field;
	 * on the other hand isr_count and highest_isr_cache are unused
	 * and must be left alone.
	 */
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	if (unlikely(vcpu->arch.apicv_active))
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		kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
					       apic_find_highest_isr(apic));
	else {
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		--apic->isr_count;
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		BUG_ON(apic->isr_count < 0);
		apic->highest_isr_cache = -1;
	}
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}

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int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
{
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	/* This may race with setting of irr in __apic_accept_irq() and
	 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
	 * will cause vmexit immediately and the value will be recalculated
	 * on the next vmentry.
	 */
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	return apic_find_highest_irr(vcpu->arch.apic);
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}

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static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
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			     int vector, int level, int trig_mode,
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			     struct dest_map *dest_map);
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int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
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		     struct dest_map *dest_map)
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{
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	struct kvm_lapic *apic = vcpu->arch.apic;
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	return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
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			irq->level, irq->trig_mode, dest_map);
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}

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static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
{

	return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
				      sizeof(val));
}

static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
{

	return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
				      sizeof(*val));
}

static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
{
	return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
}

static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
{
	u8 val;
	if (pv_eoi_get_user(vcpu, &val) < 0)
		apic_debug("Can't read EOI MSR value: 0x%llx\n",
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			   (unsigned long long)vcpu->arch.pv_eoi.msr_val);
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	return val & 0x1;
}

static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
{
	if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
		apic_debug("Can't set EOI MSR value: 0x%llx\n",
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			   (unsigned long long)vcpu->arch.pv_eoi.msr_val);
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		return;
	}
	__set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
}

static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
{
	if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
		apic_debug("Can't clear EOI MSR value: 0x%llx\n",
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			   (unsigned long long)vcpu->arch.pv_eoi.msr_val);
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		return;
	}
	__clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
}

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static void apic_update_ppr(struct kvm_lapic *apic)
{
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	u32 tpr, isrv, ppr, old_ppr;
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	int isr;

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	old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
	tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
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	isr = apic_find_highest_isr(apic);
	isrv = (isr != -1) ? isr : 0;

	if ((tpr & 0xf0) >= (isrv & 0xf0))
		ppr = tpr & 0xff;
	else
		ppr = isrv & 0xf0;

	apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
		   apic, ppr, isr, isrv);

565 566
	if (old_ppr != ppr) {
		apic_set_reg(apic, APIC_PROCPRI, ppr);
567 568
		if (ppr < old_ppr)
			kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
569
	}
E
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570 571 572 573 574 575 576 577
}

static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
{
	apic_set_reg(apic, APIC_TASKPRI, tpr);
	apic_update_ppr(apic);
}

578
static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
579
{
580 581 582 583
	if (apic_x2apic_mode(apic))
		return mda == X2APIC_BROADCAST;

	return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
584 585
}

586
static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
E
Eddie Dong 已提交
587
{
588 589 590 591 592 593 594
	if (kvm_apic_broadcast(apic, mda))
		return true;

	if (apic_x2apic_mode(apic))
		return mda == kvm_apic_id(apic);

	return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
E
Eddie Dong 已提交
595 596
}

597
static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
E
Eddie Dong 已提交
598
{
G
Gleb Natapov 已提交
599 600
	u32 logical_id;

601
	if (kvm_apic_broadcast(apic, mda))
602
		return true;
603

604
	logical_id = kvm_apic_get_reg(apic, APIC_LDR);
E
Eddie Dong 已提交
605

606
	if (apic_x2apic_mode(apic))
607 608
		return ((logical_id >> 16) == (mda >> 16))
		       && (logical_id & mda & 0xffff) != 0;
E
Eddie Dong 已提交
609

610
	logical_id = GET_APIC_LOGICAL_ID(logical_id);
611
	mda = GET_APIC_DEST_FIELD(mda);
E
Eddie Dong 已提交
612

613
	switch (kvm_apic_get_reg(apic, APIC_DFR)) {
E
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614
	case APIC_DFR_FLAT:
615
		return (logical_id & mda) != 0;
E
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616
	case APIC_DFR_CLUSTER:
617 618
		return ((logical_id >> 4) == (mda >> 4))
		       && (logical_id & mda & 0xf) != 0;
E
Eddie Dong 已提交
619
	default:
620
		apic_debug("Bad DFR vcpu %d: %08x\n",
621
			   apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
622
		return false;
E
Eddie Dong 已提交
623 624 625
	}
}

626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641
/* KVM APIC implementation has two quirks
 *  - dest always begins at 0 while xAPIC MDA has offset 24,
 *  - IOxAPIC messages have to be delivered (directly) to x2APIC.
 */
static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
                                              struct kvm_lapic *target)
{
	bool ipi = source != NULL;
	bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);

	if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
		return X2APIC_BROADCAST;

	return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
}

642
bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
643
			   int short_hand, unsigned int dest, int dest_mode)
E
Eddie Dong 已提交
644
{
645
	struct kvm_lapic *target = vcpu->arch.apic;
646
	u32 mda = kvm_apic_mda(dest, source, target);
E
Eddie Dong 已提交
647 648

	apic_debug("target %p, source %p, dest 0x%x, "
649
		   "dest_mode 0x%x, short_hand 0x%x\n",
E
Eddie Dong 已提交
650 651
		   target, source, dest, dest_mode, short_hand);

Z
Zachary Amsden 已提交
652
	ASSERT(target);
E
Eddie Dong 已提交
653 654
	switch (short_hand) {
	case APIC_DEST_NOSHORT:
655
		if (dest_mode == APIC_DEST_PHYSICAL)
656
			return kvm_apic_match_physical_addr(target, mda);
657
		else
658
			return kvm_apic_match_logical_addr(target, mda);
E
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659
	case APIC_DEST_SELF:
660
		return target == source;
E
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661
	case APIC_DEST_ALLINC:
662
		return true;
E
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663
	case APIC_DEST_ALLBUT:
664
		return target != source;
E
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665
	default:
666 667
		apic_debug("kvm: apic: Bad dest shorthand value %x\n",
			   short_hand);
668
		return false;
E
Eddie Dong 已提交
669 670 671
	}
}

672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687
int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
		       const unsigned long *bitmap, u32 bitmap_size)
{
	u32 mod;
	int i, idx = -1;

	mod = vector % dest_vcpus;

	for (i = 0; i <= mod; i++) {
		idx = find_next_bit(bitmap, bitmap_size, idx + 1);
		BUG_ON(idx == bitmap_size);
	}

	return idx;
}

688 689 690 691 692 693 694 695 696
static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
{
	if (!kvm->arch.disabled_lapic_found) {
		kvm->arch.disabled_lapic_found = true;
		printk(KERN_INFO
		       "Disabled LAPIC found during irq injection\n");
	}
}

697
bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
698
		struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
699 700 701 702 703
{
	struct kvm_apic_map *map;
	unsigned long bitmap = 1;
	struct kvm_lapic **dst;
	int i;
704
	bool ret, x2apic_ipi;
705 706 707 708

	*r = -1;

	if (irq->shorthand == APIC_DEST_SELF) {
709
		*r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
710 711 712 713 714 715
		return true;
	}

	if (irq->shorthand)
		return false;

716
	x2apic_ipi = src && apic_x2apic_mode(src);
717 718 719
	if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
		return false;

720
	ret = true;
721 722 723
	rcu_read_lock();
	map = rcu_dereference(kvm->arch.apic_map);

724 725
	if (!map) {
		ret = false;
726
		goto out;
727
	}
728

729
	if (irq->dest_mode == APIC_DEST_PHYSICAL) {
730 731 732 733
		if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
			goto out;

		dst = &map->phys_map[irq->dest_id];
734
	} else {
735 736 737 738 739 740 741
		u16 cid;

		if (!kvm_apic_logical_map_valid(map)) {
			ret = false;
			goto out;
		}

742
		apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
743 744 745

		if (cid >= ARRAY_SIZE(map->logical_map))
			goto out;
746

747
		dst = map->logical_map[cid];
748

749 750 751 752
		if (!kvm_lowest_prio_delivery(irq))
			goto set_irq;

		if (!kvm_vector_hashing_enabled()) {
753 754 755 756 757 758
			int l = -1;
			for_each_set_bit(i, &bitmap, 16) {
				if (!dst[i])
					continue;
				if (l < 0)
					l = i;
759 760
				else if (kvm_apic_compare_prio(dst[i]->vcpu,
							dst[l]->vcpu) < 0)
761 762 763
					l = i;
			}
			bitmap = (l >= 0) ? 1 << l : 0;
764 765 766 767 768 769 770 771 772 773 774
		} else {
			int idx;
			unsigned int dest_vcpus;

			dest_vcpus = hweight16(bitmap);
			if (dest_vcpus == 0)
				goto out;

			idx = kvm_vector_to_index(irq->vector,
				dest_vcpus, &bitmap, 16);

775 776
			if (!dst[idx]) {
				kvm_apic_disabled_lapic_found(kvm);
777 778 779 780
				goto out;
			}

			bitmap = (idx >= 0) ? 1 << idx : 0;
781 782 783
		}
	}

784
set_irq:
785 786 787 788 789
	for_each_set_bit(i, &bitmap, 16) {
		if (!dst[i])
			continue;
		if (*r < 0)
			*r = 0;
790
		*r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
791 792 793 794 795 796
	}
out:
	rcu_read_unlock();
	return ret;
}

797 798 799 800 801 802 803 804 805 806 807 808 809 810
/*
 * This routine tries to handler interrupts in posted mode, here is how
 * it deals with different cases:
 * - For single-destination interrupts, handle it in posted mode
 * - Else if vector hashing is enabled and it is a lowest-priority
 *   interrupt, handle it in posted mode and use the following mechanism
 *   to find the destinaiton vCPU.
 *	1. For lowest-priority interrupts, store all the possible
 *	   destination vCPUs in an array.
 *	2. Use "guest vector % max number of destination vCPUs" to find
 *	   the right destination vCPU in the array for the lowest-priority
 *	   interrupt.
 * - Otherwise, use remapped mode to inject the interrupt.
 */
811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851
bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
			struct kvm_vcpu **dest_vcpu)
{
	struct kvm_apic_map *map;
	bool ret = false;
	struct kvm_lapic *dst = NULL;

	if (irq->shorthand)
		return false;

	rcu_read_lock();
	map = rcu_dereference(kvm->arch.apic_map);

	if (!map)
		goto out;

	if (irq->dest_mode == APIC_DEST_PHYSICAL) {
		if (irq->dest_id == 0xFF)
			goto out;

		if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
			goto out;

		dst = map->phys_map[irq->dest_id];
		if (dst && kvm_apic_present(dst->vcpu))
			*dest_vcpu = dst->vcpu;
		else
			goto out;
	} else {
		u16 cid;
		unsigned long bitmap = 1;
		int i, r = 0;

		if (!kvm_apic_logical_map_valid(map))
			goto out;

		apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);

		if (cid >= ARRAY_SIZE(map->logical_map))
			goto out;

852 853 854 855 856 857 858
		if (kvm_vector_hashing_enabled() &&
				kvm_lowest_prio_delivery(irq)) {
			int idx;
			unsigned int dest_vcpus;

			dest_vcpus = hweight16(bitmap);
			if (dest_vcpus == 0)
859 860
				goto out;

861 862 863 864
			idx = kvm_vector_to_index(irq->vector, dest_vcpus,
						  &bitmap, 16);

			dst = map->logical_map[cid][idx];
865 866
			if (!dst) {
				kvm_apic_disabled_lapic_found(kvm);
867 868 869
				goto out;
			}

870
			*dest_vcpu = dst->vcpu;
871 872 873 874 875 876 877 878 879 880 881 882
		} else {
			for_each_set_bit(i, &bitmap, 16) {
				dst = map->logical_map[cid][i];
				if (++r == 2)
					goto out;
			}

			if (dst && kvm_apic_present(dst->vcpu))
				*dest_vcpu = dst->vcpu;
			else
				goto out;
		}
883 884 885 886 887 888 889 890
	}

	ret = true;
out:
	rcu_read_unlock();
	return ret;
}

E
Eddie Dong 已提交
891 892 893 894 895
/*
 * Add a pending IRQ into lapic.
 * Return 1 if successfully added and 0 if discarded.
 */
static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
896
			     int vector, int level, int trig_mode,
897
			     struct dest_map *dest_map)
E
Eddie Dong 已提交
898
{
899
	int result = 0;
900
	struct kvm_vcpu *vcpu = apic->vcpu;
E
Eddie Dong 已提交
901

902 903
	trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
				  trig_mode, vector);
E
Eddie Dong 已提交
904 905
	switch (delivery_mode) {
	case APIC_DM_LOWEST:
906 907
		vcpu->arch.apic_arb_prio++;
	case APIC_DM_FIXED:
908 909 910
		if (unlikely(trig_mode && !level))
			break;

E
Eddie Dong 已提交
911 912 913 914
		/* FIXME add logic for vcpu on reset */
		if (unlikely(!apic_enabled(apic)))
			break;

915 916
		result = 1;

917
		if (dest_map) {
918
			__set_bit(vcpu->vcpu_id, dest_map->map);
919 920
			dest_map->vectors[vcpu->vcpu_id] = vector;
		}
921

922 923 924 925 926 927 928
		if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
			if (trig_mode)
				apic_set_vector(vector, apic->regs + APIC_TMR);
			else
				apic_clear_vector(vector, apic->regs + APIC_TMR);
		}

929
		if (vcpu->arch.apicv_active)
930
			kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
931 932
		else {
			apic_set_irr(vector, apic);
933 934 935 936

			kvm_make_request(KVM_REQ_EVENT, vcpu);
			kvm_vcpu_kick(vcpu);
		}
E
Eddie Dong 已提交
937 938 939
		break;

	case APIC_DM_REMRD:
940 941 942 943
		result = 1;
		vcpu->arch.pv.pv_unhalted = 1;
		kvm_make_request(KVM_REQ_EVENT, vcpu);
		kvm_vcpu_kick(vcpu);
E
Eddie Dong 已提交
944 945 946
		break;

	case APIC_DM_SMI:
P
Paolo Bonzini 已提交
947 948 949
		result = 1;
		kvm_make_request(KVM_REQ_SMI, vcpu);
		kvm_vcpu_kick(vcpu);
E
Eddie Dong 已提交
950
		break;
951

E
Eddie Dong 已提交
952
	case APIC_DM_NMI:
953
		result = 1;
954
		kvm_inject_nmi(vcpu);
J
Jan Kiszka 已提交
955
		kvm_vcpu_kick(vcpu);
E
Eddie Dong 已提交
956 957 958
		break;

	case APIC_DM_INIT:
959
		if (!trig_mode || level) {
960
			result = 1;
961 962 963 964 965
			/* assumes that there are only KVM_APIC_INIT/SIPI */
			apic->pending_events = (1UL << KVM_APIC_INIT);
			/* make sure pending_events is visible before sending
			 * the request */
			smp_wmb();
966
			kvm_make_request(KVM_REQ_EVENT, vcpu);
967 968
			kvm_vcpu_kick(vcpu);
		} else {
969 970
			apic_debug("Ignoring de-assert INIT to vcpu %d\n",
				   vcpu->vcpu_id);
971
		}
E
Eddie Dong 已提交
972 973 974
		break;

	case APIC_DM_STARTUP:
975 976
		apic_debug("SIPI to vcpu %d vector 0x%02x\n",
			   vcpu->vcpu_id, vector);
977 978 979 980 981 982 983
		result = 1;
		apic->sipi_vector = vector;
		/* make sure sipi_vector is visible for the receiver */
		smp_wmb();
		set_bit(KVM_APIC_SIPI, &apic->pending_events);
		kvm_make_request(KVM_REQ_EVENT, vcpu);
		kvm_vcpu_kick(vcpu);
E
Eddie Dong 已提交
984 985
		break;

986 987 988 989 990 991 992 993
	case APIC_DM_EXTINT:
		/*
		 * Should only be called by kvm_apic_local_deliver() with LVT0,
		 * before NMI watchdog was enabled. Already handled by
		 * kvm_apic_accept_pic_intr().
		 */
		break;

E
Eddie Dong 已提交
994 995 996 997 998 999 1000 1001
	default:
		printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
		       delivery_mode);
		break;
	}
	return result;
}

1002
int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1003
{
1004
	return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1005 1006
}

1007 1008
static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
{
1009
	return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1010 1011
}

1012 1013
static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
{
1014 1015 1016 1017 1018
	int trigger_mode;

	/* Eoi the ioapic only if the ioapic doesn't own the vector. */
	if (!kvm_ioapic_handles_vector(apic, vector))
		return;
1019

1020 1021 1022 1023 1024
	/* Request a KVM exit to inform the userspace IOAPIC. */
	if (irqchip_split(apic->vcpu->kvm)) {
		apic->vcpu->arch.pending_ioapic_eoi = vector;
		kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
		return;
1025
	}
1026 1027 1028 1029 1030 1031 1032

	if (apic_test_vector(vector, apic->regs + APIC_TMR))
		trigger_mode = IOAPIC_LEVEL_TRIG;
	else
		trigger_mode = IOAPIC_EDGE_TRIG;

	kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1033 1034
}

1035
static int apic_set_eoi(struct kvm_lapic *apic)
E
Eddie Dong 已提交
1036 1037
{
	int vector = apic_find_highest_isr(apic);
1038 1039 1040

	trace_kvm_eoi(apic, vector);

E
Eddie Dong 已提交
1041 1042 1043 1044 1045
	/*
	 * Not every write EOI will has corresponding ISR,
	 * one example is when Kernel check timer on setup_IO_APIC
	 */
	if (vector == -1)
1046
		return vector;
E
Eddie Dong 已提交
1047

M
Michael S. Tsirkin 已提交
1048
	apic_clear_isr(vector, apic);
E
Eddie Dong 已提交
1049 1050
	apic_update_ppr(apic);

1051 1052 1053
	if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
		kvm_hv_synic_send_eoi(apic->vcpu, vector);

1054
	kvm_ioapic_send_eoi(apic, vector);
1055
	kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1056
	return vector;
E
Eddie Dong 已提交
1057 1058
}

1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073
/*
 * this interface assumes a trap-like exit, which has already finished
 * desired side effect including vISR and vPPR update.
 */
void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
{
	struct kvm_lapic *apic = vcpu->arch.apic;

	trace_kvm_eoi(apic, vector);

	kvm_ioapic_send_eoi(apic, vector);
	kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
}
EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);

E
Eddie Dong 已提交
1074 1075
static void apic_send_ipi(struct kvm_lapic *apic)
{
1076 1077
	u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
	u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
1078
	struct kvm_lapic_irq irq;
E
Eddie Dong 已提交
1079

1080 1081 1082
	irq.vector = icr_low & APIC_VECTOR_MASK;
	irq.delivery_mode = icr_low & APIC_MODE_MASK;
	irq.dest_mode = icr_low & APIC_DEST_MASK;
1083
	irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1084 1085
	irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
	irq.shorthand = icr_low & APIC_SHORT_MASK;
1086
	irq.msi_redir_hint = false;
G
Gleb Natapov 已提交
1087 1088 1089 1090
	if (apic_x2apic_mode(apic))
		irq.dest_id = icr_high;
	else
		irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
E
Eddie Dong 已提交
1091

1092 1093
	trace_kvm_apic_ipi(icr_low, irq.dest_id);

E
Eddie Dong 已提交
1094 1095
	apic_debug("icr_high 0x%x, icr_low 0x%x, "
		   "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1096 1097
		   "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
		   "msi_redir_hint 0x%x\n",
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		   icr_high, icr_low, irq.shorthand, irq.dest_id,
1099
		   irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1100
		   irq.vector, irq.msi_redir_hint);
1101

1102
	kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
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}

static u32 apic_get_tmcct(struct kvm_lapic *apic)
{
1107 1108
	ktime_t remaining;
	s64 ns;
1109
	u32 tmcct;
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	ASSERT(apic != NULL);

1113
	/* if initial count is 0, current count should also be 0 */
1114 1115
	if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
		apic->lapic_timer.period == 0)
1116 1117
		return 0;

1118
	remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
1119 1120 1121
	if (ktime_to_ns(remaining) < 0)
		remaining = ktime_set(0, 0);

1122 1123 1124
	ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
	tmcct = div64_u64(ns,
			 (APIC_BUS_CYCLE_NS * apic->divide_count));
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	return tmcct;
}

1129 1130 1131 1132 1133
static void __report_tpr_access(struct kvm_lapic *apic, bool write)
{
	struct kvm_vcpu *vcpu = apic->vcpu;
	struct kvm_run *run = vcpu->run;

1134
	kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1135
	run->tpr_access.rip = kvm_rip_read(vcpu);
1136 1137 1138 1139 1140 1141 1142 1143 1144
	run->tpr_access.is_write = write;
}

static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
{
	if (apic->vcpu->arch.tpr_access_reporting)
		__report_tpr_access(apic, write);
}

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static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
{
	u32 val = 0;

	if (offset >= LAPIC_MMIO_LENGTH)
		return 0;

	switch (offset) {
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	case APIC_ID:
		if (apic_x2apic_mode(apic))
			val = kvm_apic_id(apic);
		else
			val = kvm_apic_id(apic) << 24;
		break;
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	case APIC_ARBPRI:
1160
		apic_debug("Access APIC ARBPRI register which is for P6\n");
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		break;

	case APIC_TMCCT:	/* Timer CCR */
1164 1165 1166
		if (apic_lvtt_tscdeadline(apic))
			return 0;

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		val = apic_get_tmcct(apic);
		break;
1169 1170
	case APIC_PROCPRI:
		apic_update_ppr(apic);
1171
		val = kvm_apic_get_reg(apic, offset);
1172
		break;
1173 1174 1175
	case APIC_TASKPRI:
		report_tpr_access(apic, false);
		/* fall thru */
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	default:
1177
		val = kvm_apic_get_reg(apic, offset);
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		break;
	}

	return val;
}

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static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
{
	return container_of(dev, struct kvm_lapic, dev);
}

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static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
		void *data)
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{
	unsigned char alignment = offset & 0xf;
	u32 result;
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	/* this bitmask has a bit cleared for each reserved register */
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	static const u64 rmask = 0x43ff01ffffffe70cULL;
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	if ((alignment + len) > 4) {
1198 1199
		apic_debug("KVM_APIC_READ: alignment error %x %d\n",
			   offset, len);
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		return 1;
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	}
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	if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1204 1205
		apic_debug("KVM_APIC_READ: read reserved register %x\n",
			   offset);
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		return 1;
	}

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	result = __apic_read(apic, offset & ~0xf);

1211 1212
	trace_kvm_apic_read(offset, result);

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	switch (len) {
	case 1:
	case 2:
	case 4:
		memcpy(data, (char *)&result + alignment, len);
		break;
	default:
		printk(KERN_ERR "Local APIC read with len = %x, "
		       "should be 1,2, or 4 instead\n", len);
		break;
	}
1224
	return 0;
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}

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static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
{
1229
	return kvm_apic_hw_enabled(apic) &&
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	    addr >= apic->base_address &&
	    addr < apic->base_address + LAPIC_MMIO_LENGTH;
}

1234
static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
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			   gpa_t address, int len, void *data)
{
	struct kvm_lapic *apic = to_lapic(this);
	u32 offset = address - apic->base_address;

	if (!apic_mmio_in_range(apic, address))
		return -EOPNOTSUPP;

	apic_reg_read(apic, offset, len, data);

	return 0;
}

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static void update_divide_count(struct kvm_lapic *apic)
{
	u32 tmp1, tmp2, tdcr;

1252
	tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
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	tmp1 = tdcr & 0xf;
	tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1255
	apic->divide_count = 0x1 << (tmp2 & 0x7);
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	apic_debug("timer divide count is 0x%x\n",
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				   apic->divide_count);
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}

1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271
static void apic_update_lvtt(struct kvm_lapic *apic)
{
	u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
			apic->lapic_timer.timer_mode_mask;

	if (apic->lapic_timer.timer_mode != timer_mode) {
		apic->lapic_timer.timer_mode = timer_mode;
		hrtimer_cancel(&apic->lapic_timer.timer);
	}
}

1272 1273 1274
static void apic_timer_expired(struct kvm_lapic *apic)
{
	struct kvm_vcpu *vcpu = apic->vcpu;
1275
	struct swait_queue_head *q = &vcpu->wq;
1276
	struct kvm_timer *ktimer = &apic->lapic_timer;
1277 1278 1279 1280 1281

	if (atomic_read(&apic->lapic_timer.pending))
		return;

	atomic_inc(&apic->lapic_timer.pending);
1282
	kvm_set_pending_timer(vcpu);
1283

1284 1285
	if (swait_active(q))
		swake_up(q);
1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302

	if (apic_lvtt_tscdeadline(apic))
		ktimer->expired_tscdeadline = ktimer->tscdeadline;
}

/*
 * On APICv, this test will cause a busy wait
 * during a higher-priority task.
 */

static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
{
	struct kvm_lapic *apic = vcpu->arch.apic;
	u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);

	if (kvm_apic_hw_enabled(apic)) {
		int vec = reg & APIC_VECTOR_MASK;
1303
		void *bitmap = apic->regs + APIC_ISR;
1304

1305
		if (vcpu->arch.apicv_active)
1306 1307 1308 1309
			bitmap = apic->regs + APIC_IRR;

		if (apic_test_vector(vec, bitmap))
			return true;
1310 1311 1312 1313 1314 1315 1316 1317 1318
	}
	return false;
}

void wait_lapic_expire(struct kvm_vcpu *vcpu)
{
	struct kvm_lapic *apic = vcpu->arch.apic;
	u64 guest_tsc, tsc_deadline;

1319
	if (!lapic_in_kernel(vcpu))
1320 1321 1322 1323 1324 1325 1326 1327 1328 1329
		return;

	if (apic->lapic_timer.expired_tscdeadline == 0)
		return;

	if (!lapic_timer_int_injected(vcpu))
		return;

	tsc_deadline = apic->lapic_timer.expired_tscdeadline;
	apic->lapic_timer.expired_tscdeadline = 0;
1330
	guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1331
	trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1332 1333 1334 1335

	/* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
	if (guest_tsc < tsc_deadline)
		__delay(tsc_deadline - guest_tsc);
1336 1337
}

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static void start_apic_timer(struct kvm_lapic *apic)
{
1340
	ktime_t now;
1341

1342
	atomic_set(&apic->lapic_timer.pending, 0);
1343

1344
	if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
G
Guo Chao 已提交
1345
		/* lapic timer in oneshot or periodic mode */
1346
		now = apic->lapic_timer.timer.base->get_time();
1347
		apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367
			    * APIC_BUS_CYCLE_NS * apic->divide_count;

		if (!apic->lapic_timer.period)
			return;
		/*
		 * Do not allow the guest to program periodic timers with small
		 * interval, since the hrtimers are not throttled by the host
		 * scheduler.
		 */
		if (apic_lvtt_period(apic)) {
			s64 min_period = min_timer_period_us * 1000LL;

			if (apic->lapic_timer.period < min_period) {
				pr_info_ratelimited(
				    "kvm: vcpu %i: requested %lld ns "
				    "lapic timer period limited to %lld ns\n",
				    apic->vcpu->vcpu_id,
				    apic->lapic_timer.period, min_period);
				apic->lapic_timer.period = min_period;
			}
1368
		}
1369

1370 1371
		hrtimer_start(&apic->lapic_timer.timer,
			      ktime_add_ns(now, apic->lapic_timer.period),
1372
			      HRTIMER_MODE_ABS_PINNED);
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1374
		apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
E
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			   PRIx64 ", "
			   "timer initial count 0x%x, period %lldns, "
1377
			   "expire @ 0x%016" PRIx64 ".\n", __func__,
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			   APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1379
			   kvm_apic_get_reg(apic, APIC_TMICT),
1380
			   apic->lapic_timer.period,
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			   ktime_to_ns(ktime_add_ns(now,
1382
					apic->lapic_timer.period)));
1383 1384 1385 1386
	} else if (apic_lvtt_tscdeadline(apic)) {
		/* lapic timer in tsc deadline mode */
		u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
		u64 ns = 0;
1387
		ktime_t expire;
1388
		struct kvm_vcpu *vcpu = apic->vcpu;
1389
		unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1390 1391 1392 1393 1394 1395 1396 1397
		unsigned long flags;

		if (unlikely(!tscdeadline || !this_tsc_khz))
			return;

		local_irq_save(flags);

		now = apic->lapic_timer.timer.base->get_time();
1398
		guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1399 1400 1401
		if (likely(tscdeadline > guest_tsc)) {
			ns = (tscdeadline - guest_tsc) * 1000000ULL;
			do_div(ns, this_tsc_khz);
1402 1403
			expire = ktime_add_ns(now, ns);
			expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1404
			hrtimer_start(&apic->lapic_timer.timer,
1405
				      expire, HRTIMER_MODE_ABS_PINNED);
1406 1407
		} else
			apic_timer_expired(apic);
1408 1409 1410

		local_irq_restore(flags);
	}
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1411 1412
}

1413 1414
static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
{
1415
	bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1416

1417 1418 1419
	if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
		apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
		if (lvt0_in_nmi_mode) {
1420 1421
			apic_debug("Receive NMI setting on APIC_LVT0 "
				   "for cpu %d\n", apic->vcpu->vcpu_id);
1422
			atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1423 1424 1425
		} else
			atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
	}
1426 1427
}

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1428
static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
E
Eddie Dong 已提交
1429
{
G
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1430
	int ret = 0;
E
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1431

G
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1432
	trace_kvm_apic_write(reg, val);
E
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1433

G
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1434
	switch (reg) {
E
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1435
	case APIC_ID:		/* Local APIC ID */
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1436
		if (!apic_x2apic_mode(apic))
1437
			kvm_apic_set_id(apic, val >> 24);
G
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1438 1439
		else
			ret = 1;
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1440 1441 1442
		break;

	case APIC_TASKPRI:
1443
		report_tpr_access(apic, true);
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		apic_set_tpr(apic, val & 0xff);
		break;

	case APIC_EOI:
		apic_set_eoi(apic);
		break;

	case APIC_LDR:
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1452
		if (!apic_x2apic_mode(apic))
1453
			kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
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1454 1455
		else
			ret = 1;
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1456 1457 1458
		break;

	case APIC_DFR:
1459
		if (!apic_x2apic_mode(apic)) {
G
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1460
			apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1461 1462
			recalculate_apic_map(apic->vcpu->kvm);
		} else
G
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1463
			ret = 1;
E
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1464 1465
		break;

1466 1467
	case APIC_SPIV: {
		u32 mask = 0x3ff;
1468
		if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1469
			mask |= APIC_SPIV_DIRECTED_EOI;
1470
		apic_set_spiv(apic, val & mask);
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1471 1472 1473 1474 1475
		if (!(val & APIC_SPIV_APIC_ENABLED)) {
			int i;
			u32 lvt_val;

			for (i = 0; i < APIC_LVT_NUM; i++) {
1476
				lvt_val = kvm_apic_get_reg(apic,
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1477 1478 1479 1480
						       APIC_LVTT + 0x10 * i);
				apic_set_reg(apic, APIC_LVTT + 0x10 * i,
					     lvt_val | APIC_LVT_MASKED);
			}
1481
			apic_update_lvtt(apic);
1482
			atomic_set(&apic->lapic_timer.pending, 0);
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1483 1484 1485

		}
		break;
1486
	}
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	case APIC_ICR:
		/* No delay here, so we always clear the pending bit */
		apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
		apic_send_ipi(apic);
		break;

	case APIC_ICR2:
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		if (!apic_x2apic_mode(apic))
			val &= 0xff000000;
		apic_set_reg(apic, APIC_ICR2, val);
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		break;

1499
	case APIC_LVT0:
1500
		apic_manage_nmi_watchdog(apic, val);
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1501 1502 1503 1504 1505
	case APIC_LVTTHMR:
	case APIC_LVTPC:
	case APIC_LVT1:
	case APIC_LVTERR:
		/* TODO: Check vector */
1506
		if (!kvm_apic_sw_enabled(apic))
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			val |= APIC_LVT_MASKED;

G
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1509 1510
		val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
		apic_set_reg(apic, reg, val);
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1511 1512 1513

		break;

1514
	case APIC_LVTT:
1515
		if (!kvm_apic_sw_enabled(apic))
1516 1517 1518
			val |= APIC_LVT_MASKED;
		val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
		apic_set_reg(apic, APIC_LVTT, val);
1519
		apic_update_lvtt(apic);
1520 1521
		break;

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1522
	case APIC_TMICT:
1523 1524 1525
		if (apic_lvtt_tscdeadline(apic))
			break;

1526
		hrtimer_cancel(&apic->lapic_timer.timer);
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		apic_set_reg(apic, APIC_TMICT, val);
		start_apic_timer(apic);
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1529
		break;
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1530 1531 1532

	case APIC_TDCR:
		if (val & 4)
1533
			apic_debug("KVM_WRITE:TDCR %x\n", val);
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		apic_set_reg(apic, APIC_TDCR, val);
		update_divide_count(apic);
		break;

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1538 1539
	case APIC_ESR:
		if (apic_x2apic_mode(apic) && val != 0) {
1540
			apic_debug("KVM_WRITE:ESR not zero %x\n", val);
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			ret = 1;
		}
		break;

	case APIC_SELF_IPI:
		if (apic_x2apic_mode(apic)) {
			apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
		} else
			ret = 1;
		break;
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1551
	default:
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1552
		ret = 1;
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1553 1554
		break;
	}
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	if (ret)
		apic_debug("Local APIC Write to read-only register %x\n", reg);
	return ret;
}

1560
static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
G
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1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577
			    gpa_t address, int len, const void *data)
{
	struct kvm_lapic *apic = to_lapic(this);
	unsigned int offset = address - apic->base_address;
	u32 val;

	if (!apic_mmio_in_range(apic, address))
		return -EOPNOTSUPP;

	/*
	 * APIC register must be aligned on 128-bits boundary.
	 * 32/64/128 bits registers must be accessed thru 32 bits.
	 * Refer SDM 8.4.1
	 */
	if (len != 4 || (offset & 0xf)) {
		/* Don't shout loud, $infamous_os would cause only noise. */
		apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1578
		return 0;
G
Gleb Natapov 已提交
1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589
	}

	val = *(u32*)data;

	/* too common printing */
	if (offset != APIC_EOI)
		apic_debug("%s: offset 0x%x with length 0x%x, and value is "
			   "0x%x\n", __func__, offset, len, val);

	apic_reg_write(apic, offset & 0xff0, val);

1590
	return 0;
E
Eddie Dong 已提交
1591 1592
}

1593 1594
void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
{
1595
	apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1596 1597 1598
}
EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);

1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613
/* emulate APIC access in a trap manner */
void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
{
	u32 val = 0;

	/* hw has done the conditional check and inst decode */
	offset &= 0xff0;

	apic_reg_read(vcpu->arch.apic, offset, 4, &val);

	/* TODO: optimize to just emulate side effect w/o one more write */
	apic_reg_write(vcpu->arch.apic, offset, val);
}
EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);

1614
void kvm_free_lapic(struct kvm_vcpu *vcpu)
E
Eddie Dong 已提交
1615
{
1616 1617
	struct kvm_lapic *apic = vcpu->arch.apic;

1618
	if (!vcpu->arch.apic)
E
Eddie Dong 已提交
1619 1620
		return;

1621
	hrtimer_cancel(&apic->lapic_timer.timer);
E
Eddie Dong 已提交
1622

1623 1624 1625
	if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
		static_key_slow_dec_deferred(&apic_hw_disabled);

1626
	if (!apic->sw_enabled)
1627
		static_key_slow_dec_deferred(&apic_sw_disabled);
E
Eddie Dong 已提交
1628

1629 1630 1631 1632
	if (apic->regs)
		free_page((unsigned long)apic->regs);

	kfree(apic);
E
Eddie Dong 已提交
1633 1634 1635 1636 1637 1638 1639 1640
}

/*
 *----------------------------------------------------------------------
 * LAPIC interface
 *----------------------------------------------------------------------
 */

1641 1642 1643 1644
u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
{
	struct kvm_lapic *apic = vcpu->arch.apic;

1645
	if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1646
			apic_lvtt_period(apic))
1647 1648 1649 1650 1651 1652 1653 1654 1655
		return 0;

	return apic->lapic_timer.tscdeadline;
}

void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
{
	struct kvm_lapic *apic = vcpu->arch.apic;

1656
	if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1657
			apic_lvtt_period(apic))
1658 1659 1660 1661 1662 1663 1664
		return;

	hrtimer_cancel(&apic->lapic_timer.timer);
	apic->lapic_timer.tscdeadline = data;
	start_apic_timer(apic);
}

E
Eddie Dong 已提交
1665 1666
void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
{
1667
	struct kvm_lapic *apic = vcpu->arch.apic;
E
Eddie Dong 已提交
1668

A
Avi Kivity 已提交
1669
	apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1670
		     | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
E
Eddie Dong 已提交
1671 1672 1673 1674 1675 1676
}

u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
{
	u64 tpr;

1677
	tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
E
Eddie Dong 已提交
1678 1679 1680 1681 1682 1683

	return (tpr & 0xf0) >> 4;
}

void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
{
1684
	u64 old_value = vcpu->arch.apic_base;
1685
	struct kvm_lapic *apic = vcpu->arch.apic;
E
Eddie Dong 已提交
1686 1687 1688

	if (!apic) {
		value |= MSR_IA32_APICBASE_BSP;
1689
		vcpu->arch.apic_base = value;
E
Eddie Dong 已提交
1690 1691
		return;
	}
1692

1693 1694
	vcpu->arch.apic_base = value;

1695
	/* update jump label if enable bit changes */
1696
	if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1697 1698 1699 1700
		if (value & MSR_IA32_APICBASE_ENABLE)
			static_key_slow_dec_deferred(&apic_hw_disabled);
		else
			static_key_slow_inc(&apic_hw_disabled.key);
1701
		recalculate_apic_map(vcpu->kvm);
1702 1703
	}

1704 1705
	if ((old_value ^ value) & X2APIC_ENABLE) {
		if (value & X2APIC_ENABLE) {
1706
			kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1707 1708 1709
			kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
		} else
			kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
G
Gleb Natapov 已提交
1710
	}
1711

1712
	apic->base_address = apic->vcpu->arch.apic_base &
E
Eddie Dong 已提交
1713 1714
			     MSR_IA32_APICBASE_BASE;

1715 1716 1717 1718
	if ((value & MSR_IA32_APICBASE_ENABLE) &&
	     apic->base_address != APIC_DEFAULT_PHYS_BASE)
		pr_warn_once("APIC base relocation is unsupported by KVM");

E
Eddie Dong 已提交
1719 1720
	/* with FSB delivery interrupt, we can restart APIC functionality */
	apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1721
		   "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
E
Eddie Dong 已提交
1722 1723 1724

}

1725
void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
E
Eddie Dong 已提交
1726 1727 1728 1729
{
	struct kvm_lapic *apic;
	int i;

1730
	apic_debug("%s\n", __func__);
E
Eddie Dong 已提交
1731 1732

	ASSERT(vcpu);
1733
	apic = vcpu->arch.apic;
E
Eddie Dong 已提交
1734 1735 1736
	ASSERT(apic != NULL);

	/* Stop the timer in case it's a reset to an active apic */
1737
	hrtimer_cancel(&apic->lapic_timer.timer);
E
Eddie Dong 已提交
1738

1739 1740
	if (!init_event)
		kvm_apic_set_id(apic, vcpu->vcpu_id);
1741
	kvm_apic_set_version(apic->vcpu);
E
Eddie Dong 已提交
1742 1743 1744

	for (i = 0; i < APIC_LVT_NUM; i++)
		apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1745
	apic_update_lvtt(apic);
1746
	if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1747 1748
		apic_set_reg(apic, APIC_LVT0,
			     SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1749
	apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
E
Eddie Dong 已提交
1750 1751

	apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1752
	apic_set_spiv(apic, 0xff);
E
Eddie Dong 已提交
1753
	apic_set_reg(apic, APIC_TASKPRI, 0);
1754 1755
	if (!apic_x2apic_mode(apic))
		kvm_apic_set_ldr(apic, 0);
E
Eddie Dong 已提交
1756 1757 1758 1759 1760 1761 1762 1763 1764 1765
	apic_set_reg(apic, APIC_ESR, 0);
	apic_set_reg(apic, APIC_ICR, 0);
	apic_set_reg(apic, APIC_ICR2, 0);
	apic_set_reg(apic, APIC_TDCR, 0);
	apic_set_reg(apic, APIC_TMICT, 0);
	for (i = 0; i < 8; i++) {
		apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
		apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
		apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
	}
1766 1767
	apic->irr_pending = vcpu->arch.apicv_active;
	apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
M
Michael S. Tsirkin 已提交
1768
	apic->highest_isr_cache = -1;
1769
	update_divide_count(apic);
1770
	atomic_set(&apic->lapic_timer.pending, 0);
1771
	if (kvm_vcpu_is_bsp(vcpu))
1772 1773
		kvm_lapic_set_base(vcpu,
				vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1774
	vcpu->arch.pv_eoi.msr_val = 0;
E
Eddie Dong 已提交
1775 1776
	apic_update_ppr(apic);

1777
	vcpu->arch.apic_arb_prio = 0;
1778
	vcpu->arch.apic_attention = 0;
1779

N
Nadav Amit 已提交
1780
	apic_debug("%s: vcpu=%p, id=%d, base_msr="
1781
		   "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
E
Eddie Dong 已提交
1782
		   vcpu, kvm_apic_id(apic),
1783
		   vcpu->arch.apic_base, apic->base_address);
E
Eddie Dong 已提交
1784 1785 1786 1787 1788 1789 1790
}

/*
 *----------------------------------------------------------------------
 * timer interface
 *----------------------------------------------------------------------
 */
1791

A
Avi Kivity 已提交
1792
static bool lapic_is_periodic(struct kvm_lapic *apic)
E
Eddie Dong 已提交
1793
{
1794
	return apic_lvtt_period(apic);
E
Eddie Dong 已提交
1795 1796
}

1797 1798
int apic_has_pending_timer(struct kvm_vcpu *vcpu)
{
1799
	struct kvm_lapic *apic = vcpu->arch.apic;
1800

1801
	if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
1802
		return atomic_read(&apic->lapic_timer.pending);
1803 1804 1805 1806

	return 0;
}

A
Avi Kivity 已提交
1807
int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1808
{
1809
	u32 reg = kvm_apic_get_reg(apic, lvt_type);
1810 1811
	int vector, mode, trig_mode;

1812
	if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1813 1814 1815
		vector = reg & APIC_VECTOR_MASK;
		mode = reg & APIC_MODE_MASK;
		trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1816 1817
		return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
					NULL);
1818 1819 1820
	}
	return 0;
}
1821

1822
void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1823
{
1824 1825 1826 1827
	struct kvm_lapic *apic = vcpu->arch.apic;

	if (apic)
		kvm_apic_local_deliver(apic, APIC_LVT0);
1828 1829
}

G
Gregory Haskins 已提交
1830 1831 1832 1833 1834
static const struct kvm_io_device_ops apic_mmio_ops = {
	.read     = apic_mmio_read,
	.write    = apic_mmio_write,
};

1835 1836 1837
static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
{
	struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
A
Avi Kivity 已提交
1838
	struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1839

1840
	apic_timer_expired(apic);
1841

A
Avi Kivity 已提交
1842
	if (lapic_is_periodic(apic)) {
1843 1844 1845 1846 1847 1848
		hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
		return HRTIMER_RESTART;
	} else
		return HRTIMER_NORESTART;
}

E
Eddie Dong 已提交
1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859
int kvm_create_lapic(struct kvm_vcpu *vcpu)
{
	struct kvm_lapic *apic;

	ASSERT(vcpu != NULL);
	apic_debug("apic_init %d\n", vcpu->vcpu_id);

	apic = kzalloc(sizeof(*apic), GFP_KERNEL);
	if (!apic)
		goto nomem;

1860
	vcpu->arch.apic = apic;
E
Eddie Dong 已提交
1861

1862 1863
	apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
	if (!apic->regs) {
E
Eddie Dong 已提交
1864 1865
		printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
		       vcpu->vcpu_id);
1866
		goto nomem_free_apic;
E
Eddie Dong 已提交
1867 1868 1869
	}
	apic->vcpu = vcpu;

1870
	hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1871
		     HRTIMER_MODE_ABS_PINNED);
1872
	apic->lapic_timer.timer.function = apic_timer_fn;
1873

1874 1875 1876 1877 1878
	/*
	 * APIC is created enabled. This will prevent kvm_lapic_set_base from
	 * thinking that APIC satet has changed.
	 */
	vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1879 1880
	kvm_lapic_set_base(vcpu,
			APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
E
Eddie Dong 已提交
1881

1882
	static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1883
	kvm_lapic_reset(vcpu, false);
G
Gregory Haskins 已提交
1884
	kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
E
Eddie Dong 已提交
1885 1886

	return 0;
1887 1888
nomem_free_apic:
	kfree(apic);
E
Eddie Dong 已提交
1889 1890 1891 1892 1893 1894
nomem:
	return -ENOMEM;
}

int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
{
1895
	struct kvm_lapic *apic = vcpu->arch.apic;
E
Eddie Dong 已提交
1896 1897
	int highest_irr;

1898
	if (!apic_enabled(apic))
E
Eddie Dong 已提交
1899 1900
		return -1;

1901
	apic_update_ppr(apic);
E
Eddie Dong 已提交
1902 1903
	highest_irr = apic_find_highest_irr(apic);
	if ((highest_irr == -1) ||
1904
	    ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
E
Eddie Dong 已提交
1905 1906 1907 1908
		return -1;
	return highest_irr;
}

Q
Qing He 已提交
1909 1910
int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
{
1911
	u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
Q
Qing He 已提交
1912 1913
	int r = 0;

1914
	if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1915 1916 1917 1918
		r = 1;
	if ((lvt0 & APIC_LVT_MASKED) == 0 &&
	    GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
		r = 1;
Q
Qing He 已提交
1919 1920 1921
	return r;
}

1922 1923
void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
{
1924
	struct kvm_lapic *apic = vcpu->arch.apic;
1925

1926
	if (atomic_read(&apic->lapic_timer.pending) > 0) {
1927
		kvm_apic_local_deliver(apic, APIC_LVTT);
1928 1929
		if (apic_lvtt_tscdeadline(apic))
			apic->lapic_timer.tscdeadline = 0;
1930
		atomic_set(&apic->lapic_timer.pending, 0);
1931 1932 1933
	}
}

E
Eddie Dong 已提交
1934 1935 1936
int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
{
	int vector = kvm_apic_has_interrupt(vcpu);
1937
	struct kvm_lapic *apic = vcpu->arch.apic;
E
Eddie Dong 已提交
1938 1939 1940 1941

	if (vector == -1)
		return -1;

1942 1943 1944 1945 1946 1947 1948
	/*
	 * We get here even with APIC virtualization enabled, if doing
	 * nested virtualization and L1 runs with the "acknowledge interrupt
	 * on exit" mode.  Then we cannot inject the interrupt via RVI,
	 * because the process would deliver it through the IDT.
	 */

M
Michael S. Tsirkin 已提交
1949
	apic_set_isr(vector, apic);
E
Eddie Dong 已提交
1950 1951
	apic_update_ppr(apic);
	apic_clear_irr(vector, apic);
1952 1953 1954 1955 1956 1957

	if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
		apic_clear_isr(vector, apic);
		apic_update_ppr(apic);
	}

E
Eddie Dong 已提交
1958 1959
	return vector;
}
1960

1961 1962
void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
		struct kvm_lapic_state *s)
1963
{
1964
	struct kvm_lapic *apic = vcpu->arch.apic;
1965

1966
	kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1967 1968 1969
	/* set SPIV separately to get count of SW disabled APICs right */
	apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
	memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1970 1971
	/* call kvm_apic_set_id() to put apic into apic_map */
	kvm_apic_set_id(apic, kvm_apic_id(apic));
1972 1973
	kvm_apic_set_version(vcpu);

1974
	apic_update_ppr(apic);
1975
	hrtimer_cancel(&apic->lapic_timer.timer);
1976
	apic_update_lvtt(apic);
1977
	apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
1978 1979
	update_divide_count(apic);
	start_apic_timer(apic);
1980
	apic->irr_pending = true;
1981
	apic->isr_count = vcpu->arch.apicv_active ?
1982
				1 : count_vectors(apic->regs + APIC_ISR);
M
Michael S. Tsirkin 已提交
1983
	apic->highest_isr_cache = -1;
1984
	if (vcpu->arch.apicv_active) {
W
Wei Wang 已提交
1985 1986
		kvm_x86_ops->hwapic_irr_update(vcpu,
				apic_find_highest_irr(apic));
1987 1988
		kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
				apic_find_highest_isr(apic));
1989
	}
1990
	kvm_make_request(KVM_REQ_EVENT, vcpu);
1991 1992
	if (ioapic_in_kernel(vcpu->kvm))
		kvm_rtc_eoi_tracking_restore_one(vcpu);
1993 1994

	vcpu->arch.apic_arb_prio = 0;
1995
}
1996

1997
void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1998 1999 2000
{
	struct hrtimer *timer;

2001
	if (!lapic_in_kernel(vcpu))
2002 2003
		return;

2004
	timer = &vcpu->arch.apic->lapic_timer.timer;
2005
	if (hrtimer_cancel(timer))
2006
		hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2007
}
A
Avi Kivity 已提交
2008

2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045
/*
 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
 *
 * Detect whether guest triggered PV EOI since the
 * last entry. If yes, set EOI on guests's behalf.
 * Clear PV EOI in guest memory in any case.
 */
static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
					struct kvm_lapic *apic)
{
	bool pending;
	int vector;
	/*
	 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
	 * and KVM_PV_EOI_ENABLED in guest memory as follows:
	 *
	 * KVM_APIC_PV_EOI_PENDING is unset:
	 * 	-> host disabled PV EOI.
	 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
	 * 	-> host enabled PV EOI, guest did not execute EOI yet.
	 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
	 * 	-> host enabled PV EOI, guest executed EOI.
	 */
	BUG_ON(!pv_eoi_enabled(vcpu));
	pending = pv_eoi_get_pending(vcpu);
	/*
	 * Clear pending bit in any case: it will be set again on vmentry.
	 * While this might not be ideal from performance point of view,
	 * this makes sure pv eoi is only enabled when we know it's safe.
	 */
	pv_eoi_clr_pending(vcpu);
	if (pending)
		return;
	vector = apic_set_eoi(apic);
	trace_kvm_pv_eoi(apic, vector);
}

A
Avi Kivity 已提交
2046 2047 2048 2049
void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
{
	u32 data;

2050 2051 2052
	if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
		apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);

2053
	if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
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		return;

2056 2057 2058
	if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
				  sizeof(u32)))
		return;
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	apic_set_tpr(vcpu->arch.apic, data & 0xff);
}

2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077
/*
 * apic_sync_pv_eoi_to_guest - called before vmentry
 *
 * Detect whether it's safe to enable PV EOI and
 * if yes do so.
 */
static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
					struct kvm_lapic *apic)
{
	if (!pv_eoi_enabled(vcpu) ||
	    /* IRR set or many bits in ISR: could be nested. */
	    apic->irr_pending ||
	    /* Cache not set: could be safe but we don't bother. */
	    apic->highest_isr_cache == -1 ||
	    /* Need EOI to update ioapic. */
2078
	    kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2079 2080 2081 2082 2083 2084 2085 2086 2087 2088
		/*
		 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
		 * so we need not do anything here.
		 */
		return;
	}

	pv_eoi_set_pending(apic->vcpu);
}

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void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
{
	u32 data, tpr;
	int max_irr, max_isr;
2093
	struct kvm_lapic *apic = vcpu->arch.apic;
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2095 2096
	apic_sync_pv_eoi_to_guest(vcpu, apic);

2097
	if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
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		return;

2100
	tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
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	max_irr = apic_find_highest_irr(apic);
	if (max_irr < 0)
		max_irr = 0;
	max_isr = apic_find_highest_isr(apic);
	if (max_isr < 0)
		max_isr = 0;
	data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);

2109 2110
	kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
				sizeof(u32));
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}

2113
int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
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{
2115 2116 2117 2118 2119
	if (vapic_addr) {
		if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
					&vcpu->arch.apic->vapic_cache,
					vapic_addr, sizeof(u32)))
			return -EINVAL;
2120
		__set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2121
	} else {
2122
		__clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2123 2124 2125 2126
	}

	vcpu->arch.apic->vapic_addr = vapic_addr;
	return 0;
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}
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int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
{
	struct kvm_lapic *apic = vcpu->arch.apic;
	u32 reg = (msr - APIC_BASE_MSR) << 4;

2134
	if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
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		return 1;

2137 2138 2139
	if (reg == APIC_ICR2)
		return 1;

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	/* if this is ICR write vector before command */
2141
	if (reg == APIC_ICR)
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		apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
	return apic_reg_write(apic, reg, (u32)data);
}

int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
{
	struct kvm_lapic *apic = vcpu->arch.apic;
	u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;

2151
	if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
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		return 1;

2154 2155 2156 2157 2158 2159
	if (reg == APIC_DFR || reg == APIC_ICR2) {
		apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
			   reg);
		return 1;
	}

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	if (apic_reg_read(apic, reg, 4, &low))
		return 1;
2162
	if (reg == APIC_ICR)
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		apic_reg_read(apic, APIC_ICR2, 4, &high);

	*data = (((u64)high) << 32) | low;

	return 0;
}
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int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
{
	struct kvm_lapic *apic = vcpu->arch.apic;

2174
	if (!lapic_in_kernel(vcpu))
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		return 1;

	/* if this is ICR write vector before command */
	if (reg == APIC_ICR)
		apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
	return apic_reg_write(apic, reg, (u32)data);
}

int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
{
	struct kvm_lapic *apic = vcpu->arch.apic;
	u32 low, high = 0;

2188
	if (!lapic_in_kernel(vcpu))
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2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199
		return 1;

	if (apic_reg_read(apic, reg, 4, &low))
		return 1;
	if (reg == APIC_ICR)
		apic_reg_read(apic, APIC_ICR2, 4, &high);

	*data = (((u64)high) << 32) | low;

	return 0;
}
2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210

int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
{
	u64 addr = data & ~KVM_MSR_ENABLED;
	if (!IS_ALIGNED(addr, 4))
		return 1;

	vcpu->arch.pv_eoi.msr_val = data;
	if (!pv_eoi_enabled(vcpu))
		return 0;
	return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2211
					 addr, sizeof(u8));
2212
}
2213

2214 2215 2216
void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
{
	struct kvm_lapic *apic = vcpu->arch.apic;
2217
	u8 sipi_vector;
2218
	unsigned long pe;
2219

2220
	if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2221 2222
		return;

2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233
	/*
	 * INITs are latched while in SMM.  Because an SMM CPU cannot
	 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
	 * and delay processing of INIT until the next RSM.
	 */
	if (is_smm(vcpu)) {
		WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
		if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
			clear_bit(KVM_APIC_SIPI, &apic->pending_events);
		return;
	}
2234

2235
	pe = xchg(&apic->pending_events, 0);
2236
	if (test_bit(KVM_APIC_INIT, &pe)) {
2237 2238
		kvm_lapic_reset(vcpu, true);
		kvm_vcpu_reset(vcpu, true);
2239 2240 2241 2242 2243
		if (kvm_vcpu_is_bsp(apic->vcpu))
			vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
		else
			vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
	}
2244
	if (test_bit(KVM_APIC_SIPI, &pe) &&
2245 2246 2247 2248
	    vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
		/* evaluate pending_events before reading the vector */
		smp_rmb();
		sipi_vector = apic->sipi_vector;
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		apic_debug("vcpu %d received sipi with vector # %x\n",
2250 2251 2252 2253 2254 2255
			 vcpu->vcpu_id, sipi_vector);
		kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
		vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
	}
}

2256 2257 2258 2259
void kvm_lapic_init(void)
{
	/* do not patch jump label more than once per second */
	jump_label_rate_limit(&apic_hw_disabled, HZ);
2260
	jump_label_rate_limit(&apic_sw_disabled, HZ);
2261
}