io_64.h 10.6 KB
Newer Older
1 2 3 4 5 6 7 8 9
#ifndef __SPARC64_IO_H
#define __SPARC64_IO_H

#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/types.h>

#include <asm/page.h>      /* IO address mapping routines need this */
#include <asm/asi.h>
10
#include <asm-generic/pci_iomap.h>
11 12 13 14

/* BIO layer definitions. */
extern unsigned long kern_base, kern_size;

15 16 17 18 19 20
/* __raw_{read,write}{b,w,l,q} uses direct access.
 * Access the memory as big endian bypassing the cache
 * by using ASI_PHYS_BYPASS_EC_E
 */
#define __raw_readb __raw_readb
static inline u8 __raw_readb(const volatile void __iomem *addr)
21 22 23
{
	u8 ret;

24
	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
25
			     : "=r" (ret)
26
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
27 28 29 30

	return ret;
}

31 32
#define __raw_readw __raw_readw
static inline u16 __raw_readw(const volatile void __iomem *addr)
33 34 35
{
	u16 ret;

36
	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
37
			     : "=r" (ret)
38
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
39 40 41 42

	return ret;
}

43 44
#define __raw_readl __raw_readl
static inline u32 __raw_readl(const volatile void __iomem *addr)
45 46 47
{
	u32 ret;

48
	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
49
			     : "=r" (ret)
50
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
51 52 53 54

	return ret;
}

55 56
#define __raw_readq __raw_readq
static inline u64 __raw_readq(const volatile void __iomem *addr)
57
{
58
	u64 ret;
59

60 61 62
	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
63

64
	return ret;
65 66
}

67 68
#define __raw_writeb __raw_writeb
static inline void __raw_writeb(u8 b, const volatile void __iomem *addr)
69
{
70 71 72
	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
			     : /* no outputs */
			     : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
73 74
}

75 76
#define __raw_writew __raw_writew
static inline void __raw_writew(u16 w, const volatile void __iomem *addr)
77
{
78 79 80
	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
			     : /* no outputs */
			     : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
81 82
}

83 84
#define __raw_writel __raw_writel
static inline void __raw_writel(u32 l, const volatile void __iomem *addr)
85
{
86 87 88
	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
89 90
}

91 92
#define __raw_writeq __raw_writeq
static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
93
{
94 95 96
	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
			     : /* no outputs */
			     : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
97 98
}

99 100 101 102
/* Memory functions, same as I/O accesses on Ultra.
 * Access memory as little endian bypassing
 * the cache by using ASI_PHYS_BYPASS_EC_E_L
 */
103
#define readb readb
104
#define readb_relaxed readb
105
static inline u8 readb(const volatile void __iomem *addr)
106 107 108 109 110 111 112 113 114
{	u8 ret;

	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
	return ret;
}

115
#define readw readw
116
#define readw_relaxed readw
117
static inline u16 readw(const volatile void __iomem *addr)
118 119 120 121 122 123 124 125 126 127
{	u16 ret;

	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");

	return ret;
}

128
#define readl readl
129
#define readl_relaxed readl
130
static inline u32 readl(const volatile void __iomem *addr)
131 132 133 134 135 136 137 138 139 140
{	u32 ret;

	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");

	return ret;
}

141
#define readq readq
142
#define readq_relaxed readq
143
static inline u64 readq(const volatile void __iomem *addr)
144 145 146 147 148 149 150 151 152 153
{	u64 ret;

	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");

	return ret;
}

154
#define writeb writeb
155
#define writeb_relaxed writeb
156
static inline void writeb(u8 b, volatile void __iomem *addr)
157 158 159 160 161 162 163
{
	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
			     : /* no outputs */
			     : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

164
#define writew writew
165
#define writew_relaxed writew
166
static inline void writew(u16 w, volatile void __iomem *addr)
167 168 169 170 171 172 173
{
	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
			     : /* no outputs */
			     : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

174
#define writel writel
175
#define writel_relaxed writel
176
static inline void writel(u32 l, volatile void __iomem *addr)
177 178 179 180 181 182 183
{
	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

184
#define writeq writeq
185
#define writeq_relaxed writeq
186
static inline void writeq(u64 q, volatile void __iomem *addr)
187 188 189 190 191 192 193
{
	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
			     : /* no outputs */
			     : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

194 195
#define inb inb
static inline u8 inb(unsigned long addr)
196
{
197
	return readb((volatile void __iomem *)addr);
198 199
}

200 201
#define inw inw
static inline u16 inw(unsigned long addr)
202
{
203
	return readw((volatile void __iomem *)addr);
204 205
}

206 207
#define inl inl
static inline u32 inl(unsigned long addr)
208
{
209
	return readl((volatile void __iomem *)addr);
210 211
}

212 213
#define outb outb
static inline void outb(u8 b, unsigned long addr)
214
{
215
	writeb(b, (volatile void __iomem *)addr);
216 217
}

218 219
#define outw outw
static inline void outw(u16 w, unsigned long addr)
220
{
221
	writew(w, (volatile void __iomem *)addr);
222 223
}

224 225
#define outl outl
static inline void outl(u32 l, unsigned long addr)
226
{
227
	writel(l, (volatile void __iomem *)addr);
228 229
}

230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245

#define inb_p(__addr) 		inb(__addr)
#define outb_p(__b, __addr)	outb(__b, __addr)
#define inw_p(__addr)		inw(__addr)
#define outw_p(__w, __addr)	outw(__w, __addr)
#define inl_p(__addr)		inl(__addr)
#define outl_p(__l, __addr)	outl(__l, __addr)

void outsb(unsigned long, const void *, unsigned long);
void outsw(unsigned long, const void *, unsigned long);
void outsl(unsigned long, const void *, unsigned long);
void insb(unsigned long, void *, unsigned long);
void insw(unsigned long, void *, unsigned long);
void insl(unsigned long, void *, unsigned long);

static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
246
{
247 248 249 250 251
	insb((unsigned long __force)port, buf, count);
}
static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
{
	insw((unsigned long __force)port, buf, count);
252 253
}

254
static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
255
{
256 257 258 259 260 261
	insl((unsigned long __force)port, buf, count);
}

static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
{
	outsb((unsigned long __force)port, buf, count);
262 263
}

264 265 266 267 268 269 270 271 272 273
static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
{
	outsw((unsigned long __force)port, buf, count);
}

static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
{
	outsl((unsigned long __force)port, buf, count);
}

274 275 276 277 278 279 280 281
/* Valid I/O Space regions are anywhere, because each PCI bus supported
 * can live in an arbitrary area of the physical address range.
 */
#define IO_SPACE_LIMIT 0xffffffffffffffffUL

/* Now, SBUS variants, only difference from PCI is that we do
 * not use little-endian ASIs.
 */
282
static inline u8 sbus_readb(const volatile void __iomem *addr)
283
{
284
	return __raw_readb(addr);
285 286
}

287
static inline u16 sbus_readw(const volatile void __iomem *addr)
288
{
289
	return __raw_readw(addr);
290 291
}

292
static inline u32 sbus_readl(const volatile void __iomem *addr)
293
{
294
	return __raw_readl(addr);
295 296
}

297
static inline u64 sbus_readq(const volatile void __iomem *addr)
298
{
299
	return __raw_readq(addr);
300 301
}

302
static inline void sbus_writeb(u8 b, volatile void __iomem *addr)
303
{
304
	__raw_writeb(b, addr);
305 306
}

307
static inline void sbus_writew(u16 w, volatile void __iomem *addr)
308
{
309
	__raw_writew(w, addr);
310 311
}

312
static inline void sbus_writel(u32 l, volatile void __iomem *addr)
313
{
314
	__raw_writel(l, addr);
315 316
}

317
static inline void sbus_writeq(u64 q, volatile void __iomem *addr)
318
{
319
	__raw_writeq(q, addr);
320 321
}

322
static inline void sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
323 324 325 326 327 328 329
{
	while(n--) {
		sbus_writeb(c, dst);
		dst++;
	}
}

330
static inline void memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
331 332 333 334 335 336 337 338 339
{
	volatile void __iomem *d = dst;

	while (n--) {
		writeb(c, d);
		d++;
	}
}

340 341
static inline void sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
				      __kernel_size_t n)
342 343 344 345 346 347 348 349 350 351 352
{
	char *d = dst;

	while (n--) {
		char tmp = sbus_readb(src);
		*d++ = tmp;
		src++;
	}
}


353 354
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
				 __kernel_size_t n)
355 356 357 358 359 360 361 362 363 364
{
	char *d = dst;

	while (n--) {
		char tmp = readb(src);
		*d++ = tmp;
		src++;
	}
}

365 366
static inline void sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
				    __kernel_size_t n)
367 368 369 370 371 372 373 374 375 376 377
{
	const char *s = src;
	volatile void __iomem *d = dst;

	while (n--) {
		char tmp = *s++;
		sbus_writeb(tmp, d);
		d++;
	}
}

378 379
static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
			       __kernel_size_t n)
380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403
{
	const char *s = src;
	volatile void __iomem *d = dst;

	while (n--) {
		char tmp = *s++;
		writeb(tmp, d);
		d++;
	}
}

#define mmiowb()

#ifdef __KERNEL__

/* On sparc64 we have the whole physical IO address space accessible
 * using physically addressed loads and stores, so this does nothing.
 */
static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
{
	return (void __iomem *)offset;
}

#define ioremap_nocache(X,Y)		ioremap((X),(Y))
404
#define ioremap_wc(X,Y)			ioremap((X),(Y))
405
#define ioremap_wt(X,Y)			ioremap((X),(Y))
406 407 408 409 410

static inline void iounmap(volatile void __iomem *addr)
{
}

411 412 413 414 415 416 417 418 419 420
#define ioread8			readb
#define ioread16		readw
#define ioread16be		__raw_readw
#define ioread32		readl
#define ioread32be		__raw_readl
#define iowrite8		writeb
#define iowrite16		writew
#define iowrite16be		__raw_writew
#define iowrite32		writel
#define iowrite32be		__raw_writel
421 422

/* Create a virtual mapping cookie for an IO port range */
423 424
void __iomem *ioport_map(unsigned long port, unsigned int nr);
void ioport_unmap(void __iomem *);
425 426 427

/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
struct pci_dev;
428
void pci_iounmap(struct pci_dev *dev, void __iomem *);
429

430 431 432 433 434 435 436 437 438
static inline int sbus_can_dma_64bit(void)
{
	return 1;
}
static inline int sbus_can_burst64(void)
{
	return 1;
}
struct device;
439
void sbus_set_sbus64(struct device *, int);
440

441 442 443 444 445 446 447 448 449 450 451 452 453 454
/*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
#define xlate_dev_mem_ptr(p)	__va(p)

/*
 * Convert a virtual cached pointer to an uncached pointer
 */
#define xlate_dev_kmem_ptr(p)	p

#endif

#endif /* !(__SPARC64_IO_H) */