sdi.c 8.1 KB
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/*
 * Copyright (C) 2009 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#define DSS_SUBSYS_NAME "SDI"

#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/err.h>
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#include <linux/regulator/consumer.h>
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#include <linux/export.h>
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#include <linux/platform_device.h>
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#include <linux/string.h>
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#include <linux/of.h>
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#include "omapdss.h"
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#include "dss.h"

static struct {
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	struct platform_device *pdev;
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	struct dss_device *dss;
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	bool update_enabled;
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	struct regulator *vdds_sdi_reg;
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	struct dss_lcd_mgr_config mgr_config;
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	struct videomode vm;
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	int datapairs;
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	struct omap_dss_device output;
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	bool port_initialized;
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} sdi;
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struct sdi_clk_calc_ctx {
	unsigned long pck_min, pck_max;

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	unsigned long fck;
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	struct dispc_clock_info dispc_cinfo;
};

static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
		unsigned long pck, void *data)
{
	struct sdi_clk_calc_ctx *ctx = data;

	ctx->dispc_cinfo.lck_div = lckd;
	ctx->dispc_cinfo.pck_div = pckd;
	ctx->dispc_cinfo.lck = lck;
	ctx->dispc_cinfo.pck = pck;

	return true;
}

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static bool dpi_calc_dss_cb(unsigned long fck, void *data)
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{
	struct sdi_clk_calc_ctx *ctx = data;

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	ctx->fck = fck;
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	return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
			dpi_calc_dispc_cb, ctx);
}

static int sdi_calc_clock_div(unsigned long pclk,
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		unsigned long *fck,
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		struct dispc_clock_info *dispc_cinfo)
{
	int i;
	struct sdi_clk_calc_ctx ctx;

	/*
	 * DSS fclk gives us very few possibilities, so finding a good pixel
	 * clock may not be possible. We try multiple times to find the clock,
	 * each time widening the pixel clock range we look for, up to
	 * +/- 1MHz.
	 */

	for (i = 0; i < 10; ++i) {
		bool ok;

		memset(&ctx, 0, sizeof(ctx));
		if (pclk > 1000 * i * i * i)
			ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
		else
			ctx.pck_min = 0;
		ctx.pck_max = pclk + 1000 * i * i * i;

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		ok = dss_div_calc(sdi.dss, pclk, ctx.pck_min,
				  dpi_calc_dss_cb, &ctx);
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		if (ok) {
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			*fck = ctx.fck;
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			*dispc_cinfo = ctx.dispc_cinfo;
			return 0;
		}
	}

	return -EINVAL;
}

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static void sdi_config_lcd_manager(struct omap_dss_device *dssdev)
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{
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	sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
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	sdi.mgr_config.stallmode = false;
	sdi.mgr_config.fifohandcheck = false;

	sdi.mgr_config.video_port_width = 24;
	sdi.mgr_config.lcden_sig_polarity = 1;

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	dss_mgr_set_lcd_config(&sdi.output, &sdi.mgr_config);
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}

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static int sdi_display_enable(struct omap_dss_device *dssdev)
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{
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	struct videomode *vm = &sdi.vm;
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	unsigned long fck;
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	struct dispc_clock_info dispc_cinfo;
	unsigned long pck;
	int r;

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	if (!sdi.output.dispc_channel_connected) {
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		DSSERR("failed to enable display: no output/manager\n");
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		return -ENODEV;
	}

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	r = regulator_enable(sdi.vdds_sdi_reg);
	if (r)
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		goto err_reg_enable;
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	r = dispc_runtime_get(sdi.dss->dispc);
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	if (r)
		goto err_get_dispc;
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	/* 15.5.9.1.2 */
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	vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE;
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	r = sdi_calc_clock_div(vm->pixelclock, &fck, &dispc_cinfo);
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	if (r)
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		goto err_calc_clock_div;
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	sdi.mgr_config.clock_info = dispc_cinfo;
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	pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
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	if (pck != vm->pixelclock) {
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		DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n",
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			vm->pixelclock, pck);
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		vm->pixelclock = pck;
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	}


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	dss_mgr_set_timings(&sdi.output, vm);
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	r = dss_set_fck_rate(sdi.dss, fck);
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	if (r)
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		goto err_set_dss_clock_div;
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	sdi_config_lcd_manager(dssdev);
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	/*
	 * LCLK and PCLK divisors are located in shadow registers, and we
	 * normally write them to DISPC registers when enabling the output.
	 * However, SDI uses pck-free as source clock for its PLL, and pck-free
	 * is affected by the divisors. And as we need the PLL before enabling
	 * the output, we need to write the divisors early.
	 *
	 * It seems just writing to the DISPC register is enough, and we don't
	 * need to care about the shadow register mechanism for pck-free. The
	 * exact reason for this is unknown.
	 */
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	dispc_mgr_set_clock_div(sdi.output.dispc_channel,
				&sdi.mgr_config.clock_info);
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	dss_sdi_init(sdi.dss, sdi.datapairs);
	r = dss_sdi_enable(sdi.dss);
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	if (r)
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		goto err_sdi_enable;
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	mdelay(2);
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	r = dss_mgr_enable(&sdi.output);
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	if (r)
		goto err_mgr_enable;
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	return 0;
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err_mgr_enable:
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	dss_sdi_disable(sdi.dss);
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err_sdi_enable:
err_set_dss_clock_div:
err_calc_clock_div:
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	dispc_runtime_put(sdi.dss->dispc);
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err_get_dispc:
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	regulator_disable(sdi.vdds_sdi_reg);
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err_reg_enable:
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	return r;
}

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static void sdi_display_disable(struct omap_dss_device *dssdev)
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{
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	dss_mgr_disable(&sdi.output);
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	dss_sdi_disable(sdi.dss);
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	dispc_runtime_put(sdi.dss->dispc);
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	regulator_disable(sdi.vdds_sdi_reg);
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}

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static void sdi_set_timings(struct omap_dss_device *dssdev,
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			    struct videomode *vm)
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{
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	sdi.vm = *vm;
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}

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static void sdi_get_timings(struct omap_dss_device *dssdev,
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			    struct videomode *vm)
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{
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	*vm = sdi.vm;
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}

static int sdi_check_timings(struct omap_dss_device *dssdev,
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			     struct videomode *vm)
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{
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	enum omap_channel channel = dssdev->dispc_channel;
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	if (!dispc_mgr_timings_ok(channel, vm))
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		return -EINVAL;

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	if (vm->pixelclock == 0)
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		return -EINVAL;

	return 0;
}

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static int sdi_init_regulator(void)
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{
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	struct regulator *vdds_sdi;
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	if (sdi.vdds_sdi_reg)
		return 0;
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	vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi");
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	if (IS_ERR(vdds_sdi)) {
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		if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER)
			DSSERR("can't get VDDS_SDI regulator\n");
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		return PTR_ERR(vdds_sdi);
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	}

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	sdi.vdds_sdi_reg = vdds_sdi;

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	return 0;
}

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static int sdi_connect(struct omap_dss_device *dssdev,
		struct omap_dss_device *dst)
{
	int r;

	r = sdi_init_regulator();
	if (r)
		return r;

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	r = dss_mgr_connect(&sdi.output, dssdev);
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	if (r)
		return r;

	r = omapdss_output_set_device(dssdev, dst);
	if (r) {
		DSSERR("failed to connect output to new device: %s\n",
				dst->name);
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		dss_mgr_disconnect(&sdi.output, dssdev);
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		return r;
	}

	return 0;
}

static void sdi_disconnect(struct omap_dss_device *dssdev,
		struct omap_dss_device *dst)
{
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	WARN_ON(dst != dssdev->dst);
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	if (dst != dssdev->dst)
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		return;

	omapdss_output_unset_device(dssdev);

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	dss_mgr_disconnect(&sdi.output, dssdev);
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}

static const struct omapdss_sdi_ops sdi_ops = {
	.connect = sdi_connect,
	.disconnect = sdi_disconnect,

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	.enable = sdi_display_enable,
	.disable = sdi_display_disable,
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	.check_timings = sdi_check_timings,
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	.set_timings = sdi_set_timings,
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	.get_timings = sdi_get_timings,
};

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static void sdi_init_output(struct platform_device *pdev)
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{
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	struct omap_dss_device *out = &sdi.output;
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	out->dev = &pdev->dev;
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	out->id = OMAP_DSS_OUTPUT_SDI;
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	out->output_type = OMAP_DISPLAY_TYPE_SDI;
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	out->name = "sdi.0";
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	out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
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	/* We have SDI only on OMAP3, where it's on port 1 */
	out->port_num = 1;
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	out->ops.sdi = &sdi_ops;
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	out->owner = THIS_MODULE;
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	omapdss_register_output(out);
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}

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static void sdi_uninit_output(struct platform_device *pdev)
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{
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	struct omap_dss_device *out = &sdi.output;
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	omapdss_unregister_output(out);
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}

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int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
		  struct device_node *port)
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{
	struct device_node *ep;
	u32 datapairs;
	int r;

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	ep = of_get_next_child(port, NULL);
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	if (!ep)
		return 0;

	r = of_property_read_u32(ep, "datapairs", &datapairs);
	if (r) {
		DSSERR("failed to parse datapairs\n");
		goto err_datapairs;
	}

	sdi.datapairs = datapairs;
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	sdi.dss = dss;
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	of_node_put(ep);

	sdi.pdev = pdev;

	sdi_init_output(pdev);

	sdi.port_initialized = true;

	return 0;

err_datapairs:
	of_node_put(ep);

	return r;
}

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void sdi_uninit_port(struct device_node *port)
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{
	if (!sdi.port_initialized)
		return;

	sdi_uninit_output(sdi.pdev);
}