dss.c 31.0 KB
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/*
 * linux/drivers/video/omap2/dss/dss.c
 *
 * Copyright (C) 2009 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * Some code and ideas taken from drivers/video/omap/ driver
 * by Imre Deak.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#define DSS_SUBSYS_NAME "DSS"

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#include <linux/debugfs.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/export.h>
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#include <linux/err.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/clk.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/gfp.h>
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#include <linux/sizes.h>
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#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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#include <linux/regulator/consumer.h>
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#include <linux/suspend.h>
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#include <linux/component.h>
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#include <linux/sys_soc.h>
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#include "omapdss.h"
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#include "dss.h"
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#include "dss_features.h"
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#define DSS_SZ_REGS			SZ_512

struct dss_reg {
	u16 idx;
};

#define DSS_REG(idx)			((const struct dss_reg) { idx })

#define DSS_REVISION			DSS_REG(0x0000)
#define DSS_SYSCONFIG			DSS_REG(0x0010)
#define DSS_SYSSTATUS			DSS_REG(0x0014)
#define DSS_CONTROL			DSS_REG(0x0040)
#define DSS_SDI_CONTROL			DSS_REG(0x0044)
#define DSS_PLL_CONTROL			DSS_REG(0x0048)
#define DSS_SDI_STATUS			DSS_REG(0x005C)

#define REG_GET(idx, start, end) \
	FLD_GET(dss_read_reg(idx), start, end)

#define REG_FLD_MOD(idx, val, start, end) \
	dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))

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struct dss_ops {
	int (*dpi_select_source)(int port, enum omap_channel channel);
	int (*select_lcd_source)(enum omap_channel channel,
		enum dss_clk_source clk_src);
};

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struct dss_features {
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	enum dss_model model;
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	u8 fck_div_max;
	u8 dss_fck_multiplier;
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	const char *parent_clk_name;
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	const enum omap_display_type *ports;
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	int num_ports;
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	const struct dss_ops *ops;
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	struct dss_reg_field dispc_clk_switch;
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	bool has_lcd_clk_src;
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};

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static struct {
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	struct platform_device *pdev;
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	void __iomem    *base;
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	struct regmap	*syscon_pll_ctrl;
	u32		syscon_pll_ctrl_offset;
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	struct clk	*parent_clk;
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	struct clk	*dss_clk;
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	unsigned long	dss_clk_rate;
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	unsigned long	cache_req_pck;
	unsigned long	cache_prate;
	struct dispc_clock_info cache_dispc_cinfo;

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	enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
	enum dss_clk_source dispc_clk_source;
	enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
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	bool		ctx_valid;
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	u32		ctx[DSS_SZ_REGS / sizeof(u32)];
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	const struct dss_features *feat;
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	struct dss_pll	*video1_pll;
	struct dss_pll	*video2_pll;
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} dss;

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static const char * const dss_generic_clk_source_names[] = {
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	[DSS_CLK_SRC_FCK]	= "FCK",
	[DSS_CLK_SRC_PLL1_1]	= "PLL1:1",
	[DSS_CLK_SRC_PLL1_2]	= "PLL1:2",
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	[DSS_CLK_SRC_PLL1_3]	= "PLL1:3",
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	[DSS_CLK_SRC_PLL2_1]	= "PLL2:1",
	[DSS_CLK_SRC_PLL2_2]	= "PLL2:2",
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	[DSS_CLK_SRC_PLL2_3]	= "PLL2:3",
	[DSS_CLK_SRC_HDMI_PLL]	= "HDMI PLL",
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};

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static inline void dss_write_reg(const struct dss_reg idx, u32 val)
{
	__raw_writel(val, dss.base + idx.idx);
}

static inline u32 dss_read_reg(const struct dss_reg idx)
{
	return __raw_readl(dss.base + idx.idx);
}

#define SR(reg) \
	dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
#define RR(reg) \
	dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])

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static void dss_save_context(void)
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{
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	DSSDBG("dss_save_context\n");
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	SR(CONTROL);

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	if (dss_feat_get_supported_outputs(OMAP_DSS_CHANNEL_LCD) &
			OMAP_DSS_OUTPUT_SDI) {
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		SR(SDI_CONTROL);
		SR(PLL_CONTROL);
	}
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	dss.ctx_valid = true;

	DSSDBG("context saved\n");
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}

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static void dss_restore_context(void)
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{
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	DSSDBG("dss_restore_context\n");
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	if (!dss.ctx_valid)
		return;

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	RR(CONTROL);

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	if (dss_feat_get_supported_outputs(OMAP_DSS_CHANNEL_LCD) &
			OMAP_DSS_OUTPUT_SDI) {
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		RR(SDI_CONTROL);
		RR(PLL_CONTROL);
	}
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	DSSDBG("context restored\n");
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}

#undef SR
#undef RR

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void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable)
{
	unsigned shift;
	unsigned val;

	if (!dss.syscon_pll_ctrl)
		return;

	val = !enable;

	switch (pll_id) {
	case DSS_PLL_VIDEO1:
		shift = 0;
		break;
	case DSS_PLL_VIDEO2:
		shift = 1;
		break;
	case DSS_PLL_HDMI:
		shift = 2;
		break;
	default:
		DSSERR("illegal DSS PLL ID %d\n", pll_id);
		return;
	}

	regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
		1 << shift, val << shift);
}

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static int dss_ctrl_pll_set_control_mux(enum dss_clk_source clk_src,
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	enum omap_channel channel)
{
	unsigned shift, val;

	if (!dss.syscon_pll_ctrl)
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		return -EINVAL;
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	switch (channel) {
	case OMAP_DSS_CHANNEL_LCD:
		shift = 3;

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		switch (clk_src) {
		case DSS_CLK_SRC_PLL1_1:
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			val = 0; break;
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		case DSS_CLK_SRC_HDMI_PLL:
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			val = 1; break;
		default:
			DSSERR("error in PLL mux config for LCD\n");
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			return -EINVAL;
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		}

		break;
	case OMAP_DSS_CHANNEL_LCD2:
		shift = 5;

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		switch (clk_src) {
		case DSS_CLK_SRC_PLL1_3:
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			val = 0; break;
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		case DSS_CLK_SRC_PLL2_3:
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			val = 1; break;
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		case DSS_CLK_SRC_HDMI_PLL:
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			val = 2; break;
		default:
			DSSERR("error in PLL mux config for LCD2\n");
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			return -EINVAL;
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		}

		break;
	case OMAP_DSS_CHANNEL_LCD3:
		shift = 7;

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		switch (clk_src) {
		case DSS_CLK_SRC_PLL2_1:
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			val = 0; break;
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		case DSS_CLK_SRC_PLL1_3:
			val = 1; break;
		case DSS_CLK_SRC_HDMI_PLL:
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			val = 2; break;
		default:
			DSSERR("error in PLL mux config for LCD3\n");
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			return -EINVAL;
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		}

		break;
	default:
		DSSERR("error in PLL mux config\n");
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		return -EINVAL;
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	}

	regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
		0x3 << shift, val << shift);
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	return 0;
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}

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void dss_sdi_init(int datapairs)
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{
	u32 l;

	BUG_ON(datapairs > 3 || datapairs < 1);

	l = dss_read_reg(DSS_SDI_CONTROL);
	l = FLD_MOD(l, 0xf, 19, 15);		/* SDI_PDIV */
	l = FLD_MOD(l, datapairs-1, 3, 2);	/* SDI_PRSEL */
	l = FLD_MOD(l, 2, 1, 0);		/* SDI_BWSEL */
	dss_write_reg(DSS_SDI_CONTROL, l);

	l = dss_read_reg(DSS_PLL_CONTROL);
	l = FLD_MOD(l, 0x7, 25, 22);	/* SDI_PLL_FREQSEL */
	l = FLD_MOD(l, 0xb, 16, 11);	/* SDI_PLL_REGN */
	l = FLD_MOD(l, 0xb4, 10, 1);	/* SDI_PLL_REGM */
	dss_write_reg(DSS_PLL_CONTROL, l);
}

int dss_sdi_enable(void)
{
	unsigned long timeout;

	dispc_pck_free_enable(1);

	/* Reset SDI PLL */
	REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
	udelay(1);	/* wait 2x PCLK */

	/* Lock SDI PLL */
	REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */

	/* Waiting for PLL lock request to complete */
	timeout = jiffies + msecs_to_jiffies(500);
	while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
		if (time_after_eq(jiffies, timeout)) {
			DSSERR("PLL lock request timed out\n");
			goto err1;
		}
	}

	/* Clearing PLL_GO bit */
	REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);

	/* Waiting for PLL to lock */
	timeout = jiffies + msecs_to_jiffies(500);
	while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
		if (time_after_eq(jiffies, timeout)) {
			DSSERR("PLL lock timed out\n");
			goto err1;
		}
	}

	dispc_lcd_enable_signal(1);

	/* Waiting for SDI reset to complete */
	timeout = jiffies + msecs_to_jiffies(500);
	while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
		if (time_after_eq(jiffies, timeout)) {
			DSSERR("SDI reset timed out\n");
			goto err2;
		}
	}

	return 0;

 err2:
	dispc_lcd_enable_signal(0);
 err1:
	/* Reset SDI PLL */
	REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */

	dispc_pck_free_enable(0);

	return -ETIMEDOUT;
}

void dss_sdi_disable(void)
{
	dispc_lcd_enable_signal(0);

	dispc_pck_free_enable(0);

	/* Reset SDI PLL */
	REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
}

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const char *dss_get_clk_source_name(enum dss_clk_source clk_src)
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{
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	return dss_generic_clk_source_names[clk_src];
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}

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void dss_dump_clocks(struct seq_file *s)
{
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	const char *fclk_name;
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	unsigned long fclk_rate;
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	if (dss_runtime_get())
		return;
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	seq_printf(s, "- DSS -\n");

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	fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK);
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	fclk_rate = clk_get_rate(dss.dss_clk);
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	seq_printf(s, "%s = %lu\n",
			fclk_name,
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			fclk_rate);
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	dss_runtime_put();
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}

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static void dss_dump_regs(struct seq_file *s)
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{
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))

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	if (dss_runtime_get())
		return;
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	DUMPREG(DSS_REVISION);
	DUMPREG(DSS_SYSCONFIG);
	DUMPREG(DSS_SYSSTATUS);
	DUMPREG(DSS_CONTROL);
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	if (dss_feat_get_supported_outputs(OMAP_DSS_CHANNEL_LCD) &
			OMAP_DSS_OUTPUT_SDI) {
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		DUMPREG(DSS_SDI_CONTROL);
		DUMPREG(DSS_PLL_CONTROL);
		DUMPREG(DSS_SDI_STATUS);
	}
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	dss_runtime_put();
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#undef DUMPREG
}

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static int dss_get_channel_index(enum omap_channel channel)
{
	switch (channel) {
	case OMAP_DSS_CHANNEL_LCD:
		return 0;
	case OMAP_DSS_CHANNEL_LCD2:
		return 1;
	case OMAP_DSS_CHANNEL_LCD3:
		return 2;
	default:
		WARN_ON(1);
		return 0;
	}
}

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static void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
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{
	int b;

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	/*
	 * We always use PRCM clock as the DISPC func clock, except on DSS3,
	 * where we don't have separate DISPC and LCD clock sources.
	 */
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	if (WARN_ON(dss.feat->has_lcd_clk_src && clk_src != DSS_CLK_SRC_FCK))
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		return;

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	switch (clk_src) {
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	case DSS_CLK_SRC_FCK:
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		b = 0;
		break;
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	case DSS_CLK_SRC_PLL1_1:
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		b = 1;
		break;
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	case DSS_CLK_SRC_PLL2_1:
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		b = 2;
		break;
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	default:
		BUG();
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		return;
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	}
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	REG_FLD_MOD(DSS_CONTROL, b,			/* DISPC_CLK_SWITCH */
		    dss.feat->dispc_clk_switch.start,
		    dss.feat->dispc_clk_switch.end);
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	dss.dispc_clk_source = clk_src;
}

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void dss_select_dsi_clk_source(int dsi_module,
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		enum dss_clk_source clk_src)
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{
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	int b, pos;
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	switch (clk_src) {
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	case DSS_CLK_SRC_FCK:
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		b = 0;
		break;
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	case DSS_CLK_SRC_PLL1_2:
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		BUG_ON(dsi_module != 0);
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		b = 1;
		break;
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	case DSS_CLK_SRC_PLL2_2:
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		BUG_ON(dsi_module != 1);
		b = 1;
		break;
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	default:
		BUG();
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		return;
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	}
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	pos = dsi_module == 0 ? 1 : 10;
	REG_FLD_MOD(DSS_CONTROL, b, pos, pos);	/* DSIx_CLK_SWITCH */
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	dss.dsi_clk_source[dsi_module] = clk_src;
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}

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static int dss_lcd_clk_mux_dra7(enum omap_channel channel,
	enum dss_clk_source clk_src)
{
	const u8 ctrl_bits[] = {
		[OMAP_DSS_CHANNEL_LCD] = 0,
		[OMAP_DSS_CHANNEL_LCD2] = 12,
		[OMAP_DSS_CHANNEL_LCD3] = 19,
	};

	u8 ctrl_bit = ctrl_bits[channel];
	int r;

	if (clk_src == DSS_CLK_SRC_FCK) {
		/* LCDx_CLK_SWITCH */
		REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
		return -EINVAL;
	}

	r = dss_ctrl_pll_set_control_mux(clk_src, channel);
	if (r)
		return r;

	REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit);

	return 0;
}

static int dss_lcd_clk_mux_omap5(enum omap_channel channel,
	enum dss_clk_source clk_src)
{
	const u8 ctrl_bits[] = {
		[OMAP_DSS_CHANNEL_LCD] = 0,
		[OMAP_DSS_CHANNEL_LCD2] = 12,
		[OMAP_DSS_CHANNEL_LCD3] = 19,
	};
	const enum dss_clk_source allowed_plls[] = {
		[OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1,
		[OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_FCK,
		[OMAP_DSS_CHANNEL_LCD3] = DSS_CLK_SRC_PLL2_1,
	};

	u8 ctrl_bit = ctrl_bits[channel];

	if (clk_src == DSS_CLK_SRC_FCK) {
		/* LCDx_CLK_SWITCH */
		REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
		return -EINVAL;
	}

	if (WARN_ON(allowed_plls[channel] != clk_src))
		return -EINVAL;

	REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit);

	return 0;
}

static int dss_lcd_clk_mux_omap4(enum omap_channel channel,
	enum dss_clk_source clk_src)
{
	const u8 ctrl_bits[] = {
		[OMAP_DSS_CHANNEL_LCD] = 0,
		[OMAP_DSS_CHANNEL_LCD2] = 12,
	};
	const enum dss_clk_source allowed_plls[] = {
		[OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1,
		[OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_PLL2_1,
	};

	u8 ctrl_bit = ctrl_bits[channel];

	if (clk_src == DSS_CLK_SRC_FCK) {
		/* LCDx_CLK_SWITCH */
		REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
		return 0;
	}

	if (WARN_ON(allowed_plls[channel] != clk_src))
		return -EINVAL;

	REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit);

	return 0;
}

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void dss_select_lcd_clk_source(enum omap_channel channel,
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		enum dss_clk_source clk_src)
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{
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	int idx = dss_get_channel_index(channel);
	int r;
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	if (!dss.feat->has_lcd_clk_src) {
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		dss_select_dispc_clk_source(clk_src);
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		dss.lcd_clk_source[idx] = clk_src;
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		return;
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	}
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	r = dss.feat->ops->select_lcd_source(channel, clk_src);
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	if (r)
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		return;
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	dss.lcd_clk_source[idx] = clk_src;
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}

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enum dss_clk_source dss_get_dispc_clk_source(void)
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{
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	return dss.dispc_clk_source;
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}

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enum dss_clk_source dss_get_dsi_clk_source(int dsi_module)
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{
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	return dss.dsi_clk_source[dsi_module];
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}

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enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
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{
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	if (dss.feat->has_lcd_clk_src) {
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		int idx = dss_get_channel_index(channel);
		return dss.lcd_clk_source[idx];
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	} else {
		/* LCD_CLK source is the same as DISPC_FCLK source for
		 * OMAP2 and OMAP3 */
		return dss.dispc_clk_source;
	}
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}

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bool dss_div_calc(unsigned long pck, unsigned long fck_min,
		dss_div_calc_func func, void *data)
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{
	int fckd, fckd_start, fckd_stop;
	unsigned long fck;
	unsigned long fck_hw_max;
	unsigned long fckd_hw_max;
	unsigned long prate;
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	unsigned m;
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	fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);

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	if (dss.parent_clk == NULL) {
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		unsigned pckd;

		pckd = fck_hw_max / pck;

		fck = pck * pckd;

		fck = clk_round_rate(dss.dss_clk, fck);

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		return func(fck, data);
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	}

	fckd_hw_max = dss.feat->fck_div_max;

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	m = dss.feat->dss_fck_multiplier;
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	prate = clk_get_rate(dss.parent_clk);
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	fck_min = fck_min ? fck_min : 1;

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	fckd_start = min(prate * m / fck_min, fckd_hw_max);
	fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
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	for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
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		fck = DIV_ROUND_UP(prate, fckd) * m;
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		if (func(fck, data))
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			return true;
	}

	return false;
}

660
int dss_set_fck_rate(unsigned long rate)
661
{
662
	int r;
663

664
	DSSDBG("set fck to %lu\n", rate);
665

666 667 668
	r = clk_set_rate(dss.dss_clk, rate);
	if (r)
		return r;
669

670 671
	dss.dss_clk_rate = clk_get_rate(dss.dss_clk);

672
	WARN_ONCE(dss.dss_clk_rate != rate,
673
			"clk rate mismatch: %lu != %lu", dss.dss_clk_rate,
674
			rate);
675 676 677 678

	return 0;
}

679 680 681 682 683
unsigned long dss_get_dispc_clk_rate(void)
{
	return dss.dss_clk_rate;
}

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static int dss_setup_default_clock(void)
{
	unsigned long max_dss_fck, prate;
687
	unsigned long fck;
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	unsigned fck_div;
	int r;

	max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);

693 694 695 696
	if (dss.parent_clk == NULL) {
		fck = clk_round_rate(dss.dss_clk, max_dss_fck);
	} else {
		prate = clk_get_rate(dss.parent_clk);
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698 699
		fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
				max_dss_fck);
700
		fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier;
701
	}
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702

703
	r = dss_set_fck_rate(fck);
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704 705 706 707 708 709
	if (r)
		return r;

	return 0;
}

710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729
void dss_set_venc_output(enum omap_dss_venc_type type)
{
	int l = 0;

	if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
		l = 0;
	else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
		l = 1;
	else
		BUG();

	/* venc out selection. 0 = comp, 1 = svideo */
	REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
}

void dss_set_dac_pwrdn_bgz(bool enable)
{
	REG_FLD_MOD(DSS_CONTROL, enable, 5, 5);	/* DAC Power-Down Control */
}

730
void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
731
{
732 733 734
	enum omap_dss_output_id outputs;

	outputs = dss_feat_get_supported_outputs(OMAP_DSS_CHANNEL_DIGIT);
735 736

	/* Complain about invalid selections */
737 738
	WARN_ON((src == DSS_VENC_TV_CLK) && !(outputs & OMAP_DSS_OUTPUT_VENC));
	WARN_ON((src == DSS_HDMI_M_PCLK) && !(outputs & OMAP_DSS_OUTPUT_HDMI));
739 740

	/* Select only if we have options */
741 742
	if ((outputs & OMAP_DSS_OUTPUT_VENC) &&
	    (outputs & OMAP_DSS_OUTPUT_HDMI))
743
		REG_FLD_MOD(DSS_CONTROL, src, 15, 15);	/* VENC_HDMI_SWITCH */
744 745
}

746 747
enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
{
748
	enum omap_dss_output_id outputs;
749

750 751
	outputs = dss_feat_get_supported_outputs(OMAP_DSS_CHANNEL_DIGIT);
	if ((outputs & OMAP_DSS_OUTPUT_HDMI) == 0)
752 753
		return DSS_VENC_TV_CLK;

754
	if ((outputs & OMAP_DSS_OUTPUT_VENC) == 0)
755 756
		return DSS_HDMI_M_PCLK;

757 758 759
	return REG_GET(DSS_CONTROL, 15, 15);
}

760
static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel)
761 762 763 764 765 766 767
{
	if (channel != OMAP_DSS_CHANNEL_LCD)
		return -EINVAL;

	return 0;
}

768
static int dss_dpi_select_source_omap4(int port, enum omap_channel channel)
769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787
{
	int val;

	switch (channel) {
	case OMAP_DSS_CHANNEL_LCD2:
		val = 0;
		break;
	case OMAP_DSS_CHANNEL_DIGIT:
		val = 1;
		break;
	default:
		return -EINVAL;
	}

	REG_FLD_MOD(DSS_CONTROL, val, 17, 17);

	return 0;
}

788
static int dss_dpi_select_source_omap5(int port, enum omap_channel channel)
789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813
{
	int val;

	switch (channel) {
	case OMAP_DSS_CHANNEL_LCD:
		val = 1;
		break;
	case OMAP_DSS_CHANNEL_LCD2:
		val = 2;
		break;
	case OMAP_DSS_CHANNEL_LCD3:
		val = 3;
		break;
	case OMAP_DSS_CHANNEL_DIGIT:
		val = 0;
		break;
	default:
		return -EINVAL;
	}

	REG_FLD_MOD(DSS_CONTROL, val, 17, 16);

	return 0;
}

814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833
static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel)
{
	switch (port) {
	case 0:
		return dss_dpi_select_source_omap5(port, channel);
	case 1:
		if (channel != OMAP_DSS_CHANNEL_LCD2)
			return -EINVAL;
		break;
	case 2:
		if (channel != OMAP_DSS_CHANNEL_LCD3)
			return -EINVAL;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

834
int dss_dpi_select_source(int port, enum omap_channel channel)
835
{
836
	return dss.feat->ops->dpi_select_source(port, channel);
837 838
}

839 840
static int dss_get_clocks(void)
{
841
	struct clk *clk;
842

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843
	clk = devm_clk_get(&dss.pdev->dev, "fck");
844 845
	if (IS_ERR(clk)) {
		DSSERR("can't get clock fck\n");
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846
		return PTR_ERR(clk);
847
	}
848

849
	dss.dss_clk = clk;
850

851 852
	if (dss.feat->parent_clk_name) {
		clk = clk_get(NULL, dss.feat->parent_clk_name);
853
		if (IS_ERR(clk)) {
854
			DSSERR("Failed to get %s\n", dss.feat->parent_clk_name);
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855
			return PTR_ERR(clk);
856 857 858
		}
	} else {
		clk = NULL;
859 860
	}

861
	dss.parent_clk = clk;
862

863 864 865 866 867
	return 0;
}

static void dss_put_clocks(void)
{
868 869
	if (dss.parent_clk)
		clk_put(dss.parent_clk);
870 871
}

872
int dss_runtime_get(void)
873
{
874
	int r;
875

876
	DSSDBG("dss_runtime_get\n");
877

878 879 880
	r = pm_runtime_get_sync(&dss.pdev->dev);
	WARN_ON(r < 0);
	return r < 0 ? r : 0;
881 882
}

883
void dss_runtime_put(void)
884
{
885
	int r;
886

887
	DSSDBG("dss_runtime_put\n");
888

889
	r = pm_runtime_put_sync(&dss.pdev->dev);
890
	WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
891 892 893
}

/* DEBUGFS */
894
#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
895
static void dss_debug_dump_clocks(struct seq_file *s)
896 897 898 899 900 901 902 903
{
	dss_dump_clocks(s);
	dispc_dump_clocks(s);
#ifdef CONFIG_OMAP2_DSS_DSI
	dsi_dump_clocks(s);
#endif
}

904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965
static int dss_debug_show(struct seq_file *s, void *unused)
{
	void (*func)(struct seq_file *) = s->private;

	func(s);
	return 0;
}

static int dss_debug_open(struct inode *inode, struct file *file)
{
	return single_open(file, dss_debug_show, inode->i_private);
}

static const struct file_operations dss_debug_fops = {
	.open           = dss_debug_open,
	.read           = seq_read,
	.llseek         = seq_lseek,
	.release        = single_release,
};

static struct dentry *dss_debugfs_dir;

static int dss_initialize_debugfs(void)
{
	dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
	if (IS_ERR(dss_debugfs_dir)) {
		int err = PTR_ERR(dss_debugfs_dir);

		dss_debugfs_dir = NULL;
		return err;
	}

	debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
			&dss_debug_dump_clocks, &dss_debug_fops);

	return 0;
}

static void dss_uninitialize_debugfs(void)
{
	if (dss_debugfs_dir)
		debugfs_remove_recursive(dss_debugfs_dir);
}

int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *))
{
	struct dentry *d;

	d = debugfs_create_file(name, S_IRUGO, dss_debugfs_dir,
			write, &dss_debug_fops);

	return PTR_ERR_OR_ZERO(d);
}
#else /* CONFIG_OMAP2_DSS_DEBUGFS */
static inline int dss_initialize_debugfs(void)
{
	return 0;
}
static inline void dss_uninitialize_debugfs(void)
{
}
#endif /* CONFIG_OMAP2_DSS_DEBUGFS */
966

967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985
static const struct dss_ops dss_ops_omap2_omap3 = {
	.dpi_select_source = &dss_dpi_select_source_omap2_omap3,
};

static const struct dss_ops dss_ops_omap4 = {
	.dpi_select_source = &dss_dpi_select_source_omap4,
	.select_lcd_source = &dss_lcd_clk_mux_omap4,
};

static const struct dss_ops dss_ops_omap5 = {
	.dpi_select_source = &dss_dpi_select_source_omap5,
	.select_lcd_source = &dss_lcd_clk_mux_omap5,
};

static const struct dss_ops dss_ops_dra7 = {
	.dpi_select_source = &dss_dpi_select_source_dra7xx,
	.select_lcd_source = &dss_lcd_clk_mux_dra7,
};

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static const enum omap_display_type omap2plus_ports[] = {
987 988 989
	OMAP_DISPLAY_TYPE_DPI,
};

T
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990
static const enum omap_display_type omap34xx_ports[] = {
991 992 993 994
	OMAP_DISPLAY_TYPE_DPI,
	OMAP_DISPLAY_TYPE_SDI,
};

995 996 997 998 999 1000
static const enum omap_display_type dra7xx_ports[] = {
	OMAP_DISPLAY_TYPE_DPI,
	OMAP_DISPLAY_TYPE_DPI,
	OMAP_DISPLAY_TYPE_DPI,
};

1001
static const struct dss_features omap24xx_dss_feats = {
1002
	.model			=	DSS_MODEL_OMAP2,
1003 1004 1005 1006 1007
	/*
	 * fck div max is really 16, but the divider range has gaps. The range
	 * from 1 to 6 has no gaps, so let's use that as a max.
	 */
	.fck_div_max		=	6,
1008
	.dss_fck_multiplier	=	2,
1009
	.parent_clk_name	=	"core_ck",
1010 1011
	.ports			=	omap2plus_ports,
	.num_ports		=	ARRAY_SIZE(omap2plus_ports),
1012
	.ops			=	&dss_ops_omap2_omap3,
1013
	.dispc_clk_switch	=	{ 0, 0 },
1014
	.has_lcd_clk_src	=	false,
1015 1016
};

1017
static const struct dss_features omap34xx_dss_feats = {
1018
	.model			=	DSS_MODEL_OMAP3,
1019 1020
	.fck_div_max		=	16,
	.dss_fck_multiplier	=	2,
1021
	.parent_clk_name	=	"dpll4_ck",
1022 1023
	.ports			=	omap34xx_ports,
	.num_ports		=	ARRAY_SIZE(omap34xx_ports),
1024
	.ops			=	&dss_ops_omap2_omap3,
1025
	.dispc_clk_switch	=	{ 0, 0 },
1026
	.has_lcd_clk_src	=	false,
1027 1028
};

1029
static const struct dss_features omap3630_dss_feats = {
1030
	.model			=	DSS_MODEL_OMAP3,
1031 1032
	.fck_div_max		=	32,
	.dss_fck_multiplier	=	1,
1033
	.parent_clk_name	=	"dpll4_ck",
1034 1035
	.ports			=	omap2plus_ports,
	.num_ports		=	ARRAY_SIZE(omap2plus_ports),
1036
	.ops			=	&dss_ops_omap2_omap3,
1037
	.dispc_clk_switch	=	{ 0, 0 },
1038
	.has_lcd_clk_src	=	false,
1039 1040
};

1041
static const struct dss_features omap44xx_dss_feats = {
1042
	.model			=	DSS_MODEL_OMAP4,
1043 1044
	.fck_div_max		=	32,
	.dss_fck_multiplier	=	1,
1045
	.parent_clk_name	=	"dpll_per_x2_ck",
1046 1047
	.ports			=	omap2plus_ports,
	.num_ports		=	ARRAY_SIZE(omap2plus_ports),
1048
	.ops			=	&dss_ops_omap4,
1049
	.dispc_clk_switch	=	{ 9, 8 },
1050
	.has_lcd_clk_src	=	true,
1051 1052
};

1053
static const struct dss_features omap54xx_dss_feats = {
1054
	.model			=	DSS_MODEL_OMAP5,
1055 1056
	.fck_div_max		=	64,
	.dss_fck_multiplier	=	1,
1057
	.parent_clk_name	=	"dpll_per_x2_ck",
1058 1059
	.ports			=	omap2plus_ports,
	.num_ports		=	ARRAY_SIZE(omap2plus_ports),
1060
	.ops			=	&dss_ops_omap5,
1061
	.dispc_clk_switch	=	{ 9, 7 },
1062
	.has_lcd_clk_src	=	true,
1063 1064
};

1065
static const struct dss_features am43xx_dss_feats = {
1066
	.model			=	DSS_MODEL_OMAP3,
1067 1068 1069
	.fck_div_max		=	0,
	.dss_fck_multiplier	=	0,
	.parent_clk_name	=	NULL,
1070 1071
	.ports			=	omap2plus_ports,
	.num_ports		=	ARRAY_SIZE(omap2plus_ports),
1072
	.ops			=	&dss_ops_omap2_omap3,
1073
	.dispc_clk_switch	=	{ 0, 0 },
1074
	.has_lcd_clk_src	=	true,
1075 1076
};

1077
static const struct dss_features dra7xx_dss_feats = {
1078
	.model			=	DSS_MODEL_DRA7,
1079 1080 1081 1082 1083
	.fck_div_max		=	64,
	.dss_fck_multiplier	=	1,
	.parent_clk_name	=	"dpll_per_x2_ck",
	.ports			=	dra7xx_ports,
	.num_ports		=	ARRAY_SIZE(dra7xx_ports),
1084
	.ops			=	&dss_ops_dra7,
1085
	.dispc_clk_switch	=	{ 9, 7 },
1086
	.has_lcd_clk_src	=	true,
1087 1088
};

1089
static int dss_init_ports(struct platform_device *pdev)
T
Tomi Valkeinen 已提交
1090 1091 1092
{
	struct device_node *parent = pdev->dev.of_node;
	struct device_node *port;
1093
	int i;
T
Tomi Valkeinen 已提交
1094

1095 1096 1097
	for (i = 0; i < dss.feat->num_ports; i++) {
		port = of_graph_get_port_by_id(parent, i);
		if (!port)
1098
			continue;
T
Tomi Valkeinen 已提交
1099

1100
		switch (dss.feat->ports[i]) {
1101
		case OMAP_DISPLAY_TYPE_DPI:
1102
			dpi_init_port(pdev, port, dss.feat->model);
1103 1104 1105 1106 1107 1108 1109
			break;
		case OMAP_DISPLAY_TYPE_SDI:
			sdi_init_port(pdev, port);
			break;
		default:
			break;
		}
1110
	}
T
Tomi Valkeinen 已提交
1111 1112 1113 1114

	return 0;
}

1115
static void dss_uninit_ports(struct platform_device *pdev)
T
Tomi Valkeinen 已提交
1116
{
1117 1118
	struct device_node *parent = pdev->dev.of_node;
	struct device_node *port;
1119
	int i;
1120

1121 1122 1123
	for (i = 0; i < dss.feat->num_ports; i++) {
		port = of_graph_get_port_by_id(parent, i);
		if (!port)
1124 1125
			continue;

1126
		switch (dss.feat->ports[i]) {
1127 1128 1129 1130 1131 1132 1133 1134 1135
		case OMAP_DISPLAY_TYPE_DPI:
			dpi_uninit_port(port);
			break;
		case OMAP_DISPLAY_TYPE_SDI:
			sdi_uninit_port(port);
			break;
		default:
			break;
		}
1136
	}
T
Tomi Valkeinen 已提交
1137 1138
}

1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199
static int dss_video_pll_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct regulator *pll_regulator;
	int r;

	if (!np)
		return 0;

	if (of_property_read_bool(np, "syscon-pll-ctrl")) {
		dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np,
			"syscon-pll-ctrl");
		if (IS_ERR(dss.syscon_pll_ctrl)) {
			dev_err(&pdev->dev,
				"failed to get syscon-pll-ctrl regmap\n");
			return PTR_ERR(dss.syscon_pll_ctrl);
		}

		if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1,
				&dss.syscon_pll_ctrl_offset)) {
			dev_err(&pdev->dev,
				"failed to get syscon-pll-ctrl offset\n");
			return -EINVAL;
		}
	}

	pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video");
	if (IS_ERR(pll_regulator)) {
		r = PTR_ERR(pll_regulator);

		switch (r) {
		case -ENOENT:
			pll_regulator = NULL;
			break;

		case -EPROBE_DEFER:
			return -EPROBE_DEFER;

		default:
			DSSERR("can't get DPLL VDDA regulator\n");
			return r;
		}
	}

	if (of_property_match_string(np, "reg-names", "pll1") >= 0) {
		dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator);
		if (IS_ERR(dss.video1_pll))
			return PTR_ERR(dss.video1_pll);
	}

	if (of_property_match_string(np, "reg-names", "pll2") >= 0) {
		dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator);
		if (IS_ERR(dss.video2_pll)) {
			dss_video_pll_uninit(dss.video1_pll);
			return PTR_ERR(dss.video2_pll);
		}
	}

	return 0;
}

1200
/* DSS HW IP initialisation */
1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217
static const struct of_device_id dss_of_match[] = {
	{ .compatible = "ti,omap2-dss", .data = &omap24xx_dss_feats },
	{ .compatible = "ti,omap3-dss", .data = &omap3630_dss_feats },
	{ .compatible = "ti,omap4-dss", .data = &omap44xx_dss_feats },
	{ .compatible = "ti,omap5-dss", .data = &omap54xx_dss_feats },
	{ .compatible = "ti,dra7-dss",  .data = &dra7xx_dss_feats },
	{},
};
MODULE_DEVICE_TABLE(of, dss_of_match);

static const struct soc_device_attribute dss_soc_devices[] = {
	{ .machine = "OMAP3430/3530", .data = &omap34xx_dss_feats },
	{ .machine = "AM35??",        .data = &omap34xx_dss_feats },
	{ .family  = "AM43xx",        .data = &am43xx_dss_feats },
	{ /* sentinel */ }
};

T
Tomi Valkeinen 已提交
1218
static int dss_bind(struct device *dev)
1219
{
T
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1220
	struct platform_device *pdev = to_platform_device(dev);
1221 1222
	struct resource *dss_mem;
	u32 rev;
1223 1224
	int r;

1225
	dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
1226 1227 1228
	dss.base = devm_ioremap_resource(&pdev->dev, dss_mem);
	if (IS_ERR(dss.base))
		return PTR_ERR(dss.base);
1229

1230 1231
	r = dss_get_clocks();
	if (r)
1232
		return r;
1233

T
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1234 1235 1236 1237
	r = dss_setup_default_clock();
	if (r)
		goto err_setup_clocks;

1238 1239 1240 1241
	r = dss_video_pll_probe(pdev);
	if (r)
		goto err_pll_init;

1242 1243 1244 1245
	r = dss_init_ports(pdev);
	if (r)
		goto err_init_ports;

1246
	pm_runtime_enable(&pdev->dev);
1247

1248 1249 1250
	r = dss_runtime_get();
	if (r)
		goto err_runtime_get;
1251

1252 1253
	dss.dss_clk_rate = clk_get_rate(dss.dss_clk);

1254 1255 1256
	/* Select DPLL */
	REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);

1257
	dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
1258

1259 1260 1261 1262 1263
#ifdef CONFIG_OMAP2_DSS_VENC
	REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);	/* venc dac demen */
	REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);	/* venc clock 4x enable */
	REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);	/* venc clock mode = normal */
#endif
1264 1265 1266 1267 1268
	dss.dsi_clk_source[0] = DSS_CLK_SRC_FCK;
	dss.dsi_clk_source[1] = DSS_CLK_SRC_FCK;
	dss.dispc_clk_source = DSS_CLK_SRC_FCK;
	dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK;
	dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK;
1269

1270
	rev = dss_read_reg(DSS_REVISION);
1271
	pr_info("OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1272

1273
	dss_runtime_put();
1274

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	r = component_bind_all(&pdev->dev, NULL);
	if (r)
		goto err_component;

1279 1280
	dss_debugfs_create_file("dss", dss_dump_regs);

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	pm_set_vt_switch(0);

1283
	omapdss_gather_components(dev);
1284
	omapdss_set_is_initialized(true);
1285

1286
	return 0;
1287

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err_component:
1289 1290
err_runtime_get:
	pm_runtime_disable(&pdev->dev);
1291 1292
	dss_uninit_ports(pdev);
err_init_ports:
1293 1294 1295 1296 1297
	if (dss.video1_pll)
		dss_video_pll_uninit(dss.video1_pll);

	if (dss.video2_pll)
		dss_video_pll_uninit(dss.video2_pll);
1298
err_pll_init:
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err_setup_clocks:
1300
	dss_put_clocks();
1301 1302 1303
	return r;
}

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1304
static void dss_unbind(struct device *dev)
1305
{
T
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1306 1307
	struct platform_device *pdev = to_platform_device(dev);

1308
	omapdss_set_is_initialized(false);
1309

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1310 1311
	component_unbind_all(&pdev->dev, NULL);

1312 1313 1314 1315 1316 1317
	if (dss.video1_pll)
		dss_video_pll_uninit(dss.video1_pll);

	if (dss.video2_pll)
		dss_video_pll_uninit(dss.video2_pll);

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	dss_uninit_ports(pdev);
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1319

1320
	pm_runtime_disable(&pdev->dev);
1321 1322

	dss_put_clocks();
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1323 1324 1325 1326 1327 1328
}

static const struct component_master_ops dss_component_ops = {
	.bind = dss_bind,
	.unbind = dss_unbind,
};
1329

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1330 1331 1332 1333 1334 1335 1336 1337 1338 1339
static int dss_component_compare(struct device *dev, void *data)
{
	struct device *child = data;
	return dev == child;
}

static int dss_add_child_component(struct device *dev, void *data)
{
	struct component_match **match = data;

1340 1341 1342 1343 1344 1345 1346 1347 1348
	/*
	 * HACK
	 * We don't have a working driver for rfbi, so skip it here always.
	 * Otherwise dss will never get probed successfully, as it will wait
	 * for rfbi to get probed.
	 */
	if (strstr(dev_name(dev), "rfbi"))
		return 0;

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	component_match_add(dev->parent, match, dss_component_compare, dev);

	return 0;
}

static int dss_probe(struct platform_device *pdev)
{
1356
	const struct soc_device_attribute *soc;
T
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1357 1358 1359
	struct component_match *match = NULL;
	int r;

1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371
	dss.pdev = pdev;

	/*
	 * The various OMAP3-based SoCs can't be told apart using the compatible
	 * string, use SoC device matching.
	 */
	soc = soc_device_match(dss_soc_devices);
	if (soc)
		dss.feat = soc->data;
	else
		dss.feat = of_match_device(dss_of_match, &pdev->dev)->data;

1372 1373 1374 1375
	r = dss_initialize_debugfs();
	if (r)
		return r;

T
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1376 1377 1378 1379
	/* add all the child devices as components */
	device_for_each_child(&pdev->dev, &match, dss_add_child_component);

	r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match);
1380 1381
	if (r) {
		dss_uninitialize_debugfs();
T
Tomi Valkeinen 已提交
1382
		return r;
1383
	}
T
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1384 1385 1386 1387 1388 1389 1390

	return 0;
}

static int dss_remove(struct platform_device *pdev)
{
	component_master_del(&pdev->dev, &dss_component_ops);
1391 1392 1393

	dss_uninitialize_debugfs();

1394 1395 1396
	return 0;
}

1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411
static void dss_shutdown(struct platform_device *pdev)
{
	struct omap_dss_device *dssdev = NULL;

	DSSDBG("shutdown\n");

	for_each_dss_dev(dssdev) {
		if (!dssdev->driver)
			continue;

		if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
			dssdev->driver->disable(dssdev);
	}
}

1412 1413 1414
static int dss_runtime_suspend(struct device *dev)
{
	dss_save_context();
1415
	dss_set_min_bus_tput(dev, 0);
D
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1416 1417 1418

	pinctrl_pm_select_sleep_state(dev);

1419 1420 1421 1422 1423
	return 0;
}

static int dss_runtime_resume(struct device *dev)
{
1424
	int r;
D
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1425 1426 1427

	pinctrl_pm_select_default_state(dev);

1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438
	/*
	 * Set an arbitrarily high tput request to ensure OPP100.
	 * What we should really do is to make a request to stay in OPP100,
	 * without any tput requirements, but that is not currently possible
	 * via the PM layer.
	 */

	r = dss_set_min_bus_tput(dev, 1000000000);
	if (r)
		return r;

1439
	dss_restore_context();
1440 1441 1442 1443 1444 1445 1446 1447
	return 0;
}

static const struct dev_pm_ops dss_pm_ops = {
	.runtime_suspend = dss_runtime_suspend,
	.runtime_resume = dss_runtime_resume,
};

1448
static struct platform_driver omap_dsshw_driver = {
T
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1449 1450
	.probe		= dss_probe,
	.remove		= dss_remove,
1451
	.shutdown	= dss_shutdown,
1452 1453
	.driver         = {
		.name   = "omapdss_dss",
1454
		.pm	= &dss_pm_ops,
T
Tomi Valkeinen 已提交
1455
		.of_match_table = dss_of_match,
T
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1456
		.suppress_bind_attrs = true,
1457 1458 1459
	},
};

T
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1460
int __init dss_init_platform_driver(void)
1461
{
T
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1462
	return platform_driver_register(&omap_dsshw_driver);
1463 1464 1465 1466
}

void dss_uninit_platform_driver(void)
{
1467
	platform_driver_unregister(&omap_dsshw_driver);
1468
}