pgtable.h 45.6 KB
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/*
 *  S390 version
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 *    Copyright IBM Corp. 1999, 2000
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 *    Author(s): Hartmut Penner (hp@de.ibm.com)
 *               Ulrich Weigand (weigand@de.ibm.com)
 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
 *
 *  Derived from "include/asm-i386/pgtable.h"
 */

#ifndef _ASM_S390_PGTABLE_H
#define _ASM_S390_PGTABLE_H

/*
 * The Linux memory management assumes a three-level page table setup. For
 * s390 31 bit we "fold" the mid level into the top-level page table, so
 * that we physically have the same two-level page table as the s390 mmu
 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
 * the hardware provides (region first and region second tables are not
 * used).
 *
 * The "pgd_xxx()" functions are trivial for a folded two-level
 * setup: the pgd is never bad, and a pmd always exists (as it's folded
 * into the pgd entry)
 *
 * This file contains the functions and defines necessary to modify and use
 * the S390 page table tree.
 */
#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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#include <linux/mm_types.h>
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#include <linux/page-flags.h>
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#include <asm/bug.h>
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#include <asm/page.h>
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extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
extern void paging_init(void);
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extern void vmem_map_init(void);
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/*
 * The S390 doesn't have any external MMU info: the kernel page
 * tables contain all the necessary information.
 */
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#define update_mmu_cache(vma, address, ptep)     do { } while (0)
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#define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
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/*
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 * ZERO_PAGE is a global shared page that is always zero; used
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 * for zero-mapped memory areas etc..
 */
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extern unsigned long empty_zero_page;
extern unsigned long zero_page_mask;

#define ZERO_PAGE(vaddr) \
	(virt_to_page((void *)(empty_zero_page + \
	 (((unsigned long)(vaddr)) &zero_page_mask))))
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#define __HAVE_COLOR_ZERO_PAGE
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/* TODO: s390 cannot support io_remap_pfn_range... */
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#endif /* !__ASSEMBLY__ */

/*
 * PMD_SHIFT determines the size of the area a second-level page
 * table can map
 * PGDIR_SHIFT determines what a third-level page table entry can map
 */
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#ifndef CONFIG_64BIT
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# define PMD_SHIFT	20
# define PUD_SHIFT	20
# define PGDIR_SHIFT	20
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#else /* CONFIG_64BIT */
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# define PMD_SHIFT	20
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# define PUD_SHIFT	31
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# define PGDIR_SHIFT	42
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#endif /* CONFIG_64BIT */
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#define PMD_SIZE        (1UL << PMD_SHIFT)
#define PMD_MASK        (~(PMD_SIZE-1))
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#define PUD_SIZE	(1UL << PUD_SHIFT)
#define PUD_MASK	(~(PUD_SIZE-1))
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#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))
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/*
 * entries per page directory level: the S390 is two-level, so
 * we don't really have any PMD directory physically.
 * for S390 segment-table entries are combined to one PGD
 * that leads to 1024 pte per pgd
 */
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#define PTRS_PER_PTE	256
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#ifndef CONFIG_64BIT
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#define PTRS_PER_PMD	1
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#define PTRS_PER_PUD	1
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#else /* CONFIG_64BIT */
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#define PTRS_PER_PMD	2048
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#define PTRS_PER_PUD	2048
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#endif /* CONFIG_64BIT */
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#define PTRS_PER_PGD	2048
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#define FIRST_USER_ADDRESS  0

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#define pte_ERROR(e) \
	printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
#define pmd_ERROR(e) \
	printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
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#define pud_ERROR(e) \
	printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
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#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))

#ifndef __ASSEMBLY__
/*
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 * The vmalloc and module area will always be on the topmost area of the kernel
 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules.
 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where
 * modules will reside. That makes sure that inter module branches always
 * happen without trampolines and in addition the placement within a 2GB frame
 * is branch prediction unit friendly.
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 */
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extern unsigned long VMALLOC_START;
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extern unsigned long VMALLOC_END;
extern struct page *vmemmap;
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#define VMEM_MAX_PHYS ((unsigned long) vmemmap)
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#ifdef CONFIG_64BIT
extern unsigned long MODULES_VADDR;
extern unsigned long MODULES_END;
#define MODULES_VADDR	MODULES_VADDR
#define MODULES_END	MODULES_END
#define MODULES_LEN	(1UL << 31)
#endif

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/*
 * A 31 bit pagetable entry of S390 has following format:
 *  |   PFRA          |    |  OS  |
 * 0                   0IP0
 * 00000000001111111111222222222233
 * 01234567890123456789012345678901
 *
 * I Page-Invalid Bit:    Page is not available for address-translation
 * P Page-Protection Bit: Store access not possible for page
 *
 * A 31 bit segmenttable entry of S390 has following format:
 *  |   P-table origin      |  |PTL
 * 0                         IC
 * 00000000001111111111222222222233
 * 01234567890123456789012345678901
 *
 * I Segment-Invalid Bit:    Segment is not available for address-translation
 * C Common-Segment Bit:     Segment is not private (PoP 3-30)
 * PTL Page-Table-Length:    Page-table length (PTL+1*16 entries -> up to 256)
 *
 * The 31 bit segmenttable origin of S390 has following format:
 *
 *  |S-table origin   |     | STL |
 * X                   **GPS
 * 00000000001111111111222222222233
 * 01234567890123456789012345678901
 *
 * X Space-Switch event:
 * G Segment-Invalid Bit:     *
 * P Private-Space Bit:       Segment is not private (PoP 3-30)
 * S Storage-Alteration:
 * STL Segment-Table-Length:  Segment-table length (STL+1*16 entries -> up to 2048)
 *
 * A 64 bit pagetable entry of S390 has following format:
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 * |			 PFRA			      |0IPC|  OS  |
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 * 0000000000111111111122222222223333333333444444444455555555556666
 * 0123456789012345678901234567890123456789012345678901234567890123
 *
 * I Page-Invalid Bit:    Page is not available for address-translation
 * P Page-Protection Bit: Store access not possible for page
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 * C Change-bit override: HW is not required to set change bit
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 *
 * A 64 bit segmenttable entry of S390 has following format:
 * |        P-table origin                              |      TT
 * 0000000000111111111122222222223333333333444444444455555555556666
 * 0123456789012345678901234567890123456789012345678901234567890123
 *
 * I Segment-Invalid Bit:    Segment is not available for address-translation
 * C Common-Segment Bit:     Segment is not private (PoP 3-30)
 * P Page-Protection Bit: Store access not possible for page
 * TT Type 00
 *
 * A 64 bit region table entry of S390 has following format:
 * |        S-table origin                             |   TF  TTTL
 * 0000000000111111111122222222223333333333444444444455555555556666
 * 0123456789012345678901234567890123456789012345678901234567890123
 *
 * I Segment-Invalid Bit:    Segment is not available for address-translation
 * TT Type 01
 * TF
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 * TL Table length
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 *
 * The 64 bit regiontable origin of S390 has following format:
 * |      region table origon                          |       DTTL
 * 0000000000111111111122222222223333333333444444444455555555556666
 * 0123456789012345678901234567890123456789012345678901234567890123
 *
 * X Space-Switch event:
 * G Segment-Invalid Bit:  
 * P Private-Space Bit:    
 * S Storage-Alteration:
 * R Real space
 * TL Table-Length:
 *
 * A storage key has the following format:
 * | ACC |F|R|C|0|
 *  0   3 4 5 6 7
 * ACC: access key
 * F  : fetch protection bit
 * R  : referenced bit
 * C  : changed bit
 */

/* Hardware bits in the page table entry */
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#define _PAGE_CO	0x100		/* HW Change-bit override */
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#define _PAGE_RO	0x200		/* HW read-only bit  */
#define _PAGE_INVALID	0x400		/* HW invalid bit    */
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/* Software bits in the page table entry */
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#define _PAGE_SWT	0x001		/* SW pte type bit t */
#define _PAGE_SWX	0x002		/* SW pte type bit x */
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#define _PAGE_SWC	0x004		/* SW pte changed bit */
#define _PAGE_SWR	0x008		/* SW pte referenced bit */
#define _PAGE_SWW	0x010		/* SW pte write bit */
#define _PAGE_SPECIAL	0x020		/* SW associated with special page */
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#define __HAVE_ARCH_PTE_SPECIAL
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/* Set of bits not changed in pte_modify */
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#define _PAGE_CHG_MASK		(PAGE_MASK | _PAGE_SPECIAL | _PAGE_CO | \
				 _PAGE_SWC | _PAGE_SWR)
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/* Six different types of pages. */
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#define _PAGE_TYPE_EMPTY	0x400
#define _PAGE_TYPE_NONE		0x401
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#define _PAGE_TYPE_SWAP		0x403
#define _PAGE_TYPE_FILE		0x601	/* bit 0x002 is used for offset !! */
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#define _PAGE_TYPE_RO		0x200
#define _PAGE_TYPE_RW		0x000
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/*
 * Only four types for huge pages, using the invalid bit and protection bit
 * of a segment table entry.
 */
#define _HPAGE_TYPE_EMPTY	0x020	/* _SEGMENT_ENTRY_INV */
#define _HPAGE_TYPE_NONE	0x220
#define _HPAGE_TYPE_RO		0x200	/* _SEGMENT_ENTRY_RO  */
#define _HPAGE_TYPE_RW		0x000

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/*
 * PTE type bits are rather complicated. handle_pte_fault uses pte_present,
 * pte_none and pte_file to find out the pte type WITHOUT holding the page
 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to
 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs
 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards.
 * This change is done while holding the lock, but the intermediate step
 * of a previously valid pte with the hw invalid bit set can be observed by
 * handle_pte_fault. That makes it necessary that all valid pte types with
 * the hw invalid bit set must be distinguishable from the four pte types
 * empty, none, swap and file.
 *
 *			irxt  ipte  irxt
 * _PAGE_TYPE_EMPTY	1000   ->   1000
 * _PAGE_TYPE_NONE	1001   ->   1001
 * _PAGE_TYPE_SWAP	1011   ->   1011
 * _PAGE_TYPE_FILE	11?1   ->   11?1
 * _PAGE_TYPE_RO	0100   ->   1100
 * _PAGE_TYPE_RW	0000   ->   1000
 *
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 * pte_none is true for bits combinations 1000, 1010, 1100, 1110
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 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
 * pte_file is true for bits combinations 1101, 1111
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 * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid.
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 */

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#ifndef CONFIG_64BIT
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/* Bits in the segment table address-space-control-element */
#define _ASCE_SPACE_SWITCH	0x80000000UL	/* space switch event	    */
#define _ASCE_ORIGIN_MASK	0x7ffff000UL	/* segment table origin	    */
#define _ASCE_PRIVATE_SPACE	0x100	/* private space control	    */
#define _ASCE_ALT_EVENT		0x80	/* storage alteration event control */
#define _ASCE_TABLE_LENGTH	0x7f	/* 128 x 64 entries = 8k	    */
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/* Bits in the segment table entry */
#define _SEGMENT_ENTRY_ORIGIN	0x7fffffc0UL	/* page table origin	    */
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#define _SEGMENT_ENTRY_RO	0x200	/* page protection bit		    */
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#define _SEGMENT_ENTRY_INV	0x20	/* invalid segment table entry	    */
#define _SEGMENT_ENTRY_COMMON	0x10	/* common segment bit		    */
#define _SEGMENT_ENTRY_PTL	0x0f	/* page table length		    */
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#define _SEGMENT_ENTRY		(_SEGMENT_ENTRY_PTL)
#define _SEGMENT_ENTRY_EMPTY	(_SEGMENT_ENTRY_INV)
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/* Page status table bits for virtualization */
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#define PGSTE_ACC_BITS	0xf0000000UL
#define PGSTE_FP_BIT	0x08000000UL
#define PGSTE_PCL_BIT	0x00800000UL
#define PGSTE_HR_BIT	0x00400000UL
#define PGSTE_HC_BIT	0x00200000UL
#define PGSTE_GR_BIT	0x00040000UL
#define PGSTE_GC_BIT	0x00020000UL
#define PGSTE_UR_BIT	0x00008000UL
#define PGSTE_UC_BIT	0x00004000UL	/* user dirty (migration) */
#define PGSTE_IN_BIT	0x00002000UL	/* IPTE notify bit */
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#else /* CONFIG_64BIT */
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/* Bits in the segment/region table address-space-control-element */
#define _ASCE_ORIGIN		~0xfffUL/* segment table origin		    */
#define _ASCE_PRIVATE_SPACE	0x100	/* private space control	    */
#define _ASCE_ALT_EVENT		0x80	/* storage alteration event control */
#define _ASCE_SPACE_SWITCH	0x40	/* space switch event		    */
#define _ASCE_REAL_SPACE	0x20	/* real space control		    */
#define _ASCE_TYPE_MASK		0x0c	/* asce table type mask		    */
#define _ASCE_TYPE_REGION1	0x0c	/* region first table type	    */
#define _ASCE_TYPE_REGION2	0x08	/* region second table type	    */
#define _ASCE_TYPE_REGION3	0x04	/* region third table type	    */
#define _ASCE_TYPE_SEGMENT	0x00	/* segment table type		    */
#define _ASCE_TABLE_LENGTH	0x03	/* region table length		    */

/* Bits in the region table entry */
#define _REGION_ENTRY_ORIGIN	~0xfffUL/* region/segment table origin	    */
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#define _REGION_ENTRY_RO	0x200	/* region protection bit	    */
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#define _REGION_ENTRY_INV	0x20	/* invalid region table entry	    */
#define _REGION_ENTRY_TYPE_MASK	0x0c	/* region/segment table type mask   */
#define _REGION_ENTRY_TYPE_R1	0x0c	/* region first table type	    */
#define _REGION_ENTRY_TYPE_R2	0x08	/* region second table type	    */
#define _REGION_ENTRY_TYPE_R3	0x04	/* region third table type	    */
#define _REGION_ENTRY_LENGTH	0x03	/* region third length		    */

#define _REGION1_ENTRY		(_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
#define _REGION1_ENTRY_EMPTY	(_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV)
#define _REGION2_ENTRY		(_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
#define _REGION2_ENTRY_EMPTY	(_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV)
#define _REGION3_ENTRY		(_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
#define _REGION3_ENTRY_EMPTY	(_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV)

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#define _REGION3_ENTRY_LARGE	0x400	/* RTTE-format control, large page  */
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#define _REGION3_ENTRY_RO	0x200	/* page protection bit		    */
#define _REGION3_ENTRY_CO	0x100	/* change-recording override	    */
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/* Bits in the segment table entry */
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#define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address	    */
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#define _SEGMENT_ENTRY_ORIGIN	~0x7ffUL/* segment table origin		    */
#define _SEGMENT_ENTRY_RO	0x200	/* page protection bit		    */
#define _SEGMENT_ENTRY_INV	0x20	/* invalid segment table entry	    */
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#define _SEGMENT_ENTRY		(0)
#define _SEGMENT_ENTRY_EMPTY	(_SEGMENT_ENTRY_INV)

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#define _SEGMENT_ENTRY_LARGE	0x400	/* STE-format control, large page   */
#define _SEGMENT_ENTRY_CO	0x100	/* change-recording override   */
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#define _SEGMENT_ENTRY_SPLIT_BIT 0	/* THP splitting bit number */
#define _SEGMENT_ENTRY_SPLIT	(1UL << _SEGMENT_ENTRY_SPLIT_BIT)
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/* Set of bits not changed in pmd_modify */
#define _SEGMENT_CHG_MASK	(_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \
				 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO)

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/* Page status table bits for virtualization */
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#define PGSTE_ACC_BITS	0xf000000000000000UL
#define PGSTE_FP_BIT	0x0800000000000000UL
#define PGSTE_PCL_BIT	0x0080000000000000UL
#define PGSTE_HR_BIT	0x0040000000000000UL
#define PGSTE_HC_BIT	0x0020000000000000UL
#define PGSTE_GR_BIT	0x0004000000000000UL
#define PGSTE_GC_BIT	0x0002000000000000UL
#define PGSTE_UR_BIT	0x0000800000000000UL
#define PGSTE_UC_BIT	0x0000400000000000UL	/* user dirty (migration) */
#define PGSTE_IN_BIT	0x0000200000000000UL	/* IPTE notify bit */
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#endif /* CONFIG_64BIT */
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/*
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 * A user page table pointer has the space-switch-event bit, the
 * private-space-control bit and the storage-alteration-event-control
 * bit set. A kernel page table pointer doesn't need them.
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 */
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#define _ASCE_USER_BITS		(_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
				 _ASCE_ALT_EVENT)
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/*
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 * Page protection definitions.
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 */
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#define PAGE_NONE	__pgprot(_PAGE_TYPE_NONE)
#define PAGE_RO		__pgprot(_PAGE_TYPE_RO)
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#define PAGE_RW		__pgprot(_PAGE_TYPE_RO | _PAGE_SWW)
#define PAGE_RWC	__pgprot(_PAGE_TYPE_RW | _PAGE_SWW | _PAGE_SWC)
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#define PAGE_KERNEL	PAGE_RWC
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#define PAGE_SHARED	PAGE_KERNEL
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#define PAGE_COPY	PAGE_RO
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/*
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 * On s390 the page table entry has an invalid bit and a read-only bit.
 * Read permission implies execute permission and write permission
 * implies read permission.
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 */
         /*xwr*/
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#define __P000	PAGE_NONE
#define __P001	PAGE_RO
#define __P010	PAGE_RO
#define __P011	PAGE_RO
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#define __P100	PAGE_RO
#define __P101	PAGE_RO
#define __P110	PAGE_RO
#define __P111	PAGE_RO
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#define __S000	PAGE_NONE
#define __S001	PAGE_RO
#define __S010	PAGE_RW
#define __S011	PAGE_RW
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#define __S100	PAGE_RO
#define __S101	PAGE_RO
#define __S110	PAGE_RW
#define __S111	PAGE_RW
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/*
 * Segment entry (large page) protection definitions.
 */
#define SEGMENT_NONE	__pgprot(_HPAGE_TYPE_NONE)
#define SEGMENT_RO	__pgprot(_HPAGE_TYPE_RO)
#define SEGMENT_RW	__pgprot(_HPAGE_TYPE_RW)

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static inline int mm_exclusive(struct mm_struct *mm)
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{
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	return likely(mm == current->active_mm &&
		      atomic_read(&mm->context.attach_count) <= 1);
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}

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static inline int mm_has_pgste(struct mm_struct *mm)
{
#ifdef CONFIG_PGSTE
	if (unlikely(mm->context.has_pgste))
		return 1;
#endif
	return 0;
}
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/*
 * pgd/pmd/pte query functions
 */
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#ifndef CONFIG_64BIT
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static inline int pgd_present(pgd_t pgd) { return 1; }
static inline int pgd_none(pgd_t pgd)    { return 0; }
static inline int pgd_bad(pgd_t pgd)     { return 0; }
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static inline int pud_present(pud_t pud) { return 1; }
static inline int pud_none(pud_t pud)	 { return 0; }
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static inline int pud_large(pud_t pud)	 { return 0; }
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static inline int pud_bad(pud_t pud)	 { return 0; }

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#else /* CONFIG_64BIT */
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static inline int pgd_present(pgd_t pgd)
{
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	if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
		return 1;
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	return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
}

static inline int pgd_none(pgd_t pgd)
{
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	if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
		return 0;
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	return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL;
}

static inline int pgd_bad(pgd_t pgd)
{
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	/*
	 * With dynamic page table levels the pgd can be a region table
	 * entry or a segment table entry. Check for the bit that are
	 * invalid for either table entry.
	 */
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	unsigned long mask =
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		~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
482 483 484
		~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
	return (pgd_val(pgd) & mask) != 0;
}
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static inline int pud_present(pud_t pud)
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{
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	if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
		return 1;
490
	return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
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}

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static inline int pud_none(pud_t pud)
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{
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	if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
		return 0;
497
	return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL;
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}

500 501 502 503 504 505 506
static inline int pud_large(pud_t pud)
{
	if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3)
		return 0;
	return !!(pud_val(pud) & _REGION3_ENTRY_LARGE);
}

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static inline int pud_bad(pud_t pud)
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{
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	/*
	 * With dynamic page table levels the pud can be a region table
	 * entry or a segment table entry. Check for the bit that are
	 * invalid for either table entry.
	 */
514
	unsigned long mask =
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		~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
516 517
		~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
	return (pud_val(pud) & mask) != 0;
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}

520
#endif /* CONFIG_64BIT */
521

522
static inline int pmd_present(pmd_t pmd)
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{
524 525 526
	unsigned long mask = _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO;
	return (pmd_val(pmd) & mask) == _HPAGE_TYPE_NONE ||
	       !(pmd_val(pmd) & _SEGMENT_ENTRY_INV);
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}

529
static inline int pmd_none(pmd_t pmd)
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{
531 532
	return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) &&
	       !(pmd_val(pmd) & _SEGMENT_ENTRY_RO);
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}

535 536 537 538 539 540 541 542 543
static inline int pmd_large(pmd_t pmd)
{
#ifdef CONFIG_64BIT
	return !!(pmd_val(pmd) & _SEGMENT_ENTRY_LARGE);
#else
	return 0;
#endif
}

544
static inline int pmd_bad(pmd_t pmd)
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{
546 547
	unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV;
	return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY;
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}

550 551 552 553
#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
extern void pmdp_splitting_flush(struct vm_area_struct *vma,
				 unsigned long addr, pmd_t *pmdp);

554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573
#define  __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
extern int pmdp_set_access_flags(struct vm_area_struct *vma,
				 unsigned long address, pmd_t *pmdp,
				 pmd_t entry, int dirty);

#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
				  unsigned long address, pmd_t *pmdp);

#define __HAVE_ARCH_PMD_WRITE
static inline int pmd_write(pmd_t pmd)
{
	return (pmd_val(pmd) & _SEGMENT_ENTRY_RO) == 0;
}

static inline int pmd_young(pmd_t pmd)
{
	return 0;
}

574
static inline int pte_none(pte_t pte)
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{
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	return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT);
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}

579
static inline int pte_present(pte_t pte)
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{
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	unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX;
	return (pte_val(pte) & mask) == _PAGE_TYPE_NONE ||
		(!(pte_val(pte) & _PAGE_INVALID) &&
		 !(pte_val(pte) & _PAGE_SWT));
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}

587
static inline int pte_file(pte_t pte)
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{
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	unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT;
	return (pte_val(pte) & mask) == _PAGE_TYPE_FILE;
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}

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static inline int pte_special(pte_t pte)
{
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	return (pte_val(pte) & _PAGE_SPECIAL);
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}

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#define __HAVE_ARCH_PTE_SAME
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static inline int pte_same(pte_t a, pte_t b)
{
	return pte_val(a) == pte_val(b);
}
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604
static inline pgste_t pgste_get_lock(pte_t *ptep)
605
{
606
	unsigned long new = 0;
607
#ifdef CONFIG_PGSTE
608 609
	unsigned long old;

610
	preempt_disable();
611 612 613
	asm(
		"	lg	%0,%2\n"
		"0:	lgr	%1,%0\n"
614 615
		"	nihh	%0,0xff7f\n"	/* clear PCL bit in old */
		"	oihh	%1,0x0080\n"	/* set PCL bit in new */
616 617 618
		"	csg	%0,%1,%2\n"
		"	jl	0b\n"
		: "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
619
		: "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory");
620
#endif
621
	return __pgste(new);
622 623
}

624
static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
625 626
{
#ifdef CONFIG_PGSTE
627
	asm(
628
		"	nihh	%1,0xff7f\n"	/* clear PCL bit */
629 630
		"	stg	%1,%0\n"
		: "=Q" (ptep[PTRS_PER_PTE])
631 632
		: "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE])
		: "cc", "memory");
633 634 635 636
	preempt_enable();
#endif
}

637 638 639 640 641 642 643
static inline void pgste_set(pte_t *ptep, pgste_t pgste)
{
#ifdef CONFIG_PGSTE
	*(pgste_t *)(ptep + PTRS_PER_PTE) = pgste;
#endif
}

644
static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
645 646
{
#ifdef CONFIG_PGSTE
647
	unsigned long address, bits;
648 649
	unsigned char skey;

650
	if (pte_val(*ptep) & _PAGE_INVALID)
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		return pgste;
652 653
	address = pte_val(*ptep) & PAGE_MASK;
	skey = page_get_storage_key(address);
654 655
	bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
	/* Clear page changed & referenced bit in the storage key */
656
	if (bits & _PAGE_CHANGED)
657
		page_set_storage_key(address, skey ^ bits, 0);
658 659
	else if (bits)
		page_reset_referenced(address);
660
	/* Transfer page changed & referenced bit to guest bits in pgste */
661
	pgste_val(pgste) |= bits << 48;		/* GR bit & GC bit */
662
	/* Get host changed & referenced bits from pgste */
663
	bits |= (pgste_val(pgste) & (PGSTE_HR_BIT | PGSTE_HC_BIT)) >> 52;
664
	/* Transfer page changed & referenced bit to kvm user bits */
665
	pgste_val(pgste) |= bits << 45;		/* PGSTE_UR_BIT & PGSTE_UC_BIT */
666
	/* Clear relevant host bits in pgste. */
667 668
	pgste_val(pgste) &= ~(PGSTE_HR_BIT | PGSTE_HC_BIT);
	pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT);
669 670 671
	/* Copy page access key and fetch protection bit to pgste */
	pgste_val(pgste) |=
		(unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
672 673
	/* Transfer referenced bit to pte */
	pte_val(*ptep) |= (bits & _PAGE_REFERENCED) << 1;
674 675 676 677 678 679 680 681 682 683
#endif
	return pgste;

}

static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
{
#ifdef CONFIG_PGSTE
	int young;

684
	if (pte_val(*ptep) & _PAGE_INVALID)
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		return pgste;
686
	/* Get referenced bit from storage key */
687
	young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK);
688
	if (young)
689
		pgste_val(pgste) |= PGSTE_GR_BIT;
690
	/* Get host referenced bit from pgste */
691 692
	if (pgste_val(pgste) & PGSTE_HR_BIT) {
		pgste_val(pgste) &= ~PGSTE_HR_BIT;
693 694 695 696
		young = 1;
	}
	/* Transfer referenced bit to kvm user bits and pte */
	if (young) {
697
		pgste_val(pgste) |= PGSTE_UR_BIT;
698
		pte_val(*ptep) |= _PAGE_SWR;
699
	}
700 701 702 703
#endif
	return pgste;
}

704
static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry)
705 706
{
#ifdef CONFIG_PGSTE
707
	unsigned long address;
708
	unsigned long nkey;
709

710
	if (pte_val(entry) & _PAGE_INVALID)
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		return;
712
	VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID));
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	address = pte_val(entry) & PAGE_MASK;
714 715 716 717 718
	/*
	 * Set page access key and fetch protection bit from pgste.
	 * The guest C/R information is still in the PGSTE, set real
	 * key C/R to 0.
	 */
719
	nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56;
720
	page_set_storage_key(address, nkey, 0);
721 722 723
#endif
}

724 725 726 727 728 729 730 731 732 733 734 735 736
static inline void pgste_set_pte(pte_t *ptep, pte_t entry)
{
	if (!MACHINE_HAS_ESOP && (pte_val(entry) & _PAGE_SWW)) {
		/*
		 * Without enhanced suppression-on-protection force
		 * the dirty bit on for all writable ptes.
		 */
		pte_val(entry) |= _PAGE_SWC;
		pte_val(entry) &= ~_PAGE_RO;
	}
	*ptep = entry;
}

737 738 739 740
/**
 * struct gmap_struct - guest address space
 * @mm: pointer to the parent mm_struct
 * @table: pointer to the page directory
741
 * @asce: address space control element for gmap page table
742 743 744 745 746 747
 * @crst_list: list of all crst tables used in the guest address space
 */
struct gmap {
	struct list_head list;
	struct mm_struct *mm;
	unsigned long *table;
748
	unsigned long asce;
749
	void *private;
750 751 752 753 754
	struct list_head crst_list;
};

/**
 * struct gmap_rmap - reverse mapping for segment table entries
755
 * @gmap: pointer to the gmap_struct
756
 * @entry: pointer to a segment table entry
757
 * @vmaddr: virtual address in the guest address space
758 759 760
 */
struct gmap_rmap {
	struct list_head list;
761
	struct gmap *gmap;
762
	unsigned long *entry;
763
	unsigned long vmaddr;
764 765 766 767 768
};

/**
 * struct gmap_pgtable - gmap information attached to a page table
 * @vmaddr: address of the 1MB segment in the process virtual memory
769
 * @mapper: list of segment table entries mapping a page table
770 771 772 773 774 775
 */
struct gmap_pgtable {
	unsigned long vmaddr;
	struct list_head mapper;
};

776 777 778 779 780 781 782 783 784
/**
 * struct gmap_notifier - notify function block for page invalidation
 * @notifier_call: address of callback function
 */
struct gmap_notifier {
	struct list_head list;
	void (*notifier_call)(struct gmap *gmap, unsigned long address);
};

785 786 787 788 789
struct gmap *gmap_alloc(struct mm_struct *mm);
void gmap_free(struct gmap *gmap);
void gmap_enable(struct gmap *gmap);
void gmap_disable(struct gmap *gmap);
int gmap_map_segment(struct gmap *gmap, unsigned long from,
790
		     unsigned long to, unsigned long len);
791
int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
792 793
unsigned long __gmap_translate(unsigned long address, struct gmap *);
unsigned long gmap_translate(unsigned long address, struct gmap *);
794
unsigned long __gmap_fault(unsigned long address, struct gmap *);
795
unsigned long gmap_fault(unsigned long address, struct gmap *);
796
void gmap_discard(unsigned long from, unsigned long to, struct gmap *);
797

798 799 800 801 802 803 804 805 806 807
void gmap_register_ipte_notifier(struct gmap_notifier *);
void gmap_unregister_ipte_notifier(struct gmap_notifier *);
int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len);
void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *);

static inline pgste_t pgste_ipte_notify(struct mm_struct *mm,
					unsigned long addr,
					pte_t *ptep, pgste_t pgste)
{
#ifdef CONFIG_PGSTE
808 809
	if (pgste_val(pgste) & PGSTE_IN_BIT) {
		pgste_val(pgste) &= ~PGSTE_IN_BIT;
810 811 812 813 814 815
		gmap_do_ipte_notify(mm, addr, ptep);
	}
#endif
	return pgste;
}

816 817 818 819 820 821 822 823 824 825 826 827
/*
 * Certain architectures need to do special things when PTEs
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */
static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
			      pte_t *ptep, pte_t entry)
{
	pgste_t pgste;

	if (mm_has_pgste(mm)) {
		pgste = pgste_get_lock(ptep);
828 829
		pgste_set_key(ptep, pgste, entry);
		pgste_set_pte(ptep, entry);
830
		pgste_set_unlock(ptep, pgste);
831 832 833
	} else {
		if (!(pte_val(entry) & _PAGE_INVALID) && MACHINE_HAS_EDAT1)
			pte_val(entry) |= _PAGE_CO;
834
		*ptep = entry;
835
	}
836 837
}

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/*
 * query functions pte_write/pte_dirty/pte_young only work if
 * pte_present() is true. Undefined behaviour if not..
 */
842
static inline int pte_write(pte_t pte)
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843
{
844
	return (pte_val(pte) & _PAGE_SWW) != 0;
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845 846
}

847
static inline int pte_dirty(pte_t pte)
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848
{
849
	return (pte_val(pte) & _PAGE_SWC) != 0;
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}

852
static inline int pte_young(pte_t pte)
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{
854 855 856 857
#ifdef CONFIG_PGSTE
	if (pte_val(pte) & _PAGE_SWR)
		return 1;
#endif
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	return 0;
}

/*
 * pgd/pmd/pte modification functions
 */

865
static inline void pgd_clear(pgd_t *pgd)
866
{
867
#ifdef CONFIG_64BIT
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	if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
		pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
870
#endif
871 872
}

873
static inline void pud_clear(pud_t *pud)
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{
875
#ifdef CONFIG_64BIT
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	if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
		pud_val(*pud) = _REGION3_ENTRY_EMPTY;
878
#endif
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}

881
static inline void pmd_clear(pmd_t *pmdp)
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882
{
883
	pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
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}

886
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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887
{
888
	pte_val(*ptep) = _PAGE_TYPE_EMPTY;
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}

/*
 * The following pte modification functions only work if
 * pte_present() is true. Undefined behaviour if not..
 */
895
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
897
	pte_val(pte) &= _PAGE_CHG_MASK;
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	pte_val(pte) |= pgprot_val(newprot);
899 900
	if ((pte_val(pte) & _PAGE_SWC) && (pte_val(pte) & _PAGE_SWW))
		pte_val(pte) &= ~_PAGE_RO;
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	return pte;
}

904
static inline pte_t pte_wrprotect(pte_t pte)
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905
{
906
	pte_val(pte) &= ~_PAGE_SWW;
907
	/* Do not clobber _PAGE_TYPE_NONE pages!  */
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	if (!(pte_val(pte) & _PAGE_INVALID))
		pte_val(pte) |= _PAGE_RO;
	return pte;
}

913
static inline pte_t pte_mkwrite(pte_t pte)
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914
{
915 916 917
	pte_val(pte) |= _PAGE_SWW;
	if (pte_val(pte) & _PAGE_SWC)
		pte_val(pte) &= ~_PAGE_RO;
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	return pte;
}

921
static inline pte_t pte_mkclean(pte_t pte)
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922
{
923
	pte_val(pte) &= ~_PAGE_SWC;
924 925 926
	/* Do not clobber _PAGE_TYPE_NONE pages!  */
	if (!(pte_val(pte) & _PAGE_INVALID))
		pte_val(pte) |= _PAGE_RO;
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	return pte;
}

930
static inline pte_t pte_mkdirty(pte_t pte)
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931
{
932 933 934
	pte_val(pte) |= _PAGE_SWC;
	if (pte_val(pte) & _PAGE_SWW)
		pte_val(pte) &= ~_PAGE_RO;
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	return pte;
}

938
static inline pte_t pte_mkold(pte_t pte)
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939
{
940 941 942
#ifdef CONFIG_PGSTE
	pte_val(pte) &= ~_PAGE_SWR;
#endif
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943 944 945
	return pte;
}

946
static inline pte_t pte_mkyoung(pte_t pte)
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947 948 949 950
{
	return pte;
}

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static inline pte_t pte_mkspecial(pte_t pte)
{
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953
	pte_val(pte) |= _PAGE_SPECIAL;
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954 955 956
	return pte;
}

957 958 959 960 961 962 963 964
#ifdef CONFIG_HUGETLB_PAGE
static inline pte_t pte_mkhuge(pte_t pte)
{
	pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO);
	return pte;
}
#endif

965
/*
966
 * Get (and clear) the user dirty bit for a pte.
967
 */
968 969
static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
						 pte_t *ptep)
970
{
971 972 973 974 975 976
	pgste_t pgste;
	int dirty = 0;

	if (mm_has_pgste(mm)) {
		pgste = pgste_get_lock(ptep);
		pgste = pgste_update_all(ptep, pgste);
977 978
		dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT);
		pgste_val(pgste) &= ~PGSTE_UC_BIT;
979 980
		pgste_set_unlock(ptep, pgste);
		return dirty;
981 982 983
	}
	return dirty;
}
984 985 986 987 988 989 990 991 992 993 994 995 996

/*
 * Get (and clear) the user referenced bit for a pte.
 */
static inline int ptep_test_and_clear_user_young(struct mm_struct *mm,
						 pte_t *ptep)
{
	pgste_t pgste;
	int young = 0;

	if (mm_has_pgste(mm)) {
		pgste = pgste_get_lock(ptep);
		pgste = pgste_update_young(ptep, pgste);
997 998
		young = !!(pgste_val(pgste) & PGSTE_UR_BIT);
		pgste_val(pgste) &= ~PGSTE_UR_BIT;
999 1000 1001 1002
		pgste_set_unlock(ptep, pgste);
	}
	return young;
}
1003

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1004 1005 1006
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
					    unsigned long addr, pte_t *ptep)
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{
1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018
	pgste_t pgste;
	pte_t pte;

	if (mm_has_pgste(vma->vm_mm)) {
		pgste = pgste_get_lock(ptep);
		pgste = pgste_update_young(ptep, pgste);
		pte = *ptep;
		*ptep = pte_mkold(pte);
		pgste_set_unlock(ptep, pgste);
		return pte_young(pte);
	}
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	return 0;
}

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#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
					 unsigned long address, pte_t *ptep)
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{
1026 1027 1028 1029 1030
	/* No need to flush TLB
	 * On s390 reference bits are in storage key and never in TLB
	 * With virtualization we handle the reference bit, without we
	 * we can simply return */
	return ptep_test_and_clear_young(vma, address, ptep);
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}

1033
static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
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{
1035
	if (!(pte_val(*ptep) & _PAGE_INVALID)) {
1036
#ifndef CONFIG_64BIT
1037
		/* pto must point to the start of the segment table */
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		pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
1039 1040 1041 1042
#else
		/* ipte in zarch mode can do the math */
		pte_t *pto = ptep;
#endif
1043 1044 1045 1046
		asm volatile(
			"	ipte	%2,%3"
			: "=m" (*ptep) : "m" (*ptep),
			  "a" (pto), "a" (address));
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	}
1048 1049
}

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/*
 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
 * both clear the TLB for the unmapped pte. The reason is that
 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
 * to modify an active pte. The sequence is
 *   1) ptep_get_and_clear
 *   2) set_pte_at
 *   3) flush_tlb_range
 * On s390 the tlb needs to get flushed with the modification of the pte
 * if the pte is active. The only way how this can be implemented is to
 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
 * is a nop.
 */
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
1064 1065 1066 1067 1068 1069 1070
static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
				       unsigned long address, pte_t *ptep)
{
	pgste_t pgste;
	pte_t pte;

	mm->context.flush_mm = 1;
1071
	if (mm_has_pgste(mm)) {
1072
		pgste = pgste_get_lock(ptep);
1073 1074
		pgste = pgste_ipte_notify(mm, address, ptep, pgste);
	}
1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092

	pte = *ptep;
	if (!mm_exclusive(mm))
		__ptep_ipte(address, ptep);
	pte_val(*ptep) = _PAGE_TYPE_EMPTY;

	if (mm_has_pgste(mm)) {
		pgste = pgste_update_all(&pte, pgste);
		pgste_set_unlock(ptep, pgste);
	}
	return pte;
}

#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
					   unsigned long address,
					   pte_t *ptep)
{
1093
	pgste_t pgste;
1094 1095 1096
	pte_t pte;

	mm->context.flush_mm = 1;
1097 1098 1099 1100
	if (mm_has_pgste(mm)) {
		pgste = pgste_get_lock(ptep);
		pgste_ipte_notify(mm, address, ptep, pgste);
	}
1101 1102 1103 1104

	pte = *ptep;
	if (!mm_exclusive(mm))
		__ptep_ipte(address, ptep);
1105

1106
	if (mm_has_pgste(mm)) {
1107
		pgste = pgste_update_all(&pte, pgste);
1108 1109
		pgste_set(ptep, pgste);
	}
1110 1111 1112 1113 1114 1115 1116
	return pte;
}

static inline void ptep_modify_prot_commit(struct mm_struct *mm,
					   unsigned long address,
					   pte_t *ptep, pte_t pte)
{
1117 1118
	pgste_t pgste;

1119
	if (mm_has_pgste(mm)) {
1120 1121
		pgste = *(pgste_t *)(ptep + PTRS_PER_PTE);
		pgste_set_key(ptep, pgste, pte);
1122
		pgste_set_pte(ptep, pte);
1123
		pgste_set_unlock(ptep, pgste);
1124 1125
	} else
		*ptep = pte;
1126
}
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#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
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static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
				     unsigned long address, pte_t *ptep)
{
1132 1133 1134
	pgste_t pgste;
	pte_t pte;

1135
	if (mm_has_pgste(vma->vm_mm)) {
1136
		pgste = pgste_get_lock(ptep);
1137 1138
		pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
	}
1139 1140 1141 1142 1143 1144 1145 1146 1147

	pte = *ptep;
	__ptep_ipte(address, ptep);
	pte_val(*ptep) = _PAGE_TYPE_EMPTY;

	if (mm_has_pgste(vma->vm_mm)) {
		pgste = pgste_update_all(&pte, pgste);
		pgste_set_unlock(ptep, pgste);
	}
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	return pte;
}

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/*
 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
 * cannot be accessed while the batched unmap is running. In this case
 * full==1 and a simple pte_clear is enough. See tlb.h.
 */
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
1160
					    unsigned long address,
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					    pte_t *ptep, int full)
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{
1163 1164 1165
	pgste_t pgste;
	pte_t pte;

1166
	if (mm_has_pgste(mm)) {
1167
		pgste = pgste_get_lock(ptep);
1168 1169 1170
		if (!full)
			pgste = pgste_ipte_notify(mm, address, ptep, pgste);
	}
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1172 1173 1174 1175 1176 1177 1178 1179 1180
	pte = *ptep;
	if (!full)
		__ptep_ipte(address, ptep);
	pte_val(*ptep) = _PAGE_TYPE_EMPTY;

	if (mm_has_pgste(mm)) {
		pgste = pgste_update_all(&pte, pgste);
		pgste_set_unlock(ptep, pgste);
	}
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	return pte;
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}

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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
1185 1186 1187 1188 1189 1190 1191 1192
static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
				       unsigned long address, pte_t *ptep)
{
	pgste_t pgste;
	pte_t pte = *ptep;

	if (pte_write(pte)) {
		mm->context.flush_mm = 1;
1193
		if (mm_has_pgste(mm)) {
1194
			pgste = pgste_get_lock(ptep);
1195 1196
			pgste = pgste_ipte_notify(mm, address, ptep, pgste);
		}
1197 1198 1199

		if (!mm_exclusive(mm))
			__ptep_ipte(address, ptep);
1200
		pte = pte_wrprotect(pte);
1201

1202 1203
		if (mm_has_pgste(mm)) {
			pgste_set_pte(ptep, pte);
1204
			pgste_set_unlock(ptep, pgste);
1205 1206
		} else
			*ptep = pte;
1207 1208 1209
	}
	return pte;
}
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#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
1212 1213 1214 1215 1216 1217 1218 1219
static inline int ptep_set_access_flags(struct vm_area_struct *vma,
					unsigned long address, pte_t *ptep,
					pte_t entry, int dirty)
{
	pgste_t pgste;

	if (pte_same(*ptep, entry))
		return 0;
1220
	if (mm_has_pgste(vma->vm_mm)) {
1221
		pgste = pgste_get_lock(ptep);
1222 1223
		pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
	}
1224 1225 1226

	__ptep_ipte(address, ptep);

1227 1228
	if (mm_has_pgste(vma->vm_mm)) {
		pgste_set_pte(ptep, entry);
1229
		pgste_set_unlock(ptep, pgste);
1230 1231
	} else
		*ptep = entry;
1232 1233
	return 1;
}
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/*
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 */
static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
{
	pte_t __pte;
	pte_val(__pte) = physpage + pgprot_val(pgprot);
	return __pte;
}

1246 1247
static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
{
1248
	unsigned long physpage = page_to_phys(page);
1249
	pte_t __pte = mk_pte_phys(physpage, pgprot);
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1251 1252 1253 1254 1255
	if ((pte_val(__pte) & _PAGE_SWW) && PageDirty(page)) {
		pte_val(__pte) |= _PAGE_SWC;
		pte_val(__pte) &= ~_PAGE_RO;
	}
	return __pte;
1256 1257
}

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#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
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#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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1266
#ifndef CONFIG_64BIT
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#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
#define pud_deref(pmd) ({ BUG(); 0UL; })
#define pgd_deref(pmd) ({ BUG(); 0UL; })
1271

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#define pud_offset(pgd, address) ((pud_t *) pgd)
#define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
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1275
#else /* CONFIG_64BIT */
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#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
#define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
1279
#define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
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1281 1282
static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
{
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	pud_t *pud = (pud_t *) pgd;
	if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
		pud = (pud_t *) pgd_deref(*pgd);
1286 1287
	return pud  + pud_index(address);
}
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static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
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{
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	pmd_t *pmd = (pmd_t *) pud;
	if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
		pmd = (pmd_t *) pud_deref(*pud);
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	return pmd + pmd_index(address);
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}

1297
#endif /* CONFIG_64BIT */
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#define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
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/* Find an entry in the lowest level page table.. */
#define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
#define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
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#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
#define pte_unmap(pte) do { } while (0)

1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326
static inline void __pmd_idte(unsigned long address, pmd_t *pmdp)
{
	unsigned long sto = (unsigned long) pmdp -
			    pmd_index(address) * sizeof(pmd_t);

	if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INV)) {
		asm volatile(
			"	.insn	rrf,0xb98e0000,%2,%3,0,0"
			: "=m" (*pmdp)
			: "m" (*pmdp), "a" (sto),
			  "a" ((address & HPAGE_MASK))
			: "cc"
		);
	}
}

1327
#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
1328 1329
static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
{
1330 1331 1332 1333 1334 1335 1336 1337 1338
	/*
	 * pgprot is PAGE_NONE, PAGE_RO, or PAGE_RW (see __Pxxx / __Sxxx)
	 * Convert to segment table entry format.
	 */
	if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
		return pgprot_val(SEGMENT_NONE);
	if (pgprot_val(pgprot) == pgprot_val(PAGE_RO))
		return pgprot_val(SEGMENT_RO);
	return pgprot_val(SEGMENT_RW);
1339 1340 1341 1342 1343 1344 1345 1346 1347
}

static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
{
	pmd_val(pmd) &= _SEGMENT_CHG_MASK;
	pmd_val(pmd) |= massage_pgprot_pmd(newprot);
	return pmd;
}

1348
static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1349
{
1350 1351 1352
	pmd_t __pmd;
	pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot);
	return __pmd;
1353 1354 1355 1356
}

static inline pmd_t pmd_mkwrite(pmd_t pmd)
{
1357 1358 1359
	/* Do not clobber _HPAGE_TYPE_NONE pages! */
	if (!(pmd_val(pmd) & _SEGMENT_ENTRY_INV))
		pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO;
1360 1361
	return pmd;
}
1362 1363 1364 1365 1366
#endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */

#ifdef CONFIG_TRANSPARENT_HUGEPAGE

#define __HAVE_ARCH_PGTABLE_DEPOSIT
1367 1368
extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
				       pgtable_t pgtable);
1369 1370

#define __HAVE_ARCH_PGTABLE_WITHDRAW
1371
extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390

static inline int pmd_trans_splitting(pmd_t pmd)
{
	return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT;
}

static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
			      pmd_t *pmdp, pmd_t entry)
{
	if (!(pmd_val(entry) & _SEGMENT_ENTRY_INV) && MACHINE_HAS_EDAT1)
		pmd_val(entry) |= _SEGMENT_ENTRY_CO;
	*pmdp = entry;
}

static inline pmd_t pmd_mkhuge(pmd_t pmd)
{
	pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE;
	return pmd;
}
1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474

static inline pmd_t pmd_wrprotect(pmd_t pmd)
{
	pmd_val(pmd) |= _SEGMENT_ENTRY_RO;
	return pmd;
}

static inline pmd_t pmd_mkdirty(pmd_t pmd)
{
	/* No dirty bit in the segment table entry. */
	return pmd;
}

static inline pmd_t pmd_mkold(pmd_t pmd)
{
	/* No referenced bit in the segment table entry. */
	return pmd;
}

static inline pmd_t pmd_mkyoung(pmd_t pmd)
{
	/* No referenced bit in the segment table entry. */
	return pmd;
}

#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
					    unsigned long address, pmd_t *pmdp)
{
	unsigned long pmd_addr = pmd_val(*pmdp) & HPAGE_MASK;
	long tmp, rc;
	int counter;

	rc = 0;
	if (MACHINE_HAS_RRBM) {
		counter = PTRS_PER_PTE >> 6;
		asm volatile(
			"0:	.insn	rre,0xb9ae0000,%0,%3\n"	/* rrbm */
			"	ogr	%1,%0\n"
			"	la	%3,0(%4,%3)\n"
			"	brct	%2,0b\n"
			: "=&d" (tmp), "+&d" (rc), "+d" (counter),
			  "+a" (pmd_addr)
			: "a" (64 * 4096UL) : "cc");
		rc = !!rc;
	} else {
		counter = PTRS_PER_PTE;
		asm volatile(
			"0:	rrbe	0,%2\n"
			"	la	%2,0(%3,%2)\n"
			"	brc	12,1f\n"
			"	lhi	%0,1\n"
			"1:	brct	%1,0b\n"
			: "+d" (rc), "+d" (counter), "+a" (pmd_addr)
			: "a" (4096UL) : "cc");
	}
	return rc;
}

#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
				       unsigned long address, pmd_t *pmdp)
{
	pmd_t pmd = *pmdp;

	__pmd_idte(address, pmdp);
	pmd_clear(pmdp);
	return pmd;
}

#define __HAVE_ARCH_PMDP_CLEAR_FLUSH
static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma,
				     unsigned long address, pmd_t *pmdp)
{
	return pmdp_get_and_clear(vma->vm_mm, address, pmdp);
}

#define __HAVE_ARCH_PMDP_INVALIDATE
static inline void pmdp_invalidate(struct vm_area_struct *vma,
				   unsigned long address, pmd_t *pmdp)
{
	__pmd_idte(address, pmdp);
}

1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486
#define __HAVE_ARCH_PMDP_SET_WRPROTECT
static inline void pmdp_set_wrprotect(struct mm_struct *mm,
				      unsigned long address, pmd_t *pmdp)
{
	pmd_t pmd = *pmdp;

	if (pmd_write(pmd)) {
		__pmd_idte(address, pmdp);
		set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd));
	}
}

1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501
#define pfn_pmd(pfn, pgprot)	mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot))
#define mk_pmd(page, pgprot)	pfn_pmd(page_to_pfn(page), (pgprot))

static inline int pmd_trans_huge(pmd_t pmd)
{
	return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE;
}

static inline int has_transparent_hugepage(void)
{
	return MACHINE_HAS_HPAGE ? 1 : 0;
}

static inline unsigned long pmd_pfn(pmd_t pmd)
{
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	return pmd_val(pmd) >> PAGE_SHIFT;
1503
}
1504 1505
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */

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/*
 * 31 bit swap entry format:
 * A page-table entry has some bits we have to treat in a special way.
 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
 * exception will occur instead of a page translation exception. The
 * specifiation exception has the bad habit not to store necessary
 * information in the lowcore.
 * Bit 21 and bit 22 are the page invalid bit and the page protection
 * bit. We set both to indicate a swapped page.
 * Bit 30 and 31 are used to distinguish the different page types. For
 * a swapped page these bits need to be zero.
 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
 * plus 24 for the offset.
 * 0|     offset        |0110|o|type |00|
 * 0 0000000001111111111 2222 2 22222 33
 * 0 1234567890123456789 0123 4 56789 01
 *
 * 64 bit swap entry format:
 * A page-table entry has some bits we have to treat in a special way.
 * Bits 52 and bit 55 have to be zero, otherwise an specification
 * exception will occur instead of a page translation exception. The
 * specifiation exception has the bad habit not to store necessary
 * information in the lowcore.
 * Bit 53 and bit 54 are the page invalid bit and the page protection
 * bit. We set both to indicate a swapped page.
 * Bit 62 and 63 are used to distinguish the different page types. For
 * a swapped page these bits need to be zero.
 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
 * plus 56 for the offset.
 * |                      offset                        |0110|o|type |00|
 *  0000000000111111111122222222223333333333444444444455 5555 5 55566 66
 *  0123456789012345678901234567890123456789012345678901 2345 6 78901 23
 */
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#ifndef CONFIG_64BIT
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#define __SWP_OFFSET_MASK (~0UL >> 12)
#else
#define __SWP_OFFSET_MASK (~0UL >> 11)
#endif
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static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
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{
	pte_t pte;
	offset &= __SWP_OFFSET_MASK;
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	pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
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		((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
	return pte;
}

#define __swp_type(entry)	(((entry).val >> 2) & 0x1f)
#define __swp_offset(entry)	(((entry).val >> 11) | (((entry).val >> 7) & 1))
#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })

#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)	((pte_t) { (x).val })

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#ifndef CONFIG_64BIT
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# define PTE_FILE_MAX_BITS	26
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#else /* CONFIG_64BIT */
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# define PTE_FILE_MAX_BITS	59
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#endif /* CONFIG_64BIT */
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#define pte_to_pgoff(__pte) \
	((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))

#define pgoff_to_pte(__off) \
	((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
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		   | _PAGE_TYPE_FILE })
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#endif /* !__ASSEMBLY__ */

#define kern_addr_valid(addr)   (1)

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extern int vmem_add_mapping(unsigned long start, unsigned long size);
extern int vmem_remove_mapping(unsigned long start, unsigned long size);
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extern int s390_enable_sie(void);
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/*
 * No page table caches to initialise
 */
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static inline void pgtable_cache_init(void) { }
static inline void check_pgt_cache(void) { }
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#include <asm-generic/pgtable.h>

#endif /* _S390_PAGE_H */