talitos.c 89.3 KB
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/*
 * talitos - Freescale Integrated Security Engine (SEC) device driver
 *
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 * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
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 *
 * Scatterlist Crypto API glue code copied from files with the following:
 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
 *
 * Crypto algorithm registration code copied from hifn driver:
 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/crypto.h>
#include <linux/hw_random.h>
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#include <linux/of_address.h>
#include <linux/of_irq.h>
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#include <linux/of_platform.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/rtnetlink.h>
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#include <linux/slab.h>
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#include <crypto/algapi.h>
#include <crypto/aes.h>
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#include <crypto/des.h>
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#include <crypto/sha.h>
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#include <crypto/md5.h>
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#include <crypto/internal/aead.h>
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#include <crypto/authenc.h>
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#include <crypto/skcipher.h>
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#include <crypto/hash.h>
#include <crypto/internal/hash.h>
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#include <crypto/scatterwalk.h>
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#include "talitos.h"

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static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
			   bool is_sec1)
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{
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	ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
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	if (!is_sec1)
		ptr->eptr = upper_32_bits(dma_addr);
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}

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static void to_talitos_ptr_len(struct talitos_ptr *ptr, unsigned int len,
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			       bool is_sec1)
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{
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	if (is_sec1) {
		ptr->res = 0;
		ptr->len1 = cpu_to_be16(len);
	} else {
		ptr->len = cpu_to_be16(len);
	}
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}

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static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
					   bool is_sec1)
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{
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	if (is_sec1)
		return be16_to_cpu(ptr->len1);
	else
		return be16_to_cpu(ptr->len);
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}

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static void to_talitos_ptr_extent_clear(struct talitos_ptr *ptr, bool is_sec1)
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{
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	if (!is_sec1)
		ptr->j_extent = 0;
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}

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/*
 * map virtual single (contiguous) pointer to h/w descriptor pointer
 */
static void map_single_talitos_ptr(struct device *dev,
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				   struct talitos_ptr *ptr,
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				   unsigned int len, void *data,
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				   enum dma_data_direction dir)
{
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	dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
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	struct talitos_private *priv = dev_get_drvdata(dev);
	bool is_sec1 = has_ftr_sec1(priv);
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	to_talitos_ptr_len(ptr, len, is_sec1);
	to_talitos_ptr(ptr, dma_addr, is_sec1);
	to_talitos_ptr_extent_clear(ptr, is_sec1);
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}

/*
 * unmap bus single (contiguous) h/w descriptor pointer
 */
static void unmap_single_talitos_ptr(struct device *dev,
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				     struct talitos_ptr *ptr,
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				     enum dma_data_direction dir)
{
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	struct talitos_private *priv = dev_get_drvdata(dev);
	bool is_sec1 = has_ftr_sec1(priv);

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	dma_unmap_single(dev, be32_to_cpu(ptr->ptr),
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			 from_talitos_ptr_len(ptr, is_sec1), dir);
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}

static int reset_channel(struct device *dev, int ch)
{
	struct talitos_private *priv = dev_get_drvdata(dev);
	unsigned int timeout = TALITOS_TIMEOUT;
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	bool is_sec1 = has_ftr_sec1(priv);
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	if (is_sec1) {
		setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
			  TALITOS1_CCCR_LO_RESET);
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		while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR_LO) &
			TALITOS1_CCCR_LO_RESET) && --timeout)
			cpu_relax();
	} else {
		setbits32(priv->chan[ch].reg + TALITOS_CCCR,
			  TALITOS2_CCCR_RESET);

		while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
			TALITOS2_CCCR_RESET) && --timeout)
			cpu_relax();
	}
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	if (timeout == 0) {
		dev_err(dev, "failed to reset channel %d\n", ch);
		return -EIO;
	}

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	/* set 36-bit addressing, done writeback enable and done IRQ enable */
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	setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
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		  TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
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	/* and ICCR writeback, if available */
	if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
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		setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
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		          TALITOS_CCCR_LO_IWSE);

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	return 0;
}

static int reset_device(struct device *dev)
{
	struct talitos_private *priv = dev_get_drvdata(dev);
	unsigned int timeout = TALITOS_TIMEOUT;
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	bool is_sec1 = has_ftr_sec1(priv);
	u32 mcr = is_sec1 ? TALITOS1_MCR_SWR : TALITOS2_MCR_SWR;
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	setbits32(priv->reg + TALITOS_MCR, mcr);
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	while ((in_be32(priv->reg + TALITOS_MCR) & mcr)
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	       && --timeout)
		cpu_relax();

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	if (priv->irq[1]) {
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		mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
		setbits32(priv->reg + TALITOS_MCR, mcr);
	}

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	if (timeout == 0) {
		dev_err(dev, "failed to reset device\n");
		return -EIO;
	}

	return 0;
}

/*
 * Reset and initialize the device
 */
static int init_device(struct device *dev)
{
	struct talitos_private *priv = dev_get_drvdata(dev);
	int ch, err;
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	bool is_sec1 = has_ftr_sec1(priv);
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	/*
	 * Master reset
	 * errata documentation: warning: certain SEC interrupts
	 * are not fully cleared by writing the MCR:SWR bit,
	 * set bit twice to completely reset
	 */
	err = reset_device(dev);
	if (err)
		return err;

	err = reset_device(dev);
	if (err)
		return err;

	/* reset channels */
	for (ch = 0; ch < priv->num_channels; ch++) {
		err = reset_channel(dev, ch);
		if (err)
			return err;
	}

	/* enable channel done and error interrupts */
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	if (is_sec1) {
		clrbits32(priv->reg + TALITOS_IMR, TALITOS1_IMR_INIT);
		clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT);
		/* disable parity error check in DEU (erroneous? test vect.) */
		setbits32(priv->reg_deu + TALITOS_EUICR, TALITOS1_DEUICR_KPE);
	} else {
		setbits32(priv->reg + TALITOS_IMR, TALITOS2_IMR_INIT);
		setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT);
	}
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	/* disable integrity check error interrupts (use writeback instead) */
	if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
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		setbits32(priv->reg_mdeu + TALITOS_EUICR_LO,
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		          TALITOS_MDEUICR_LO_ICE);

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	return 0;
}

/**
 * talitos_submit - submits a descriptor to the device for processing
 * @dev:	the SEC device to be used
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 * @ch:		the SEC device channel to be used
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 * @desc:	the descriptor to be processed by the device
 * @callback:	whom to call when processing is complete
 * @context:	a handle for use by caller (optional)
 *
 * desc must contain valid dma-mapped (bus physical) address pointers.
 * callback must check err and feedback in descriptor header
 * for device processing status.
 */
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int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
		   void (*callback)(struct device *dev,
				    struct talitos_desc *desc,
				    void *context, int error),
		   void *context)
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{
	struct talitos_private *priv = dev_get_drvdata(dev);
	struct talitos_request *request;
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	unsigned long flags;
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	int head;
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	bool is_sec1 = has_ftr_sec1(priv);
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	spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
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	if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
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		/* h/w fifo is full */
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		spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
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		return -EAGAIN;
	}

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	head = priv->chan[ch].head;
	request = &priv->chan[ch].fifo[head];
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	/* map descriptor and save caller data */
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	if (is_sec1) {
		desc->hdr1 = desc->hdr;
		desc->next_desc = 0;
		request->dma_desc = dma_map_single(dev, &desc->hdr1,
						   TALITOS_DESC_SIZE,
						   DMA_BIDIRECTIONAL);
	} else {
		request->dma_desc = dma_map_single(dev, desc,
						   TALITOS_DESC_SIZE,
						   DMA_BIDIRECTIONAL);
	}
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	request->callback = callback;
	request->context = context;

	/* increment fifo head */
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	priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
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	smp_wmb();
	request->desc = desc;

	/* GO! */
	wmb();
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	out_be32(priv->chan[ch].reg + TALITOS_FF,
		 upper_32_bits(request->dma_desc));
	out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
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		 lower_32_bits(request->dma_desc));
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	spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
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	return -EINPROGRESS;
}
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EXPORT_SYMBOL(talitos_submit);
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/*
 * process what was done, notify callback of error if not
 */
static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
{
	struct talitos_private *priv = dev_get_drvdata(dev);
	struct talitos_request *request, saved_req;
	unsigned long flags;
	int tail, status;
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	bool is_sec1 = has_ftr_sec1(priv);
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	spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
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	tail = priv->chan[ch].tail;
	while (priv->chan[ch].fifo[tail].desc) {
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		__be32 hdr;

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		request = &priv->chan[ch].fifo[tail];
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		/* descriptors with their done bits set don't get the error */
		rmb();
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		hdr = is_sec1 ? request->desc->hdr1 : request->desc->hdr;

		if ((hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
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			status = 0;
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		else
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			if (!error)
				break;
			else
				status = error;

		dma_unmap_single(dev, request->dma_desc,
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				 TALITOS_DESC_SIZE,
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				 DMA_BIDIRECTIONAL);
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		/* copy entries so we can call callback outside lock */
		saved_req.desc = request->desc;
		saved_req.callback = request->callback;
		saved_req.context = request->context;

		/* release request entry in fifo */
		smp_wmb();
		request->desc = NULL;

		/* increment fifo tail */
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		priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
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		spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
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		atomic_dec(&priv->chan[ch].submit_count);
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		saved_req.callback(dev, saved_req.desc, saved_req.context,
				   status);
		/* channel may resume processing in single desc error case */
		if (error && !reset_ch && status == error)
			return;
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		spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
		tail = priv->chan[ch].tail;
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	}

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	spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
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}

/*
 * process completed requests for channels that have done status
 */
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#define DEF_TALITOS1_DONE(name, ch_done_mask)				\
static void talitos1_done_##name(unsigned long data)			\
{									\
	struct device *dev = (struct device *)data;			\
	struct talitos_private *priv = dev_get_drvdata(dev);		\
	unsigned long flags;						\
									\
	if (ch_done_mask & 0x10000000)					\
		flush_channel(dev, 0, 0, 0);			\
	if (priv->num_channels == 1)					\
		goto out;						\
	if (ch_done_mask & 0x40000000)					\
		flush_channel(dev, 1, 0, 0);			\
	if (ch_done_mask & 0x00010000)					\
		flush_channel(dev, 2, 0, 0);			\
	if (ch_done_mask & 0x00040000)					\
		flush_channel(dev, 3, 0, 0);			\
									\
out:									\
	/* At this point, all completed channels have been processed */	\
	/* Unmask done interrupts for channels completed later on. */	\
	spin_lock_irqsave(&priv->reg_lock, flags);			\
	clrbits32(priv->reg + TALITOS_IMR, ch_done_mask);		\
	clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT);	\
	spin_unlock_irqrestore(&priv->reg_lock, flags);			\
}

DEF_TALITOS1_DONE(4ch, TALITOS1_ISR_4CHDONE)

#define DEF_TALITOS2_DONE(name, ch_done_mask)				\
static void talitos2_done_##name(unsigned long data)			\
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{									\
	struct device *dev = (struct device *)data;			\
	struct talitos_private *priv = dev_get_drvdata(dev);		\
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	unsigned long flags;						\
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									\
	if (ch_done_mask & 1)						\
		flush_channel(dev, 0, 0, 0);				\
	if (priv->num_channels == 1)					\
		goto out;						\
	if (ch_done_mask & (1 << 2))					\
		flush_channel(dev, 1, 0, 0);				\
	if (ch_done_mask & (1 << 4))					\
		flush_channel(dev, 2, 0, 0);				\
	if (ch_done_mask & (1 << 6))					\
		flush_channel(dev, 3, 0, 0);				\
									\
out:									\
	/* At this point, all completed channels have been processed */	\
	/* Unmask done interrupts for channels completed later on. */	\
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	spin_lock_irqsave(&priv->reg_lock, flags);			\
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	setbits32(priv->reg + TALITOS_IMR, ch_done_mask);		\
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	setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT);	\
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	spin_unlock_irqrestore(&priv->reg_lock, flags);			\
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}
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DEF_TALITOS2_DONE(4ch, TALITOS2_ISR_4CHDONE)
DEF_TALITOS2_DONE(ch0_2, TALITOS2_ISR_CH_0_2_DONE)
DEF_TALITOS2_DONE(ch1_3, TALITOS2_ISR_CH_1_3_DONE)
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/*
 * locate current (offending) descriptor
 */
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static u32 current_desc_hdr(struct device *dev, int ch)
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{
	struct talitos_private *priv = dev_get_drvdata(dev);
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	int tail, iter;
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	dma_addr_t cur_desc;

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	cur_desc = ((u64)in_be32(priv->chan[ch].reg + TALITOS_CDPR)) << 32;
	cur_desc |= in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
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	if (!cur_desc) {
		dev_err(dev, "CDPR is NULL, giving up search for offending descriptor\n");
		return 0;
	}

	tail = priv->chan[ch].tail;

	iter = tail;
	while (priv->chan[ch].fifo[iter].dma_desc != cur_desc) {
		iter = (iter + 1) & (priv->fifo_len - 1);
		if (iter == tail) {
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			dev_err(dev, "couldn't locate current descriptor\n");
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			return 0;
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		}
	}

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	return priv->chan[ch].fifo[iter].desc->hdr;
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}

/*
 * user diagnostics; report root cause of error based on execution unit status
 */
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static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
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{
	struct talitos_private *priv = dev_get_drvdata(dev);
	int i;

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	if (!desc_hdr)
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		desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
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	switch (desc_hdr & DESC_HDR_SEL0_MASK) {
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	case DESC_HDR_SEL0_AFEU:
		dev_err(dev, "AFEUISR 0x%08x_%08x\n",
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			in_be32(priv->reg_afeu + TALITOS_EUISR),
			in_be32(priv->reg_afeu + TALITOS_EUISR_LO));
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		break;
	case DESC_HDR_SEL0_DEU:
		dev_err(dev, "DEUISR 0x%08x_%08x\n",
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			in_be32(priv->reg_deu + TALITOS_EUISR),
			in_be32(priv->reg_deu + TALITOS_EUISR_LO));
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		break;
	case DESC_HDR_SEL0_MDEUA:
	case DESC_HDR_SEL0_MDEUB:
		dev_err(dev, "MDEUISR 0x%08x_%08x\n",
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			in_be32(priv->reg_mdeu + TALITOS_EUISR),
			in_be32(priv->reg_mdeu + TALITOS_EUISR_LO));
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		break;
	case DESC_HDR_SEL0_RNG:
		dev_err(dev, "RNGUISR 0x%08x_%08x\n",
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			in_be32(priv->reg_rngu + TALITOS_ISR),
			in_be32(priv->reg_rngu + TALITOS_ISR_LO));
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		break;
	case DESC_HDR_SEL0_PKEU:
		dev_err(dev, "PKEUISR 0x%08x_%08x\n",
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			in_be32(priv->reg_pkeu + TALITOS_EUISR),
			in_be32(priv->reg_pkeu + TALITOS_EUISR_LO));
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		break;
	case DESC_HDR_SEL0_AESU:
		dev_err(dev, "AESUISR 0x%08x_%08x\n",
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			in_be32(priv->reg_aesu + TALITOS_EUISR),
			in_be32(priv->reg_aesu + TALITOS_EUISR_LO));
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		break;
	case DESC_HDR_SEL0_CRCU:
		dev_err(dev, "CRCUISR 0x%08x_%08x\n",
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			in_be32(priv->reg_crcu + TALITOS_EUISR),
			in_be32(priv->reg_crcu + TALITOS_EUISR_LO));
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		break;
	case DESC_HDR_SEL0_KEU:
		dev_err(dev, "KEUISR 0x%08x_%08x\n",
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			in_be32(priv->reg_pkeu + TALITOS_EUISR),
			in_be32(priv->reg_pkeu + TALITOS_EUISR_LO));
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		break;
	}

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	switch (desc_hdr & DESC_HDR_SEL1_MASK) {
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	case DESC_HDR_SEL1_MDEUA:
	case DESC_HDR_SEL1_MDEUB:
		dev_err(dev, "MDEUISR 0x%08x_%08x\n",
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			in_be32(priv->reg_mdeu + TALITOS_EUISR),
			in_be32(priv->reg_mdeu + TALITOS_EUISR_LO));
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		break;
	case DESC_HDR_SEL1_CRCU:
		dev_err(dev, "CRCUISR 0x%08x_%08x\n",
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			in_be32(priv->reg_crcu + TALITOS_EUISR),
			in_be32(priv->reg_crcu + TALITOS_EUISR_LO));
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		break;
	}

	for (i = 0; i < 8; i++)
		dev_err(dev, "DESCBUF 0x%08x_%08x\n",
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			in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
			in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
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}

/*
 * recover from error interrupts
 */
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static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
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{
	struct talitos_private *priv = dev_get_drvdata(dev);
	unsigned int timeout = TALITOS_TIMEOUT;
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	int ch, error, reset_dev = 0;
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	u32 v_lo;
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	bool is_sec1 = has_ftr_sec1(priv);
	int reset_ch = is_sec1 ? 1 : 0; /* only SEC2 supports continuation */
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	for (ch = 0; ch < priv->num_channels; ch++) {
		/* skip channels without errors */
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		if (is_sec1) {
			/* bits 29, 31, 17, 19 */
			if (!(isr & (1 << (29 + (ch & 1) * 2 - (ch & 2) * 6))))
				continue;
		} else {
			if (!(isr & (1 << (ch * 2 + 1))))
				continue;
		}
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		error = -EINVAL;

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		v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
564 565 566 567 568 569 570 571 572 573 574 575 576 577

		if (v_lo & TALITOS_CCPSR_LO_DOF) {
			dev_err(dev, "double fetch fifo overflow error\n");
			error = -EAGAIN;
			reset_ch = 1;
		}
		if (v_lo & TALITOS_CCPSR_LO_SOF) {
			/* h/w dropped descriptor */
			dev_err(dev, "single fetch fifo overflow error\n");
			error = -EAGAIN;
		}
		if (v_lo & TALITOS_CCPSR_LO_MDTE)
			dev_err(dev, "master data transfer error\n");
		if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
578 579
			dev_err(dev, is_sec1 ? "pointeur not complete error\n"
					     : "s/g data length zero error\n");
580
		if (v_lo & TALITOS_CCPSR_LO_FPZ)
581 582
			dev_err(dev, is_sec1 ? "parity error\n"
					     : "fetch pointer zero error\n");
583 584 585
		if (v_lo & TALITOS_CCPSR_LO_IDH)
			dev_err(dev, "illegal descriptor header error\n");
		if (v_lo & TALITOS_CCPSR_LO_IEU)
586 587
			dev_err(dev, is_sec1 ? "static assignment error\n"
					     : "invalid exec unit error\n");
588
		if (v_lo & TALITOS_CCPSR_LO_EU)
589
			report_eu_error(dev, ch, current_desc_hdr(dev, ch));
590 591 592 593 594 595 596 597 598 599
		if (!is_sec1) {
			if (v_lo & TALITOS_CCPSR_LO_GB)
				dev_err(dev, "gather boundary error\n");
			if (v_lo & TALITOS_CCPSR_LO_GRL)
				dev_err(dev, "gather return/length error\n");
			if (v_lo & TALITOS_CCPSR_LO_SB)
				dev_err(dev, "scatter boundary error\n");
			if (v_lo & TALITOS_CCPSR_LO_SRL)
				dev_err(dev, "scatter return/length error\n");
		}
600 601 602 603 604 605

		flush_channel(dev, ch, error, reset_ch);

		if (reset_ch) {
			reset_channel(dev, ch);
		} else {
606
			setbits32(priv->chan[ch].reg + TALITOS_CCCR,
607
				  TALITOS2_CCCR_CONT);
608 609
			setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
			while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
610
			       TALITOS2_CCCR_CONT) && --timeout)
611 612 613 614 615 616 617 618
				cpu_relax();
			if (timeout == 0) {
				dev_err(dev, "failed to restart channel %d\n",
					ch);
				reset_dev = 1;
			}
		}
	}
619 620 621 622 623 624 625 626
	if (reset_dev || (is_sec1 && isr & ~TALITOS1_ISR_4CHERR) ||
	    (!is_sec1 && isr & ~TALITOS2_ISR_4CHERR) || isr_lo) {
		if (is_sec1 && (isr_lo & TALITOS1_ISR_TEA_ERR))
			dev_err(dev, "TEA error: ISR 0x%08x_%08x\n",
				isr, isr_lo);
		else
			dev_err(dev, "done overflow, internal time out, or "
				"rngu error: ISR 0x%08x_%08x\n", isr, isr_lo);
627 628 629 630 631 632 633 634 635 636

		/* purge request queues */
		for (ch = 0; ch < priv->num_channels; ch++)
			flush_channel(dev, ch, -EIO, 1);

		/* reset and reinitialize the device */
		init_device(dev);
	}
}

637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673
#define DEF_TALITOS1_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet)	       \
static irqreturn_t talitos1_interrupt_##name(int irq, void *data)	       \
{									       \
	struct device *dev = data;					       \
	struct talitos_private *priv = dev_get_drvdata(dev);		       \
	u32 isr, isr_lo;						       \
	unsigned long flags;						       \
									       \
	spin_lock_irqsave(&priv->reg_lock, flags);			       \
	isr = in_be32(priv->reg + TALITOS_ISR);				       \
	isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);			       \
	/* Acknowledge interrupt */					       \
	out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
	out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);			       \
									       \
	if (unlikely(isr & ch_err_mask || isr_lo & TALITOS1_IMR_LO_INIT)) {    \
		spin_unlock_irqrestore(&priv->reg_lock, flags);		       \
		talitos_error(dev, isr & ch_err_mask, isr_lo);		       \
	}								       \
	else {								       \
		if (likely(isr & ch_done_mask)) {			       \
			/* mask further done interrupts. */		       \
			setbits32(priv->reg + TALITOS_IMR, ch_done_mask);      \
			/* done_task will unmask done interrupts at exit */    \
			tasklet_schedule(&priv->done_task[tlet]);	       \
		}							       \
		spin_unlock_irqrestore(&priv->reg_lock, flags);		       \
	}								       \
									       \
	return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED :  \
								IRQ_NONE;      \
}

DEF_TALITOS1_INTERRUPT(4ch, TALITOS1_ISR_4CHDONE, TALITOS1_ISR_4CHERR, 0)

#define DEF_TALITOS2_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet)	       \
static irqreturn_t talitos2_interrupt_##name(int irq, void *data)	       \
674 675 676 677
{									       \
	struct device *dev = data;					       \
	struct talitos_private *priv = dev_get_drvdata(dev);		       \
	u32 isr, isr_lo;						       \
678
	unsigned long flags;						       \
679
									       \
680
	spin_lock_irqsave(&priv->reg_lock, flags);			       \
681 682 683 684 685 686
	isr = in_be32(priv->reg + TALITOS_ISR);				       \
	isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);			       \
	/* Acknowledge interrupt */					       \
	out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
	out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);			       \
									       \
687 688 689 690 691
	if (unlikely(isr & ch_err_mask || isr_lo)) {			       \
		spin_unlock_irqrestore(&priv->reg_lock, flags);		       \
		talitos_error(dev, isr & ch_err_mask, isr_lo);		       \
	}								       \
	else {								       \
692 693 694 695 696 697
		if (likely(isr & ch_done_mask)) {			       \
			/* mask further done interrupts. */		       \
			clrbits32(priv->reg + TALITOS_IMR, ch_done_mask);      \
			/* done_task will unmask done interrupts at exit */    \
			tasklet_schedule(&priv->done_task[tlet]);	       \
		}							       \
698 699
		spin_unlock_irqrestore(&priv->reg_lock, flags);		       \
	}								       \
700 701 702
									       \
	return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED :  \
								IRQ_NONE;      \
703
}
704 705 706 707 708 709

DEF_TALITOS2_INTERRUPT(4ch, TALITOS2_ISR_4CHDONE, TALITOS2_ISR_4CHERR, 0)
DEF_TALITOS2_INTERRUPT(ch0_2, TALITOS2_ISR_CH_0_2_DONE, TALITOS2_ISR_CH_0_2_ERR,
		       0)
DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
		       1)
710 711 712 713 714 715 716 717 718 719 720 721

/*
 * hwrng
 */
static int talitos_rng_data_present(struct hwrng *rng, int wait)
{
	struct device *dev = (struct device *)rng->priv;
	struct talitos_private *priv = dev_get_drvdata(dev);
	u32 ofl;
	int i;

	for (i = 0; i < 20; i++) {
722
		ofl = in_be32(priv->reg_rngu + TALITOS_EUSR_LO) &
723 724 725 726 727 728 729 730 731 732 733 734 735 736 737
		      TALITOS_RNGUSR_LO_OFL;
		if (ofl || !wait)
			break;
		udelay(10);
	}

	return !!ofl;
}

static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
{
	struct device *dev = (struct device *)rng->priv;
	struct talitos_private *priv = dev_get_drvdata(dev);

	/* rng fifo requires 64-bit accesses */
738 739
	*data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO);
	*data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO_LO);
740 741 742 743 744 745 746 747 748 749

	return sizeof(u32);
}

static int talitos_rng_init(struct hwrng *rng)
{
	struct device *dev = (struct device *)rng->priv;
	struct talitos_private *priv = dev_get_drvdata(dev);
	unsigned int timeout = TALITOS_TIMEOUT;

750 751 752
	setbits32(priv->reg_rngu + TALITOS_EURCR_LO, TALITOS_RNGURCR_LO_SR);
	while (!(in_be32(priv->reg_rngu + TALITOS_EUSR_LO)
		 & TALITOS_RNGUSR_LO_RD)
753 754 755 756 757 758 759 760
	       && --timeout)
		cpu_relax();
	if (timeout == 0) {
		dev_err(dev, "failed to reset rng hw\n");
		return -ENODEV;
	}

	/* start generating */
761
	setbits32(priv->reg_rngu + TALITOS_EUDSR_LO, 0);
762 763 764 765 766 767 768

	return 0;
}

static int talitos_register_rng(struct device *dev)
{
	struct talitos_private *priv = dev_get_drvdata(dev);
769
	int err;
770 771 772 773 774 775 776

	priv->rng.name		= dev_driver_string(dev),
	priv->rng.init		= talitos_rng_init,
	priv->rng.data_present	= talitos_rng_data_present,
	priv->rng.data_read	= talitos_rng_data_read,
	priv->rng.priv		= (unsigned long)dev;

777 778 779 780 781
	err = hwrng_register(&priv->rng);
	if (!err)
		priv->rng_registered = true;

	return err;
782 783 784 785 786 787
}

static void talitos_unregister_rng(struct device *dev)
{
	struct talitos_private *priv = dev_get_drvdata(dev);

788 789 790
	if (!priv->rng_registered)
		return;

791
	hwrng_unregister(&priv->rng);
792
	priv->rng_registered = false;
793 794 795 796 797 798
}

/*
 * crypto alg
 */
#define TALITOS_CRA_PRIORITY		3000
799
#define TALITOS_MAX_KEY_SIZE		96
800
#define TALITOS_MAX_IV_LENGTH		16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
801

802 803
struct talitos_ctx {
	struct device *dev;
804
	int ch;
805 806
	__be32 desc_hdr_template;
	u8 key[TALITOS_MAX_KEY_SIZE];
807
	u8 iv[TALITOS_MAX_IV_LENGTH];
808 809 810 811 812
	unsigned int keylen;
	unsigned int enckeylen;
	unsigned int authkeylen;
};

813 814 815 816
#define HASH_MAX_BLOCK_SIZE		SHA512_BLOCK_SIZE
#define TALITOS_MDEU_MAX_CONTEXT_SIZE	TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512

struct talitos_ahash_req_ctx {
817
	u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
818 819 820
	unsigned int hw_context_size;
	u8 buf[HASH_MAX_BLOCK_SIZE];
	u8 bufnext[HASH_MAX_BLOCK_SIZE];
821
	unsigned int swinit;
822 823 824
	unsigned int first;
	unsigned int last;
	unsigned int to_hash_later;
825
	unsigned int nbuf;
826 827 828 829
	struct scatterlist bufsl[2];
	struct scatterlist *psrc;
};

830 831 832 833 834 835 836 837 838 839
struct talitos_export_state {
	u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
	u8 buf[HASH_MAX_BLOCK_SIZE];
	unsigned int swinit;
	unsigned int first;
	unsigned int last;
	unsigned int to_hash_later;
	unsigned int nbuf;
};

840 841
static int aead_setkey(struct crypto_aead *authenc,
		       const u8 *key, unsigned int keylen)
842 843
{
	struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
844
	struct crypto_authenc_keys keys;
845

846
	if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
847 848
		goto badkey;

849
	if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
850 851
		goto badkey;

852 853
	memcpy(ctx->key, keys.authkey, keys.authkeylen);
	memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
854

855 856 857
	ctx->keylen = keys.authkeylen + keys.enckeylen;
	ctx->enckeylen = keys.enckeylen;
	ctx->authkeylen = keys.authkeylen;
858 859 860 861 862 863 864 865 866

	return 0;

badkey:
	crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
	return -EINVAL;
}

/*
867
 * talitos_edesc - s/w-extended descriptor
868 869
 * @src_nents: number of segments in input scatterlist
 * @dst_nents: number of segments in output scatterlist
870
 * @icv_ool: whether ICV is out-of-line
871
 * @iv_dma: dma address of iv for checking continuity and link table
872
 * @dma_len: length of dma mapped link_tbl space
873
 * @dma_link_tbl: bus physical address of link_tbl/buf
874
 * @desc: h/w descriptor
875 876
 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1) (SEC2)
 * @buf: input and output buffeur (if {src,dst}_nents > 1) (SEC1)
877 878 879 880 881
 *
 * if decrypting (with authcheck), or either one of src_nents or dst_nents
 * is greater than 1, an integrity check value is concatenated to the end
 * of link_tbl data
 */
882
struct talitos_edesc {
883 884
	int src_nents;
	int dst_nents;
885
	bool icv_ool;
886
	dma_addr_t iv_dma;
887 888 889
	int dma_len;
	dma_addr_t dma_link_tbl;
	struct talitos_desc desc;
890 891 892 893
	union {
		struct talitos_ptr link_tbl[0];
		u8 buf[0];
	};
894 895
};

896 897 898 899 900 901 902 903 904
static void talitos_sg_unmap(struct device *dev,
			     struct talitos_edesc *edesc,
			     struct scatterlist *src,
			     struct scatterlist *dst)
{
	unsigned int src_nents = edesc->src_nents ? : 1;
	unsigned int dst_nents = edesc->dst_nents ? : 1;

	if (src != dst) {
905
		dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
906

907
		if (dst) {
908
			dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
909
		}
910
	} else
911
		dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
912 913
}

914
static void ipsec_esp_unmap(struct device *dev,
915
			    struct talitos_edesc *edesc,
916 917 918 919 920 921 922
			    struct aead_request *areq)
{
	unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
	unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
	unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
	unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);

923
	talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
924 925 926 927 928 929 930 931 932 933 934 935 936 937 938

	if (edesc->dma_len)
		dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
				 DMA_BIDIRECTIONAL);
}

/*
 * ipsec_esp descriptor callbacks
 */
static void ipsec_esp_encrypt_done(struct device *dev,
				   struct talitos_desc *desc, void *context,
				   int err)
{
	struct aead_request *areq = context;
	struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
939
	unsigned int authsize = crypto_aead_authsize(authenc);
940
	struct talitos_edesc *edesc;
941 942 943
	struct scatterlist *sg;
	void *icvdata;

944 945
	edesc = container_of(desc, struct talitos_edesc, desc);

946 947 948
	ipsec_esp_unmap(dev, edesc, areq);

	/* copy the generated ICV to dst */
949
	if (edesc->icv_ool) {
950
		icvdata = &edesc->link_tbl[edesc->src_nents +
951
					   edesc->dst_nents + 2];
952
		sg = sg_last(areq->dst, edesc->dst_nents);
953 954
		memcpy((char *)sg_virt(sg) + sg->length - authsize,
		       icvdata, authsize);
955 956 957 958 959 960 961
	}

	kfree(edesc);

	aead_request_complete(areq, err);
}

962
static void ipsec_esp_decrypt_swauth_done(struct device *dev,
963 964
					  struct talitos_desc *desc,
					  void *context, int err)
965 966 967
{
	struct aead_request *req = context;
	struct crypto_aead *authenc = crypto_aead_reqtfm(req);
968
	unsigned int authsize = crypto_aead_authsize(authenc);
969
	struct talitos_edesc *edesc;
970
	struct scatterlist *sg;
971
	char *oicv, *icv;
972

973 974
	edesc = container_of(desc, struct talitos_edesc, desc);

975 976 977 978 979
	ipsec_esp_unmap(dev, edesc, req);

	if (!err) {
		/* auth check */
		sg = sg_last(req->dst, edesc->dst_nents ? : 1);
980 981 982 983 984 985 986 987 988 989
		icv = (char *)sg_virt(sg) + sg->length - authsize;

		if (edesc->dma_len) {
			oicv = (char *)&edesc->link_tbl[edesc->src_nents +
							edesc->dst_nents + 2];
			if (edesc->icv_ool)
				icv = oicv + authsize;
		} else
			oicv = (char *)&edesc->link_tbl[0];

990
		err = crypto_memneq(oicv, icv, authsize) ? -EBADMSG : 0;
991 992 993 994 995 996 997
	}

	kfree(edesc);

	aead_request_complete(req, err);
}

998
static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
999 1000
					  struct talitos_desc *desc,
					  void *context, int err)
1001 1002
{
	struct aead_request *req = context;
1003 1004 1005
	struct talitos_edesc *edesc;

	edesc = container_of(desc, struct talitos_edesc, desc);
1006 1007 1008 1009

	ipsec_esp_unmap(dev, edesc, req);

	/* check ICV auth status */
1010 1011 1012
	if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
		     DESC_HDR_LO_ICCR1_PASS))
		err = -EBADMSG;
1013 1014 1015 1016 1017 1018

	kfree(edesc);

	aead_request_complete(req, err);
}

1019 1020 1021 1022
/*
 * convert scatterlist to SEC h/w link table format
 * stop at cryptlen bytes
 */
1023 1024 1025
static int sg_to_link_tbl_offset(struct scatterlist *sg, int sg_count,
				 unsigned int offset, int cryptlen,
				 struct talitos_ptr *link_tbl_ptr)
1026
{
1027
	int n_sg = sg_count;
1028
	int count = 0;
1029

1030 1031
	while (cryptlen && sg && n_sg--) {
		unsigned int len = sg_dma_len(sg);
1032

1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052
		if (offset >= len) {
			offset -= len;
			goto next;
		}

		len -= offset;

		if (len > cryptlen)
			len = cryptlen;

		to_talitos_ptr(link_tbl_ptr + count,
			       sg_dma_address(sg) + offset, 0);
		link_tbl_ptr[count].len = cpu_to_be16(len);
		link_tbl_ptr[count].j_extent = 0;
		count++;
		cryptlen -= len;
		offset = 0;

next:
		sg = sg_next(sg);
1053
	}
1054 1055

	/* tag end of link table */
1056 1057
	if (count > 0)
		link_tbl_ptr[count - 1].j_extent = DESC_PTR_LNKTBL_RETURN;
1058

1059 1060 1061 1062 1063 1064 1065 1066 1067
	return count;
}

static inline int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
				 int cryptlen,
				 struct talitos_ptr *link_tbl_ptr)
{
	return sg_to_link_tbl_offset(sg, sg_count, 0, cryptlen,
				     link_tbl_ptr);
1068 1069 1070 1071 1072
}

/*
 * fill in and submit ipsec_esp descriptor
 */
1073
static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
1074 1075 1076
		     void (*callback)(struct device *dev,
				      struct talitos_desc *desc,
				      void *context, int error))
1077 1078
{
	struct crypto_aead *aead = crypto_aead_reqtfm(areq);
1079
	unsigned int authsize = crypto_aead_authsize(aead);
1080 1081 1082 1083
	struct talitos_ctx *ctx = crypto_aead_ctx(aead);
	struct device *dev = ctx->dev;
	struct talitos_desc *desc = &edesc->desc;
	unsigned int cryptlen = areq->cryptlen;
1084
	unsigned int ivsize = crypto_aead_ivsize(aead);
1085
	int tbl_off = 0;
1086
	int sg_count, ret;
1087
	int sg_link_tbl_len;
1088 1089 1090

	/* hmac key */
	map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
1091
			       DMA_TO_DEVICE);
1092

1093 1094 1095
	sg_count = dma_map_sg(dev, areq->src, edesc->src_nents ?: 1,
			      (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
							   : DMA_TO_DEVICE);
1096

1097
	/* hmac data */
1098 1099 1100 1101 1102 1103
	desc->ptr[1].len = cpu_to_be16(areq->assoclen);
	if (sg_count > 1 &&
	    (ret = sg_to_link_tbl_offset(areq->src, sg_count, 0,
					 areq->assoclen,
					 &edesc->link_tbl[tbl_off])) > 1) {
		tbl_off += ret;
1104 1105

		to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
1106
			       sizeof(struct talitos_ptr), 0);
1107 1108 1109 1110 1111
		desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;

		dma_sync_single_for_device(dev, edesc->dma_link_tbl,
					   edesc->dma_len, DMA_BIDIRECTIONAL);
	} else {
1112
		to_talitos_ptr(&desc->ptr[1], sg_dma_address(areq->src), 0);
1113 1114 1115
		desc->ptr[1].j_extent = 0;
	}

1116
	/* cipher iv */
1117
	to_talitos_ptr(&desc->ptr[2], edesc->iv_dma, 0);
1118 1119
	desc->ptr[2].len = cpu_to_be16(ivsize);
	desc->ptr[2].j_extent = 0;
1120 1121 1122

	/* cipher key */
	map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
1123
			       (char *)&ctx->key + ctx->authkeylen,
1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134
			       DMA_TO_DEVICE);

	/*
	 * cipher in
	 * map and adjust cipher len to aead request cryptlen.
	 * extent is bytes of HMAC postpended to ciphertext,
	 * typically 12 for ipsec
	 */
	desc->ptr[4].len = cpu_to_be16(cryptlen);
	desc->ptr[4].j_extent = authsize;

1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151
	sg_link_tbl_len = cryptlen;
	if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
		sg_link_tbl_len += authsize;

	if (sg_count > 1 &&
	    (ret = sg_to_link_tbl_offset(areq->src, sg_count, areq->assoclen,
					 sg_link_tbl_len,
					 &edesc->link_tbl[tbl_off])) > 1) {
		tbl_off += ret;
		desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
		to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
					      tbl_off *
					      sizeof(struct talitos_ptr), 0);
		dma_sync_single_for_device(dev, edesc->dma_link_tbl,
					   edesc->dma_len,
					   DMA_BIDIRECTIONAL);
	} else
1152
		to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src), 0);
1153 1154 1155 1156 1157

	/* cipher out */
	desc->ptr[5].len = cpu_to_be16(cryptlen);
	desc->ptr[5].j_extent = authsize;

1158
	if (areq->src != areq->dst)
1159 1160
		sg_count = dma_map_sg(dev, areq->dst, edesc->dst_nents ? : 1,
				      DMA_FROM_DEVICE);
1161

1162 1163 1164 1165 1166 1167 1168
	edesc->icv_ool = false;

	if (sg_count > 1 &&
	    (sg_count = sg_to_link_tbl_offset(areq->dst, sg_count,
					      areq->assoclen, cryptlen,
					      &edesc->link_tbl[tbl_off])) >
	    1) {
1169
		struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
1170

1171
		to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1172
			       tbl_off * sizeof(struct talitos_ptr), 0);
1173

1174
		/* Add an entry to the link table for ICV data */
1175 1176 1177 1178 1179
		tbl_ptr += sg_count - 1;
		tbl_ptr->j_extent = 0;
		tbl_ptr++;
		tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
		tbl_ptr->len = cpu_to_be16(authsize);
1180 1181

		/* icv data follows link tables */
1182
		to_talitos_ptr(tbl_ptr, edesc->dma_link_tbl +
1183 1184 1185
					(edesc->src_nents + edesc->dst_nents +
					 2) * sizeof(struct talitos_ptr) +
					authsize, 0);
1186 1187 1188
		desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
		dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
					   edesc->dma_len, DMA_BIDIRECTIONAL);
1189 1190 1191 1192

		edesc->icv_ool = true;
	} else
		to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst), 0);
1193 1194

	/* iv out */
1195
	map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv,
1196 1197
			       DMA_FROM_DEVICE);

1198
	ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1199 1200 1201 1202 1203
	if (ret != -EINPROGRESS) {
		ipsec_esp_unmap(dev, edesc, areq);
		kfree(edesc);
	}
	return ret;
1204 1205 1206
}

/*
1207
 * allocate and map the extended descriptor
1208
 */
1209 1210 1211
static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
						 struct scatterlist *src,
						 struct scatterlist *dst,
1212 1213
						 u8 *iv,
						 unsigned int assoclen,
1214 1215
						 unsigned int cryptlen,
						 unsigned int authsize,
1216
						 unsigned int ivsize,
1217
						 int icv_stashing,
1218 1219
						 u32 cryptoflags,
						 bool encrypt)
1220
{
1221
	struct talitos_edesc *edesc;
1222
	int src_nents, dst_nents, alloc_len, dma_len;
1223
	dma_addr_t iv_dma = 0;
1224
	gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1225
		      GFP_ATOMIC;
1226 1227 1228
	struct talitos_private *priv = dev_get_drvdata(dev);
	bool is_sec1 = has_ftr_sec1(priv);
	int max_len = is_sec1 ? TALITOS1_MAX_DATA_LEN : TALITOS2_MAX_DATA_LEN;
1229
	void *err;
1230

1231
	if (cryptlen + authsize > max_len) {
1232
		dev_err(dev, "length exceeds h/w max limit\n");
1233 1234 1235
		return ERR_PTR(-EINVAL);
	}

1236
	if (ivsize)
1237 1238
		iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);

1239
	if (!dst || dst == src) {
1240 1241
		src_nents = sg_nents_for_len(src,
					     assoclen + cryptlen + authsize);
1242 1243 1244 1245 1246
		if (src_nents < 0) {
			dev_err(dev, "Invalid number of src SG.\n");
			err = ERR_PTR(-EINVAL);
			goto error_sg;
		}
1247 1248 1249
		src_nents = (src_nents == 1) ? 0 : src_nents;
		dst_nents = dst ? src_nents : 0;
	} else { /* dst && dst != src*/
1250 1251
		src_nents = sg_nents_for_len(src, assoclen + cryptlen +
						 (encrypt ? 0 : authsize));
1252 1253 1254 1255 1256
		if (src_nents < 0) {
			dev_err(dev, "Invalid number of src SG.\n");
			err = ERR_PTR(-EINVAL);
			goto error_sg;
		}
1257
		src_nents = (src_nents == 1) ? 0 : src_nents;
1258 1259
		dst_nents = sg_nents_for_len(dst, assoclen + cryptlen +
						 (encrypt ? authsize : 0));
1260 1261 1262 1263 1264
		if (dst_nents < 0) {
			dev_err(dev, "Invalid number of dst SG.\n");
			err = ERR_PTR(-EINVAL);
			goto error_sg;
		}
1265
		dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1266 1267 1268 1269
	}

	/*
	 * allocate space for base edesc plus the link tables,
1270 1271
	 * allowing for two separate entries for AD and generated ICV (+ 2),
	 * and space for two sets of ICVs (stashed and generated)
1272
	 */
1273
	alloc_len = sizeof(struct talitos_edesc);
1274
	if (src_nents || dst_nents) {
1275
		if (is_sec1)
1276 1277
			dma_len = (src_nents ? cryptlen : 0) +
				  (dst_nents ? cryptlen : 0);
1278
		else
1279 1280
			dma_len = (src_nents + dst_nents + 2) *
				  sizeof(struct talitos_ptr) + authsize * 2;
1281 1282 1283
		alloc_len += dma_len;
	} else {
		dma_len = 0;
1284
		alloc_len += icv_stashing ? authsize : 0;
1285 1286
	}

1287
	edesc = kmalloc(alloc_len, GFP_DMA | flags);
1288
	if (!edesc) {
1289
		dev_err(dev, "could not allocate edescriptor\n");
1290 1291
		err = ERR_PTR(-ENOMEM);
		goto error_sg;
1292 1293 1294 1295
	}

	edesc->src_nents = src_nents;
	edesc->dst_nents = dst_nents;
1296
	edesc->iv_dma = iv_dma;
1297
	edesc->dma_len = dma_len;
1298 1299 1300 1301
	if (dma_len)
		edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
						     edesc->dma_len,
						     DMA_BIDIRECTIONAL);
1302 1303

	return edesc;
1304 1305 1306 1307
error_sg:
	if (iv_dma)
		dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
	return err;
1308 1309
}

1310
static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
1311
					      int icv_stashing, bool encrypt)
1312 1313
{
	struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1314
	unsigned int authsize = crypto_aead_authsize(authenc);
1315
	struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1316
	unsigned int ivsize = crypto_aead_ivsize(authenc);
1317

1318
	return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
1319
				   iv, areq->assoclen, areq->cryptlen,
1320
				   authsize, ivsize, icv_stashing,
1321
				   areq->base.flags, encrypt);
1322 1323
}

1324
static int aead_encrypt(struct aead_request *req)
1325 1326 1327
{
	struct crypto_aead *authenc = crypto_aead_reqtfm(req);
	struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1328
	struct talitos_edesc *edesc;
1329 1330

	/* allocate extended descriptor */
1331
	edesc = aead_edesc_alloc(req, req->iv, 0, true);
1332 1333 1334 1335
	if (IS_ERR(edesc))
		return PTR_ERR(edesc);

	/* set encrypt */
1336
	edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1337

1338
	return ipsec_esp(edesc, req, ipsec_esp_encrypt_done);
1339 1340
}

1341
static int aead_decrypt(struct aead_request *req)
1342 1343
{
	struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1344
	unsigned int authsize = crypto_aead_authsize(authenc);
1345
	struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1346
	struct talitos_private *priv = dev_get_drvdata(ctx->dev);
1347
	struct talitos_edesc *edesc;
1348 1349 1350 1351 1352 1353
	struct scatterlist *sg;
	void *icvdata;

	req->cryptlen -= authsize;

	/* allocate extended descriptor */
1354
	edesc = aead_edesc_alloc(req, req->iv, 1, false);
1355 1356 1357
	if (IS_ERR(edesc))
		return PTR_ERR(edesc);

1358
	if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
1359 1360
	    ((!edesc->src_nents && !edesc->dst_nents) ||
	     priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
1361

1362
		/* decrypt and check the ICV */
1363 1364
		edesc->desc.hdr = ctx->desc_hdr_template |
				  DESC_HDR_DIR_INBOUND |
1365
				  DESC_HDR_MODE1_MDEU_CICV;
1366

1367 1368
		/* reset integrity check result bits */
		edesc->desc.hdr_lo = 0;
1369

1370
		return ipsec_esp(edesc, req, ipsec_esp_decrypt_hwauth_done);
1371
	}
1372

1373 1374
	/* Have to check the ICV with software */
	edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1375

1376 1377
	/* stash incoming ICV for later cmp with ICV generated by the h/w */
	if (edesc->dma_len)
1378 1379
		icvdata = (char *)&edesc->link_tbl[edesc->src_nents +
						   edesc->dst_nents + 2];
1380 1381
	else
		icvdata = &edesc->link_tbl[0];
1382

1383
	sg = sg_last(req->src, edesc->src_nents ? : 1);
1384

1385
	memcpy(icvdata, (char *)sg_virt(sg) + sg->length - authsize, authsize);
1386

1387
	return ipsec_esp(edesc, req, ipsec_esp_decrypt_swauth_done);
1388 1389
}

1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400
static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
			     const u8 *key, unsigned int keylen)
{
	struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);

	memcpy(&ctx->key, key, keylen);
	ctx->keylen = keylen;

	return 0;
}

1401 1402 1403 1404
static void unmap_sg_talitos_ptr(struct device *dev, struct scatterlist *src,
				 struct scatterlist *dst, unsigned int len,
				 struct talitos_edesc *edesc)
{
1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425
	struct talitos_private *priv = dev_get_drvdata(dev);
	bool is_sec1 = has_ftr_sec1(priv);

	if (is_sec1) {
		if (!edesc->src_nents) {
			dma_unmap_sg(dev, src, 1,
				     dst != src ? DMA_TO_DEVICE
						: DMA_BIDIRECTIONAL);
		}
		if (dst && edesc->dst_nents) {
			dma_sync_single_for_device(dev,
						   edesc->dma_link_tbl + len,
						   len, DMA_FROM_DEVICE);
			sg_copy_from_buffer(dst, edesc->dst_nents ? : 1,
					    edesc->buf + len, len);
		} else if (dst && dst != src) {
			dma_unmap_sg(dev, dst, 1, DMA_FROM_DEVICE);
		}
	} else {
		talitos_sg_unmap(dev, edesc, src, dst);
	}
1426 1427
}

1428 1429 1430 1431 1432
static void common_nonsnoop_unmap(struct device *dev,
				  struct talitos_edesc *edesc,
				  struct ablkcipher_request *areq)
{
	unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1433 1434

	unmap_sg_talitos_ptr(dev, areq->src, areq->dst, areq->nbytes, edesc);
1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447
	unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
	unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);

	if (edesc->dma_len)
		dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
				 DMA_BIDIRECTIONAL);
}

static void ablkcipher_done(struct device *dev,
			    struct talitos_desc *desc, void *context,
			    int err)
{
	struct ablkcipher_request *areq = context;
1448 1449 1450
	struct talitos_edesc *edesc;

	edesc = container_of(desc, struct talitos_edesc, desc);
1451 1452 1453 1454 1455 1456 1457 1458

	common_nonsnoop_unmap(dev, edesc, areq);

	kfree(edesc);

	areq->base.complete(&areq->base, err);
}

1459 1460 1461 1462 1463
int map_sg_in_talitos_ptr(struct device *dev, struct scatterlist *src,
			  unsigned int len, struct talitos_edesc *edesc,
			  enum dma_data_direction dir, struct talitos_ptr *ptr)
{
	int sg_count;
1464 1465
	struct talitos_private *priv = dev_get_drvdata(dev);
	bool is_sec1 = has_ftr_sec1(priv);
1466

1467
	to_talitos_ptr_len(ptr, len, is_sec1);
1468

1469 1470
	if (is_sec1) {
		sg_count = edesc->src_nents ? : 1;
1471

1472 1473 1474
		if (sg_count == 1) {
			dma_map_sg(dev, src, 1, dir);
			to_talitos_ptr(ptr, sg_dma_address(src), is_sec1);
1475
		} else {
1476 1477 1478 1479 1480 1481 1482 1483
			sg_copy_to_buffer(src, sg_count, edesc->buf, len);
			to_talitos_ptr(ptr, edesc->dma_link_tbl, is_sec1);
			dma_sync_single_for_device(dev, edesc->dma_link_tbl,
						   len, DMA_TO_DEVICE);
		}
	} else {
		to_talitos_ptr_extent_clear(ptr, is_sec1);

1484
		sg_count = dma_map_sg(dev, src, edesc->src_nents ? : 1, dir);
1485 1486

		if (sg_count == 1) {
1487
			to_talitos_ptr(ptr, sg_dma_address(src), is_sec1);
1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502
		} else {
			sg_count = sg_to_link_tbl(src, sg_count, len,
						  &edesc->link_tbl[0]);
			if (sg_count > 1) {
				to_talitos_ptr(ptr, edesc->dma_link_tbl, 0);
				ptr->j_extent |= DESC_PTR_LNKTBL_JUMP;
				dma_sync_single_for_device(dev,
							   edesc->dma_link_tbl,
							   edesc->dma_len,
							   DMA_BIDIRECTIONAL);
			} else {
				/* Only one segment now, so no link tbl needed*/
				to_talitos_ptr(ptr, sg_dma_address(src),
					       is_sec1);
			}
1503 1504 1505 1506 1507 1508 1509 1510 1511 1512
		}
	}
	return sg_count;
}

void map_sg_out_talitos_ptr(struct device *dev, struct scatterlist *dst,
			    unsigned int len, struct talitos_edesc *edesc,
			    enum dma_data_direction dir,
			    struct talitos_ptr *ptr, int sg_count)
{
1513 1514 1515
	struct talitos_private *priv = dev_get_drvdata(dev);
	bool is_sec1 = has_ftr_sec1(priv);

1516
	if (dir != DMA_NONE)
1517
		sg_count = dma_map_sg(dev, dst, edesc->dst_nents ? : 1, dir);
1518

1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531
	to_talitos_ptr_len(ptr, len, is_sec1);

	if (is_sec1) {
		if (sg_count == 1) {
			if (dir != DMA_NONE)
				dma_map_sg(dev, dst, 1, dir);
			to_talitos_ptr(ptr, sg_dma_address(dst), is_sec1);
		} else {
			to_talitos_ptr(ptr, edesc->dma_link_tbl + len, is_sec1);
			dma_sync_single_for_device(dev,
						   edesc->dma_link_tbl + len,
						   len, DMA_FROM_DEVICE);
		}
1532
	} else {
1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544
		to_talitos_ptr_extent_clear(ptr, is_sec1);

		if (sg_count == 1) {
			to_talitos_ptr(ptr, sg_dma_address(dst), is_sec1);
		} else {
			struct talitos_ptr *link_tbl_ptr =
				&edesc->link_tbl[edesc->src_nents + 1];

			to_talitos_ptr(ptr, edesc->dma_link_tbl +
					    (edesc->src_nents + 1) *
					     sizeof(struct talitos_ptr), 0);
			ptr->j_extent |= DESC_PTR_LNKTBL_JUMP;
1545
			sg_to_link_tbl(dst, sg_count, len, link_tbl_ptr);
1546 1547 1548 1549
			dma_sync_single_for_device(dev, edesc->dma_link_tbl,
						   edesc->dma_len,
						   DMA_BIDIRECTIONAL);
		}
1550 1551 1552
	}
}

1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563
static int common_nonsnoop(struct talitos_edesc *edesc,
			   struct ablkcipher_request *areq,
			   void (*callback) (struct device *dev,
					     struct talitos_desc *desc,
					     void *context, int error))
{
	struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
	struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
	struct device *dev = ctx->dev;
	struct talitos_desc *desc = &edesc->desc;
	unsigned int cryptlen = areq->nbytes;
1564
	unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1565
	int sg_count, ret;
1566 1567
	struct talitos_private *priv = dev_get_drvdata(dev);
	bool is_sec1 = has_ftr_sec1(priv);
1568 1569

	/* first DWORD empty */
1570
	desc->ptr[0] = zero_entry;
1571 1572

	/* cipher iv */
1573 1574 1575
	to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, is_sec1);
	to_talitos_ptr_len(&desc->ptr[1], ivsize, is_sec1);
	to_talitos_ptr_extent_clear(&desc->ptr[1], is_sec1);
1576 1577 1578

	/* cipher key */
	map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1579
			       (char *)&ctx->key, DMA_TO_DEVICE);
1580 1581 1582 1583

	/*
	 * cipher in
	 */
1584 1585 1586 1587
	sg_count = map_sg_in_talitos_ptr(dev, areq->src, cryptlen, edesc,
					 (areq->src == areq->dst) ?
					  DMA_BIDIRECTIONAL : DMA_TO_DEVICE,
					  &desc->ptr[3]);
1588 1589

	/* cipher out */
1590 1591 1592 1593
	map_sg_out_talitos_ptr(dev, areq->dst, cryptlen, edesc,
			       (areq->src == areq->dst) ? DMA_NONE
							: DMA_FROM_DEVICE,
			       &desc->ptr[4], sg_count);
1594 1595

	/* iv out */
1596
	map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv,
1597 1598 1599
			       DMA_FROM_DEVICE);

	/* last DWORD empty */
1600
	desc->ptr[6] = zero_entry;
1601

1602
	ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1603 1604 1605 1606 1607 1608 1609
	if (ret != -EINPROGRESS) {
		common_nonsnoop_unmap(dev, edesc, areq);
		kfree(edesc);
	}
	return ret;
}

1610
static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1611
						    areq, bool encrypt)
1612 1613 1614
{
	struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
	struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1615
	unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1616

1617
	return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
1618
				   areq->info, 0, areq->nbytes, 0, ivsize, 0,
1619
				   areq->base.flags, encrypt);
1620 1621 1622 1623 1624 1625 1626 1627 1628
}

static int ablkcipher_encrypt(struct ablkcipher_request *areq)
{
	struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
	struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
	struct talitos_edesc *edesc;

	/* allocate extended descriptor */
1629
	edesc = ablkcipher_edesc_alloc(areq, true);
1630 1631 1632 1633 1634 1635
	if (IS_ERR(edesc))
		return PTR_ERR(edesc);

	/* set encrypt */
	edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;

1636
	return common_nonsnoop(edesc, areq, ablkcipher_done);
1637 1638 1639 1640 1641 1642 1643 1644 1645
}

static int ablkcipher_decrypt(struct ablkcipher_request *areq)
{
	struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
	struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
	struct talitos_edesc *edesc;

	/* allocate extended descriptor */
1646
	edesc = ablkcipher_edesc_alloc(areq, false);
1647 1648 1649 1650 1651
	if (IS_ERR(edesc))
		return PTR_ERR(edesc);

	edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;

1652
	return common_nonsnoop(edesc, areq, ablkcipher_done);
1653 1654
}

1655 1656 1657 1658 1659
static void common_nonsnoop_hash_unmap(struct device *dev,
				       struct talitos_edesc *edesc,
				       struct ahash_request *areq)
{
	struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1660 1661
	struct talitos_private *priv = dev_get_drvdata(dev);
	bool is_sec1 = has_ftr_sec1(priv);
1662 1663 1664

	unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);

1665 1666
	unmap_sg_talitos_ptr(dev, req_ctx->psrc, NULL, 0, edesc);

1667
	/* When using hashctx-in, must unmap it. */
1668
	if (from_talitos_ptr_len(&edesc->desc.ptr[1], is_sec1))
1669 1670 1671
		unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
					 DMA_TO_DEVICE);

1672
	if (from_talitos_ptr_len(&edesc->desc.ptr[2], is_sec1))
1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693
		unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
					 DMA_TO_DEVICE);

	if (edesc->dma_len)
		dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
				 DMA_BIDIRECTIONAL);

}

static void ahash_done(struct device *dev,
		       struct talitos_desc *desc, void *context,
		       int err)
{
	struct ahash_request *areq = context;
	struct talitos_edesc *edesc =
		 container_of(desc, struct talitos_edesc, desc);
	struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);

	if (!req_ctx->last && req_ctx->to_hash_later) {
		/* Position any partial block for next update/final/finup */
		memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
1694
		req_ctx->nbuf = req_ctx->to_hash_later;
1695 1696 1697 1698 1699 1700 1701 1702
	}
	common_nonsnoop_hash_unmap(dev, edesc, areq);

	kfree(edesc);

	areq->base.complete(&areq->base, err);
}

1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723
/*
 * SEC1 doesn't like hashing of 0 sized message, so we do the padding
 * ourself and submit a padded block
 */
void talitos_handle_buggy_hash(struct talitos_ctx *ctx,
			       struct talitos_edesc *edesc,
			       struct talitos_ptr *ptr)
{
	static u8 padded_hash[64] = {
		0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	};

	pr_err_once("Bug in SEC1, padding ourself\n");
	edesc->desc.hdr &= ~DESC_HDR_MODE0_MDEU_PAD;
	map_single_talitos_ptr(ctx->dev, ptr, sizeof(padded_hash),
			       (char *)padded_hash, DMA_TO_DEVICE);
}

1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734
static int common_nonsnoop_hash(struct talitos_edesc *edesc,
				struct ahash_request *areq, unsigned int length,
				void (*callback) (struct device *dev,
						  struct talitos_desc *desc,
						  void *context, int error))
{
	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
	struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
	struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
	struct device *dev = ctx->dev;
	struct talitos_desc *desc = &edesc->desc;
1735
	int ret;
1736 1737
	struct talitos_private *priv = dev_get_drvdata(dev);
	bool is_sec1 = has_ftr_sec1(priv);
1738 1739 1740 1741

	/* first DWORD empty */
	desc->ptr[0] = zero_entry;

1742 1743
	/* hash context in */
	if (!req_ctx->first || req_ctx->swinit) {
1744 1745
		map_single_talitos_ptr(dev, &desc->ptr[1],
				       req_ctx->hw_context_size,
1746
				       (char *)req_ctx->hw_context,
1747
				       DMA_TO_DEVICE);
1748
		req_ctx->swinit = 0;
1749 1750 1751 1752 1753 1754 1755 1756 1757
	} else {
		desc->ptr[1] = zero_entry;
		/* Indicate next op is not the first. */
		req_ctx->first = 0;
	}

	/* HMAC key */
	if (ctx->keylen)
		map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1758
				       (char *)&ctx->key, DMA_TO_DEVICE);
1759 1760 1761 1762 1763 1764
	else
		desc->ptr[2] = zero_entry;

	/*
	 * data in
	 */
1765 1766
	map_sg_in_talitos_ptr(dev, req_ctx->psrc, length, edesc,
			      DMA_TO_DEVICE, &desc->ptr[3]);
1767 1768 1769 1770 1771 1772 1773 1774

	/* fifth DWORD empty */
	desc->ptr[4] = zero_entry;

	/* hash/HMAC out -or- hash context out */
	if (req_ctx->last)
		map_single_talitos_ptr(dev, &desc->ptr[5],
				       crypto_ahash_digestsize(tfm),
1775
				       areq->result, DMA_FROM_DEVICE);
1776 1777 1778
	else
		map_single_talitos_ptr(dev, &desc->ptr[5],
				       req_ctx->hw_context_size,
1779
				       req_ctx->hw_context, DMA_FROM_DEVICE);
1780 1781 1782 1783

	/* last DWORD empty */
	desc->ptr[6] = zero_entry;

1784 1785 1786
	if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) == 0)
		talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]);

1787
	ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801
	if (ret != -EINPROGRESS) {
		common_nonsnoop_hash_unmap(dev, edesc, areq);
		kfree(edesc);
	}
	return ret;
}

static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
					       unsigned int nbytes)
{
	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
	struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
	struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);

1802
	return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, NULL, 0,
1803
				   nbytes, 0, 0, 0, areq->base.flags, false);
1804 1805 1806 1807 1808 1809 1810 1811
}

static int ahash_init(struct ahash_request *areq)
{
	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
	struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);

	/* Initialize the context */
1812
	req_ctx->nbuf = 0;
1813 1814
	req_ctx->first = 1; /* first indicates h/w must init its context */
	req_ctx->swinit = 0; /* assume h/w init of context */
1815 1816 1817 1818 1819 1820 1821 1822
	req_ctx->hw_context_size =
		(crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
			? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
			: TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;

	return 0;
}

1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833
/*
 * on h/w without explicit sha224 support, we initialize h/w context
 * manually with sha224 constants, and tell it to run sha256.
 */
static int ahash_init_sha224_swinit(struct ahash_request *areq)
{
	struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);

	ahash_init(areq);
	req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/

1834 1835 1836 1837 1838 1839 1840 1841
	req_ctx->hw_context[0] = SHA224_H0;
	req_ctx->hw_context[1] = SHA224_H1;
	req_ctx->hw_context[2] = SHA224_H2;
	req_ctx->hw_context[3] = SHA224_H3;
	req_ctx->hw_context[4] = SHA224_H4;
	req_ctx->hw_context[5] = SHA224_H5;
	req_ctx->hw_context[6] = SHA224_H6;
	req_ctx->hw_context[7] = SHA224_H7;
1842 1843 1844 1845 1846 1847 1848 1849

	/* init 64-bit count */
	req_ctx->hw_context[8] = 0;
	req_ctx->hw_context[9] = 0;

	return 0;
}

1850 1851 1852 1853 1854 1855 1856 1857 1858 1859
static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
{
	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
	struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
	struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
	struct talitos_edesc *edesc;
	unsigned int blocksize =
			crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
	unsigned int nbytes_to_hash;
	unsigned int to_hash_later;
1860
	unsigned int nsg;
1861
	int nents;
1862

1863 1864
	if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
		/* Buffer up to one whole block */
1865 1866 1867 1868 1869 1870
		nents = sg_nents_for_len(areq->src, nbytes);
		if (nents < 0) {
			dev_err(ctx->dev, "Invalid number of src SG.\n");
			return nents;
		}
		sg_copy_to_buffer(areq->src, nents,
1871 1872
				  req_ctx->buf + req_ctx->nbuf, nbytes);
		req_ctx->nbuf += nbytes;
1873 1874 1875
		return 0;
	}

1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896
	/* At least (blocksize + 1) bytes are available to hash */
	nbytes_to_hash = nbytes + req_ctx->nbuf;
	to_hash_later = nbytes_to_hash & (blocksize - 1);

	if (req_ctx->last)
		to_hash_later = 0;
	else if (to_hash_later)
		/* There is a partial block. Hash the full block(s) now */
		nbytes_to_hash -= to_hash_later;
	else {
		/* Keep one block buffered */
		nbytes_to_hash -= blocksize;
		to_hash_later = blocksize;
	}

	/* Chain in any previously buffered data */
	if (req_ctx->nbuf) {
		nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
		sg_init_table(req_ctx->bufsl, nsg);
		sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
		if (nsg > 1)
1897
			sg_chain(req_ctx->bufsl, 2, areq->src);
1898
		req_ctx->psrc = req_ctx->bufsl;
1899
	} else
1900
		req_ctx->psrc = areq->src;
1901 1902

	if (to_hash_later) {
1903 1904 1905 1906 1907
		nents = sg_nents_for_len(areq->src, nbytes);
		if (nents < 0) {
			dev_err(ctx->dev, "Invalid number of src SG.\n");
			return nents;
		}
1908
		sg_pcopy_to_buffer(areq->src, nents,
1909 1910 1911
				      req_ctx->bufnext,
				      to_hash_later,
				      nbytes - to_hash_later);
1912
	}
1913
	req_ctx->to_hash_later = to_hash_later;
1914

1915
	/* Allocate extended descriptor */
1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927
	edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
	if (IS_ERR(edesc))
		return PTR_ERR(edesc);

	edesc->desc.hdr = ctx->desc_hdr_template;

	/* On last one, request SEC to pad; otherwise continue */
	if (req_ctx->last)
		edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
	else
		edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;

1928 1929
	/* request SEC to INIT hash. */
	if (req_ctx->first && !req_ctx->swinit)
1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971
		edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;

	/* When the tfm context has a keylen, it's an HMAC.
	 * A first or last (ie. not middle) descriptor must request HMAC.
	 */
	if (ctx->keylen && (req_ctx->first || req_ctx->last))
		edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;

	return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
				    ahash_done);
}

static int ahash_update(struct ahash_request *areq)
{
	struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);

	req_ctx->last = 0;

	return ahash_process_req(areq, areq->nbytes);
}

static int ahash_final(struct ahash_request *areq)
{
	struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);

	req_ctx->last = 1;

	return ahash_process_req(areq, 0);
}

static int ahash_finup(struct ahash_request *areq)
{
	struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);

	req_ctx->last = 1;

	return ahash_process_req(areq, areq->nbytes);
}

static int ahash_digest(struct ahash_request *areq)
{
	struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1972
	struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
1973

1974
	ahash->init(areq);
1975 1976 1977 1978 1979
	req_ctx->last = 1;

	return ahash_process_req(areq, areq->nbytes);
}

1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019
static int ahash_export(struct ahash_request *areq, void *out)
{
	struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
	struct talitos_export_state *export = out;

	memcpy(export->hw_context, req_ctx->hw_context,
	       req_ctx->hw_context_size);
	memcpy(export->buf, req_ctx->buf, req_ctx->nbuf);
	export->swinit = req_ctx->swinit;
	export->first = req_ctx->first;
	export->last = req_ctx->last;
	export->to_hash_later = req_ctx->to_hash_later;
	export->nbuf = req_ctx->nbuf;

	return 0;
}

static int ahash_import(struct ahash_request *areq, const void *in)
{
	struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
	const struct talitos_export_state *export = in;

	memset(req_ctx, 0, sizeof(*req_ctx));
	req_ctx->hw_context_size =
		(crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
			? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
			: TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
	memcpy(req_ctx->hw_context, export->hw_context,
	       req_ctx->hw_context_size);
	memcpy(req_ctx->buf, export->buf, export->nbuf);
	req_ctx->swinit = export->swinit;
	req_ctx->first = export->first;
	req_ctx->last = export->last;
	req_ctx->to_hash_later = export->to_hash_later;
	req_ctx->nbuf = export->nbuf;

	return 0;
}

L
Lee Nipper 已提交
2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110
struct keyhash_result {
	struct completion completion;
	int err;
};

static void keyhash_complete(struct crypto_async_request *req, int err)
{
	struct keyhash_result *res = req->data;

	if (err == -EINPROGRESS)
		return;

	res->err = err;
	complete(&res->completion);
}

static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
		   u8 *hash)
{
	struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));

	struct scatterlist sg[1];
	struct ahash_request *req;
	struct keyhash_result hresult;
	int ret;

	init_completion(&hresult.completion);

	req = ahash_request_alloc(tfm, GFP_KERNEL);
	if (!req)
		return -ENOMEM;

	/* Keep tfm keylen == 0 during hash of the long key */
	ctx->keylen = 0;
	ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
				   keyhash_complete, &hresult);

	sg_init_one(&sg[0], key, keylen);

	ahash_request_set_crypt(req, sg, hash, keylen);
	ret = crypto_ahash_digest(req);
	switch (ret) {
	case 0:
		break;
	case -EINPROGRESS:
	case -EBUSY:
		ret = wait_for_completion_interruptible(
			&hresult.completion);
		if (!ret)
			ret = hresult.err;
		break;
	default:
		break;
	}
	ahash_request_free(req);

	return ret;
}

static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
			unsigned int keylen)
{
	struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
	unsigned int blocksize =
			crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
	unsigned int digestsize = crypto_ahash_digestsize(tfm);
	unsigned int keysize = keylen;
	u8 hash[SHA512_DIGEST_SIZE];
	int ret;

	if (keylen <= blocksize)
		memcpy(ctx->key, key, keysize);
	else {
		/* Must get the hash of the long key */
		ret = keyhash(tfm, key, keylen, hash);

		if (ret) {
			crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
			return -EINVAL;
		}

		keysize = digestsize;
		memcpy(ctx->key, hash, digestsize);
	}

	ctx->keylen = keysize;

	return 0;
}


2111
struct talitos_alg_template {
2112 2113 2114
	u32 type;
	union {
		struct crypto_alg crypto;
2115
		struct ahash_alg hash;
2116
		struct aead_alg aead;
2117
	} alg;
2118 2119 2120 2121
	__be32 desc_hdr_template;
};

static struct talitos_alg_template driver_algs[] = {
2122
	/* AEAD algorithms.  These use a single-pass ipsec_esp descriptor */
2123
	{	.type = CRYPTO_ALG_TYPE_AEAD,
2124 2125 2126 2127 2128 2129 2130 2131 2132 2133
		.alg.aead = {
			.base = {
				.cra_name = "authenc(hmac(sha1),cbc(aes))",
				.cra_driver_name = "authenc-hmac-sha1-"
						   "cbc-aes-talitos",
				.cra_blocksize = AES_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_ASYNC,
			},
			.ivsize = AES_BLOCK_SIZE,
			.maxauthsize = SHA1_DIGEST_SIZE,
2134
		},
2135 2136 2137 2138 2139 2140 2141
		.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
			             DESC_HDR_SEL0_AESU |
		                     DESC_HDR_MODE0_AESU_CBC |
		                     DESC_HDR_SEL1_MDEUA |
		                     DESC_HDR_MODE1_MDEU_INIT |
		                     DESC_HDR_MODE1_MDEU_PAD |
		                     DESC_HDR_MODE1_MDEU_SHA1_HMAC,
2142
	},
2143
	{	.type = CRYPTO_ALG_TYPE_AEAD,
2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154
		.alg.aead = {
			.base = {
				.cra_name = "authenc(hmac(sha1),"
					    "cbc(des3_ede))",
				.cra_driver_name = "authenc-hmac-sha1-"
						   "cbc-3des-talitos",
				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_ASYNC,
			},
			.ivsize = DES3_EDE_BLOCK_SIZE,
			.maxauthsize = SHA1_DIGEST_SIZE,
2155
		},
2156 2157 2158 2159 2160 2161 2162 2163
		.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
			             DESC_HDR_SEL0_DEU |
		                     DESC_HDR_MODE0_DEU_CBC |
		                     DESC_HDR_MODE0_DEU_3DES |
		                     DESC_HDR_SEL1_MDEUA |
		                     DESC_HDR_MODE1_MDEU_INIT |
		                     DESC_HDR_MODE1_MDEU_PAD |
		                     DESC_HDR_MODE1_MDEU_SHA1_HMAC,
2164
	},
2165
	{       .type = CRYPTO_ALG_TYPE_AEAD,
2166 2167 2168 2169 2170 2171 2172 2173 2174 2175
		.alg.aead = {
			.base = {
				.cra_name = "authenc(hmac(sha224),cbc(aes))",
				.cra_driver_name = "authenc-hmac-sha224-"
						   "cbc-aes-talitos",
				.cra_blocksize = AES_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_ASYNC,
			},
			.ivsize = AES_BLOCK_SIZE,
			.maxauthsize = SHA224_DIGEST_SIZE,
2176 2177 2178 2179 2180 2181 2182 2183 2184 2185
		},
		.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
				     DESC_HDR_SEL0_AESU |
				     DESC_HDR_MODE0_AESU_CBC |
				     DESC_HDR_SEL1_MDEUA |
				     DESC_HDR_MODE1_MDEU_INIT |
				     DESC_HDR_MODE1_MDEU_PAD |
				     DESC_HDR_MODE1_MDEU_SHA224_HMAC,
	},
	{	.type = CRYPTO_ALG_TYPE_AEAD,
2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196
		.alg.aead = {
			.base = {
				.cra_name = "authenc(hmac(sha224),"
					    "cbc(des3_ede))",
				.cra_driver_name = "authenc-hmac-sha224-"
						   "cbc-3des-talitos",
				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_ASYNC,
			},
			.ivsize = DES3_EDE_BLOCK_SIZE,
			.maxauthsize = SHA224_DIGEST_SIZE,
2197 2198 2199 2200 2201 2202 2203 2204 2205 2206
		},
		.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
			             DESC_HDR_SEL0_DEU |
		                     DESC_HDR_MODE0_DEU_CBC |
		                     DESC_HDR_MODE0_DEU_3DES |
		                     DESC_HDR_SEL1_MDEUA |
		                     DESC_HDR_MODE1_MDEU_INIT |
		                     DESC_HDR_MODE1_MDEU_PAD |
		                     DESC_HDR_MODE1_MDEU_SHA224_HMAC,
	},
2207
	{	.type = CRYPTO_ALG_TYPE_AEAD,
2208 2209 2210 2211 2212 2213 2214 2215 2216 2217
		.alg.aead = {
			.base = {
				.cra_name = "authenc(hmac(sha256),cbc(aes))",
				.cra_driver_name = "authenc-hmac-sha256-"
						   "cbc-aes-talitos",
				.cra_blocksize = AES_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_ASYNC,
			},
			.ivsize = AES_BLOCK_SIZE,
			.maxauthsize = SHA256_DIGEST_SIZE,
2218
		},
2219 2220 2221 2222 2223 2224 2225 2226
		.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
			             DESC_HDR_SEL0_AESU |
		                     DESC_HDR_MODE0_AESU_CBC |
		                     DESC_HDR_SEL1_MDEUA |
		                     DESC_HDR_MODE1_MDEU_INIT |
		                     DESC_HDR_MODE1_MDEU_PAD |
		                     DESC_HDR_MODE1_MDEU_SHA256_HMAC,
	},
2227
	{	.type = CRYPTO_ALG_TYPE_AEAD,
2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238
		.alg.aead = {
			.base = {
				.cra_name = "authenc(hmac(sha256),"
					    "cbc(des3_ede))",
				.cra_driver_name = "authenc-hmac-sha256-"
						   "cbc-3des-talitos",
				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_ASYNC,
			},
			.ivsize = DES3_EDE_BLOCK_SIZE,
			.maxauthsize = SHA256_DIGEST_SIZE,
2239
		},
2240 2241 2242 2243 2244 2245 2246 2247 2248
		.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
			             DESC_HDR_SEL0_DEU |
		                     DESC_HDR_MODE0_DEU_CBC |
		                     DESC_HDR_MODE0_DEU_3DES |
		                     DESC_HDR_SEL1_MDEUA |
		                     DESC_HDR_MODE1_MDEU_INIT |
		                     DESC_HDR_MODE1_MDEU_PAD |
		                     DESC_HDR_MODE1_MDEU_SHA256_HMAC,
	},
2249
	{	.type = CRYPTO_ALG_TYPE_AEAD,
2250 2251 2252 2253 2254 2255 2256 2257 2258 2259
		.alg.aead = {
			.base = {
				.cra_name = "authenc(hmac(sha384),cbc(aes))",
				.cra_driver_name = "authenc-hmac-sha384-"
						   "cbc-aes-talitos",
				.cra_blocksize = AES_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_ASYNC,
			},
			.ivsize = AES_BLOCK_SIZE,
			.maxauthsize = SHA384_DIGEST_SIZE,
2260 2261 2262 2263 2264 2265 2266 2267 2268 2269
		},
		.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
			             DESC_HDR_SEL0_AESU |
		                     DESC_HDR_MODE0_AESU_CBC |
		                     DESC_HDR_SEL1_MDEUB |
		                     DESC_HDR_MODE1_MDEU_INIT |
		                     DESC_HDR_MODE1_MDEU_PAD |
		                     DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
	},
	{	.type = CRYPTO_ALG_TYPE_AEAD,
2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280
		.alg.aead = {
			.base = {
				.cra_name = "authenc(hmac(sha384),"
					    "cbc(des3_ede))",
				.cra_driver_name = "authenc-hmac-sha384-"
						   "cbc-3des-talitos",
				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_ASYNC,
			},
			.ivsize = DES3_EDE_BLOCK_SIZE,
			.maxauthsize = SHA384_DIGEST_SIZE,
2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291
		},
		.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
			             DESC_HDR_SEL0_DEU |
		                     DESC_HDR_MODE0_DEU_CBC |
		                     DESC_HDR_MODE0_DEU_3DES |
		                     DESC_HDR_SEL1_MDEUB |
		                     DESC_HDR_MODE1_MDEU_INIT |
		                     DESC_HDR_MODE1_MDEU_PAD |
		                     DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
	},
	{	.type = CRYPTO_ALG_TYPE_AEAD,
2292 2293 2294 2295 2296 2297 2298 2299 2300 2301
		.alg.aead = {
			.base = {
				.cra_name = "authenc(hmac(sha512),cbc(aes))",
				.cra_driver_name = "authenc-hmac-sha512-"
						   "cbc-aes-talitos",
				.cra_blocksize = AES_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_ASYNC,
			},
			.ivsize = AES_BLOCK_SIZE,
			.maxauthsize = SHA512_DIGEST_SIZE,
2302 2303 2304 2305 2306 2307 2308 2309 2310 2311
		},
		.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
			             DESC_HDR_SEL0_AESU |
		                     DESC_HDR_MODE0_AESU_CBC |
		                     DESC_HDR_SEL1_MDEUB |
		                     DESC_HDR_MODE1_MDEU_INIT |
		                     DESC_HDR_MODE1_MDEU_PAD |
		                     DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
	},
	{	.type = CRYPTO_ALG_TYPE_AEAD,
2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322
		.alg.aead = {
			.base = {
				.cra_name = "authenc(hmac(sha512),"
					    "cbc(des3_ede))",
				.cra_driver_name = "authenc-hmac-sha512-"
						   "cbc-3des-talitos",
				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_ASYNC,
			},
			.ivsize = DES3_EDE_BLOCK_SIZE,
			.maxauthsize = SHA512_DIGEST_SIZE,
2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333
		},
		.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
			             DESC_HDR_SEL0_DEU |
		                     DESC_HDR_MODE0_DEU_CBC |
		                     DESC_HDR_MODE0_DEU_3DES |
		                     DESC_HDR_SEL1_MDEUB |
		                     DESC_HDR_MODE1_MDEU_INIT |
		                     DESC_HDR_MODE1_MDEU_PAD |
		                     DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
	},
	{	.type = CRYPTO_ALG_TYPE_AEAD,
2334 2335 2336 2337 2338 2339 2340 2341 2342 2343
		.alg.aead = {
			.base = {
				.cra_name = "authenc(hmac(md5),cbc(aes))",
				.cra_driver_name = "authenc-hmac-md5-"
						   "cbc-aes-talitos",
				.cra_blocksize = AES_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_ASYNC,
			},
			.ivsize = AES_BLOCK_SIZE,
			.maxauthsize = MD5_DIGEST_SIZE,
2344
		},
2345 2346 2347 2348 2349 2350 2351 2352
		.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
			             DESC_HDR_SEL0_AESU |
		                     DESC_HDR_MODE0_AESU_CBC |
		                     DESC_HDR_SEL1_MDEUA |
		                     DESC_HDR_MODE1_MDEU_INIT |
		                     DESC_HDR_MODE1_MDEU_PAD |
		                     DESC_HDR_MODE1_MDEU_MD5_HMAC,
	},
2353
	{	.type = CRYPTO_ALG_TYPE_AEAD,
2354 2355 2356 2357 2358 2359 2360 2361 2362 2363
		.alg.aead = {
			.base = {
				.cra_name = "authenc(hmac(md5),cbc(des3_ede))",
				.cra_driver_name = "authenc-hmac-md5-"
						   "cbc-3des-talitos",
				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_ASYNC,
			},
			.ivsize = DES3_EDE_BLOCK_SIZE,
			.maxauthsize = MD5_DIGEST_SIZE,
2364
		},
2365 2366 2367 2368 2369 2370 2371 2372
		.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
			             DESC_HDR_SEL0_DEU |
		                     DESC_HDR_MODE0_DEU_CBC |
		                     DESC_HDR_MODE0_DEU_3DES |
		                     DESC_HDR_SEL1_MDEUA |
		                     DESC_HDR_MODE1_MDEU_INIT |
		                     DESC_HDR_MODE1_MDEU_PAD |
		                     DESC_HDR_MODE1_MDEU_MD5_HMAC,
2373 2374
	},
	/* ABLKCIPHER algorithms. */
2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390
	{	.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
		.alg.crypto = {
			.cra_name = "ecb(aes)",
			.cra_driver_name = "ecb-aes-talitos",
			.cra_blocksize = AES_BLOCK_SIZE,
			.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
				     CRYPTO_ALG_ASYNC,
			.cra_ablkcipher = {
				.min_keysize = AES_MIN_KEY_SIZE,
				.max_keysize = AES_MAX_KEY_SIZE,
				.ivsize = AES_BLOCK_SIZE,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_AESU,
	},
2391 2392
	{	.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
		.alg.crypto = {
2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407
			.cra_name = "cbc(aes)",
			.cra_driver_name = "cbc-aes-talitos",
			.cra_blocksize = AES_BLOCK_SIZE,
			.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
                                     CRYPTO_ALG_ASYNC,
			.cra_ablkcipher = {
				.min_keysize = AES_MIN_KEY_SIZE,
				.max_keysize = AES_MAX_KEY_SIZE,
				.ivsize = AES_BLOCK_SIZE,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_AESU |
				     DESC_HDR_MODE0_AESU_CBC,
	},
2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474
	{	.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
		.alg.crypto = {
			.cra_name = "ctr(aes)",
			.cra_driver_name = "ctr-aes-talitos",
			.cra_blocksize = AES_BLOCK_SIZE,
			.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
				     CRYPTO_ALG_ASYNC,
			.cra_ablkcipher = {
				.min_keysize = AES_MIN_KEY_SIZE,
				.max_keysize = AES_MAX_KEY_SIZE,
				.ivsize = AES_BLOCK_SIZE,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_AESU |
				     DESC_HDR_MODE0_AESU_CTR,
	},
	{	.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
		.alg.crypto = {
			.cra_name = "ecb(des)",
			.cra_driver_name = "ecb-des-talitos",
			.cra_blocksize = DES_BLOCK_SIZE,
			.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
				     CRYPTO_ALG_ASYNC,
			.cra_ablkcipher = {
				.min_keysize = DES_KEY_SIZE,
				.max_keysize = DES_KEY_SIZE,
				.ivsize = DES_BLOCK_SIZE,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_DEU,
	},
	{	.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
		.alg.crypto = {
			.cra_name = "cbc(des)",
			.cra_driver_name = "cbc-des-talitos",
			.cra_blocksize = DES_BLOCK_SIZE,
			.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
				     CRYPTO_ALG_ASYNC,
			.cra_ablkcipher = {
				.min_keysize = DES_KEY_SIZE,
				.max_keysize = DES_KEY_SIZE,
				.ivsize = DES_BLOCK_SIZE,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_DEU |
				     DESC_HDR_MODE0_DEU_CBC,
	},
	{	.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
		.alg.crypto = {
			.cra_name = "ecb(des3_ede)",
			.cra_driver_name = "ecb-3des-talitos",
			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
			.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
				     CRYPTO_ALG_ASYNC,
			.cra_ablkcipher = {
				.min_keysize = DES3_EDE_KEY_SIZE,
				.max_keysize = DES3_EDE_KEY_SIZE,
				.ivsize = DES3_EDE_BLOCK_SIZE,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_DEU |
				     DESC_HDR_MODE0_DEU_3DES,
	},
2475 2476
	{	.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
		.alg.crypto = {
2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491
			.cra_name = "cbc(des3_ede)",
			.cra_driver_name = "cbc-3des-talitos",
			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
			.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
                                     CRYPTO_ALG_ASYNC,
			.cra_ablkcipher = {
				.min_keysize = DES3_EDE_KEY_SIZE,
				.max_keysize = DES3_EDE_KEY_SIZE,
				.ivsize = DES3_EDE_BLOCK_SIZE,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
			             DESC_HDR_SEL0_DEU |
		                     DESC_HDR_MODE0_DEU_CBC |
		                     DESC_HDR_MODE0_DEU_3DES,
2492 2493 2494 2495 2496
	},
	/* AHASH algorithms. */
	{	.type = CRYPTO_ALG_TYPE_AHASH,
		.alg.hash = {
			.halg.digestsize = MD5_DIGEST_SIZE,
2497
			.halg.statesize = sizeof(struct talitos_export_state),
2498 2499 2500
			.halg.base = {
				.cra_name = "md5",
				.cra_driver_name = "md5-talitos",
2501
				.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512
				.cra_flags = CRYPTO_ALG_TYPE_AHASH |
					     CRYPTO_ALG_ASYNC,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_MDEUA |
				     DESC_HDR_MODE0_MDEU_MD5,
	},
	{	.type = CRYPTO_ALG_TYPE_AHASH,
		.alg.hash = {
			.halg.digestsize = SHA1_DIGEST_SIZE,
2513
			.halg.statesize = sizeof(struct talitos_export_state),
2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525
			.halg.base = {
				.cra_name = "sha1",
				.cra_driver_name = "sha1-talitos",
				.cra_blocksize = SHA1_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_TYPE_AHASH |
					     CRYPTO_ALG_ASYNC,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_MDEUA |
				     DESC_HDR_MODE0_MDEU_SHA1,
	},
2526 2527 2528
	{	.type = CRYPTO_ALG_TYPE_AHASH,
		.alg.hash = {
			.halg.digestsize = SHA224_DIGEST_SIZE,
2529
			.halg.statesize = sizeof(struct talitos_export_state),
2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541
			.halg.base = {
				.cra_name = "sha224",
				.cra_driver_name = "sha224-talitos",
				.cra_blocksize = SHA224_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_TYPE_AHASH |
					     CRYPTO_ALG_ASYNC,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_MDEUA |
				     DESC_HDR_MODE0_MDEU_SHA224,
	},
2542 2543 2544
	{	.type = CRYPTO_ALG_TYPE_AHASH,
		.alg.hash = {
			.halg.digestsize = SHA256_DIGEST_SIZE,
2545
			.halg.statesize = sizeof(struct talitos_export_state),
2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560
			.halg.base = {
				.cra_name = "sha256",
				.cra_driver_name = "sha256-talitos",
				.cra_blocksize = SHA256_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_TYPE_AHASH |
					     CRYPTO_ALG_ASYNC,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_MDEUA |
				     DESC_HDR_MODE0_MDEU_SHA256,
	},
	{	.type = CRYPTO_ALG_TYPE_AHASH,
		.alg.hash = {
			.halg.digestsize = SHA384_DIGEST_SIZE,
2561
			.halg.statesize = sizeof(struct talitos_export_state),
2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576
			.halg.base = {
				.cra_name = "sha384",
				.cra_driver_name = "sha384-talitos",
				.cra_blocksize = SHA384_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_TYPE_AHASH |
					     CRYPTO_ALG_ASYNC,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_MDEUB |
				     DESC_HDR_MODE0_MDEUB_SHA384,
	},
	{	.type = CRYPTO_ALG_TYPE_AHASH,
		.alg.hash = {
			.halg.digestsize = SHA512_DIGEST_SIZE,
2577
			.halg.statesize = sizeof(struct talitos_export_state),
2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589
			.halg.base = {
				.cra_name = "sha512",
				.cra_driver_name = "sha512-talitos",
				.cra_blocksize = SHA512_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_TYPE_AHASH |
					     CRYPTO_ALG_ASYNC,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_MDEUB |
				     DESC_HDR_MODE0_MDEUB_SHA512,
	},
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	{	.type = CRYPTO_ALG_TYPE_AHASH,
		.alg.hash = {
			.halg.digestsize = MD5_DIGEST_SIZE,
2593
			.halg.statesize = sizeof(struct talitos_export_state),
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			.halg.base = {
				.cra_name = "hmac(md5)",
				.cra_driver_name = "hmac-md5-talitos",
2597
				.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
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				.cra_flags = CRYPTO_ALG_TYPE_AHASH |
					     CRYPTO_ALG_ASYNC,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_MDEUA |
				     DESC_HDR_MODE0_MDEU_MD5,
	},
	{	.type = CRYPTO_ALG_TYPE_AHASH,
		.alg.hash = {
			.halg.digestsize = SHA1_DIGEST_SIZE,
2609
			.halg.statesize = sizeof(struct talitos_export_state),
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			.halg.base = {
				.cra_name = "hmac(sha1)",
				.cra_driver_name = "hmac-sha1-talitos",
				.cra_blocksize = SHA1_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_TYPE_AHASH |
					     CRYPTO_ALG_ASYNC,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_MDEUA |
				     DESC_HDR_MODE0_MDEU_SHA1,
	},
	{	.type = CRYPTO_ALG_TYPE_AHASH,
		.alg.hash = {
			.halg.digestsize = SHA224_DIGEST_SIZE,
2625
			.halg.statesize = sizeof(struct talitos_export_state),
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			.halg.base = {
				.cra_name = "hmac(sha224)",
				.cra_driver_name = "hmac-sha224-talitos",
				.cra_blocksize = SHA224_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_TYPE_AHASH |
					     CRYPTO_ALG_ASYNC,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_MDEUA |
				     DESC_HDR_MODE0_MDEU_SHA224,
	},
	{	.type = CRYPTO_ALG_TYPE_AHASH,
		.alg.hash = {
			.halg.digestsize = SHA256_DIGEST_SIZE,
2641
			.halg.statesize = sizeof(struct talitos_export_state),
L
Lee Nipper 已提交
2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656
			.halg.base = {
				.cra_name = "hmac(sha256)",
				.cra_driver_name = "hmac-sha256-talitos",
				.cra_blocksize = SHA256_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_TYPE_AHASH |
					     CRYPTO_ALG_ASYNC,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_MDEUA |
				     DESC_HDR_MODE0_MDEU_SHA256,
	},
	{	.type = CRYPTO_ALG_TYPE_AHASH,
		.alg.hash = {
			.halg.digestsize = SHA384_DIGEST_SIZE,
2657
			.halg.statesize = sizeof(struct talitos_export_state),
L
Lee Nipper 已提交
2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672
			.halg.base = {
				.cra_name = "hmac(sha384)",
				.cra_driver_name = "hmac-sha384-talitos",
				.cra_blocksize = SHA384_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_TYPE_AHASH |
					     CRYPTO_ALG_ASYNC,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_MDEUB |
				     DESC_HDR_MODE0_MDEUB_SHA384,
	},
	{	.type = CRYPTO_ALG_TYPE_AHASH,
		.alg.hash = {
			.halg.digestsize = SHA512_DIGEST_SIZE,
2673
			.halg.statesize = sizeof(struct talitos_export_state),
L
Lee Nipper 已提交
2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685
			.halg.base = {
				.cra_name = "hmac(sha512)",
				.cra_driver_name = "hmac-sha512-talitos",
				.cra_blocksize = SHA512_BLOCK_SIZE,
				.cra_flags = CRYPTO_ALG_TYPE_AHASH |
					     CRYPTO_ALG_ASYNC,
			}
		},
		.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
				     DESC_HDR_SEL0_MDEUB |
				     DESC_HDR_MODE0_MDEUB_SHA512,
	}
2686 2687 2688 2689 2690
};

struct talitos_crypto_alg {
	struct list_head entry;
	struct device *dev;
2691
	struct talitos_alg_template algt;
2692 2693 2694 2695 2696
};

static int talitos_cra_init(struct crypto_tfm *tfm)
{
	struct crypto_alg *alg = tfm->__crt_alg;
2697
	struct talitos_crypto_alg *talitos_alg;
2698
	struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2699
	struct talitos_private *priv;
2700

2701 2702 2703 2704 2705 2706 2707
	if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
		talitos_alg = container_of(__crypto_ahash_alg(alg),
					   struct talitos_crypto_alg,
					   algt.alg.hash);
	else
		talitos_alg = container_of(alg, struct talitos_crypto_alg,
					   algt.alg.crypto);
2708

2709 2710
	/* update context with ptr to dev */
	ctx->dev = talitos_alg->dev;
2711

2712 2713 2714 2715 2716
	/* assign SEC channel to tfm in round-robin fashion */
	priv = dev_get_drvdata(ctx->dev);
	ctx->ch = atomic_inc_return(&priv->last_chan) &
		  (priv->num_channels - 1);

2717
	/* copy descriptor header template value */
2718
	ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
2719

2720 2721 2722
	/* select done notification */
	ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;

2723 2724 2725
	return 0;
}

2726
static int talitos_cra_init_aead(struct crypto_aead *tfm)
2727
{
2728
	talitos_cra_init(crypto_aead_tfm(tfm));
2729 2730 2731
	return 0;
}

2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744
static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
{
	struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);

	talitos_cra_init(tfm);

	ctx->keylen = 0;
	crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
				 sizeof(struct talitos_ahash_req_ctx));

	return 0;
}

2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764
/*
 * given the alg's descriptor header template, determine whether descriptor
 * type and primary/secondary execution units required match the hw
 * capabilities description provided in the device tree node.
 */
static int hw_supports(struct device *dev, __be32 desc_hdr_template)
{
	struct talitos_private *priv = dev_get_drvdata(dev);
	int ret;

	ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
	      (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);

	if (SECONDARY_EU(desc_hdr_template))
		ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
		              & priv->exec_units);

	return ret;
}

2765
static int talitos_remove(struct platform_device *ofdev)
2766 2767 2768 2769 2770 2771 2772
{
	struct device *dev = &ofdev->dev;
	struct talitos_private *priv = dev_get_drvdata(dev);
	struct talitos_crypto_alg *t_alg, *n;
	int i;

	list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
2773 2774 2775
		switch (t_alg->algt.type) {
		case CRYPTO_ALG_TYPE_ABLKCIPHER:
			break;
2776 2777
		case CRYPTO_ALG_TYPE_AEAD:
			crypto_unregister_aead(&t_alg->algt.alg.aead);
2778 2779 2780 2781
		case CRYPTO_ALG_TYPE_AHASH:
			crypto_unregister_ahash(&t_alg->algt.alg.hash);
			break;
		}
2782 2783 2784 2785 2786 2787 2788
		list_del(&t_alg->entry);
		kfree(t_alg);
	}

	if (hw_supports(dev, DESC_HDR_SEL0_RNG))
		talitos_unregister_rng(dev);

2789
	for (i = 0; priv->chan && i < priv->num_channels; i++)
2790
		kfree(priv->chan[i].fifo);
2791

2792
	kfree(priv->chan);
2793

2794
	for (i = 0; i < 2; i++)
2795
		if (priv->irq[i]) {
2796 2797 2798
			free_irq(priv->irq[i], dev);
			irq_dispose_mapping(priv->irq[i]);
		}
2799

2800
	tasklet_kill(&priv->done_task[0]);
2801
	if (priv->irq[1])
2802
		tasklet_kill(&priv->done_task[1]);
2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814

	iounmap(priv->reg);

	kfree(priv);

	return 0;
}

static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
						    struct talitos_alg_template
						           *template)
{
2815
	struct talitos_private *priv = dev_get_drvdata(dev);
2816 2817 2818 2819 2820 2821 2822
	struct talitos_crypto_alg *t_alg;
	struct crypto_alg *alg;

	t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
	if (!t_alg)
		return ERR_PTR(-ENOMEM);

2823 2824 2825 2826
	t_alg->algt = *template;

	switch (t_alg->algt.type) {
	case CRYPTO_ALG_TYPE_ABLKCIPHER:
2827 2828
		alg = &t_alg->algt.alg.crypto;
		alg->cra_init = talitos_cra_init;
2829
		alg->cra_type = &crypto_ablkcipher_type;
2830 2831 2832 2833
		alg->cra_ablkcipher.setkey = ablkcipher_setkey;
		alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
		alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
		alg->cra_ablkcipher.geniv = "eseqiv";
2834
		break;
2835
	case CRYPTO_ALG_TYPE_AEAD:
2836 2837 2838 2839 2840
		alg = &t_alg->algt.alg.aead.base;
		t_alg->algt.alg.aead.init = talitos_cra_init_aead;
		t_alg->algt.alg.aead.setkey = aead_setkey;
		t_alg->algt.alg.aead.encrypt = aead_encrypt;
		t_alg->algt.alg.aead.decrypt = aead_decrypt;
2841 2842 2843
		break;
	case CRYPTO_ALG_TYPE_AHASH:
		alg = &t_alg->algt.alg.hash.halg.base;
2844
		alg->cra_init = talitos_cra_init_ahash;
2845
		alg->cra_type = &crypto_ahash_type;
2846 2847 2848 2849 2850 2851
		t_alg->algt.alg.hash.init = ahash_init;
		t_alg->algt.alg.hash.update = ahash_update;
		t_alg->algt.alg.hash.final = ahash_final;
		t_alg->algt.alg.hash.finup = ahash_finup;
		t_alg->algt.alg.hash.digest = ahash_digest;
		t_alg->algt.alg.hash.setkey = ahash_setkey;
2852 2853
		t_alg->algt.alg.hash.import = ahash_import;
		t_alg->algt.alg.hash.export = ahash_export;
2854

L
Lee Nipper 已提交
2855
		if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
K
Kim Phillips 已提交
2856 2857
		    !strncmp(alg->cra_name, "hmac", 4)) {
			kfree(t_alg);
L
Lee Nipper 已提交
2858
			return ERR_PTR(-ENOTSUPP);
K
Kim Phillips 已提交
2859
		}
2860
		if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
L
Lee Nipper 已提交
2861 2862
		    (!strcmp(alg->cra_name, "sha224") ||
		     !strcmp(alg->cra_name, "hmac(sha224)"))) {
2863 2864 2865 2866 2867 2868
			t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
			t_alg->algt.desc_hdr_template =
					DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
					DESC_HDR_SEL0_MDEUA |
					DESC_HDR_MODE0_MDEU_SHA256;
		}
2869
		break;
2870 2871
	default:
		dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2872
		kfree(t_alg);
2873
		return ERR_PTR(-EINVAL);
2874
	}
2875 2876 2877 2878 2879

	alg->cra_module = THIS_MODULE;
	alg->cra_priority = TALITOS_CRA_PRIORITY;
	alg->cra_alignmask = 0;
	alg->cra_ctxsize = sizeof(struct talitos_ctx);
2880
	alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
2881 2882 2883 2884 2885 2886

	t_alg->dev = dev;

	return t_alg;
}

2887 2888 2889 2890 2891 2892
static int talitos_probe_irq(struct platform_device *ofdev)
{
	struct device *dev = &ofdev->dev;
	struct device_node *np = ofdev->dev.of_node;
	struct talitos_private *priv = dev_get_drvdata(dev);
	int err;
2893
	bool is_sec1 = has_ftr_sec1(priv);
2894 2895

	priv->irq[0] = irq_of_parse_and_map(np, 0);
2896
	if (!priv->irq[0]) {
2897 2898 2899
		dev_err(dev, "failed to map irq\n");
		return -EINVAL;
	}
2900 2901 2902 2903 2904
	if (is_sec1) {
		err = request_irq(priv->irq[0], talitos1_interrupt_4ch, 0,
				  dev_driver_string(dev), dev);
		goto primary_out;
	}
2905 2906 2907 2908

	priv->irq[1] = irq_of_parse_and_map(np, 1);

	/* get the primary irq line */
2909
	if (!priv->irq[1]) {
2910
		err = request_irq(priv->irq[0], talitos2_interrupt_4ch, 0,
2911 2912 2913 2914
				  dev_driver_string(dev), dev);
		goto primary_out;
	}

2915
	err = request_irq(priv->irq[0], talitos2_interrupt_ch0_2, 0,
2916 2917 2918 2919 2920
			  dev_driver_string(dev), dev);
	if (err)
		goto primary_out;

	/* get the secondary irq line */
2921
	err = request_irq(priv->irq[1], talitos2_interrupt_ch1_3, 0,
2922 2923 2924 2925
			  dev_driver_string(dev), dev);
	if (err) {
		dev_err(dev, "failed to request secondary irq\n");
		irq_dispose_mapping(priv->irq[1]);
2926
		priv->irq[1] = 0;
2927 2928 2929 2930 2931 2932 2933 2934
	}

	return err;

primary_out:
	if (err) {
		dev_err(dev, "failed to request primary irq\n");
		irq_dispose_mapping(priv->irq[0]);
2935
		priv->irq[0] = 0;
2936 2937 2938 2939 2940
	}

	return err;
}

2941
static int talitos_probe(struct platform_device *ofdev)
2942 2943
{
	struct device *dev = &ofdev->dev;
2944
	struct device_node *np = ofdev->dev.of_node;
2945 2946 2947
	struct talitos_private *priv;
	const unsigned int *prop;
	int i, err;
2948
	int stride;
2949 2950 2951 2952 2953

	priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

2954 2955
	INIT_LIST_HEAD(&priv->alg_list);

2956 2957 2958 2959
	dev_set_drvdata(dev, priv);

	priv->ofdev = ofdev;

2960 2961
	spin_lock_init(&priv->reg_lock);

2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992
	priv->reg = of_iomap(np, 0);
	if (!priv->reg) {
		dev_err(dev, "failed to of_iomap\n");
		err = -ENOMEM;
		goto err_out;
	}

	/* get SEC version capabilities from device tree */
	prop = of_get_property(np, "fsl,num-channels", NULL);
	if (prop)
		priv->num_channels = *prop;

	prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
	if (prop)
		priv->chfifo_len = *prop;

	prop = of_get_property(np, "fsl,exec-units-mask", NULL);
	if (prop)
		priv->exec_units = *prop;

	prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
	if (prop)
		priv->desc_types = *prop;

	if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
	    !priv->exec_units || !priv->desc_types) {
		dev_err(dev, "invalid property data in device tree node\n");
		err = -EINVAL;
		goto err_out;
	}

2993 2994 2995
	if (of_device_is_compatible(np, "fsl,sec3.0"))
		priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;

2996
	if (of_device_is_compatible(np, "fsl,sec2.1"))
2997
		priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
L
Lee Nipper 已提交
2998 2999
				  TALITOS_FTR_SHA224_HWINIT |
				  TALITOS_FTR_HMAC_OK;
3000

3001 3002 3003
	if (of_device_is_compatible(np, "fsl,sec1.0"))
		priv->features |= TALITOS_FTR_SEC1;

3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028
	if (of_device_is_compatible(np, "fsl,sec1.2")) {
		priv->reg_deu = priv->reg + TALITOS12_DEU;
		priv->reg_aesu = priv->reg + TALITOS12_AESU;
		priv->reg_mdeu = priv->reg + TALITOS12_MDEU;
		stride = TALITOS1_CH_STRIDE;
	} else if (of_device_is_compatible(np, "fsl,sec1.0")) {
		priv->reg_deu = priv->reg + TALITOS10_DEU;
		priv->reg_aesu = priv->reg + TALITOS10_AESU;
		priv->reg_mdeu = priv->reg + TALITOS10_MDEU;
		priv->reg_afeu = priv->reg + TALITOS10_AFEU;
		priv->reg_rngu = priv->reg + TALITOS10_RNGU;
		priv->reg_pkeu = priv->reg + TALITOS10_PKEU;
		stride = TALITOS1_CH_STRIDE;
	} else {
		priv->reg_deu = priv->reg + TALITOS2_DEU;
		priv->reg_aesu = priv->reg + TALITOS2_AESU;
		priv->reg_mdeu = priv->reg + TALITOS2_MDEU;
		priv->reg_afeu = priv->reg + TALITOS2_AFEU;
		priv->reg_rngu = priv->reg + TALITOS2_RNGU;
		priv->reg_pkeu = priv->reg + TALITOS2_PKEU;
		priv->reg_keu = priv->reg + TALITOS2_KEU;
		priv->reg_crcu = priv->reg + TALITOS2_CRCU;
		stride = TALITOS2_CH_STRIDE;
	}

3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047
	err = talitos_probe_irq(ofdev);
	if (err)
		goto err_out;

	if (of_device_is_compatible(np, "fsl,sec1.0")) {
		tasklet_init(&priv->done_task[0], talitos1_done_4ch,
			     (unsigned long)dev);
	} else {
		if (!priv->irq[1]) {
			tasklet_init(&priv->done_task[0], talitos2_done_4ch,
				     (unsigned long)dev);
		} else {
			tasklet_init(&priv->done_task[0], talitos2_done_ch0_2,
				     (unsigned long)dev);
			tasklet_init(&priv->done_task[1], talitos2_done_ch1_3,
				     (unsigned long)dev);
		}
	}

3048 3049 3050 3051
	priv->chan = kzalloc(sizeof(struct talitos_channel) *
			     priv->num_channels, GFP_KERNEL);
	if (!priv->chan) {
		dev_err(dev, "failed to allocate channel management space\n");
3052 3053 3054 3055
		err = -ENOMEM;
		goto err_out;
	}

3056 3057
	priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);

3058
	for (i = 0; i < priv->num_channels; i++) {
3059
		priv->chan[i].reg = priv->reg + stride * (i + 1);
3060
		if (!priv->irq[1] || !(i & 1))
3061
			priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
3062

3063 3064
		spin_lock_init(&priv->chan[i].head_lock);
		spin_lock_init(&priv->chan[i].tail_lock);
3065

3066 3067 3068
		priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
					     priv->fifo_len, GFP_KERNEL);
		if (!priv->chan[i].fifo) {
3069 3070 3071 3072 3073
			dev_err(dev, "failed to allocate request fifo %d\n", i);
			err = -ENOMEM;
			goto err_out;
		}

3074 3075
		atomic_set(&priv->chan[i].submit_count,
			   -(priv->chfifo_len - 1));
3076
	}
3077

3078 3079
	dma_set_mask(dev, DMA_BIT_MASK(36));

3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100
	/* reset and initialize the h/w */
	err = init_device(dev);
	if (err) {
		dev_err(dev, "failed to initialize device\n");
		goto err_out;
	}

	/* register the RNG, if available */
	if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
		err = talitos_register_rng(dev);
		if (err) {
			dev_err(dev, "failed to register hwrng: %d\n", err);
			goto err_out;
		} else
			dev_info(dev, "hwrng\n");
	}

	/* register crypto algorithms the device supports */
	for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
		if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
			struct talitos_crypto_alg *t_alg;
3101
			struct crypto_alg *alg = NULL;
3102 3103 3104 3105

			t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
			if (IS_ERR(t_alg)) {
				err = PTR_ERR(t_alg);
K
Kim Phillips 已提交
3106
				if (err == -ENOTSUPP)
L
Lee Nipper 已提交
3107
					continue;
3108 3109 3110
				goto err_out;
			}

3111 3112 3113 3114
			switch (t_alg->algt.type) {
			case CRYPTO_ALG_TYPE_ABLKCIPHER:
				err = crypto_register_alg(
						&t_alg->algt.alg.crypto);
3115
				alg = &t_alg->algt.alg.crypto;
3116
				break;
3117 3118 3119 3120 3121 3122 3123

			case CRYPTO_ALG_TYPE_AEAD:
				err = crypto_register_aead(
					&t_alg->algt.alg.aead);
				alg = &t_alg->algt.alg.aead.base;
				break;

3124 3125 3126
			case CRYPTO_ALG_TYPE_AHASH:
				err = crypto_register_ahash(
						&t_alg->algt.alg.hash);
3127
				alg = &t_alg->algt.alg.hash.halg.base;
3128 3129
				break;
			}
3130 3131
			if (err) {
				dev_err(dev, "%s alg registration failed\n",
3132
					alg->cra_driver_name);
3133
				kfree(t_alg);
3134
			} else
3135 3136 3137
				list_add_tail(&t_alg->entry, &priv->alg_list);
		}
	}
3138 3139 3140
	if (!list_empty(&priv->alg_list))
		dev_info(dev, "%s algorithms registered in /proc/crypto\n",
			 (char *)of_get_property(np, "compatible", NULL));
3141 3142 3143 3144 3145 3146 3147 3148 3149

	return 0;

err_out:
	talitos_remove(ofdev);

	return err;
}

3150
static const struct of_device_id talitos_match[] = {
3151 3152 3153 3154 3155 3156
#ifdef CONFIG_CRYPTO_DEV_TALITOS1
	{
		.compatible = "fsl,sec1.0",
	},
#endif
#ifdef CONFIG_CRYPTO_DEV_TALITOS2
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	{
		.compatible = "fsl,sec2.0",
	},
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#endif
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	{},
};
MODULE_DEVICE_TABLE(of, talitos_match);

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static struct platform_driver talitos_driver = {
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	.driver = {
		.name = "talitos",
		.of_match_table = talitos_match,
	},
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	.probe = talitos_probe,
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	.remove = talitos_remove,
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};

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module_platform_driver(talitos_driver);
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MODULE_LICENSE("GPL");
MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");