init_64.c 77.2 KB
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// SPDX-License-Identifier: GPL-2.0
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/*
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 *  arch/sparc64/mm/init.c
 *
 *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */
 
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#include <linux/extable.h>
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#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/init.h>
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#include <linux/memblock.h>
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#include <linux/mm.h>
#include <linux/hugetlb.h>
#include <linux/initrd.h>
#include <linux/swap.h>
#include <linux/pagemap.h>
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#include <linux/poison.h>
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#include <linux/fs.h>
#include <linux/seq_file.h>
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#include <linux/kprobes.h>
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#include <linux/cache.h>
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#include <linux/sort.h>
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#include <linux/ioport.h>
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#include <linux/percpu.h>
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#include <linux/mmzone.h>
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#include <linux/gfp.h>
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#include <asm/head.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/oplib.h>
#include <asm/iommu.h>
#include <asm/io.h>
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#include <linux/uaccess.h>
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#include <asm/mmu_context.h>
#include <asm/tlbflush.h>
#include <asm/dma.h>
#include <asm/starfire.h>
#include <asm/tlb.h>
#include <asm/spitfire.h>
#include <asm/sections.h>
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#include <asm/tsb.h>
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#include <asm/hypervisor.h>
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#include <asm/prom.h>
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#include <asm/mdesc.h>
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#include <asm/cpudata.h>
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#include <asm/setup.h>
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#include <asm/irq.h>
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#include "init_64.h"
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unsigned long kern_linear_pte_xor[4] __read_mostly;
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static unsigned long page_cache4v_flag;
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/* A bitmap, two bits for every 256MB of physical memory.  These two
 * bits determine what page size we use for kernel linear
 * translations.  They form an index into kern_linear_pte_xor[].  The
 * value in the indexed slot is XOR'd with the TLB miss virtual
 * address to form the resulting TTE.  The mapping is:
 *
 *	0	==>	4MB
 *	1	==>	256MB
 *	2	==>	2GB
 *	3	==>	16GB
 *
 * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
 * support 2GB pages, and hopefully future cpus will support the 16GB
 * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
 * if these larger page sizes are not supported by the cpu.
 *
 * It would be nice to determine this from the machine description
 * 'cpu' properties, but we need to have this table setup before the
 * MDESC is initialized.
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 */

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#ifndef CONFIG_DEBUG_PAGEALLOC
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/* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
 * Space is allocated for this right after the trap table in
 * arch/sparc64/kernel/head.S
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 */
extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
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#endif
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extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
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static unsigned long cpu_pgsz_mask;

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#define MAX_BANKS	1024
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static struct linux_prom64_registers pavail[MAX_BANKS];
static int pavail_ents;
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u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];

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static int cmp_p64(const void *a, const void *b)
{
	const struct linux_prom64_registers *x = a, *y = b;

	if (x->phys_addr > y->phys_addr)
		return 1;
	if (x->phys_addr < y->phys_addr)
		return -1;
	return 0;
}

static void __init read_obp_memory(const char *property,
				   struct linux_prom64_registers *regs,
				   int *num_ents)
{
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	phandle node = prom_finddevice("/memory");
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	int prop_size = prom_getproplen(node, property);
	int ents, ret, i;

	ents = prop_size / sizeof(struct linux_prom64_registers);
	if (ents > MAX_BANKS) {
		prom_printf("The machine has more %s property entries than "
			    "this kernel can support (%d).\n",
			    property, MAX_BANKS);
		prom_halt();
	}

	ret = prom_getproperty(node, property, (char *) regs, prop_size);
	if (ret == -1) {
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		prom_printf("Couldn't get %s property from /memory.\n",
				property);
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		prom_halt();
	}

	/* Sanitize what we got from the firmware, by page aligning
	 * everything.
	 */
	for (i = 0; i < ents; i++) {
		unsigned long base, size;

		base = regs[i].phys_addr;
		size = regs[i].reg_size;
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		size &= PAGE_MASK;
		if (base & ~PAGE_MASK) {
			unsigned long new_base = PAGE_ALIGN(base);

			size -= new_base - base;
			if ((long) size < 0L)
				size = 0UL;
			base = new_base;
		}
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		if (size == 0UL) {
			/* If it is empty, simply get rid of it.
			 * This simplifies the logic of the other
			 * functions that process these arrays.
			 */
			memmove(&regs[i], &regs[i + 1],
				(ents - i - 1) * sizeof(regs[0]));
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			i--;
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			ents--;
			continue;
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		}
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		regs[i].phys_addr = base;
		regs[i].reg_size = size;
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	}

	*num_ents = ents;

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	sort(regs, ents, sizeof(struct linux_prom64_registers),
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	     cmp_p64, NULL);
}
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/* Kernel physical address base and size in bytes.  */
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unsigned long kern_base __read_mostly;
unsigned long kern_size __read_mostly;
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/* Initial ramdisk setup */
extern unsigned long sparc_ramdisk_image64;
extern unsigned int sparc_ramdisk_image;
extern unsigned int sparc_ramdisk_size;

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struct page *mem_map_zero __read_mostly;
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EXPORT_SYMBOL(mem_map_zero);
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unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;

unsigned long sparc64_kern_pri_context __read_mostly;
unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
unsigned long sparc64_kern_sec_context __read_mostly;

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int num_kernel_image_mappings;
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#ifdef CONFIG_DEBUG_DCFLUSH
atomic_t dcpage_flushes = ATOMIC_INIT(0);
#ifdef CONFIG_SMP
atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
#endif
#endif

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inline void flush_dcache_page_impl(struct page *page)
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{
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	BUG_ON(tlb_type == hypervisor);
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#ifdef CONFIG_DEBUG_DCFLUSH
	atomic_inc(&dcpage_flushes);
#endif

#ifdef DCACHE_ALIASING_POSSIBLE
	__flush_dcache_page(page_address(page),
			    ((tlb_type == spitfire) &&
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			     page_mapping_file(page) != NULL));
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#else
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	if (page_mapping_file(page) != NULL &&
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	    tlb_type == spitfire)
		__flush_icache_page(__pa(page_address(page)));
#endif
}

#define PG_dcache_dirty		PG_arch_1
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#define PG_dcache_cpu_shift	32UL
#define PG_dcache_cpu_mask	\
	((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
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#define dcache_dirty_cpu(page) \
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	(((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
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static inline void set_dcache_dirty(struct page *page, int this_cpu)
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{
	unsigned long mask = this_cpu;
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	unsigned long non_cpu_bits;

	non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
	mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);

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	__asm__ __volatile__("1:\n\t"
			     "ldx	[%2], %%g7\n\t"
			     "and	%%g7, %1, %%g1\n\t"
			     "or	%%g1, %0, %%g1\n\t"
			     "casx	[%2], %%g7, %%g1\n\t"
			     "cmp	%%g7, %%g1\n\t"
			     "bne,pn	%%xcc, 1b\n\t"
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			     " nop"
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			     : /* no outputs */
			     : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
			     : "g1", "g7");
}

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static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
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{
	unsigned long mask = (1UL << PG_dcache_dirty);

	__asm__ __volatile__("! test_and_clear_dcache_dirty\n"
			     "1:\n\t"
			     "ldx	[%2], %%g7\n\t"
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			     "srlx	%%g7, %4, %%g1\n\t"
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			     "and	%%g1, %3, %%g1\n\t"
			     "cmp	%%g1, %0\n\t"
			     "bne,pn	%%icc, 2f\n\t"
			     " andn	%%g7, %1, %%g1\n\t"
			     "casx	[%2], %%g7, %%g1\n\t"
			     "cmp	%%g7, %%g1\n\t"
			     "bne,pn	%%xcc, 1b\n\t"
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			     " nop\n"
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			     "2:"
			     : /* no outputs */
			     : "r" (cpu), "r" (mask), "r" (&page->flags),
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			       "i" (PG_dcache_cpu_mask),
			       "i" (PG_dcache_cpu_shift)
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			     : "g1", "g7");
}

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static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
{
	unsigned long tsb_addr = (unsigned long) ent;

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	if (tlb_type == cheetah_plus || tlb_type == hypervisor)
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		tsb_addr = __pa(tsb_addr);

	__tsb_insert(tsb_addr, tag, pte);
}

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unsigned long _PAGE_ALL_SZ_BITS __read_mostly;

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static void flush_dcache(unsigned long pfn)
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{
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	struct page *page;
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	page = pfn_to_page(pfn);
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	if (page) {
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		unsigned long pg_flags;

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		pg_flags = page->flags;
		if (pg_flags & (1UL << PG_dcache_dirty)) {
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			int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
				   PG_dcache_cpu_mask);
			int this_cpu = get_cpu();

			/* This is just to optimize away some function calls
			 * in the SMP case.
			 */
			if (cpu == this_cpu)
				flush_dcache_page_impl(page);
			else
				smp_flush_dcache_page_impl(page, cpu);

			clear_dcache_dirty_cpu(page, cpu);

			put_cpu();
		}
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	}
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}

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/* mm->context.lock must be held */
static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
				    unsigned long tsb_hash_shift, unsigned long address,
				    unsigned long tte)
{
	struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
	unsigned long tag;

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	if (unlikely(!tsb))
		return;

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	tsb += ((address >> tsb_hash_shift) &
		(mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
	tag = (address >> 22UL);
	tsb_insert(tsb, tag, tte);
}

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#ifdef CONFIG_HUGETLB_PAGE
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static void __init add_huge_page_size(unsigned long size)
{
	unsigned int order;

	if (size_to_hstate(size))
		return;

	order = ilog2(size) - PAGE_SHIFT;
	hugetlb_add_hstate(order);
}

static int __init hugetlbpage_init(void)
{
	add_huge_page_size(1UL << HPAGE_64K_SHIFT);
	add_huge_page_size(1UL << HPAGE_SHIFT);
	add_huge_page_size(1UL << HPAGE_256MB_SHIFT);
	add_huge_page_size(1UL << HPAGE_2GB_SHIFT);

	return 0;
}

arch_initcall(hugetlbpage_init);

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static void __init pud_huge_patch(void)
{
	struct pud_huge_patch_entry *p;
	unsigned long addr;

	p = &__pud_huge_patch;
	addr = p->addr;
	*(unsigned int *)addr = p->insn;

	__asm__ __volatile__("flush %0" : : "r" (addr));
}

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bool __init arch_hugetlb_valid_size(unsigned long size)
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{
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	unsigned int hugepage_shift = ilog2(size);
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	unsigned short hv_pgsz_idx;
	unsigned int hv_pgsz_mask;

	switch (hugepage_shift) {
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	case HPAGE_16GB_SHIFT:
		hv_pgsz_mask = HV_PGSZ_MASK_16GB;
		hv_pgsz_idx = HV_PGSZ_IDX_16GB;
		pud_huge_patch();
		break;
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	case HPAGE_2GB_SHIFT:
		hv_pgsz_mask = HV_PGSZ_MASK_2GB;
		hv_pgsz_idx = HV_PGSZ_IDX_2GB;
		break;
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	case HPAGE_256MB_SHIFT:
		hv_pgsz_mask = HV_PGSZ_MASK_256MB;
		hv_pgsz_idx = HV_PGSZ_IDX_256MB;
		break;
	case HPAGE_SHIFT:
		hv_pgsz_mask = HV_PGSZ_MASK_4MB;
		hv_pgsz_idx = HV_PGSZ_IDX_4MB;
		break;
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	case HPAGE_64K_SHIFT:
		hv_pgsz_mask = HV_PGSZ_MASK_64K;
		hv_pgsz_idx = HV_PGSZ_IDX_64K;
		break;
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	default:
		hv_pgsz_mask = 0;
	}

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	if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U)
		return false;

	return true;
}
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#endif	/* CONFIG_HUGETLB_PAGE */

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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
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{
	struct mm_struct *mm;
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	unsigned long flags;
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	bool is_huge_tsb;
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	pte_t pte = *ptep;
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	if (tlb_type != hypervisor) {
		unsigned long pfn = pte_pfn(pte);

		if (pfn_valid(pfn))
			flush_dcache(pfn);
	}
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	mm = vma->vm_mm;
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	/* Don't insert a non-valid PTE into the TSB, we'll deadlock.  */
	if (!pte_accessible(mm, pte))
		return;

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	spin_lock_irqsave(&mm->context.lock, flags);

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	is_huge_tsb = false;
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#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
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	if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
		unsigned long hugepage_size = PAGE_SIZE;

		if (is_vm_hugetlb_page(vma))
			hugepage_size = huge_page_size(hstate_vma(vma));

		if (hugepage_size >= PUD_SIZE) {
			unsigned long mask = 0x1ffc00000UL;

			/* Transfer bits [32:22] from address to resolve
			 * at 4M granularity.
			 */
			pte_val(pte) &= ~mask;
			pte_val(pte) |= (address & mask);
		} else if (hugepage_size >= PMD_SIZE) {
			/* We are fabricating 8MB pages using 4MB
			 * real hw pages.
			 */
			pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
		}

		if (hugepage_size >= PMD_SIZE) {
			__update_mmu_tsb_insert(mm, MM_TSB_HUGE,
				REAL_HPAGE_SHIFT, address, pte_val(pte));
			is_huge_tsb = true;
		}
	}
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#endif
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	if (!is_huge_tsb)
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		__update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
					address, pte_val(pte));
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	spin_unlock_irqrestore(&mm->context.lock, flags);
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}

void flush_dcache_page(struct page *page)
{
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	struct address_space *mapping;
	int this_cpu;
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	if (tlb_type == hypervisor)
		return;

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	/* Do not bother with the expensive D-cache flush if it
	 * is merely the zero page.  The 'bigcore' testcase in GDB
	 * causes this case to run millions of times.
	 */
	if (page == ZERO_PAGE(0))
		return;

	this_cpu = get_cpu();

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	mapping = page_mapping_file(page);
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	if (mapping && !mapping_mapped(mapping)) {
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		int dirty = test_bit(PG_dcache_dirty, &page->flags);
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		if (dirty) {
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			int dirty_cpu = dcache_dirty_cpu(page);

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			if (dirty_cpu == this_cpu)
				goto out;
			smp_flush_dcache_page_impl(page, dirty_cpu);
		}
		set_dcache_dirty(page, this_cpu);
	} else {
		/* We could delay the flush for the !page_mapping
		 * case too.  But that case is for exec env/arg
		 * pages and those are %99 certainly going to get
		 * faulted into the tlb (and thus flushed) anyways.
		 */
		flush_dcache_page_impl(page);
	}

out:
	put_cpu();
}
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EXPORT_SYMBOL(flush_dcache_page);
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void __kprobes flush_icache_range(unsigned long start, unsigned long end)
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{
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	/* Cheetah and Hypervisor platform cpus have coherent I-cache. */
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	if (tlb_type == spitfire) {
		unsigned long kaddr;

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		/* This code only runs on Spitfire cpus so this is
		 * why we can assume _PAGE_PADDR_4U.
		 */
		for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
			unsigned long paddr, mask = _PAGE_PADDR_4U;

			if (kaddr >= PAGE_OFFSET)
				paddr = kaddr & mask;
			else {
				pgd_t *pgdp = pgd_offset_k(kaddr);
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				p4d_t *p4dp = p4d_offset(pgdp, kaddr);
				pud_t *pudp = pud_offset(p4dp, kaddr);
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				pmd_t *pmdp = pmd_offset(pudp, kaddr);
				pte_t *ptep = pte_offset_kernel(pmdp, kaddr);

				paddr = pte_val(*ptep) & mask;
			}
			__flush_icache_page(paddr);
		}
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	}
}
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EXPORT_SYMBOL(flush_icache_range);
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void mmu_info(struct seq_file *m)
{
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	static const char *pgsz_strings[] = {
		"8K", "64K", "512K", "4MB", "32MB",
		"256MB", "2GB", "16GB",
	};
	int i, printed;

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	if (tlb_type == cheetah)
		seq_printf(m, "MMU Type\t: Cheetah\n");
	else if (tlb_type == cheetah_plus)
		seq_printf(m, "MMU Type\t: Cheetah+\n");
	else if (tlb_type == spitfire)
		seq_printf(m, "MMU Type\t: Spitfire\n");
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	else if (tlb_type == hypervisor)
		seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
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	else
		seq_printf(m, "MMU Type\t: ???\n");

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	seq_printf(m, "MMU PGSZs\t: ");
	printed = 0;
	for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
		if (cpu_pgsz_mask & (1UL << i)) {
			seq_printf(m, "%s%s",
				   printed ? "," : "", pgsz_strings[i]);
			printed++;
		}
	}
	seq_putc(m, '\n');

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#ifdef CONFIG_DEBUG_DCFLUSH
	seq_printf(m, "DCPageFlushes\t: %d\n",
		   atomic_read(&dcpage_flushes));
#ifdef CONFIG_SMP
	seq_printf(m, "DCPageFlushesXC\t: %d\n",
		   atomic_read(&dcpage_flushes_xcall));
#endif /* CONFIG_SMP */
#endif /* CONFIG_DEBUG_DCFLUSH */
}

572 573 574
struct linux_prom_translation prom_trans[512] __read_mostly;
unsigned int prom_trans_ents __read_mostly;

L
Linus Torvalds 已提交
575 576
unsigned long kern_locked_tte_data;

577 578
/* The obp translations are saved based on 8k pagesize, since obp can
 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
579
 * HI_OBP_ADDRESS range are handled in ktlb.S.
580
 */
581 582 583 584 585 586
static inline int in_obp_range(unsigned long vaddr)
{
	return (vaddr >= LOW_OBP_ADDRESS &&
		vaddr < HI_OBP_ADDRESS);
}

587
static int cmp_ptrans(const void *a, const void *b)
588
{
589
	const struct linux_prom_translation *x = a, *y = b;
590

591 592 593 594 595
	if (x->virt > y->virt)
		return 1;
	if (x->virt < y->virt)
		return -1;
	return 0;
596 597
}

598
/* Read OBP translations property into 'prom_trans[]'.  */
599
static void __init read_obp_translations(void)
600
{
601
	int n, node, ents, first, last, i;
L
Linus Torvalds 已提交
602 603 604

	node = prom_finddevice("/virtual-memory");
	n = prom_getproplen(node, "translations");
605
	if (unlikely(n == 0 || n == -1)) {
606
		prom_printf("prom_mappings: Couldn't get size.\n");
L
Linus Torvalds 已提交
607 608
		prom_halt();
	}
609
	if (unlikely(n > sizeof(prom_trans))) {
610
		prom_printf("prom_mappings: Size %d is too big.\n", n);
L
Linus Torvalds 已提交
611 612
		prom_halt();
	}
613

614
	if ((n = prom_getproperty(node, "translations",
615 616
				  (char *)&prom_trans[0],
				  sizeof(prom_trans))) == -1) {
617
		prom_printf("prom_mappings: Couldn't get property.\n");
L
Linus Torvalds 已提交
618 619
		prom_halt();
	}
620

621
	n = n / sizeof(struct linux_prom_translation);
622

623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657
	ents = n;

	sort(prom_trans, ents, sizeof(struct linux_prom_translation),
	     cmp_ptrans, NULL);

	/* Now kick out all the non-OBP entries.  */
	for (i = 0; i < ents; i++) {
		if (in_obp_range(prom_trans[i].virt))
			break;
	}
	first = i;
	for (; i < ents; i++) {
		if (!in_obp_range(prom_trans[i].virt))
			break;
	}
	last = i;

	for (i = 0; i < (last - first); i++) {
		struct linux_prom_translation *src = &prom_trans[i + first];
		struct linux_prom_translation *dest = &prom_trans[i];

		*dest = *src;
	}
	for (; i < ents; i++) {
		struct linux_prom_translation *dest = &prom_trans[i];
		dest->virt = dest->size = dest->data = 0x0UL;
	}

	prom_trans_ents = last - first;

	if (tlb_type == spitfire) {
		/* Clear diag TTE bits. */
		for (i = 0; i < prom_trans_ents; i++)
			prom_trans[i].data &= ~0x0003fe0000000000UL;
	}
658 659 660 661 662

	/* Force execute bit on.  */
	for (i = 0; i < prom_trans_ents; i++)
		prom_trans[i].data |= (tlb_type == hypervisor ?
				       _PAGE_EXEC_4V : _PAGE_EXEC_4U);
663
}
L
Linus Torvalds 已提交
664

665 666 667 668
static void __init hypervisor_tlb_lock(unsigned long vaddr,
				       unsigned long pte,
				       unsigned long mmu)
{
669 670 671
	unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);

	if (ret != 0) {
672
		prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
673
			    "errors with %lx\n", vaddr, 0, pte, mmu, ret);
674 675
		prom_halt();
	}
676 677
}

678 679
static unsigned long kern_large_tte(unsigned long paddr);

680
static void __init remap_kernel(void)
681 682
{
	unsigned long phys_page, tte_vaddr, tte_data;
683
	int i, tlb_ent = sparc64_highest_locked_tlbent();
684

L
Linus Torvalds 已提交
685
	tte_vaddr = (unsigned long) KERNBASE;
686
	phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
687
	tte_data = kern_large_tte(phys_page);
L
Linus Torvalds 已提交
688 689 690

	kern_locked_tte_data = tte_data;

691 692
	/* Now lock us into the TLBs via Hypervisor or OBP. */
	if (tlb_type == hypervisor) {
693
		for (i = 0; i < num_kernel_image_mappings; i++) {
694 695
			hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
			hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
696 697
			tte_vaddr += 0x400000;
			tte_data += 0x400000;
698 699
		}
	} else {
700 701 702 703 704
		for (i = 0; i < num_kernel_image_mappings; i++) {
			prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
			prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
			tte_vaddr += 0x400000;
			tte_data += 0x400000;
705
		}
706
		sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
L
Linus Torvalds 已提交
707
	}
708 709 710 711 712 713
	if (tlb_type == cheetah_plus) {
		sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
					    CTX_CHEETAH_PLUS_NUC);
		sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
		sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
	}
714
}
L
Linus Torvalds 已提交
715

716

717
static void __init inherit_prom_mappings(void)
718
{
719
	/* Now fixup OBP's idea about where we really are mapped. */
720
	printk("Remapping the kernel... ");
721
	remap_kernel();
722
	printk("done.\n");
L
Linus Torvalds 已提交
723 724 725 726 727
}

void prom_world(int enter)
{
	if (!enter)
728
		set_fs(get_fs());
L
Linus Torvalds 已提交
729

730
	__asm__ __volatile__("flushw");
L
Linus Torvalds 已提交
731 732 733 734 735 736 737 738 739 740 741 742 743 744
}

void __flush_dcache_range(unsigned long start, unsigned long end)
{
	unsigned long va;

	if (tlb_type == spitfire) {
		int n = 0;

		for (va = start; va < end; va += 32) {
			spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
			if (++n >= 512)
				break;
		}
745
	} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
L
Linus Torvalds 已提交
746 747 748 749 750 751 752 753 754 755
		start = __pa(start);
		end = __pa(end);
		for (va = start; va < end; va += 32)
			__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
					     "membar #Sync"
					     : /* no outputs */
					     : "r" (va),
					       "i" (ASI_DCACHE_INVALIDATE));
	}
}
756
EXPORT_SYMBOL(__flush_dcache_range);
L
Linus Torvalds 已提交
757

758 759
/* get_new_mmu_context() uses "cache + 1".  */
DEFINE_SPINLOCK(ctx_alloc_lock);
P
Pavel Tatashin 已提交
760
unsigned long tlb_context_cache = CTX_FIRST_VERSION;
761 762 763
#define MAX_CTX_NR	(1UL << CTX_NR_BITS)
#define CTX_BMAP_SLOTS	BITS_TO_LONGS(MAX_CTX_NR)
DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
764
DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
765

P
Pavel Tatashin 已提交
766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812
static void mmu_context_wrap(void)
{
	unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
	unsigned long new_ver, new_ctx, old_ctx;
	struct mm_struct *mm;
	int cpu;

	bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);

	/* Reserve kernel context */
	set_bit(0, mmu_context_bmap);

	new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
	if (unlikely(new_ver == 0))
		new_ver = CTX_FIRST_VERSION;
	tlb_context_cache = new_ver;

	/*
	 * Make sure that any new mm that are added into per_cpu_secondary_mm,
	 * are going to go through get_new_mmu_context() path.
	 */
	mb();

	/*
	 * Updated versions to current on those CPUs that had valid secondary
	 * contexts
	 */
	for_each_online_cpu(cpu) {
		/*
		 * If a new mm is stored after we took this mm from the array,
		 * it will go into get_new_mmu_context() path, because we
		 * already bumped the version in tlb_context_cache.
		 */
		mm = per_cpu(per_cpu_secondary_mm, cpu);

		if (unlikely(!mm || mm == &init_mm))
			continue;

		old_ctx = mm->context.sparc64_ctx_val;
		if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
			new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
			set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
			mm->context.sparc64_ctx_val = new_ctx;
		}
	}
}

L
Linus Torvalds 已提交
813 814 815 816 817 818 819
/* Caller does TLB context flushing on local CPU if necessary.
 * The caller also ensures that CTX_VALID(mm->context) is false.
 *
 * We must be careful about boundary cases so that we never
 * let the user have CTX 0 (nucleus) or we ever use a CTX
 * version of zero (and thus NO_CONTEXT would not be caught
 * by version mis-match tests in mmu_context.h).
820 821
 *
 * Always invoked with interrupts disabled.
L
Linus Torvalds 已提交
822 823 824 825 826 827
 */
void get_new_mmu_context(struct mm_struct *mm)
{
	unsigned long ctx, new_ctx;
	unsigned long orig_pgsz_bits;

828
	spin_lock(&ctx_alloc_lock);
P
Pavel Tatashin 已提交
829 830 831 832
retry:
	/* wrap might have happened, test again if our context became valid */
	if (unlikely(CTX_VALID(mm->context)))
		goto out;
L
Linus Torvalds 已提交
833 834 835 836 837 838
	orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
	ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
	new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
	if (new_ctx >= (1 << CTX_NR_BITS)) {
		new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
		if (new_ctx >= ctx) {
P
Pavel Tatashin 已提交
839 840
			mmu_context_wrap();
			goto retry;
L
Linus Torvalds 已提交
841 842
		}
	}
843 844
	if (mm->context.sparc64_ctx_val)
		cpumask_clear(mm_cpumask(mm));
L
Linus Torvalds 已提交
845 846 847 848
	mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
	new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
	tlb_context_cache = new_ctx;
	mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
P
Pavel Tatashin 已提交
849
out:
850
	spin_unlock(&ctx_alloc_lock);
L
Linus Torvalds 已提交
851 852
}

D
David S. Miller 已提交
853 854 855 856
static int numa_enabled = 1;
static int numa_debug;

static int __init early_numa(char *p)
L
Linus Torvalds 已提交
857
{
D
David S. Miller 已提交
858 859 860 861 862
	if (!p)
		return 0;

	if (strstr(p, "off"))
		numa_enabled = 0;
863

D
David S. Miller 已提交
864 865
	if (strstr(p, "debug"))
		numa_debug = 1;
866

D
David S. Miller 已提交
867
	return 0;
868
}
D
David S. Miller 已提交
869 870 871 872 873 874
early_param("numa", early_numa);

#define numadbg(f, a...) \
do {	if (numa_debug) \
		printk(KERN_INFO f, ## a); \
} while (0)
875

876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900
static void __init find_ramdisk(unsigned long phys_base)
{
#ifdef CONFIG_BLK_DEV_INITRD
	if (sparc_ramdisk_image || sparc_ramdisk_image64) {
		unsigned long ramdisk_image;

		/* Older versions of the bootloader only supported a
		 * 32-bit physical address for the ramdisk image
		 * location, stored at sparc_ramdisk_image.  Newer
		 * SILO versions set sparc_ramdisk_image to zero and
		 * provide a full 64-bit physical address at
		 * sparc_ramdisk_image64.
		 */
		ramdisk_image = sparc_ramdisk_image;
		if (!ramdisk_image)
			ramdisk_image = sparc_ramdisk_image64;

		/* Another bootloader quirk.  The bootloader normalizes
		 * the physical address to KERNBASE, so we have to
		 * factor that back out and add in the lowest valid
		 * physical page address to get the true physical address.
		 */
		ramdisk_image -= KERNBASE;
		ramdisk_image += phys_base;

D
David S. Miller 已提交
901 902 903
		numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
			ramdisk_image, sparc_ramdisk_size);

904 905
		initrd_start = ramdisk_image;
		initrd_end = ramdisk_image + sparc_ramdisk_size;
906

Y
Yinghai Lu 已提交
907
		memblock_reserve(initrd_start, sparc_ramdisk_size);
908 909 910

		initrd_start += PAGE_OFFSET;
		initrd_end += PAGE_OFFSET;
911 912 913 914
	}
#endif
}

D
David S. Miller 已提交
915 916
struct node_mem_mask {
	unsigned long mask;
917
	unsigned long match;
D
David S. Miller 已提交
918 919 920 921
};
static struct node_mem_mask node_masks[MAX_NUMNODES];
static int num_node_masks;

922 923
#ifdef CONFIG_NEED_MULTIPLE_NODES

924 925 926 927 928 929 930 931 932 933
struct mdesc_mlgroup {
	u64	node;
	u64	latency;
	u64	match;
	u64	mask;
};

static struct mdesc_mlgroup *mlgroups;
static int num_mlgroups;

D
David S. Miller 已提交
934 935 936 937 938 939 940 941 942 943 944
int numa_cpu_lookup_table[NR_CPUS];
cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];

struct mdesc_mblock {
	u64	base;
	u64	size;
	u64	offset; /* RA-to-PA */
};
static struct mdesc_mblock *mblocks;
static int num_mblocks;

945
static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
D
David S. Miller 已提交
946
{
947
	struct mdesc_mblock *m = NULL;
D
David S. Miller 已提交
948 949 950
	int i;

	for (i = 0; i < num_mblocks; i++) {
951
		m = &mblocks[i];
D
David S. Miller 已提交
952 953 954 955 956 957

		if (addr >= m->base &&
		    addr < (m->base + m->size)) {
			break;
		}
	}
958 959

	return m;
D
David S. Miller 已提交
960 961
}

962
static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
D
David S. Miller 已提交
963
{
964
	int prev_nid, new_nid;
D
David S. Miller 已提交
965

966
	prev_nid = NUMA_NO_NODE;
967 968 969
	for ( ; start < end; start += PAGE_SIZE) {
		for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
			struct node_mem_mask *p = &node_masks[new_nid];
D
David S. Miller 已提交
970

971
			if ((start & p->mask) == p->match) {
972
				if (prev_nid == NUMA_NO_NODE)
973 974 975
					prev_nid = new_nid;
				break;
			}
976
		}
977 978 979 980 981 982 983 984 985 986

		if (new_nid == num_node_masks) {
			prev_nid = 0;
			WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
				  start);
			break;
		}

		if (prev_nid != new_nid)
			break;
987
	}
988
	*nid = prev_nid;
989

990
	return start > end ? end : start;
D
David S. Miller 已提交
991 992
}

993
static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
D
David S. Miller 已提交
994
{
995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014
	u64 ret_end, pa_start, m_mask, m_match, m_end;
	struct mdesc_mblock *mblock;
	int _nid, i;

	if (tlb_type != hypervisor)
		return memblock_nid_range_sun4u(start, end, nid);

	mblock = addr_to_mblock(start);
	if (!mblock) {
		WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
			  start);

		_nid = 0;
		ret_end = end;
		goto done;
	}

	pa_start = start + mblock->offset;
	m_match = 0;
	m_mask = 0;
D
David S. Miller 已提交
1015

1016 1017 1018 1019 1020 1021
	for (_nid = 0; _nid < num_node_masks; _nid++) {
		struct node_mem_mask *const m = &node_masks[_nid];

		if ((pa_start & m->mask) == m->match) {
			m_match = m->match;
			m_mask = m->mask;
D
David S. Miller 已提交
1022
			break;
1023
		}
D
David S. Miller 已提交
1024 1025
	}

1026 1027 1028 1029 1030 1031 1032 1033 1034
	if (num_node_masks == _nid) {
		/* We could not find NUMA group, so default to 0, but lets
		 * search for latency group, so we could calculate the correct
		 * end address that we return
		 */
		_nid = 0;

		for (i = 0; i < num_mlgroups; i++) {
			struct mdesc_mlgroup *const m = &mlgroups[i];
1035

1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066
			if ((pa_start & m->mask) == m->match) {
				m_match = m->match;
				m_mask = m->mask;
				break;
			}
		}

		if (i == num_mlgroups) {
			WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
				  start);

			ret_end = end;
			goto done;
		}
	}

	/*
	 * Each latency group has match and mask, and each memory block has an
	 * offset.  An address belongs to a latency group if its address matches
	 * the following formula: ((addr + offset) & mask) == match
	 * It is, however, slow to check every single page if it matches a
	 * particular latency group. As optimization we calculate end value by
	 * using bit arithmetics.
	 */
	m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
	m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
	ret_end = m_end > end ? end : m_end;

done:
	*nid = _nid;
	return ret_end;
D
David S. Miller 已提交
1067 1068 1069 1070
}
#endif

/* This must be invoked after performing all of the necessary
T
Tejun Heo 已提交
1071
 * memblock_set_node() calls for 'nid'.  We need to be able to get
D
David S. Miller 已提交
1072
 * correct data from get_pfn_range_for_nid().
1073
 */
D
David S. Miller 已提交
1074 1075 1076
static void __init allocate_node_data(int nid)
{
	struct pglist_data *p;
1077
	unsigned long start_pfn, end_pfn;
D
David S. Miller 已提交
1078
#ifdef CONFIG_NEED_MULTIPLE_NODES
1079

1080 1081 1082
	NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data),
					     SMP_CACHE_BYTES, nid);
	if (!NODE_DATA(nid)) {
D
David S. Miller 已提交
1083 1084 1085 1086
		prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
		prom_halt();
	}

1087
	NODE_DATA(nid)->node_id = nid;
D
David S. Miller 已提交
1088 1089 1090 1091 1092 1093 1094 1095 1096 1097
#endif

	p = NODE_DATA(nid);

	get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
	p->node_start_pfn = start_pfn;
	p->node_spanned_pages = end_pfn - start_pfn;
}

static void init_node_masks_nonnuma(void)
1098
{
1099
#ifdef CONFIG_NEED_MULTIPLE_NODES
L
Linus Torvalds 已提交
1100
	int i;
1101
#endif
L
Linus Torvalds 已提交
1102

D
David S. Miller 已提交
1103
	numadbg("Initializing tables for non-numa.\n");
1104

1105 1106
	node_masks[0].mask = 0;
	node_masks[0].match = 0;
D
David S. Miller 已提交
1107
	num_node_masks = 1;
1108

1109
#ifdef CONFIG_NEED_MULTIPLE_NODES
D
David S. Miller 已提交
1110 1111
	for (i = 0; i < NR_CPUS; i++)
		numa_cpu_lookup_table[i] = 0;
L
Linus Torvalds 已提交
1112

1113
	cpumask_setall(&numa_cpumask_lookup_table[0]);
1114
#endif
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}

#ifdef CONFIG_NEED_MULTIPLE_NODES
struct pglist_data *node_data[MAX_NUMNODES];

EXPORT_SYMBOL(numa_cpu_lookup_table);
EXPORT_SYMBOL(numa_cpumask_lookup_table);
EXPORT_SYMBOL(node_data);

static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
				   u32 cfg_handle)
{
	u64 arc;

	mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
		u64 target = mdesc_arc_target(md, arc);
		const u64 *val;

		val = mdesc_get_property(md, target,
					 "cfg-handle", NULL);
		if (val && *val == cfg_handle)
			return 0;
	}
	return -ENODEV;
}

static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
				    u32 cfg_handle)
{
	u64 arc, candidate, best_latency = ~(u64)0;

	candidate = MDESC_NODE_NULL;
	mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
		u64 target = mdesc_arc_target(md, arc);
		const char *name = mdesc_node_name(md, target);
		const u64 *val;

		if (strcmp(name, "pio-latency-group"))
			continue;

		val = mdesc_get_property(md, target, "latency", NULL);
		if (!val)
			continue;

		if (*val < best_latency) {
			candidate = target;
			best_latency = *val;
		}
	}

	if (candidate == MDESC_NODE_NULL)
		return -ENODEV;

	return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
}

int of_node_to_nid(struct device_node *dp)
{
	const struct linux_prom64_registers *regs;
	struct mdesc_handle *md;
	u32 cfg_handle;
	int count, nid;
	u64 grp;

1179 1180 1181 1182
	/* This is the right thing to do on currently supported
	 * SUN4U NUMA platforms as well, as the PCI controller does
	 * not sit behind any particular memory controller.
	 */
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	if (!mlgroups)
		return -1;

	regs = of_get_property(dp, "reg", NULL);
	if (!regs)
		return -1;

	cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;

	md = mdesc_grab();

	count = 0;
1195
	nid = NUMA_NO_NODE;
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	mdesc_for_each_node_by_name(md, grp, "group") {
		if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
			nid = count;
			break;
		}
		count++;
	}

	mdesc_release(md);

	return nid;
}

1209
static void __init add_node_ranges(void)
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{
1211
	struct memblock_region *reg;
1212 1213 1214 1215
	unsigned long prev_max;

memblock_resized:
	prev_max = memblock.memory.max;
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1217 1218
	for_each_memblock(memory, reg) {
		unsigned long size = reg->size;
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		unsigned long start, end;

1221
		start = reg->base;
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		end = start + size;
		while (start < end) {
			unsigned long this_end;
			int nid;

1227
			this_end = memblock_nid_range(start, end, &nid);
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T
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1229
			numadbg("Setting memblock NUMA node nid[%d] "
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				"start[%lx] end[%lx]\n",
				nid, start, this_end);

1233 1234
			memblock_set_node(start, this_end - start,
					  &memblock.memory, nid);
1235 1236
			if (memblock.memory.max != prev_max)
				goto memblock_resized;
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			start = this_end;
		}
	}
}

static int __init grab_mlgroups(struct mdesc_handle *md)
{
	unsigned long paddr;
	int count = 0;
	u64 node;

	mdesc_for_each_node_by_name(md, node, "memory-latency-group")
		count++;
	if (!count)
		return -ENOENT;

1253 1254
	paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup),
				    SMP_CACHE_BYTES);
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	if (!paddr)
		return -ENOMEM;

	mlgroups = __va(paddr);
	num_mlgroups = count;

	count = 0;
	mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
		struct mdesc_mlgroup *m = &mlgroups[count++];
		const u64 *val;

		m->node = node;

		val = mdesc_get_property(md, node, "latency", NULL);
		m->latency = *val;
		val = mdesc_get_property(md, node, "address-match", NULL);
		m->match = *val;
		val = mdesc_get_property(md, node, "address-mask", NULL);
		m->mask = *val;

1275 1276
		numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
			"match[%llx] mask[%llx]\n",
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			count - 1, m->node, m->latency, m->match, m->mask);
	}

	return 0;
}

static int __init grab_mblocks(struct mdesc_handle *md)
{
	unsigned long paddr;
	int count = 0;
	u64 node;

	mdesc_for_each_node_by_name(md, node, "mblock")
		count++;
	if (!count)
		return -ENOENT;

1294 1295
	paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock),
				    SMP_CACHE_BYTES);
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	if (!paddr)
		return -ENOMEM;

	mblocks = __va(paddr);
	num_mblocks = count;

	count = 0;
	mdesc_for_each_node_by_name(md, node, "mblock") {
		struct mdesc_mblock *m = &mblocks[count++];
		const u64 *val;

		val = mdesc_get_property(md, node, "base", NULL);
		m->base = *val;
		val = mdesc_get_property(md, node, "size", NULL);
		m->size = *val;
		val = mdesc_get_property(md, node,
					 "address-congruence-offset", NULL);
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		/* The address-congruence-offset property is optional.
		 * Explicity zero it be identifty this.
		 */
		if (val)
			m->offset = *val;
		else
			m->offset = 0UL;
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1322
		numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
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			count - 1, m->base, m->size, m->offset);
	}

	return 0;
}

static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
					       u64 grp, cpumask_t *mask)
{
	u64 arc;

1334
	cpumask_clear(mask);
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	mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
		u64 target = mdesc_arc_target(md, arc);
		const char *name = mdesc_node_name(md, target);
		const u64 *id;

		if (strcmp(name, "cpu"))
			continue;
		id = mdesc_get_property(md, target, "id", NULL);
1344
		if (*id < nr_cpu_ids)
1345
			cpumask_set_cpu(*id, mask);
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	}
}

static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
{
	int i;

	for (i = 0; i < num_mlgroups; i++) {
		struct mdesc_mlgroup *m = &mlgroups[i];
		if (m->node == node)
			return m;
	}
	return NULL;
}

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int __node_distance(int from, int to)
{
	if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
		pr_warn("Returning default NUMA distance value for %d->%d\n",
			from, to);
		return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
	}
	return numa_latency[from][to];
}
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EXPORT_SYMBOL(__node_distance);
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1372
static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
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{
	int i;

	for (i = 0; i < MAX_NUMNODES; i++) {
		struct node_mem_mask *n = &node_masks[i];

1379
		if ((grp->mask == n->mask) && (grp->match == n->match))
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			break;
	}
	return i;
}

1385 1386
static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
						 u64 grp, int index)
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{
	u64 arc;

	mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
		int tnode;
		u64 target = mdesc_arc_target(md, arc);
		struct mdesc_mlgroup *m = find_mlgroup(target);

		if (!m)
			continue;
		tnode = find_best_numa_node_for_mlgroup(m);
		if (tnode == MAX_NUMNODES)
			continue;
		numa_latency[index][tnode] = m->latency;
	}
}

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static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
				      int index)
{
	struct mdesc_mlgroup *candidate = NULL;
	u64 arc, best_latency = ~(u64)0;
	struct node_mem_mask *n;

	mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
		u64 target = mdesc_arc_target(md, arc);
		struct mdesc_mlgroup *m = find_mlgroup(target);
		if (!m)
			continue;
		if (m->latency < best_latency) {
			candidate = m;
			best_latency = m->latency;
		}
	}
	if (!candidate)
		return -ENOENT;

	if (num_node_masks != index) {
		printk(KERN_ERR "Inconsistent NUMA state, "
		       "index[%d] != num_node_masks[%d]\n",
		       index, num_node_masks);
		return -EINVAL;
	}

	n = &node_masks[num_node_masks++];

	n->mask = candidate->mask;
1434
	n->match = candidate->match;
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1436 1437
	numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
		index, n->mask, n->match, candidate->latency);
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	return 0;
}

static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
					 int index)
{
	cpumask_t mask;
	int cpu;

	numa_parse_mdesc_group_cpus(md, grp, &mask);

1450
	for_each_cpu(cpu, &mask)
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		numa_cpu_lookup_table[cpu] = index;
1452
	cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
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	if (numa_debug) {
		printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1456
		for_each_cpu(cpu, &mask)
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			printk("%d ", cpu);
		printk("]\n");
	}

	return numa_attach_mlgroup(md, grp, index);
}

static int __init numa_parse_mdesc(void)
{
	struct mdesc_handle *md = mdesc_grab();
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	int i, j, err, count;
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	u64 node;

	node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
	if (node == MDESC_NODE_NULL) {
		mdesc_release(md);
		return -ENOENT;
	}

	err = grab_mblocks(md);
	if (err < 0)
		goto out;

	err = grab_mlgroups(md);
	if (err < 0)
		goto out;

	count = 0;
	mdesc_for_each_node_by_name(md, node, "group") {
		err = numa_parse_mdesc_group(md, node, count);
		if (err < 0)
			break;
		count++;
	}

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	count = 0;
	mdesc_for_each_node_by_name(md, node, "group") {
		find_numa_latencies_for_group(md, node, count);
		count++;
	}

	/* Normalize numa latency matrix according to ACPI SLIT spec. */
	for (i = 0; i < MAX_NUMNODES; i++) {
		u64 self_latency = numa_latency[i][i];

		for (j = 0; j < MAX_NUMNODES; j++) {
			numa_latency[i][j] =
				(numa_latency[i][j] * LOCAL_DISTANCE) /
				self_latency;
		}
	}

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	add_node_ranges();

	for (i = 0; i < num_node_masks; i++) {
		allocate_node_data(i);
		node_set_online(i);
	}

	err = 0;
out:
	mdesc_release(md);
	return err;
}

1522 1523 1524 1525 1526 1527 1528 1529 1530 1531
static int __init numa_parse_jbus(void)
{
	unsigned long cpu, index;

	/* NUMA node id is encoded in bits 36 and higher, and there is
	 * a 1-to-1 mapping from CPU ID to NUMA node ID.
	 */
	index = 0;
	for_each_present_cpu(cpu) {
		numa_cpu_lookup_table[cpu] = index;
1532
		cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1533
		node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1534
		node_masks[index].match = cpu << 36UL;
1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549

		index++;
	}
	num_node_masks = index;

	add_node_ranges();

	for (index = 0; index < num_node_masks; index++) {
		allocate_node_data(index);
		node_set_online(index);
	}

	return 0;
}

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static int __init numa_parse_sun4u(void)
{
1552 1553 1554 1555 1556 1557 1558 1559
	if (tlb_type == cheetah || tlb_type == cheetah_plus) {
		unsigned long ver;

		__asm__ ("rdpr %%ver, %0" : "=r" (ver));
		if ((ver >> 32UL) == __JALAPENO_ID ||
		    (ver >> 32UL) == __SERRANO_ID)
			return numa_parse_jbus();
	}
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	return -1;
}

static int __init bootmem_init_numa(void)
{
1565
	int i, j;
D
David S. Miller 已提交
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	int err = -1;

	numadbg("bootmem_init_numa()\n");

1570 1571 1572 1573 1574 1575 1576
	/* Some sane defaults for numa latency values */
	for (i = 0; i < MAX_NUMNODES; i++) {
		for (j = 0; j < MAX_NUMNODES; j++)
			numa_latency[i][j] = (i == j) ?
				LOCAL_DISTANCE : REMOTE_DISTANCE;
	}

D
David S. Miller 已提交
1577 1578 1579 1580 1581 1582 1583 1584 1585 1586
	if (numa_enabled) {
		if (tlb_type == hypervisor)
			err = numa_parse_mdesc();
		else
			err = numa_parse_sun4u();
	}
	return err;
}

#else
L
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1588 1589 1590 1591 1592 1593 1594 1595 1596
static int bootmem_init_numa(void)
{
	return -1;
}

#endif

static void __init bootmem_init_nonnuma(void)
{
Y
Yinghai Lu 已提交
1597 1598
	unsigned long top_of_ram = memblock_end_of_DRAM();
	unsigned long total_ram = memblock_phys_mem_size();
D
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	numadbg("bootmem_init_nonnuma()\n");

	printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
	       top_of_ram, total_ram);
	printk(KERN_INFO "Memory hole size: %ldMB\n",
	       (top_of_ram - total_ram) >> 20);

	init_node_masks_nonnuma();
1608
	memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
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	allocate_node_data(0);
	node_set_online(0);
}

static unsigned long __init bootmem_init(unsigned long phys_base)
{
	unsigned long end_pfn;

Y
Yinghai Lu 已提交
1617
	end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
D
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1618 1619 1620 1621 1622 1623
	max_pfn = max_low_pfn = end_pfn;
	min_low_pfn = (phys_base >> PAGE_SHIFT);

	if (bootmem_init_numa() < 0)
		bootmem_init_nonnuma();

1624 1625
	/* Dump memblock with node info. */
	memblock_dump_all();
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David S. Miller 已提交
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1627
	/* XXX cpu notifier XXX */
1628

1629
	sparse_memory_present_with_active_regions(MAX_NUMNODES);
1630 1631
	sparse_init();

L
Linus Torvalds 已提交
1632 1633 1634
	return end_pfn;
}

1635 1636 1637
static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
static int pall_ents __initdata;

1638 1639 1640 1641 1642
static unsigned long max_phys_bits = 40;

bool kern_addr_valid(unsigned long addr)
{
	pgd_t *pgd;
1643
	p4d_t *p4d;
1644 1645 1646 1647
	pud_t *pud;
	pmd_t *pmd;
	pte_t *pte;

1648
	if ((long)addr < 0L) {
1649 1650
		unsigned long pa = __pa(addr);

B
bob picco 已提交
1651
		if ((pa >> max_phys_bits) != 0UL)
1652 1653
			return false;

1654 1655 1656
		return pfn_valid(pa >> PAGE_SHIFT);
	}

1657 1658 1659 1660
	if (addr >= (unsigned long) KERNBASE &&
	    addr < (unsigned long)&_end)
		return true;

1661 1662 1663 1664
	pgd = pgd_offset_k(addr);
	if (pgd_none(*pgd))
		return 0;

1665 1666 1667 1668 1669
	p4d = p4d_offset(pgd, addr);
	if (p4d_none(*p4d))
		return 0;

	pud = pud_offset(p4d, addr);
1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777
	if (pud_none(*pud))
		return 0;

	if (pud_large(*pud))
		return pfn_valid(pud_pfn(*pud));

	pmd = pmd_offset(pud, addr);
	if (pmd_none(*pmd))
		return 0;

	if (pmd_large(*pmd))
		return pfn_valid(pmd_pfn(*pmd));

	pte = pte_offset_kernel(pmd, addr);
	if (pte_none(*pte))
		return 0;

	return pfn_valid(pte_pfn(*pte));
}
EXPORT_SYMBOL(kern_addr_valid);

static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
					      unsigned long vend,
					      pud_t *pud)
{
	const unsigned long mask16gb = (1UL << 34) - 1UL;
	u64 pte_val = vstart;

	/* Each PUD is 8GB */
	if ((vstart & mask16gb) ||
	    (vend - vstart <= mask16gb)) {
		pte_val ^= kern_linear_pte_xor[2];
		pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;

		return vstart + PUD_SIZE;
	}

	pte_val ^= kern_linear_pte_xor[3];
	pte_val |= _PAGE_PUD_HUGE;

	vend = vstart + mask16gb + 1UL;
	while (vstart < vend) {
		pud_val(*pud) = pte_val;

		pte_val += PUD_SIZE;
		vstart += PUD_SIZE;
		pud++;
	}
	return vstart;
}

static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
				   bool guard)
{
	if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
		return true;

	return false;
}

static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
					      unsigned long vend,
					      pmd_t *pmd)
{
	const unsigned long mask256mb = (1UL << 28) - 1UL;
	const unsigned long mask2gb = (1UL << 31) - 1UL;
	u64 pte_val = vstart;

	/* Each PMD is 8MB */
	if ((vstart & mask256mb) ||
	    (vend - vstart <= mask256mb)) {
		pte_val ^= kern_linear_pte_xor[0];
		pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;

		return vstart + PMD_SIZE;
	}

	if ((vstart & mask2gb) ||
	    (vend - vstart <= mask2gb)) {
		pte_val ^= kern_linear_pte_xor[1];
		pte_val |= _PAGE_PMD_HUGE;
		vend = vstart + mask256mb + 1UL;
	} else {
		pte_val ^= kern_linear_pte_xor[2];
		pte_val |= _PAGE_PMD_HUGE;
		vend = vstart + mask2gb + 1UL;
	}

	while (vstart < vend) {
		pmd_val(*pmd) = pte_val;

		pte_val += PMD_SIZE;
		vstart += PMD_SIZE;
		pmd++;
	}

	return vstart;
}

static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
				   bool guard)
{
	if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
		return true;

	return false;
}

1778
static unsigned long __ref kernel_map_range(unsigned long pstart,
1779 1780
					    unsigned long pend, pgprot_t prot,
					    bool use_huge)
1781 1782 1783 1784 1785 1786
{
	unsigned long vstart = PAGE_OFFSET + pstart;
	unsigned long vend = PAGE_OFFSET + pend;
	unsigned long alloc_bytes = 0UL;

	if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1787
		prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1788 1789 1790 1791 1792 1793 1794
			    vstart, vend);
		prom_halt();
	}

	while (vstart < vend) {
		unsigned long this_end, paddr = __pa(vstart);
		pgd_t *pgd = pgd_offset_k(vstart);
1795
		p4d_t *p4d;
1796 1797 1798 1799
		pud_t *pud;
		pmd_t *pmd;
		pte_t *pte;

1800 1801 1802
		if (pgd_none(*pgd)) {
			pud_t *new;

1803 1804
			new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
						  PAGE_SIZE);
1805 1806
			if (!new)
				goto err_alloc;
1807 1808 1809
			alloc_bytes += PAGE_SIZE;
			pgd_populate(&init_mm, pgd, new);
		}
1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823

		p4d = p4d_offset(pgd, vstart);
		if (p4d_none(*p4d)) {
			pud_t *new;

			new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
						  PAGE_SIZE);
			if (!new)
				goto err_alloc;
			alloc_bytes += PAGE_SIZE;
			p4d_populate(&init_mm, p4d, new);
		}

		pud = pud_offset(p4d, vstart);
1824 1825 1826
		if (pud_none(*pud)) {
			pmd_t *new;

1827 1828 1829 1830
			if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
				vstart = kernel_map_hugepud(vstart, vend, pud);
				continue;
			}
1831 1832
			new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
						  PAGE_SIZE);
1833 1834
			if (!new)
				goto err_alloc;
1835 1836 1837 1838 1839
			alloc_bytes += PAGE_SIZE;
			pud_populate(&init_mm, pud, new);
		}

		pmd = pmd_offset(pud, vstart);
1840
		if (pmd_none(*pmd)) {
1841 1842
			pte_t *new;

1843 1844 1845 1846
			if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
				vstart = kernel_map_hugepmd(vstart, vend, pmd);
				continue;
			}
1847 1848
			new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
						  PAGE_SIZE);
1849 1850
			if (!new)
				goto err_alloc;
1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869
			alloc_bytes += PAGE_SIZE;
			pmd_populate_kernel(&init_mm, pmd, new);
		}

		pte = pte_offset_kernel(pmd, vstart);
		this_end = (vstart + PMD_SIZE) & PMD_MASK;
		if (this_end > vend)
			this_end = vend;

		while (vstart < this_end) {
			pte_val(*pte) = (paddr | pgprot_val(prot));

			vstart += PAGE_SIZE;
			paddr += PAGE_SIZE;
			pte++;
		}
	}

	return alloc_bytes;
1870 1871 1872 1873 1874

err_alloc:
	panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n",
	      __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
	return -ENOMEM;
1875 1876
}

1877
static void __init flush_all_kernel_tsbs(void)
1878
{
1879
	int i;
1880

1881 1882
	for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
		struct tsb *ent = &swapper_tsb[i];
1883

1884
		ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1885
	}
1886 1887 1888
#ifndef CONFIG_DEBUG_PAGEALLOC
	for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
		struct tsb *ent = &swapper_4m_tsb[i];
1889

1890
		ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1891
	}
1892
#endif
1893
}
1894

1895
extern unsigned int kvmap_linear_patch[1];
1896

1897 1898 1899
static void __init kernel_physical_mapping_init(void)
{
	unsigned long i, mem_alloced = 0UL;
1900
	bool use_huge = true;
1901

1902 1903 1904
#ifdef CONFIG_DEBUG_PAGEALLOC
	use_huge = false;
#endif
1905 1906 1907 1908 1909 1910
	for (i = 0; i < pall_ents; i++) {
		unsigned long phys_start, phys_end;

		phys_start = pall[i].phys_addr;
		phys_end = phys_start + pall[i].reg_size;

1911
		mem_alloced += kernel_map_range(phys_start, phys_end,
1912
						PAGE_KERNEL, use_huge);
1913 1914 1915 1916 1917 1918 1919 1920
	}

	printk("Allocated %ld bytes for kernel page tables.\n",
	       mem_alloced);

	kvmap_linear_patch[0] = 0x01000000; /* nop */
	flushi(&kvmap_linear_patch[0]);

1921 1922
	flush_all_kernel_tsbs();

1923 1924 1925
	__flush_tlb_all();
}

1926
#ifdef CONFIG_DEBUG_PAGEALLOC
1927
void __kernel_map_pages(struct page *page, int numpages, int enable)
1928 1929 1930 1931 1932
{
	unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
	unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);

	kernel_map_range(phys_start, phys_end,
1933
			 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1934

1935 1936 1937
	flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
			       PAGE_OFFSET + phys_end);

1938 1939 1940 1941 1942 1943 1944 1945
	/* we should perform an IPI and flush all tlbs,
	 * but that can deadlock->flush only current cpu.
	 */
	__flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
				 PAGE_OFFSET + phys_end);
}
#endif

1946 1947
unsigned long __init find_ecache_flush_span(unsigned long size)
{
1948 1949
	int i;

1950 1951 1952
	for (i = 0; i < pavail_ents; i++) {
		if (pavail[i].reg_size >= size)
			return pavail[i].phys_addr;
1953 1954
	}

1955
	return ~0UL;
1956 1957
}

1958 1959 1960
unsigned long PAGE_OFFSET;
EXPORT_SYMBOL(PAGE_OFFSET);

1961 1962 1963
unsigned long VMALLOC_END   = 0x0000010000000000UL;
EXPORT_SYMBOL(VMALLOC_END);

1964 1965 1966
unsigned long sparc64_va_hole_top =    0xfffff80000000000UL;
unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;

1967 1968 1969
static void __init setup_page_offset(void)
{
	if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1970 1971 1972 1973 1974 1975 1976
		/* Cheetah/Panther support a full 64-bit virtual
		 * address, so we can use all that our page tables
		 * support.
		 */
		sparc64_va_hole_top =    0xfff0000000000000UL;
		sparc64_va_hole_bottom = 0x0010000000000000UL;

1977 1978 1979 1980 1981
		max_phys_bits = 42;
	} else if (tlb_type == hypervisor) {
		switch (sun4v_chip_type) {
		case SUN4V_CHIP_NIAGARA1:
		case SUN4V_CHIP_NIAGARA2:
1982 1983 1984 1985
			/* T1 and T2 support 48-bit virtual addresses.  */
			sparc64_va_hole_top =    0xffff800000000000UL;
			sparc64_va_hole_bottom = 0x0000800000000000UL;

1986 1987 1988
			max_phys_bits = 39;
			break;
		case SUN4V_CHIP_NIAGARA3:
1989 1990 1991 1992
			/* T3 supports 48-bit virtual addresses.  */
			sparc64_va_hole_top =    0xffff800000000000UL;
			sparc64_va_hole_bottom = 0x0000800000000000UL;

1993 1994 1995 1996 1997
			max_phys_bits = 43;
			break;
		case SUN4V_CHIP_NIAGARA4:
		case SUN4V_CHIP_NIAGARA5:
		case SUN4V_CHIP_SPARC64X:
1998
		case SUN4V_CHIP_SPARC_M6:
1999 2000 2001
			/* T4 and later support 52-bit virtual addresses.  */
			sparc64_va_hole_top =    0xfff8000000000000UL;
			sparc64_va_hole_bottom = 0x0008000000000000UL;
2002 2003
			max_phys_bits = 47;
			break;
2004
		case SUN4V_CHIP_SPARC_M7:
2005
		case SUN4V_CHIP_SPARC_SN:
2006 2007 2008 2009 2010
			/* M7 and later support 52-bit virtual addresses.  */
			sparc64_va_hole_top =    0xfff8000000000000UL;
			sparc64_va_hole_bottom = 0x0008000000000000UL;
			max_phys_bits = 49;
			break;
2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021
		case SUN4V_CHIP_SPARC_M8:
		default:
			/* M8 and later support 54-bit virtual addresses.
			 * However, restricting M8 and above VA bits to 53
			 * as 4-level page table cannot support more than
			 * 53 VA bits.
			 */
			sparc64_va_hole_top =    0xfff0000000000000UL;
			sparc64_va_hole_bottom = 0x0010000000000000UL;
			max_phys_bits = 51;
			break;
2022 2023 2024 2025 2026 2027 2028 2029 2030
		}
	}

	if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
		prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
			    max_phys_bits);
		prom_halt();
	}

2031 2032 2033
	PAGE_OFFSET = sparc64_va_hole_top;
	VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
		       (sparc64_va_hole_bottom >> 2));
2034

2035
	pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2036
		PAGE_OFFSET, max_phys_bits);
2037 2038 2039 2040
	pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
		VMALLOC_START, VMALLOC_END);
	pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
		VMEMMAP_BASE, VMEMMAP_BASE << 1);
2041 2042
}

2043 2044
static void __init tsb_phys_patch(void)
{
2045
	struct tsb_ldquad_phys_patch_entry *pquad;
2046 2047
	struct tsb_phys_patch_entry *p;

2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063
	pquad = &__tsb_ldquad_phys_patch;
	while (pquad < &__tsb_ldquad_phys_patch_end) {
		unsigned long addr = pquad->addr;

		if (tlb_type == hypervisor)
			*(unsigned int *) addr = pquad->sun4v_insn;
		else
			*(unsigned int *) addr = pquad->sun4u_insn;
		wmb();
		__asm__ __volatile__("flush	%0"
				     : /* no outputs */
				     : "r" (addr));

		pquad++;
	}

2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077
	p = &__tsb_phys_patch;
	while (p < &__tsb_phys_patch_end) {
		unsigned long addr = p->addr;

		*(unsigned int *) addr = p->insn;
		wmb();
		__asm__ __volatile__("flush	%0"
				     : /* no outputs */
				     : "r" (addr));

		p++;
	}
}

2078
/* Don't mark as init, we give this to the Hypervisor.  */
2079 2080 2081 2082 2083 2084
#ifndef CONFIG_DEBUG_PAGEALLOC
#define NUM_KTSB_DESCR	2
#else
#define NUM_KTSB_DESCR	1
#endif
static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2085

2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098
/* The swapper TSBs are loaded with a base sequence of:
 *
 *	sethi	%uhi(SYMBOL), REG1
 *	sethi	%hi(SYMBOL), REG2
 *	or	REG1, %ulo(SYMBOL), REG1
 *	or	REG2, %lo(SYMBOL), REG2
 *	sllx	REG1, 32, REG1
 *	or	REG1, REG2, REG1
 *
 * When we use physical addressing for the TSB accesses, we patch the
 * first four instructions in the above sequence.
 */

2099 2100
static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
{
2101 2102 2103 2104
	unsigned long high_bits, low_bits;

	high_bits = (pa >> 32) & 0xffffffff;
	low_bits = (pa >> 0) & 0xffffffff;
2105 2106 2107 2108

	while (start < end) {
		unsigned int *ia = (unsigned int *)(unsigned long)*start;

2109
		ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2110 2111
		__asm__ __volatile__("flush	%0" : : "r" (ia));

2112
		ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2113 2114
		__asm__ __volatile__("flush	%0" : : "r" (ia + 1));

2115 2116 2117 2118 2119 2120
		ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
		__asm__ __volatile__("flush	%0" : : "r" (ia + 2));

		ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
		__asm__ __volatile__("flush	%0" : : "r" (ia + 3));

2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134
		start++;
	}
}

static void ktsb_phys_patch(void)
{
	extern unsigned int __swapper_tsb_phys_patch;
	extern unsigned int __swapper_tsb_phys_patch_end;
	unsigned long ktsb_pa;

	ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
	patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
			    &__swapper_tsb_phys_patch_end, ktsb_pa);
#ifndef CONFIG_DEBUG_PAGEALLOC
2135 2136 2137
	{
	extern unsigned int __swapper_4m_tsb_phys_patch;
	extern unsigned int __swapper_4m_tsb_phys_patch_end;
2138 2139 2140 2141
	ktsb_pa = (kern_base +
		   ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
	patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
			    &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2142
	}
2143 2144 2145
#endif
}

2146 2147 2148 2149
static void __init sun4v_ktsb_init(void)
{
	unsigned long ktsb_pa;

2150
	/* First KTSB for PAGE_SIZE mappings.  */
2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173
	ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);

	switch (PAGE_SIZE) {
	case 8 * 1024:
	default:
		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
		break;

	case 64 * 1024:
		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
		break;

	case 512 * 1024:
		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
		break;

	case 4 * 1024 * 1024:
		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
		break;
2174
	}
2175

2176
	ktsb_descr[0].assoc = 1;
2177 2178 2179 2180 2181
	ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
	ktsb_descr[0].ctx_idx = 0;
	ktsb_descr[0].tsb_base = ktsb_pa;
	ktsb_descr[0].resv = 0;

2182
#ifndef CONFIG_DEBUG_PAGEALLOC
2183
	/* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
2184 2185 2186 2187
	ktsb_pa = (kern_base +
		   ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));

	ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2188 2189 2190 2191 2192
	ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
				    HV_PGSZ_MASK_256MB |
				    HV_PGSZ_MASK_2GB |
				    HV_PGSZ_MASK_16GB) &
				   cpu_pgsz_mask);
2193 2194 2195 2196 2197
	ktsb_descr[1].assoc = 1;
	ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
	ktsb_descr[1].ctx_idx = 0;
	ktsb_descr[1].tsb_base = ktsb_pa;
	ktsb_descr[1].resv = 0;
2198
#endif
2199 2200
}

2201
void sun4v_ktsb_register(void)
2202
{
2203
	unsigned long pa, ret;
2204 2205 2206

	pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);

2207 2208 2209 2210 2211 2212
	ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
	if (ret != 0) {
		prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
			    "errors with %lx\n", pa, ret);
		prom_halt();
	}
2213 2214
}

2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225
static void __init sun4u_linear_pte_xor_finalize(void)
{
#ifndef CONFIG_DEBUG_PAGEALLOC
	/* This is where we would add Panther support for
	 * 32MB and 256MB pages.
	 */
#endif
}

static void __init sun4v_linear_pte_xor_finalize(void)
{
2226 2227 2228 2229 2230 2231 2232
	unsigned long pagecv_flag;

	/* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
	 * enables MCD error. Do not set bit 9 on M7 processor.
	 */
	switch (sun4v_chip_type) {
	case SUN4V_CHIP_SPARC_M7:
2233
	case SUN4V_CHIP_SPARC_M8:
2234
	case SUN4V_CHIP_SPARC_SN:
2235 2236 2237 2238 2239 2240
		pagecv_flag = 0x00;
		break;
	default:
		pagecv_flag = _PAGE_CV_4V;
		break;
	}
2241 2242 2243
#ifndef CONFIG_DEBUG_PAGEALLOC
	if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
		kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2244
			PAGE_OFFSET;
2245
		kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2246 2247 2248 2249 2250 2251 2252
					   _PAGE_P_4V | _PAGE_W_4V);
	} else {
		kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
	}

	if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
		kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2253
			PAGE_OFFSET;
2254
		kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2255 2256 2257 2258 2259 2260 2261
					   _PAGE_P_4V | _PAGE_W_4V);
	} else {
		kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
	}

	if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
		kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2262
			PAGE_OFFSET;
2263
		kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2264 2265 2266 2267 2268 2269 2270
					   _PAGE_P_4V | _PAGE_W_4V);
	} else {
		kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
	}
#endif
}

L
Linus Torvalds 已提交
2271 2272 2273
/* paging_init() sets up the page tables */

static unsigned long last_valid_pfn;
2274

2275 2276 2277
static void sun4u_pgprot_init(void);
static void sun4v_pgprot_init(void);

2278 2279 2280 2281 2282 2283 2284
#define _PAGE_CACHE_4U	(_PAGE_CP_4U | _PAGE_CV_4U)
#define _PAGE_CACHE_4V	(_PAGE_CP_4V | _PAGE_CV_4V)
#define __DIRTY_BITS_4U	 (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
#define __DIRTY_BITS_4V	 (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)

B
bob picco 已提交
2285 2286 2287 2288 2289 2290
/* We need to exclude reserved regions. This exclusion will include
 * vmlinux and initrd. To be more precise the initrd size could be used to
 * compute a new lower limit because it is freed later during initialization.
 */
static void __init reduce_memory(phys_addr_t limit_ram)
{
2291 2292
	limit_ram += memblock_reserved_size();
	memblock_enforce_memory_limit(limit_ram);
B
bob picco 已提交
2293 2294
}

L
Linus Torvalds 已提交
2295 2296
void __init paging_init(void)
{
D
David S. Miller 已提交
2297
	unsigned long end_pfn, shift, phys_base;
2298 2299
	unsigned long real_end, i;

2300 2301
	setup_page_offset();

2302 2303 2304 2305 2306 2307 2308 2309
	/* These build time checkes make sure that the dcache_dirty_cpu()
	 * page->flags usage will work.
	 *
	 * When a page gets marked as dcache-dirty, we store the
	 * cpu number starting at bit 32 in the page->flags.  Also,
	 * functions like clear_dcache_dirty_cpu use the cpu mask
	 * in 13-bit signed-immediate instruction fields.
	 */
2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321

	/*
	 * Page flags must not reach into upper 32 bits that are used
	 * for the cpu number
	 */
	BUILD_BUG_ON(NR_PAGEFLAGS > 32);

	/*
	 * The bit fields placed in the high range must not reach below
	 * the 32 bit boundary. Otherwise we cannot place the cpu field
	 * at the 32 bit boundary.
	 */
2322
	BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2323 2324
		ilog2(roundup_pow_of_two(NR_CPUS)) > 32);

2325 2326
	BUILD_BUG_ON(NR_CPUS > 4096);

2327
	kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2328 2329
	kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;

2330
	/* Invalidate both kernel TSBs.  */
2331
	memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2332
#ifndef CONFIG_DEBUG_PAGEALLOC
2333
	memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2334
#endif
2335

2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347
	/* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
	 * bit on M7 processor. This is a conflicting usage of the same
	 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
	 * Detection error on all pages and this will lead to problems
	 * later. Kernel does not run with MCD enabled and hence rest
	 * of the required steps to fully configure memory corruption
	 * detection are not taken. We need to ensure TTE.mcde is not
	 * set on M7 processor. Compute the value of cacheability
	 * flag for use later taking this into consideration.
	 */
	switch (sun4v_chip_type) {
	case SUN4V_CHIP_SPARC_M7:
2348
	case SUN4V_CHIP_SPARC_M8:
2349
	case SUN4V_CHIP_SPARC_SN:
2350 2351 2352 2353 2354 2355 2356
		page_cache4v_flag = _PAGE_CP_4V;
		break;
	default:
		page_cache4v_flag = _PAGE_CACHE_4V;
		break;
	}

2357 2358 2359 2360 2361
	if (tlb_type == hypervisor)
		sun4v_pgprot_init();
	else
		sun4u_pgprot_init();

2362
	if (tlb_type == cheetah_plus ||
2363
	    tlb_type == hypervisor) {
2364
		tsb_phys_patch();
2365 2366
		ktsb_phys_patch();
	}
2367

2368
	if (tlb_type == hypervisor)
2369 2370
		sun4v_patch_tlb_handlers();

2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381
	/* Find available physical memory...
	 *
	 * Read it twice in order to work around a bug in openfirmware.
	 * The call to grab this table itself can cause openfirmware to
	 * allocate memory, which in turn can take away some space from
	 * the list of available memory.  Reading it twice makes sure
	 * we really do get the final value.
	 */
	read_obp_translations();
	read_obp_memory("reg", &pall[0], &pall_ents);
	read_obp_memory("available", &pavail[0], &pavail_ents);
2382
	read_obp_memory("available", &pavail[0], &pavail_ents);
2383 2384

	phys_base = 0xffffffffffffffffUL;
2385
	for (i = 0; i < pavail_ents; i++) {
2386
		phys_base = min(phys_base, pavail[i].phys_addr);
Y
Yinghai Lu 已提交
2387
		memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2388 2389
	}

Y
Yinghai Lu 已提交
2390
	memblock_reserve(kern_base, kern_size);
2391

2392 2393
	find_ramdisk(phys_base);

B
bob picco 已提交
2394 2395
	if (cmdline_memory_size)
		reduce_memory(cmdline_memory_size);
2396

2397
	memblock_allow_resize();
Y
Yinghai Lu 已提交
2398
	memblock_dump_all();
2399

L
Linus Torvalds 已提交
2400 2401
	set_bit(0, mmu_context_bmap);

2402 2403
	shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);

L
Linus Torvalds 已提交
2404
	real_end = (unsigned long)_end;
2405
	num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2406 2407
	printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
	       num_kernel_image_mappings);
2408 2409

	/* Set kernel pgd to upper alias so physical page computations
L
Linus Torvalds 已提交
2410 2411 2412 2413
	 * work.
	 */
	init_mm.pgd += ((shift) / (sizeof(pgd_t)));
	
2414
	memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2415

2416
	inherit_prom_mappings();
2417
	
2418 2419
	/* Ok, we can use our TLB miss and window trap handlers safely.  */
	setup_tba();
L
Linus Torvalds 已提交
2420

2421
	__flush_tlb_all();
2422

2423
	prom_build_devicetree();
2424
	of_populate_present_mask();
2425 2426 2427
#ifndef CONFIG_SMP
	of_fill_in_cpu_data();
#endif
2428

2429
	if (tlb_type == hypervisor) {
2430
		sun4v_mdesc_init();
2431
		mdesc_populate_present_mask(cpu_all_mask);
2432 2433 2434
#ifndef CONFIG_SMP
		mdesc_fill_in_cpu_data(cpu_all_mask);
#endif
2435
		mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2436 2437 2438 2439 2440

		sun4v_linear_pte_xor_finalize();

		sun4v_ktsb_init();
		sun4v_ktsb_register();
2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451
	} else {
		unsigned long impl, ver;

		cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
				 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);

		__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
		impl = ((ver >> 32) & 0xffff);
		if (impl == PANTHER_IMPL)
			cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
					  HV_PGSZ_MASK_256MB);
2452 2453

		sun4u_linear_pte_xor_finalize();
2454
	}
2455

2456 2457 2458 2459 2460 2461 2462 2463 2464
	/* Flush the TLBs and the 4M TSB so that the updated linear
	 * pte XOR settings are realized for all mappings.
	 */
	__flush_tlb_all();
#ifndef CONFIG_DEBUG_PAGEALLOC
	memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
#endif
	__flush_tlb_all();

2465 2466 2467
	/* Setup bootmem... */
	last_valid_pfn = end_pfn = bootmem_init(phys_base);

2468 2469
	kernel_physical_mapping_init();

L
Linus Torvalds 已提交
2470
	{
D
David S. Miller 已提交
2471
		unsigned long max_zone_pfns[MAX_NR_ZONES];
L
Linus Torvalds 已提交
2472

D
David S. Miller 已提交
2473
		memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
L
Linus Torvalds 已提交
2474

D
David S. Miller 已提交
2475
		max_zone_pfns[ZONE_NORMAL] = end_pfn;
L
Linus Torvalds 已提交
2476

2477
		free_area_init(max_zone_pfns);
L
Linus Torvalds 已提交
2478 2479
	}

2480
	printk("Booting Linux...\n");
L
Linus Torvalds 已提交
2481 2482
}

2483
int page_in_phys_avail(unsigned long paddr)
D
David S. Miller 已提交
2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508
{
	int i;

	paddr &= PAGE_MASK;

	for (i = 0; i < pavail_ents; i++) {
		unsigned long start, end;

		start = pavail[i].phys_addr;
		end = start + pavail[i].reg_size;

		if (paddr >= start && paddr < end)
			return 1;
	}
	if (paddr >= kern_base && paddr < (kern_base + kern_size))
		return 1;
#ifdef CONFIG_BLK_DEV_INITRD
	if (paddr >= __pa(initrd_start) &&
	    paddr < __pa(PAGE_ALIGN(initrd_end)))
		return 1;
#endif

	return 0;
}

2509 2510 2511 2512 2513 2514 2515 2516 2517 2518
static void __init register_page_bootmem_info(void)
{
#ifdef CONFIG_NEED_MULTIPLE_NODES
	int i;

	for_each_online_node(i)
		if (NODE_DATA(i)->node_spanned_pages)
			register_page_bootmem_info_node(NODE_DATA(i));
#endif
}
L
Linus Torvalds 已提交
2519 2520 2521 2522
void __init mem_init(void)
{
	high_memory = __va(last_valid_pfn << PAGE_SHIFT);

2523
	memblock_free_all();
D
David S. Miller 已提交
2524

2525 2526 2527
	/*
	 * Must be done after boot memory is put on freelist, because here we
	 * might set fields in deferred struct pages that have not yet been
2528
	 * initialized, and memblock_free_all() initializes all the reserved
2529 2530 2531 2532
	 * deferred pages for us.
	 */
	register_page_bootmem_info();

L
Linus Torvalds 已提交
2533 2534 2535 2536 2537 2538 2539 2540 2541
	/*
	 * Set up the zero page, mark it reserved, so that page count
	 * is not manipulated when freeing the page from user ptes.
	 */
	mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
	if (mem_map_zero == NULL) {
		prom_printf("paging_init: Cannot alloc zero page.\n");
		prom_halt();
	}
2542
	mark_page_reserved(mem_map_zero);
L
Linus Torvalds 已提交
2543

2544
	mem_init_print_info(NULL);
L
Linus Torvalds 已提交
2545 2546 2547 2548 2549

	if (tlb_type == cheetah || tlb_type == cheetah_plus)
		cheetah_ecache_flush_init();
}

2550
void free_initmem(void)
L
Linus Torvalds 已提交
2551 2552
{
	unsigned long addr, initend;
2553 2554 2555 2556 2557 2558 2559 2560 2561
	int do_free = 1;

	/* If the physical memory maps were trimmed by kernel command
	 * line options, don't even try freeing this initmem stuff up.
	 * The kernel image could have been in the trimmed out region
	 * and if so the freeing below will free invalid page structs.
	 */
	if (cmdline_memory_size)
		do_free = 0;
L
Linus Torvalds 已提交
2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573

	/*
	 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
	 */
	addr = PAGE_ALIGN((unsigned long)(__init_begin));
	initend = (unsigned long)(__init_end) & PAGE_MASK;
	for (; addr < initend; addr += PAGE_SIZE) {
		unsigned long page;

		page = (addr +
			((unsigned long) __va(kern_base)) -
			((unsigned long) KERNBASE));
2574
		memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
L
Linus Torvalds 已提交
2575

2576 2577
		if (do_free)
			free_reserved_page(virt_to_page(page));
L
Linus Torvalds 已提交
2578 2579 2580
	}
}

2581 2582 2583 2584 2585
pgprot_t PAGE_KERNEL __read_mostly;
EXPORT_SYMBOL(PAGE_KERNEL);

pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
pgprot_t PAGE_COPY __read_mostly;
2586 2587 2588 2589

pgprot_t PAGE_SHARED __read_mostly;
EXPORT_SYMBOL(PAGE_SHARED);

2590 2591 2592
unsigned long pg_iobits __read_mostly;

unsigned long _PAGE_IE __read_mostly;
2593
EXPORT_SYMBOL(_PAGE_IE);
2594

2595
unsigned long _PAGE_E __read_mostly;
2596 2597
EXPORT_SYMBOL(_PAGE_E);

2598
unsigned long _PAGE_CACHE __read_mostly;
2599
EXPORT_SYMBOL(_PAGE_CACHE);
2600

D
David Miller 已提交
2601
#ifdef CONFIG_SPARSEMEM_VMEMMAP
2602
int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2603
			       int node, struct vmem_altmap *altmap)
D
David Miller 已提交
2604 2605 2606 2607 2608 2609 2610 2611
{
	unsigned long pte_base;

	pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
		    _PAGE_CP_4U | _PAGE_CV_4U |
		    _PAGE_P_4U | _PAGE_W_4U);
	if (tlb_type == hypervisor)
		pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2612
			    page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
D
David Miller 已提交
2613

2614
	pte_base |= _PAGE_PMD_HUGE;
D
David Miller 已提交
2615

2616 2617 2618
	vstart = vstart & PMD_MASK;
	vend = ALIGN(vend, PMD_SIZE);
	for (; vstart < vend; vstart += PMD_SIZE) {
2619
		pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
2620
		unsigned long pte;
2621
		p4d_t *p4d;
2622 2623 2624
		pud_t *pud;
		pmd_t *pmd;

2625 2626
		if (!pgd)
			return -ENOMEM;
2627

2628 2629 2630 2631 2632
		p4d = vmemmap_p4d_populate(pgd, vstart, node);
		if (!p4d)
			return -ENOMEM;

		pud = vmemmap_pud_populate(p4d, vstart, node);
2633 2634
		if (!pud)
			return -ENOMEM;
2635

2636 2637 2638 2639 2640 2641 2642 2643 2644 2645
		pmd = pmd_offset(pud, vstart);
		pte = pmd_val(*pmd);
		if (!(pte & _PAGE_VALID)) {
			void *block = vmemmap_alloc_block(PMD_SIZE, node);

			if (!block)
				return -ENOMEM;

			pmd_val(*pmd) = pte_base | __pa(block);
		}
2646
	}
2647 2648

	return 0;
2649
}
2650

2651 2652
void vmemmap_free(unsigned long start, unsigned long end,
		struct vmem_altmap *altmap)
2653 2654
{
}
D
David Miller 已提交
2655 2656
#endif /* CONFIG_SPARSEMEM_VMEMMAP */

2657 2658 2659 2660 2661 2662 2663
static void prot_init_common(unsigned long page_none,
			     unsigned long page_shared,
			     unsigned long page_copy,
			     unsigned long page_readonly,
			     unsigned long page_exec_bit)
{
	PAGE_COPY = __pgprot(page_copy);
2664
	PAGE_SHARED = __pgprot(page_shared);
2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687

	protection_map[0x0] = __pgprot(page_none);
	protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
	protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
	protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
	protection_map[0x4] = __pgprot(page_readonly);
	protection_map[0x5] = __pgprot(page_readonly);
	protection_map[0x6] = __pgprot(page_copy);
	protection_map[0x7] = __pgprot(page_copy);
	protection_map[0x8] = __pgprot(page_none);
	protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
	protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
	protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
	protection_map[0xc] = __pgprot(page_readonly);
	protection_map[0xd] = __pgprot(page_readonly);
	protection_map[0xe] = __pgprot(page_shared);
	protection_map[0xf] = __pgprot(page_shared);
}

static void __init sun4u_pgprot_init(void)
{
	unsigned long page_none, page_shared, page_copy, page_readonly;
	unsigned long page_exec_bit;
2688
	int i;
2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705

	PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
				_PAGE_CACHE_4U | _PAGE_P_4U |
				__ACCESS_BITS_4U | __DIRTY_BITS_4U |
				_PAGE_EXEC_4U);
	PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
				       _PAGE_CACHE_4U | _PAGE_P_4U |
				       __ACCESS_BITS_4U | __DIRTY_BITS_4U |
				       _PAGE_EXEC_4U | _PAGE_L_4U);

	_PAGE_IE = _PAGE_IE_4U;
	_PAGE_E = _PAGE_E_4U;
	_PAGE_CACHE = _PAGE_CACHE_4U;

	pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
		     __ACCESS_BITS_4U | _PAGE_E_4U);

2706
#ifdef CONFIG_DEBUG_PAGEALLOC
2707
	kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2708
#else
2709
	kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2710
		PAGE_OFFSET;
2711
#endif
2712 2713 2714
	kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
				   _PAGE_P_4U | _PAGE_W_4U);

2715 2716
	for (i = 1; i < 4; i++)
		kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740

	_PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
			      _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
			      _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);


	page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
	page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
		       __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
	page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
		       __ACCESS_BITS_4U | _PAGE_EXEC_4U);
	page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
			   __ACCESS_BITS_4U | _PAGE_EXEC_4U);

	page_exec_bit = _PAGE_EXEC_4U;

	prot_init_common(page_none, page_shared, page_copy, page_readonly,
			 page_exec_bit);
}

static void __init sun4v_pgprot_init(void)
{
	unsigned long page_none, page_shared, page_copy, page_readonly;
	unsigned long page_exec_bit;
2741
	int i;
2742 2743

	PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2744
				page_cache4v_flag | _PAGE_P_4V |
2745 2746 2747 2748 2749 2750
				__ACCESS_BITS_4V | __DIRTY_BITS_4V |
				_PAGE_EXEC_4V);
	PAGE_KERNEL_LOCKED = PAGE_KERNEL;

	_PAGE_IE = _PAGE_IE_4V;
	_PAGE_E = _PAGE_E_4V;
2751
	_PAGE_CACHE = page_cache4v_flag;
2752

2753
#ifdef CONFIG_DEBUG_PAGEALLOC
2754
	kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2755
#else
2756
	kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2757
		PAGE_OFFSET;
2758
#endif
2759 2760
	kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
				   _PAGE_W_4V);
2761

2762 2763
	for (i = 1; i < 4; i++)
		kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2764

2765 2766 2767 2768 2769 2770 2771 2772
	pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
		     __ACCESS_BITS_4V | _PAGE_E_4V);

	_PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
			     _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
			     _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
			     _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);

2773 2774
	page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
	page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2775
		       __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2776
	page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2777
		       __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2778
	page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799
			 __ACCESS_BITS_4V | _PAGE_EXEC_4V);

	page_exec_bit = _PAGE_EXEC_4V;

	prot_init_common(page_none, page_shared, page_copy, page_readonly,
			 page_exec_bit);
}

unsigned long pte_sz_bits(unsigned long sz)
{
	if (tlb_type == hypervisor) {
		switch (sz) {
		case 8 * 1024:
		default:
			return _PAGE_SZ8K_4V;
		case 64 * 1024:
			return _PAGE_SZ64K_4V;
		case 512 * 1024:
			return _PAGE_SZ512K_4V;
		case 4 * 1024 * 1024:
			return _PAGE_SZ4MB_4V;
2800
		}
2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811
	} else {
		switch (sz) {
		case 8 * 1024:
		default:
			return _PAGE_SZ8K_4U;
		case 64 * 1024:
			return _PAGE_SZ64K_4U;
		case 512 * 1024:
			return _PAGE_SZ512K_4U;
		case 4 * 1024 * 1024:
			return _PAGE_SZ4MB_4U;
2812
		}
2813 2814 2815 2816 2817 2818
	}
}

pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
{
	pte_t pte;
2819 2820

	pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2821 2822 2823
	pte_val(pte) |= (((unsigned long)space) << 32);
	pte_val(pte) |= pte_sz_bits(page_size);

2824
	return pte;
2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835
}

static unsigned long kern_large_tte(unsigned long paddr)
{
	unsigned long val;

	val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
	       _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
	       _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
	if (tlb_type == hypervisor)
		val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2836
		       page_cache4v_flag | _PAGE_P_4V |
2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852
		       _PAGE_EXEC_4V | _PAGE_W_4V);

	return val | paddr;
}

/* If not locked, zap it. */
void __flush_tlb_all(void)
{
	unsigned long pstate;
	int i;

	__asm__ __volatile__("flushw\n\t"
			     "rdpr	%%pstate, %0\n\t"
			     "wrpr	%0, %1, %%pstate"
			     : "=r" (pstate)
			     : "i" (PSTATE_IE));
2853 2854 2855
	if (tlb_type == hypervisor) {
		sun4v_mmu_demap_all();
	} else if (tlb_type == spitfire) {
2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899
		for (i = 0; i < 64; i++) {
			/* Spitfire Errata #32 workaround */
			/* NOTE: Always runs on spitfire, so no
			 *       cheetah+ page size encodings.
			 */
			__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
					     "flush	%%g6"
					     : /* No outputs */
					     : "r" (0),
					     "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));

			if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
				__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
						     "membar #Sync"
						     : /* no outputs */
						     : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
				spitfire_put_dtlb_data(i, 0x0UL);
			}

			/* Spitfire Errata #32 workaround */
			/* NOTE: Always runs on spitfire, so no
			 *       cheetah+ page size encodings.
			 */
			__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
					     "flush	%%g6"
					     : /* No outputs */
					     : "r" (0),
					     "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));

			if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
				__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
						     "membar #Sync"
						     : /* no outputs */
						     : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
				spitfire_put_itlb_data(i, 0x0UL);
			}
		}
	} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
		cheetah_flush_dtlb_all();
		cheetah_flush_itlb_all();
	}
	__asm__ __volatile__("wrpr	%0, 0, %%pstate"
			     : : "r" (pstate));
}
2900

2901
pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
2902
{
2903
	struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2904
	pte_t *pte = NULL;
2905 2906 2907 2908 2909 2910 2911

	if (page)
		pte = (pte_t *) page_address(page);

	return pte;
}

2912
pgtable_t pte_alloc_one(struct mm_struct *mm)
2913
{
2914
	struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2915 2916
	if (!page)
		return NULL;
2917
	if (!pgtable_pte_page_ctor(page)) {
2918
		free_unref_page(page);
2919
		return NULL;
2920
	}
2921
	return (pte_t *) page_address(page);
2922 2923 2924 2925
}

void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
{
2926
	free_page((unsigned long)pte);
2927 2928 2929 2930 2931
}

static void __pte_free(pgtable_t pte)
{
	struct page *page = virt_to_page(pte);
2932

2933
	pgtable_pte_page_dtor(page);
2934
	__free_page(page);
2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948
}

void pte_free(struct mm_struct *mm, pgtable_t pte)
{
	__pte_free(pte);
}

void pgtable_free(void *table, bool is_page)
{
	if (is_page)
		__pte_free(table);
	else
		kmem_cache_free(pgtable_cache, table);
}
2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960

#ifdef CONFIG_TRANSPARENT_HUGEPAGE
void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
			  pmd_t *pmd)
{
	unsigned long pte, flags;
	struct mm_struct *mm;
	pmd_t entry = *pmd;

	if (!pmd_large(entry) || !pmd_young(entry))
		return;

2961
	pte = pmd_val(entry);
2962

2963 2964 2965 2966
	/* Don't insert a non-valid PMD into the TSB, we'll deadlock.  */
	if (!(pte & _PAGE_VALID))
		return;

2967 2968
	/* We are fabricating 8MB pages using 4MB real hw pages.  */
	pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2969 2970 2971 2972 2973 2974

	mm = vma->vm_mm;

	spin_lock_irqsave(&mm->context.lock, flags);

	if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2975
		__update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990
					addr, pte);

	spin_unlock_irqrestore(&mm->context.lock, flags);
}
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */

#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
static void context_reload(void *__data)
{
	struct mm_struct *mm = __data;

	if (mm == current->mm)
		load_secondary_context(mm);
}

2991
void hugetlb_setup(struct pt_regs *regs)
2992
{
2993 2994
	struct mm_struct *mm = current->mm;
	struct tsb_config *tp;
2995

2996
	if (faulthandler_disabled() || !mm) {
2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011
		const struct exception_table_entry *entry;

		entry = search_exception_tables(regs->tpc);
		if (entry) {
			regs->tpc = entry->fixup;
			regs->tnpc = regs->tpc + 4;
			return;
		}
		pr_alert("Unexpected HugeTLB setup in atomic context.\n");
		die_if_kernel("HugeTSB in atomic", regs);
	}

	tp = &mm->context.tsb_block[MM_TSB_HUGE];
	if (likely(tp->tsb == NULL))
		tsb_grow(mm, MM_TSB_HUGE, 0);
3012 3013 3014 3015 3016 3017 3018 3019

	tsb_context_switch(mm);
	smp_tsb_sync(mm);

	/* On UltraSPARC-III+ and later, configure the second half of
	 * the Data-TLB for huge pages.
	 */
	if (tlb_type == cheetah_plus) {
3020
		bool need_context_reload = false;
3021 3022
		unsigned long ctx;

3023
		spin_lock_irq(&ctx_alloc_lock);
3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041
		ctx = mm->context.sparc64_ctx_val;
		ctx &= ~CTX_PGSZ_MASK;
		ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
		ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;

		if (ctx != mm->context.sparc64_ctx_val) {
			/* When changing the page size fields, we
			 * must perform a context flush so that no
			 * stale entries match.  This flush must
			 * occur with the original context register
			 * settings.
			 */
			do_flush_tlb_mm(mm);

			/* Reload the context register of all processors
			 * also executing in this address space.
			 */
			mm->context.sparc64_ctx_val = ctx;
3042
			need_context_reload = true;
3043
		}
3044 3045 3046 3047
		spin_unlock_irq(&ctx_alloc_lock);

		if (need_context_reload)
			on_each_cpu(context_reload, mm, 0);
3048 3049 3050
	}
}
#endif
B
bob picco 已提交
3051 3052 3053

static struct resource code_resource = {
	.name	= "Kernel code",
3054
	.flags	= IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
B
bob picco 已提交
3055 3056 3057 3058
};

static struct resource data_resource = {
	.name	= "Kernel data",
3059
	.flags	= IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
B
bob picco 已提交
3060 3061 3062 3063
};

static struct resource bss_resource = {
	.name	= "Kernel bss",
3064
	.flags	= IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
B
bob picco 已提交
3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099
};

static inline resource_size_t compute_kern_paddr(void *addr)
{
	return (resource_size_t) (addr - KERNBASE + kern_base);
}

static void __init kernel_lds_init(void)
{
	code_resource.start = compute_kern_paddr(_text);
	code_resource.end   = compute_kern_paddr(_etext - 1);
	data_resource.start = compute_kern_paddr(_etext);
	data_resource.end   = compute_kern_paddr(_edata - 1);
	bss_resource.start  = compute_kern_paddr(__bss_start);
	bss_resource.end    = compute_kern_paddr(_end - 1);
}

static int __init report_memory(void)
{
	int i;
	struct resource *res;

	kernel_lds_init();

	for (i = 0; i < pavail_ents; i++) {
		res = kzalloc(sizeof(struct resource), GFP_KERNEL);

		if (!res) {
			pr_warn("Failed to allocate source.\n");
			break;
		}

		res->name = "System RAM";
		res->start = pavail[i].phys_addr;
		res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3100
		res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
B
bob picco 已提交
3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113

		if (insert_resource(&iomem_resource, res) < 0) {
			pr_warn("Resource insertion failed.\n");
			break;
		}

		insert_resource(res, &code_resource);
		insert_resource(res, &data_resource);
		insert_resource(res, &bss_resource);
	}

	return 0;
}
D
David S. Miller 已提交
3114
arch_initcall(report_memory);
3115

3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129
#ifdef CONFIG_SMP
#define do_flush_tlb_kernel_range	smp_flush_tlb_kernel_range
#else
#define do_flush_tlb_kernel_range	__flush_tlb_kernel_range
#endif

void flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
	if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
		if (start < LOW_OBP_ADDRESS) {
			flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
			do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
		}
		if (end > HI_OBP_ADDRESS) {
3130 3131
			flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
			do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3132 3133 3134 3135 3136 3137
		}
	} else {
		flush_tsb_kernel_range(start, end);
		do_flush_tlb_kernel_range(start, end);
	}
}
3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206

void copy_user_highpage(struct page *to, struct page *from,
	unsigned long vaddr, struct vm_area_struct *vma)
{
	char *vfrom, *vto;

	vfrom = kmap_atomic(from);
	vto = kmap_atomic(to);
	copy_user_page(vto, vfrom, vaddr, to);
	kunmap_atomic(vto);
	kunmap_atomic(vfrom);

	/* If this page has ADI enabled, copy over any ADI tags
	 * as well
	 */
	if (vma->vm_flags & VM_SPARC_ADI) {
		unsigned long pfrom, pto, i, adi_tag;

		pfrom = page_to_phys(from);
		pto = page_to_phys(to);

		for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
			asm volatile("ldxa [%1] %2, %0\n\t"
					: "=r" (adi_tag)
					:  "r" (i), "i" (ASI_MCD_REAL));
			asm volatile("stxa %0, [%1] %2\n\t"
					:
					: "r" (adi_tag), "r" (pto),
					  "i" (ASI_MCD_REAL));
			pto += adi_blksize();
		}
		asm volatile("membar #Sync\n\t");
	}
}
EXPORT_SYMBOL(copy_user_highpage);

void copy_highpage(struct page *to, struct page *from)
{
	char *vfrom, *vto;

	vfrom = kmap_atomic(from);
	vto = kmap_atomic(to);
	copy_page(vto, vfrom);
	kunmap_atomic(vto);
	kunmap_atomic(vfrom);

	/* If this platform is ADI enabled, copy any ADI tags
	 * as well
	 */
	if (adi_capable()) {
		unsigned long pfrom, pto, i, adi_tag;

		pfrom = page_to_phys(from);
		pto = page_to_phys(to);

		for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
			asm volatile("ldxa [%1] %2, %0\n\t"
					: "=r" (adi_tag)
					:  "r" (i), "i" (ASI_MCD_REAL));
			asm volatile("stxa %0, [%1] %2\n\t"
					:
					: "r" (adi_tag), "r" (pto),
					  "i" (ASI_MCD_REAL));
			pto += adi_blksize();
		}
		asm volatile("membar #Sync\n\t");
	}
}
EXPORT_SYMBOL(copy_highpage);