radeon.h 41.6 KB
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/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#ifndef __RADEON_H__
#define __RADEON_H__

/* TODO: Here are things that needs to be done :
 *	- surface allocator & initializer : (bit like scratch reg) should
 *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
 *	  related to surface
 *	- WB : write back stuff (do it bit like scratch reg things)
 *	- Vblank : look at Jesse's rework and what we should do
 *	- r600/r700: gart & cp
 *	- cs : clean cs ioctl use bitmap & things like that.
 *	- power management stuff
 *	- Barrier in gart code
 *	- Unmappabled vram ?
 *	- TESTING, TESTING, TESTING
 */

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/* Initialization path:
 *  We expect that acceleration initialization might fail for various
 *  reasons even thought we work hard to make it works on most
 *  configurations. In order to still have a working userspace in such
 *  situation the init path must succeed up to the memory controller
 *  initialization point. Failure before this point are considered as
 *  fatal error. Here is the init callchain :
 *      radeon_device_init  perform common structure, mutex initialization
 *      asic_init           setup the GPU memory layout and perform all
 *                          one time initialization (failure in this
 *                          function are considered fatal)
 *      asic_startup        setup the GPU acceleration, in order to
 *                          follow guideline the first thing this
 *                          function should do is setting the GPU
 *                          memory controller (only MC setup failure
 *                          are considered as fatal)
 */

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#include <asm/atomic.h>
#include <linux/wait.h>
#include <linux/list.h>
#include <linux/kref.h>

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#include <ttm/ttm_bo_api.h>
#include <ttm/ttm_bo_driver.h>
#include <ttm/ttm_placement.h>
#include <ttm/ttm_module.h>

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#include "radeon_family.h"
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#include "radeon_mode.h"
#include "radeon_reg.h"

/*
 * Modules parameters.
 */
extern int radeon_no_wb;
extern int radeon_modeset;
extern int radeon_dynclks;
extern int radeon_r4xx_atom;
extern int radeon_agpmode;
extern int radeon_vram_limit;
extern int radeon_gart_size;
extern int radeon_benchmarking;
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extern int radeon_testing;
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extern int radeon_connector_table;
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extern int radeon_tv;
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extern int radeon_new_pll;
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extern int radeon_dynpm;
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extern int radeon_audio;
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/*
 * Copy from radeon_drv.h so we don't have to include both and have conflicting
 * symbol;
 */
#define RADEON_MAX_USEC_TIMEOUT		100000	/* 100 ms */
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/* RADEON_IB_POOL_SIZE must be a power of 2 */
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#define RADEON_IB_POOL_SIZE		16
#define RADEON_DEBUGFS_MAX_NUM_FILES	32
#define RADEONFB_CONN_LIMIT		4
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#define RADEON_BIOS_NUM_SCRATCH		8
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/*
 * Errata workarounds.
 */
enum radeon_pll_errata {
	CHIP_ERRATA_R300_CG             = 0x00000001,
	CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
	CHIP_ERRATA_PLL_DELAY           = 0x00000004
};


struct radeon_device;


/*
 * BIOS.
 */
bool radeon_get_bios(struct radeon_device *rdev);

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/*
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 * Dummy page
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 */
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struct radeon_dummy_page {
	struct page	*page;
	dma_addr_t	addr;
};
int radeon_dummy_page_init(struct radeon_device *rdev);
void radeon_dummy_page_fini(struct radeon_device *rdev);

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/*
 * Clocks
 */
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struct radeon_clock {
	struct radeon_pll p1pll;
	struct radeon_pll p2pll;
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	struct radeon_pll dcpll;
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	struct radeon_pll spll;
	struct radeon_pll mpll;
	/* 10 Khz units */
	uint32_t default_mclk;
	uint32_t default_sclk;
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	uint32_t default_dispclk;
	uint32_t dp_extclk;
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};

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/*
 * Power management
 */
int radeon_pm_init(struct radeon_device *rdev);
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void radeon_pm_compute_clocks(struct radeon_device *rdev);
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void radeon_combios_get_power_modes(struct radeon_device *rdev);
void radeon_atombios_get_power_modes(struct radeon_device *rdev);
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/*
 * Fences.
 */
struct radeon_fence_driver {
	uint32_t			scratch_reg;
	atomic_t			seq;
	uint32_t			last_seq;
	unsigned long			count_timeout;
	wait_queue_head_t		queue;
	rwlock_t			lock;
	struct list_head		created;
	struct list_head		emited;
	struct list_head		signaled;
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	bool				initialized;
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};

struct radeon_fence {
	struct radeon_device		*rdev;
	struct kref			kref;
	struct list_head		list;
	/* protected by radeon_fence.lock */
	uint32_t			seq;
	unsigned long			timeout;
	bool				emited;
	bool				signaled;
};

int radeon_fence_driver_init(struct radeon_device *rdev);
void radeon_fence_driver_fini(struct radeon_device *rdev);
int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
void radeon_fence_process(struct radeon_device *rdev);
bool radeon_fence_signaled(struct radeon_fence *fence);
int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
int radeon_fence_wait_next(struct radeon_device *rdev);
int radeon_fence_wait_last(struct radeon_device *rdev);
struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
void radeon_fence_unref(struct radeon_fence **fence);

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/*
 * Tiling registers
 */
struct radeon_surface_reg {
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	struct radeon_bo *bo;
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};

#define RADEON_GEM_MAX_SURFACES 8
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/*
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 * TTM.
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 */
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struct radeon_mman {
	struct ttm_bo_global_ref        bo_global_ref;
	struct ttm_global_reference	mem_global_ref;
	struct ttm_bo_device		bdev;
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	bool				mem_global_referenced;
	bool				initialized;
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};

struct radeon_bo {
	/* Protected by gem.mutex */
	struct list_head		list;
	/* Protected by tbo.reserved */
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	u32				placements[3];
	struct ttm_placement		placement;
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	struct ttm_buffer_object	tbo;
	struct ttm_bo_kmap_obj		kmap;
	unsigned			pin_count;
	void				*kptr;
	u32				tiling_flags;
	u32				pitch;
	int				surface_reg;
	/* Constant after initialization */
	struct radeon_device		*rdev;
	struct drm_gem_object		*gobj;
};
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struct radeon_bo_list {
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	struct list_head	list;
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	struct radeon_bo	*bo;
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	uint64_t		gpu_offset;
	unsigned		rdomain;
	unsigned		wdomain;
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	u32			tiling_flags;
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};

/*
 * GEM objects.
 */
struct radeon_gem {
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	struct mutex		mutex;
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	struct list_head	objects;
};

int radeon_gem_init(struct radeon_device *rdev);
void radeon_gem_fini(struct radeon_device *rdev);
int radeon_gem_object_create(struct radeon_device *rdev, int size,
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				int alignment, int initial_domain,
				bool discardable, bool kernel,
				struct drm_gem_object **obj);
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int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
			  uint64_t *gpu_addr);
void radeon_gem_object_unpin(struct drm_gem_object *obj);


/*
 * GART structures, functions & helpers
 */
struct radeon_mc;

struct radeon_gart_table_ram {
	volatile uint32_t		*ptr;
};

struct radeon_gart_table_vram {
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	struct radeon_bo		*robj;
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	volatile uint32_t		*ptr;
};

union radeon_gart_table {
	struct radeon_gart_table_ram	ram;
	struct radeon_gart_table_vram	vram;
};

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#define RADEON_GPU_PAGE_SIZE 4096

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struct radeon_gart {
	dma_addr_t			table_addr;
	unsigned			num_gpu_pages;
	unsigned			num_cpu_pages;
	unsigned			table_size;
	union radeon_gart_table		table;
	struct page			**pages;
	dma_addr_t			*pages_addr;
	bool				ready;
};

int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
void radeon_gart_table_ram_free(struct radeon_device *rdev);
int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
void radeon_gart_table_vram_free(struct radeon_device *rdev);
int radeon_gart_init(struct radeon_device *rdev);
void radeon_gart_fini(struct radeon_device *rdev);
void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
			int pages);
int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
		     int pages, struct page **pagelist);


/*
 * GPU MC structures, functions & helpers
 */
struct radeon_mc {
	resource_size_t		aper_size;
	resource_size_t		aper_base;
	resource_size_t		agp_base;
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	/* for some chips with <= 32MB we need to lie
	 * about vram size near mc fb location */
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	u64			mc_vram_size;
	u64			gtt_location;
	u64			gtt_size;
	u64			gtt_start;
	u64			gtt_end;
	u64			vram_location;
	u64			vram_start;
	u64			vram_end;
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	unsigned		vram_width;
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	u64			real_vram_size;
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	int			vram_mtrr;
	bool			vram_is_ddr;
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	bool                    igp_sideport_enabled;
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};

int radeon_mc_setup(struct radeon_device *rdev);
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bool radeon_combios_sideport_present(struct radeon_device *rdev);
bool radeon_atombios_sideport_present(struct radeon_device *rdev);
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/*
 * GPU scratch registers structures, functions & helpers
 */
struct radeon_scratch {
	unsigned		num_reg;
	bool			free[32];
	uint32_t		reg[32];
};

int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);


/*
 * IRQS.
 */
struct radeon_irq {
	bool		installed;
	bool		sw_int;
	/* FIXME: use a define max crtc rather than hardcode it */
	bool		crtc_vblank_int[2];
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	wait_queue_head_t	vblank_queue;
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	/* FIXME: use defines for max hpd/dacs */
	bool            hpd[6];
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	spinlock_t sw_lock;
	int sw_refcount;
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};

int radeon_irq_kms_init(struct radeon_device *rdev);
void radeon_irq_kms_fini(struct radeon_device *rdev);
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void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
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/*
 * CP & ring.
 */
struct radeon_ib {
	struct list_head	list;
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	unsigned		idx;
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	uint64_t		gpu_addr;
	struct radeon_fence	*fence;
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	uint32_t		*ptr;
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	uint32_t		length_dw;
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	bool			free;
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};

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/*
 * locking -
 * mutex protects scheduled_ibs, ready, alloc_bm
 */
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struct radeon_ib_pool {
	struct mutex		mutex;
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	struct radeon_bo	*robj;
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	struct list_head	bogus_ib;
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	struct radeon_ib	ibs[RADEON_IB_POOL_SIZE];
	bool			ready;
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	unsigned		head_id;
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};

struct radeon_cp {
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	struct radeon_bo	*ring_obj;
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	volatile uint32_t	*ring;
	unsigned		rptr;
	unsigned		wptr;
	unsigned		wptr_old;
	unsigned		ring_size;
	unsigned		ring_free_dw;
	int			count_dw;
	uint64_t		gpu_addr;
	uint32_t		align_mask;
	uint32_t		ptr_mask;
	struct mutex		mutex;
	bool			ready;
};

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/*
 * R6xx+ IH ring
 */
struct r600_ih {
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	struct radeon_bo	*ring_obj;
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	volatile uint32_t	*ring;
	unsigned		rptr;
	unsigned		wptr;
	unsigned		wptr_old;
	unsigned		ring_size;
	uint64_t		gpu_addr;
	uint32_t		ptr_mask;
	spinlock_t              lock;
	bool                    enabled;
};

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struct r600_blit {
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	struct mutex		mutex;
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	struct radeon_bo	*shader_obj;
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	u64 shader_gpu_addr;
	u32 vs_offset, ps_offset;
	u32 state_offset;
	u32 state_len;
	u32 vb_used, vb_total;
	struct radeon_ib *vb_ib;
};

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int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
int radeon_ib_pool_init(struct radeon_device *rdev);
void radeon_ib_pool_fini(struct radeon_device *rdev);
int radeon_ib_test(struct radeon_device *rdev);
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extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
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/* Ring access between begin & end cannot sleep */
void radeon_ring_free_size(struct radeon_device *rdev);
int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
void radeon_ring_unlock_commit(struct radeon_device *rdev);
void radeon_ring_unlock_undo(struct radeon_device *rdev);
int radeon_ring_test(struct radeon_device *rdev);
int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
void radeon_ring_fini(struct radeon_device *rdev);


/*
 * CS.
 */
struct radeon_cs_reloc {
	struct drm_gem_object		*gobj;
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	struct radeon_bo		*robj;
	struct radeon_bo_list		lobj;
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	uint32_t			handle;
	uint32_t			flags;
};

struct radeon_cs_chunk {
	uint32_t		chunk_id;
	uint32_t		length_dw;
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	int kpage_idx[2];
	uint32_t                *kpage[2];
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	uint32_t		*kdata;
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	void __user *user_ptr;
	int last_copied_page;
	int last_page_index;
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};

struct radeon_cs_parser {
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	struct device		*dev;
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	struct radeon_device	*rdev;
	struct drm_file		*filp;
	/* chunks */
	unsigned		nchunks;
	struct radeon_cs_chunk	*chunks;
	uint64_t		*chunks_array;
	/* IB */
	unsigned		idx;
	/* relocations */
	unsigned		nrelocs;
	struct radeon_cs_reloc	*relocs;
	struct radeon_cs_reloc	**relocs_ptr;
	struct list_head	validated;
	/* indices of various chunks */
	int			chunk_ib_idx;
	int			chunk_relocs_idx;
	struct radeon_ib	*ib;
	void			*track;
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	unsigned		family;
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	int parser_error;
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};

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extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);


static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
{
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	u32 pg_idx, pg_offset;
	u32 idx_value = 0;
	int new_page;

	pg_idx = (idx * 4) / PAGE_SIZE;
	pg_offset = (idx * 4) % PAGE_SIZE;

	if (ibc->kpage_idx[0] == pg_idx)
		return ibc->kpage[0][pg_offset/4];
	if (ibc->kpage_idx[1] == pg_idx)
		return ibc->kpage[1][pg_offset/4];

	new_page = radeon_cs_update_pages(p, pg_idx);
	if (new_page < 0) {
		p->parser_error = new_page;
		return 0;
	}

	idx_value = ibc->kpage[new_page][pg_offset/4];
	return idx_value;
}

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struct radeon_cs_packet {
	unsigned	idx;
	unsigned	type;
	unsigned	reg;
	unsigned	opcode;
	int		count;
	unsigned	one_reg_wr;
};

typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
				      struct radeon_cs_packet *pkt,
				      unsigned idx, unsigned reg);
typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
				      struct radeon_cs_packet *pkt);


/*
 * AGP
 */
int radeon_agp_init(struct radeon_device *rdev);
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void radeon_agp_resume(struct radeon_device *rdev);
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void radeon_agp_fini(struct radeon_device *rdev);


/*
 * Writeback
 */
struct radeon_wb {
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	struct radeon_bo	*wb_obj;
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	volatile uint32_t	*wb;
	uint64_t		gpu_addr;
};

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/**
 * struct radeon_pm - power management datas
 * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 * @sclk:          	GPU clock Mhz (core bandwith depends of this clock)
 * @needed_bandwidth:   current bandwidth needs
 *
 * It keeps track of various data needed to take powermanagement decision.
 * Bandwith need is used to determine minimun clock of the GPU and memory.
 * Equation between gpu/memory clock and available bandwidth is hw dependent
 * (type of memory, bus size, efficiency, ...)
 */
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enum radeon_pm_state {
	PM_STATE_DISABLED,
	PM_STATE_MINIMUM,
	PM_STATE_PAUSED,
	PM_STATE_ACTIVE
};
enum radeon_pm_action {
	PM_ACTION_NONE,
	PM_ACTION_MINIMUM,
	PM_ACTION_DOWNCLOCK,
	PM_ACTION_UPCLOCK
};
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enum radeon_voltage_type {
	VOLTAGE_NONE = 0,
	VOLTAGE_GPIO,
	VOLTAGE_VDDC,
	VOLTAGE_SW
};

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enum radeon_pm_state_type {
	POWER_STATE_TYPE_DEFAULT,
	POWER_STATE_TYPE_POWERSAVE,
	POWER_STATE_TYPE_BATTERY,
	POWER_STATE_TYPE_BALANCED,
	POWER_STATE_TYPE_PERFORMANCE,
};

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enum radeon_pm_clock_mode_type {
	POWER_MODE_TYPE_DEFAULT,
	POWER_MODE_TYPE_LOW,
	POWER_MODE_TYPE_MID,
	POWER_MODE_TYPE_HIGH,
};

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struct radeon_voltage {
	enum radeon_voltage_type type;
	/* gpio voltage */
	struct radeon_gpio_rec gpio;
	u32 delay; /* delay in usec from voltage drop to sclk change */
	bool active_high; /* voltage drop is active when bit is high */
	/* VDDC voltage */
	u8 vddc_id; /* index into vddc voltage table */
	u8 vddci_id; /* index into vddci voltage table */
	bool vddci_enabled;
	/* r6xx+ sw */
	u32 voltage;
};

struct radeon_pm_non_clock_info {
	/* pcie lanes */
	int pcie_lanes;
	/* standardized non-clock flags */
	u32 flags;
};

struct radeon_pm_clock_info {
	/* memory clock */
	u32 mclk;
	/* engine clock */
	u32 sclk;
	/* voltage info */
	struct radeon_voltage voltage;
	/* standardized clock flags - not sure we'll need these */
	u32 flags;
};

struct radeon_power_state {
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	enum radeon_pm_state_type type;
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	/* XXX: use a define for num clock modes */
	struct radeon_pm_clock_info clock_info[8];
	/* number of valid clock modes in this power state */
	int num_clock_modes;
	/* currently selected clock mode */
	struct radeon_pm_clock_info *current_clock_mode;
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	struct radeon_pm_clock_info *requested_clock_mode;
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	struct radeon_pm_clock_info *default_clock_mode;
	/* non clock info about this state */
	struct radeon_pm_non_clock_info non_clock_info;
	bool voltage_drop_active;
};

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/*
 * Some modes are overclocked by very low value, accept them
 */
#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */

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struct radeon_pm {
671 672 673 674 675 676 677 678
	struct mutex		mutex;
	struct delayed_work	idle_work;
	enum radeon_pm_state	state;
	enum radeon_pm_action	planned_action;
	unsigned long		action_timeout;
	bool 			downclocked;
	int			active_crtcs;
	int			req_vblank;
679 680 681 682 683 684 685 686 687 688 689
	fixed20_12		max_bandwidth;
	fixed20_12		igp_sideport_mclk;
	fixed20_12		igp_system_mclk;
	fixed20_12		igp_ht_link_clk;
	fixed20_12		igp_ht_link_width;
	fixed20_12		k8_bandwidth;
	fixed20_12		sideport_bandwidth;
	fixed20_12		ht_bandwidth;
	fixed20_12		core_bandwidth;
	fixed20_12		sclk;
	fixed20_12		needed_bandwidth;
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	/* XXX: use a define for num power modes */
	struct radeon_power_state power_state[8];
	/* number of valid power states */
	int                     num_power_states;
	struct radeon_power_state *current_power_state;
695
	struct radeon_power_state *requested_power_state;
696
	struct radeon_power_state *default_power_state;
697 698
};

699 700 701 702 703 704 705

/*
 * Benchmarking
 */
void radeon_benchmark(struct radeon_device *rdev);


706 707 708 709 710 711
/*
 * Testing
 */
void radeon_test_moves(struct radeon_device *rdev);


712 713 714 715 716 717 718 719 720 721 722 723 724 725 726
/*
 * Debugfs
 */
int radeon_debugfs_add_files(struct radeon_device *rdev,
			     struct drm_info_list *files,
			     unsigned nfiles);
int radeon_debugfs_fence_init(struct radeon_device *rdev);
int r100_debugfs_rbbm_init(struct radeon_device *rdev);
int r100_debugfs_cp_init(struct radeon_device *rdev);


/*
 * ASIC specific functions.
 */
struct radeon_asic {
727
	int (*init)(struct radeon_device *rdev);
728 729 730
	void (*fini)(struct radeon_device *rdev);
	int (*resume)(struct radeon_device *rdev);
	int (*suspend)(struct radeon_device *rdev);
731
	void (*vga_set_state)(struct radeon_device *rdev, bool state);
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	int (*gpu_reset)(struct radeon_device *rdev);
	void (*gart_tlb_flush)(struct radeon_device *rdev);
	int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
	int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
	void (*cp_fini)(struct radeon_device *rdev);
	void (*cp_disable)(struct radeon_device *rdev);
738
	void (*cp_commit)(struct radeon_device *rdev);
739
	void (*ring_start)(struct radeon_device *rdev);
740 741
	int (*ring_test)(struct radeon_device *rdev);
	void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
742 743
	int (*irq_set)(struct radeon_device *rdev);
	int (*irq_process)(struct radeon_device *rdev);
744
	u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
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	void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
	int (*cs_parse)(struct radeon_cs_parser *p);
	int (*copy_blit)(struct radeon_device *rdev,
			 uint64_t src_offset,
			 uint64_t dst_offset,
			 unsigned num_pages,
			 struct radeon_fence *fence);
	int (*copy_dma)(struct radeon_device *rdev,
			uint64_t src_offset,
			uint64_t dst_offset,
			unsigned num_pages,
			struct radeon_fence *fence);
	int (*copy)(struct radeon_device *rdev,
		    uint64_t src_offset,
		    uint64_t dst_offset,
		    unsigned num_pages,
		    struct radeon_fence *fence);
762
	uint32_t (*get_engine_clock)(struct radeon_device *rdev);
763
	void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
764
	uint32_t (*get_memory_clock)(struct radeon_device *rdev);
765
	void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
766
	int (*get_pcie_lanes)(struct radeon_device *rdev);
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	void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
	void (*set_clock_gating)(struct radeon_device *rdev, int enable);
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	int (*set_surface_reg)(struct radeon_device *rdev, int reg,
			       uint32_t tiling_flags, uint32_t pitch,
			       uint32_t offset, uint32_t obj_size);
	int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
773
	void (*bandwidth_update)(struct radeon_device *rdev);
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	void (*hpd_init)(struct radeon_device *rdev);
	void (*hpd_fini)(struct radeon_device *rdev);
	bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
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	/* ioctl hw specific callback. Some hw might want to perform special
	 * operation on specific ioctl. For instance on wait idle some hw
	 * might want to perform and HDP flush through MMIO as it seems that
	 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
	 * through ring.
	 */
	void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
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};

787 788 789
/*
 * Asic structures
 */
790 791 792
struct r100_asic {
	const unsigned	*reg_safe_bm;
	unsigned	reg_safe_bm_size;
793
	u32		hdp_cntl;
794 795
};

796 797 798
struct r300_asic {
	const unsigned	*reg_safe_bm;
	unsigned	reg_safe_bm_size;
799
	u32		resync_scratch;
800
	u32		hdp_cntl;
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};

struct r600_asic {
	unsigned max_pipes;
	unsigned max_tile_pipes;
	unsigned max_simds;
	unsigned max_backends;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_stack_entries;
	unsigned max_hw_contexts;
	unsigned max_gs_threads;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned sq_num_cf_insts;
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	unsigned tiling_nbanks;
	unsigned tiling_npipes;
	unsigned tiling_group_size;
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};

struct rv770_asic {
	unsigned max_pipes;
	unsigned max_tile_pipes;
	unsigned max_simds;
	unsigned max_backends;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_stack_entries;
	unsigned max_hw_contexts;
	unsigned max_gs_threads;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned sq_num_cf_insts;
	unsigned sx_num_of_sets;
	unsigned sc_prim_fifo_size;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_fize;
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	unsigned tiling_nbanks;
	unsigned tiling_npipes;
	unsigned tiling_group_size;
843 844
};

845 846
union radeon_asic_config {
	struct r300_asic	r300;
847
	struct r100_asic	r100;
848 849
	struct r600_asic	r600;
	struct rv770_asic	rv770;
850 851
};

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/*
 * IOCTL.
 */
int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp);
int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *filp);
int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp);
int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp);
int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp);
int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *filp);
int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
877 878 879 880
int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp);
int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp);
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/*
 * Core structure, functions and helpers.
 */
typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);

struct radeon_device {
890
	struct device			*dev;
891 892 893
	struct drm_device		*ddev;
	struct pci_dev			*pdev;
	/* ASIC */
894
	union radeon_asic_config	config;
895 896 897 898 899
	enum radeon_family		family;
	unsigned long			flags;
	int				usec_timeout;
	enum radeon_pll_errata		pll_errata;
	int				num_gb_pipes;
900
	int				num_z_pipes;
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	int				disp_priority;
	/* BIOS */
	uint8_t				*bios;
	bool				is_atom_bios;
	uint16_t			bios_header_start;
906
	struct radeon_bo		*stollen_vga_memory;
907
	struct fb_info			*fbdev_info;
908
	struct radeon_bo		*fbdev_rbo;
909 910
	struct radeon_framebuffer	*fbdev_rfb;
	/* Register mmio */
911 912
	resource_size_t			rmmio_base;
	resource_size_t			rmmio_size;
913 914 915 916 917
	void				*rmmio;
	radeon_rreg_t			mc_rreg;
	radeon_wreg_t			mc_wreg;
	radeon_rreg_t			pll_rreg;
	radeon_wreg_t			pll_wreg;
918
	uint32_t                        pcie_reg_mask;
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	radeon_rreg_t			pciep_rreg;
	radeon_wreg_t			pciep_wreg;
	struct radeon_clock             clock;
	struct radeon_mc		mc;
	struct radeon_gart		gart;
	struct radeon_mode_info		mode_info;
	struct radeon_scratch		scratch;
	struct radeon_mman		mman;
	struct radeon_fence_driver	fence_drv;
	struct radeon_cp		cp;
	struct radeon_ib_pool		ib_pool;
	struct radeon_irq		irq;
	struct radeon_asic		*asic;
	struct radeon_gem		gem;
933
	struct radeon_pm		pm;
934
	uint32_t			bios_scratch[RADEON_BIOS_NUM_SCRATCH];
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	struct mutex			cs_mutex;
	struct radeon_wb		wb;
937
	struct radeon_dummy_page	dummy_page;
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	bool				gpu_lockup;
	bool				shutdown;
	bool				suspend;
D
Dave Airlie 已提交
941
	bool				need_dma32;
942
	bool				accel_working;
943
	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
944 945
	const struct firmware *me_fw;	/* all family ME firmware */
	const struct firmware *pfp_fw;	/* r6/700 PFP firmware */
946
	const struct firmware *rlc_fw;	/* r6/700 RLC firmware */
947
	struct r600_blit r600_blit;
A
Alex Deucher 已提交
948
	int msi_enabled; /* msi enabled */
949
	struct r600_ih ih; /* r6/700 interrupt ring */
A
Alex Deucher 已提交
950 951
	struct workqueue_struct *wq;
	struct work_struct hotplug_work;
952
	int num_crtc; /* number of crtcs */
953
	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
954 955 956 957 958 959 960 961

	/* audio stuff */
	struct timer_list	audio_timer;
	int			audio_channels;
	int			audio_rate;
	int			audio_bits_per_sample;
	uint8_t			audio_status_bits;
	uint8_t			audio_category_code;
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};

int radeon_device_init(struct radeon_device *rdev,
		       struct drm_device *ddev,
		       struct pci_dev *pdev,
		       uint32_t flags);
void radeon_device_fini(struct radeon_device *rdev);
int radeon_gpu_wait_for_idle(struct radeon_device *rdev);

971 972 973 974 975 976 977
/* r600 blit */
int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
void r600_kms_blit_copy(struct radeon_device *rdev,
			u64 src_gpu_addr, u64 dst_gpu_addr,
			int size_bytes);

978 979
static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
{
980
	if (reg < rdev->rmmio_size)
981 982 983 984 985 986 987 988 989
		return readl(((void __iomem *)rdev->rmmio) + reg);
	else {
		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
	}
}

static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
990
	if (reg < rdev->rmmio_size)
991 992 993 994 995 996 997
		writel(v, ((void __iomem *)rdev->rmmio) + reg);
	else {
		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
	}
}

998 999 1000 1001
/*
 * Cast helper
 */
#define to_radeon_fence(p) ((struct radeon_fence *)(p))
1002 1003 1004 1005 1006 1007

/*
 * Registers read & write functions.
 */
#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1008
#define RREG32(reg) r100_mm_rreg(rdev, (reg))
1009
#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1010
#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1011 1012 1013 1014 1015 1016
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1017 1018
#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032
#define WREG32_P(reg, val, mask)				\
	do {							\
		uint32_t tmp_ = RREG32(reg);			\
		tmp_ &= (mask);					\
		tmp_ |= ((val) & ~(mask));			\
		WREG32(reg, tmp_);				\
	} while (0)
#define WREG32_PLL_P(reg, val, mask)				\
	do {							\
		uint32_t tmp_ = RREG32_PLL(reg);		\
		tmp_ &= (mask);					\
		tmp_ |= ((val) & ~(mask));			\
		WREG32_PLL(reg, tmp_);				\
	} while (0)
1033
#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1034

1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052
/*
 * Indirect registers accessor
 */
static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
{
	uint32_t r;

	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
	r = RREG32(RADEON_PCIE_DATA);
	return r;
}

static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
	WREG32(RADEON_PCIE_DATA, (v));
}

1053 1054 1055 1056 1057 1058
void r100_pll_errata_after_index(struct radeon_device *rdev);


/*
 * ASICs helpers.
 */
1059 1060
#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
			    (rdev->pdev->device == 0x5969))
1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079
#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
		(rdev->family == CHIP_RV200) || \
		(rdev->family == CHIP_RS100) || \
		(rdev->family == CHIP_RS200) || \
		(rdev->family == CHIP_RV250) || \
		(rdev->family == CHIP_RV280) || \
		(rdev->family == CHIP_RS300))
#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||	\
		(rdev->family == CHIP_RV350) ||			\
		(rdev->family == CHIP_R350)  ||			\
		(rdev->family == CHIP_RV380) ||			\
		(rdev->family == CHIP_R420)  ||			\
		(rdev->family == CHIP_R423)  ||			\
		(rdev->family == CHIP_RV410) ||			\
		(rdev->family == CHIP_RS400) ||			\
		(rdev->family == CHIP_RS480))
#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1080
#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114

/*
 * BIOS helpers.
 */
#define RBIOS8(i) (rdev->bios[i])
#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))

int radeon_combios_init(struct radeon_device *rdev);
void radeon_combios_fini(struct radeon_device *rdev);
int radeon_atombios_init(struct radeon_device *rdev);
void radeon_atombios_fini(struct radeon_device *rdev);


/*
 * RING helpers.
 */
static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
{
#if DRM_DEBUG_CODE
	if (rdev->cp.count_dw <= 0) {
		DRM_ERROR("radeon: writting more dword to ring than expected !\n");
	}
#endif
	rdev->cp.ring[rdev->cp.wptr++] = v;
	rdev->cp.wptr &= rdev->cp.ptr_mask;
	rdev->cp.count_dw--;
	rdev->cp.ring_free_dw--;
}


/*
 * ASICs macro.
 */
1115
#define radeon_init(rdev) (rdev)->asic->init((rdev))
1116 1117 1118
#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1119
#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1120
#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1121 1122 1123
#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1124
#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1125
#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1126 1127
#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1128 1129
#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1130
#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1131 1132 1133 1134
#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1135
#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1136
#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1137
#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1138
#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1139
#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1140 1141
#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1142 1143
#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1144
#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1145 1146 1147 1148
#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1149

1150
/* Common functions */
1151 1152
/* AGP */
extern void radeon_agp_disable(struct radeon_device *rdev);
1153
extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1154
extern void radeon_gart_restore(struct radeon_device *rdev);
1155 1156
extern int radeon_modeset_init(struct radeon_device *rdev);
extern void radeon_modeset_fini(struct radeon_device *rdev);
1157
extern bool radeon_card_posted(struct radeon_device *rdev);
1158
extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1159 1160 1161 1162 1163
extern int radeon_clocks_init(struct radeon_device *rdev);
extern void radeon_clocks_fini(struct radeon_device *rdev);
extern void radeon_scratch_init(struct radeon_device *rdev);
extern void radeon_surface_init(struct radeon_device *rdev);
extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1164
extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1165
extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1166
extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1167
extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1168

1169
/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180
struct r100_mc_save {
	u32	GENMO_WT;
	u32	CRTC_EXT_CNTL;
	u32	CRTC_GEN_CNTL;
	u32	CRTC2_GEN_CNTL;
	u32	CUR_OFFSET;
	u32	CUR2_OFFSET;
};
extern void r100_cp_disable(struct radeon_device *rdev);
extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
extern void r100_cp_fini(struct radeon_device *rdev);
1181
extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1182 1183
extern int r100_pci_gart_init(struct radeon_device *rdev);
extern void r100_pci_gart_fini(struct radeon_device *rdev);
1184 1185 1186
extern int r100_pci_gart_enable(struct radeon_device *rdev);
extern void r100_pci_gart_disable(struct radeon_device *rdev);
extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1187 1188 1189 1190 1191 1192 1193 1194
extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
extern void r100_ib_fini(struct radeon_device *rdev);
extern int r100_ib_init(struct radeon_device *rdev);
extern void r100_irq_disable(struct radeon_device *rdev);
extern int r100_irq_set(struct radeon_device *rdev);
extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1195
extern void r100_vram_init_sizes(struct radeon_device *rdev);
1196 1197 1198
extern void r100_wb_disable(struct radeon_device *rdev);
extern void r100_wb_fini(struct radeon_device *rdev);
extern int r100_wb_init(struct radeon_device *rdev);
1199 1200 1201
extern void r100_hdp_reset(struct radeon_device *rdev);
extern int r100_rb2d_reset(struct radeon_device *rdev);
extern int r100_cp_reset(struct radeon_device *rdev);
1202
extern void r100_vga_render_disable(struct radeon_device *rdev);
1203 1204
extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
						struct radeon_cs_packet *pkt,
1205
						struct radeon_bo *robj);
1206 1207 1208 1209 1210 1211 1212
extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
				struct radeon_cs_packet *pkt,
				const unsigned *auth, unsigned n,
				radeon_packet0_check_t check);
extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
				struct radeon_cs_packet *pkt,
				unsigned idx);
1213
extern void r100_enable_bm(struct radeon_device *rdev);
1214
extern void r100_set_common_regs(struct radeon_device *rdev);
1215

1216 1217
/* rv200,rv250,rv280 */
extern void r200_set_safe_registers(struct radeon_device *rdev);
1218 1219 1220 1221 1222

/* r300,r350,rv350,rv370,rv380 */
extern void r300_set_reg_safe(struct radeon_device *rdev);
extern void r300_mc_program(struct radeon_device *rdev);
extern void r300_vram_info(struct radeon_device *rdev);
1223 1224
extern void r300_clock_startup(struct radeon_device *rdev);
extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1225 1226 1227
extern int rv370_pcie_gart_init(struct radeon_device *rdev);
extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1228
extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1229

1230
/* r420,r423,rv410 */
1231
extern int r420_mc_init(struct radeon_device *rdev);
1232 1233
extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1234
extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1235
extern void r420_pipes_init(struct radeon_device *rdev);
1236

1237
/* rv515 */
1238 1239 1240 1241 1242 1243 1244 1245
struct rv515_mc_save {
	u32 d1vga_control;
	u32 d2vga_control;
	u32 vga_render_control;
	u32 vga_hdp_control;
	u32 d1crtc_control;
	u32 d2crtc_control;
};
1246
extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1247 1248
extern void rv515_vga_render_disable(struct radeon_device *rdev);
extern void rv515_set_safe_registers(struct radeon_device *rdev);
1249 1250 1251 1252 1253
extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
extern void rv515_clock_startup(struct radeon_device *rdev);
extern void rv515_debugfs(struct radeon_device *rdev);
extern int rv515_suspend(struct radeon_device *rdev);
1254

1255 1256 1257 1258 1259 1260 1261 1262 1263
/* rs400 */
extern int rs400_gart_init(struct radeon_device *rdev);
extern int rs400_gart_enable(struct radeon_device *rdev);
extern void rs400_gart_adjust_size(struct radeon_device *rdev);
extern void rs400_gart_disable(struct radeon_device *rdev);
extern void rs400_gart_fini(struct radeon_device *rdev);

/* rs600 */
extern void rs600_set_safe_registers(struct radeon_device *rdev);
1264 1265
extern int rs600_irq_set(struct radeon_device *rdev);
extern void rs600_irq_disable(struct radeon_device *rdev);
1266

1267 1268 1269 1270 1271 1272 1273 1274 1275 1276
/* rs690, rs740 */
extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
					struct drm_display_mode *mode1,
					struct drm_display_mode *mode2);

/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
extern bool r600_card_posted(struct radeon_device *rdev);
extern void r600_cp_stop(struct radeon_device *rdev);
extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
extern int r600_cp_resume(struct radeon_device *rdev);
1277
extern void r600_cp_fini(struct radeon_device *rdev);
1278 1279
extern int r600_count_pipe_bits(uint32_t val);
extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1280
extern int r600_pcie_gart_init(struct radeon_device *rdev);
1281 1282 1283 1284
extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
extern int r600_ib_test(struct radeon_device *rdev);
extern int r600_ring_test(struct radeon_device *rdev);
extern void r600_wb_fini(struct radeon_device *rdev);
1285 1286
extern int r600_wb_enable(struct radeon_device *rdev);
extern void r600_wb_disable(struct radeon_device *rdev);
1287 1288 1289
extern void r600_scratch_init(struct radeon_device *rdev);
extern int r600_blit_init(struct radeon_device *rdev);
extern void r600_blit_fini(struct radeon_device *rdev);
1290
extern int r600_init_microcode(struct radeon_device *rdev);
1291
extern int r600_gpu_reset(struct radeon_device *rdev);
1292 1293 1294 1295 1296
/* r600 irq */
extern int r600_irq_init(struct radeon_device *rdev);
extern void r600_irq_fini(struct radeon_device *rdev);
extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
extern int r600_irq_set(struct radeon_device *rdev);
1297 1298
extern void r600_irq_suspend(struct radeon_device *rdev);
/* r600 audio */
1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313
extern int r600_audio_init(struct radeon_device *rdev);
extern int r600_audio_tmds_index(struct drm_encoder *encoder);
extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
extern void r600_audio_fini(struct radeon_device *rdev);
extern void r600_hdmi_init(struct drm_encoder *encoder);
extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
					    int channels,
					    int rate,
					    int bps,
					    uint8_t status_bits,
					    uint8_t category_code);

1314 1315 1316 1317 1318 1319 1320 1321
/* evergreen */
struct evergreen_mc_save {
	u32 vga_control[6];
	u32 vga_render_control;
	u32 vga_hdp_control;
	u32 crtc_control[6];
};

1322 1323
#include "radeon_object.h"

1324
#endif