lapic.c 46.2 KB
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/*
 * Local APIC virtualization
 *
 * Copyright (C) 2006 Qumranet, Inc.
 * Copyright (C) 2007 Novell
 * Copyright (C) 2007 Intel
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 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
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 *
 * Authors:
 *   Dor Laor <dor.laor@qumranet.com>
 *   Gregory Haskins <ghaskins@novell.com>
 *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
 *
 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 */

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#include <linux/kvm_host.h>
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#include <linux/kvm.h>
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/smp.h>
#include <linux/hrtimer.h>
#include <linux/io.h>
#include <linux/module.h>
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#include <linux/math64.h>
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#include <linux/slab.h>
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#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/page.h>
#include <asm/current.h>
#include <asm/apicdef.h>
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#include <linux/atomic.h>
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#include <linux/jump_label.h>
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#include "kvm_cache_regs.h"
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#include "irq.h"
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#include "trace.h"
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#include "x86.h"
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#include "cpuid.h"
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#ifndef CONFIG_X86_64
#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
#else
#define mod_64(x, y) ((x) % (y))
#endif

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#define PRId64 "d"
#define PRIx64 "llx"
#define PRIu64 "u"
#define PRIo64 "o"

#define APIC_BUS_CYCLE_NS 1

/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
#define apic_debug(fmt, arg...)

#define APIC_LVT_NUM			6
/* 14 is the version for Xeon and Pentium 8.4.8*/
#define APIC_VERSION			(0x14UL | ((APIC_LVT_NUM - 1) << 16))
#define LAPIC_MMIO_LENGTH		(1 << 12)
/* followed define is not in apicdef.h */
#define APIC_SHORT_MASK			0xc0000
#define APIC_DEST_NOSHORT		0x0
#define APIC_DEST_MASK			0x800
#define MAX_APIC_VECTOR			256
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#define APIC_VECTORS_PER_REG		32
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#define VEC_POS(v) ((v) & (32 - 1))
#define REG_POS(v) (((v) >> 5) << 4)
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static unsigned int min_timer_period_us = 500;
module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);

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static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
{
	*((u32 *) (apic->regs + reg_off)) = val;
}

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static inline int apic_test_vector(int vec, void *bitmap)
{
	return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

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bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
{
	struct kvm_lapic *apic = vcpu->arch.apic;

	return apic_test_vector(vector, apic->regs + APIC_ISR) ||
		apic_test_vector(vector, apic->regs + APIC_IRR);
}

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static inline void apic_set_vector(int vec, void *bitmap)
{
	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

static inline void apic_clear_vector(int vec, void *bitmap)
{
	clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

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static inline int __apic_test_and_set_vector(int vec, void *bitmap)
{
	return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
{
	return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

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struct static_key_deferred apic_hw_disabled __read_mostly;
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struct static_key_deferred apic_sw_disabled __read_mostly;

static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
{
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	if ((kvm_apic_get_reg(apic, APIC_SPIV) ^ val) & APIC_SPIV_APIC_ENABLED) {
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		if (val & APIC_SPIV_APIC_ENABLED)
			static_key_slow_dec_deferred(&apic_sw_disabled);
		else
			static_key_slow_inc(&apic_sw_disabled.key);
	}
	apic_set_reg(apic, APIC_SPIV, val);
}

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static inline int apic_enabled(struct kvm_lapic *apic)
{
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	return kvm_apic_sw_enabled(apic) &&	kvm_apic_hw_enabled(apic);
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}

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#define LVT_MASK	\
	(APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)

#define LINT_MASK	\
	(LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
	 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)

static inline int kvm_apic_id(struct kvm_lapic *apic)
{
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	return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
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}

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static void recalculate_apic_map(struct kvm *kvm)
{
	struct kvm_apic_map *new, *old = NULL;
	struct kvm_vcpu *vcpu;
	int i;

	new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);

	mutex_lock(&kvm->arch.apic_map_lock);

	if (!new)
		goto out;

	new->ldr_bits = 8;
	/* flat mode is default */
	new->cid_shift = 8;
	new->cid_mask = 0;
	new->lid_mask = 0xff;

	kvm_for_each_vcpu(i, vcpu, kvm) {
		struct kvm_lapic *apic = vcpu->arch.apic;
		u16 cid, lid;
		u32 ldr;

		if (!kvm_apic_present(vcpu))
			continue;

		/*
		 * All APICs have to be configured in the same mode by an OS.
		 * We take advatage of this while building logical id loockup
		 * table. After reset APICs are in xapic/flat mode, so if we
		 * find apic with different setting we assume this is the mode
		 * OS wants all apics to be in; build lookup table accordingly.
		 */
		if (apic_x2apic_mode(apic)) {
			new->ldr_bits = 32;
			new->cid_shift = 16;
			new->cid_mask = new->lid_mask = 0xffff;
		} else if (kvm_apic_sw_enabled(apic) &&
				!new->cid_mask /* flat mode */ &&
				kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_CLUSTER) {
			new->cid_shift = 4;
			new->cid_mask = 0xf;
			new->lid_mask = 0xf;
		}

		new->phys_map[kvm_apic_id(apic)] = apic;

		ldr = kvm_apic_get_reg(apic, APIC_LDR);
		cid = apic_cluster_id(new, ldr);
		lid = apic_logical_id(new, ldr);

		if (lid)
			new->logical_map[cid][ffs(lid) - 1] = apic;
	}
out:
	old = rcu_dereference_protected(kvm->arch.apic_map,
			lockdep_is_held(&kvm->arch.apic_map_lock));
	rcu_assign_pointer(kvm->arch.apic_map, new);
	mutex_unlock(&kvm->arch.apic_map_lock);

	if (old)
		kfree_rcu(old, rcu);
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	kvm_vcpu_request_scan_ioapic(kvm);
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}

static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
{
	apic_set_reg(apic, APIC_ID, id << 24);
	recalculate_apic_map(apic->vcpu->kvm);
}

static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
{
	apic_set_reg(apic, APIC_LDR, id);
	recalculate_apic_map(apic->vcpu->kvm);
}

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static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
{
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	return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
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}

static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
{
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	return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
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}

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static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
{
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	return ((kvm_apic_get_reg(apic, APIC_LVTT) &
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		apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
}

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static inline int apic_lvtt_period(struct kvm_lapic *apic)
{
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	return ((kvm_apic_get_reg(apic, APIC_LVTT) &
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		apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
}

static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
{
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	return ((kvm_apic_get_reg(apic, APIC_LVTT) &
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		apic->lapic_timer.timer_mode_mask) ==
			APIC_LVT_TIMER_TSCDEADLINE);
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}

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static inline int apic_lvt_nmi_mode(u32 lvt_val)
{
	return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
}

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void kvm_apic_set_version(struct kvm_vcpu *vcpu)
{
	struct kvm_lapic *apic = vcpu->arch.apic;
	struct kvm_cpuid_entry2 *feat;
	u32 v = APIC_VERSION;

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	if (!kvm_vcpu_has_lapic(vcpu))
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		return;

	feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
	if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
		v |= APIC_LVR_DIRECTED_EOI;
	apic_set_reg(apic, APIC_LVR, v);
}

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static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
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	LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
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	LVT_MASK | APIC_MODE_MASK,	/* LVTTHMR */
	LVT_MASK | APIC_MODE_MASK,	/* LVTPC */
	LINT_MASK, LINT_MASK,	/* LVT0-1 */
	LVT_MASK		/* LVTERR */
};

static int find_highest_vector(void *bitmap)
{
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	int vec;
	u32 *reg;
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	for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
	     vec >= 0; vec -= APIC_VECTORS_PER_REG) {
		reg = bitmap + REG_POS(vec);
		if (*reg)
			return fls(*reg) - 1 + vec;
	}
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	return -1;
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}

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static u8 count_vectors(void *bitmap)
{
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	int vec;
	u32 *reg;
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	u8 count = 0;
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	for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
		reg = bitmap + REG_POS(vec);
		count += hweight32(*reg);
	}

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	return count;
}

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void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
{
	u32 i, pir_val;
	struct kvm_lapic *apic = vcpu->arch.apic;

	for (i = 0; i <= 7; i++) {
		pir_val = xchg(&pir[i], 0);
		if (pir_val)
			*((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
	}
}
EXPORT_SYMBOL_GPL(kvm_apic_update_irr);

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static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
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{
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	apic->irr_pending = true;
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	apic_set_vector(vec, apic->regs + APIC_IRR);
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}

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static inline int apic_search_irr(struct kvm_lapic *apic)
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{
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	return find_highest_vector(apic->regs + APIC_IRR);
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}

static inline int apic_find_highest_irr(struct kvm_lapic *apic)
{
	int result;

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	/*
	 * Note that irr_pending is just a hint. It will be always
	 * true with virtual interrupt delivery enabled.
	 */
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	if (!apic->irr_pending)
		return -1;

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	kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
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	result = apic_search_irr(apic);
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	ASSERT(result == -1 || result >= 16);

	return result;
}

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static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
{
	apic->irr_pending = false;
	apic_clear_vector(vec, apic->regs + APIC_IRR);
	if (apic_search_irr(apic) != -1)
		apic->irr_pending = true;
}

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static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
{
	if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
		++apic->isr_count;
	BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
	/*
	 * ISR (in service register) bit is set when injecting an interrupt.
	 * The highest vector is injected. Thus the latest bit set matches
	 * the highest bit in ISR.
	 */
	apic->highest_isr_cache = vec;
}

static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
{
	if (__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
		--apic->isr_count;
	BUG_ON(apic->isr_count < 0);
	apic->highest_isr_cache = -1;
}

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int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
{
	int highest_irr;

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	/* This may race with setting of irr in __apic_accept_irq() and
	 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
	 * will cause vmexit immediately and the value will be recalculated
	 * on the next vmentry.
	 */
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	if (!kvm_vcpu_has_lapic(vcpu))
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		return 0;
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	highest_irr = apic_find_highest_irr(vcpu->arch.apic);
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	return highest_irr;
}

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static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
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			     int vector, int level, int trig_mode,
			     unsigned long *dest_map);
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int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
		unsigned long *dest_map)
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{
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	struct kvm_lapic *apic = vcpu->arch.apic;
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	return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
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			irq->level, irq->trig_mode, dest_map);
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}

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static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
{

	return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
				      sizeof(val));
}

static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
{

	return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
				      sizeof(*val));
}

static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
{
	return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
}

static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
{
	u8 val;
	if (pv_eoi_get_user(vcpu, &val) < 0)
		apic_debug("Can't read EOI MSR value: 0x%llx\n",
			   (unsigned long long)vcpi->arch.pv_eoi.msr_val);
	return val & 0x1;
}

static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
{
	if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
		apic_debug("Can't set EOI MSR value: 0x%llx\n",
			   (unsigned long long)vcpi->arch.pv_eoi.msr_val);
		return;
	}
	__set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
}

static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
{
	if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
		apic_debug("Can't clear EOI MSR value: 0x%llx\n",
			   (unsigned long long)vcpi->arch.pv_eoi.msr_val);
		return;
	}
	__clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
}

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static inline int apic_find_highest_isr(struct kvm_lapic *apic)
{
	int result;
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	/* Note that isr_count is always 1 with vid enabled */
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	if (!apic->isr_count)
		return -1;
	if (likely(apic->highest_isr_cache != -1))
		return apic->highest_isr_cache;
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	result = find_highest_vector(apic->regs + APIC_ISR);
	ASSERT(result == -1 || result >= 16);

	return result;
}

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void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
{
	struct kvm_lapic *apic = vcpu->arch.apic;
	int i;

	for (i = 0; i < 8; i++)
		apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
}

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static void apic_update_ppr(struct kvm_lapic *apic)
{
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	u32 tpr, isrv, ppr, old_ppr;
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	int isr;

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	old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
	tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
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	isr = apic_find_highest_isr(apic);
	isrv = (isr != -1) ? isr : 0;

	if ((tpr & 0xf0) >= (isrv & 0xf0))
		ppr = tpr & 0xff;
	else
		ppr = isrv & 0xf0;

	apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
		   apic, ppr, isr, isrv);

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	if (old_ppr != ppr) {
		apic_set_reg(apic, APIC_PROCPRI, ppr);
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		if (ppr < old_ppr)
			kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
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	}
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}

static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
{
	apic_set_reg(apic, APIC_TASKPRI, tpr);
	apic_update_ppr(apic);
}

int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
{
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	return dest == 0xff || kvm_apic_id(apic) == dest;
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}

int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
{
	int result = 0;
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	u32 logical_id;

	if (apic_x2apic_mode(apic)) {
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		logical_id = kvm_apic_get_reg(apic, APIC_LDR);
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		return logical_id & mda;
	}
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	logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
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	switch (kvm_apic_get_reg(apic, APIC_DFR)) {
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	case APIC_DFR_FLAT:
		if (logical_id & mda)
			result = 1;
		break;
	case APIC_DFR_CLUSTER:
		if (((logical_id >> 4) == (mda >> 0x4))
		    && (logical_id & mda & 0xf))
			result = 1;
		break;
	default:
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		apic_debug("Bad DFR vcpu %d: %08x\n",
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			   apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
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		break;
	}

	return result;
}

551
int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
E
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			   int short_hand, int dest, int dest_mode)
{
	int result = 0;
555
	struct kvm_lapic *target = vcpu->arch.apic;
E
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	apic_debug("target %p, source %p, dest 0x%x, "
558
		   "dest_mode 0x%x, short_hand 0x%x\n",
E
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		   target, source, dest, dest_mode, short_hand);

Z
Zachary Amsden 已提交
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	ASSERT(target);
E
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	switch (short_hand) {
	case APIC_DEST_NOSHORT:
564
		if (dest_mode == 0)
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			/* Physical mode. */
566 567
			result = kvm_apic_match_physical_addr(target, dest);
		else
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			/* Logical mode. */
			result = kvm_apic_match_logical_addr(target, dest);
		break;
	case APIC_DEST_SELF:
572
		result = (target == source);
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		break;
	case APIC_DEST_ALLINC:
		result = 1;
		break;
	case APIC_DEST_ALLBUT:
578
		result = (target != source);
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		break;
	default:
581 582
		apic_debug("kvm: apic: Bad dest shorthand value %x\n",
			   short_hand);
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		break;
	}

	return result;
}

589
bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
590
		struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
591 592 593 594 595 596 597 598 599 600
{
	struct kvm_apic_map *map;
	unsigned long bitmap = 1;
	struct kvm_lapic **dst;
	int i;
	bool ret = false;

	*r = -1;

	if (irq->shorthand == APIC_DEST_SELF) {
601
		*r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645
		return true;
	}

	if (irq->shorthand)
		return false;

	rcu_read_lock();
	map = rcu_dereference(kvm->arch.apic_map);

	if (!map)
		goto out;

	if (irq->dest_mode == 0) { /* physical mode */
		if (irq->delivery_mode == APIC_DM_LOWEST ||
				irq->dest_id == 0xff)
			goto out;
		dst = &map->phys_map[irq->dest_id & 0xff];
	} else {
		u32 mda = irq->dest_id << (32 - map->ldr_bits);

		dst = map->logical_map[apic_cluster_id(map, mda)];

		bitmap = apic_logical_id(map, mda);

		if (irq->delivery_mode == APIC_DM_LOWEST) {
			int l = -1;
			for_each_set_bit(i, &bitmap, 16) {
				if (!dst[i])
					continue;
				if (l < 0)
					l = i;
				else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
					l = i;
			}

			bitmap = (l >= 0) ? 1 << l : 0;
		}
	}

	for_each_set_bit(i, &bitmap, 16) {
		if (!dst[i])
			continue;
		if (*r < 0)
			*r = 0;
646
		*r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
647 648 649 650 651 652 653 654
	}

	ret = true;
out:
	rcu_read_unlock();
	return ret;
}

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/*
 * Add a pending IRQ into lapic.
 * Return 1 if successfully added and 0 if discarded.
 */
static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
660 661
			     int vector, int level, int trig_mode,
			     unsigned long *dest_map)
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{
663
	int result = 0;
664
	struct kvm_vcpu *vcpu = apic->vcpu;
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	switch (delivery_mode) {
	case APIC_DM_LOWEST:
668 669
		vcpu->arch.apic_arb_prio++;
	case APIC_DM_FIXED:
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		/* FIXME add logic for vcpu on reset */
		if (unlikely(!apic_enabled(apic)))
			break;

674 675
		result = 1;

676 677
		if (dest_map)
			__set_bit(vcpu->vcpu_id, dest_map);
678

679
		if (kvm_x86_ops->deliver_posted_interrupt)
680
			kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
681 682
		else {
			apic_set_irr(vector, apic);
683 684 685 686 687

			kvm_make_request(KVM_REQ_EVENT, vcpu);
			kvm_vcpu_kick(vcpu);
		}
		trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
688
					  trig_mode, vector, false);
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		break;

	case APIC_DM_REMRD:
692 693 694 695
		result = 1;
		vcpu->arch.pv.pv_unhalted = 1;
		kvm_make_request(KVM_REQ_EVENT, vcpu);
		kvm_vcpu_kick(vcpu);
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		break;

	case APIC_DM_SMI:
699
		apic_debug("Ignoring guest SMI\n");
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700
		break;
701

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702
	case APIC_DM_NMI:
703
		result = 1;
704
		kvm_inject_nmi(vcpu);
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Jan Kiszka 已提交
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		kvm_vcpu_kick(vcpu);
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		break;

	case APIC_DM_INIT:
709
		if (!trig_mode || level) {
710
			result = 1;
711 712 713 714 715
			/* assumes that there are only KVM_APIC_INIT/SIPI */
			apic->pending_events = (1UL << KVM_APIC_INIT);
			/* make sure pending_events is visible before sending
			 * the request */
			smp_wmb();
716
			kvm_make_request(KVM_REQ_EVENT, vcpu);
717 718
			kvm_vcpu_kick(vcpu);
		} else {
719 720
			apic_debug("Ignoring de-assert INIT to vcpu %d\n",
				   vcpu->vcpu_id);
721
		}
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		break;

	case APIC_DM_STARTUP:
725 726
		apic_debug("SIPI to vcpu %d vector 0x%02x\n",
			   vcpu->vcpu_id, vector);
727 728 729 730 731 732 733
		result = 1;
		apic->sipi_vector = vector;
		/* make sure sipi_vector is visible for the receiver */
		smp_wmb();
		set_bit(KVM_APIC_SIPI, &apic->pending_events);
		kvm_make_request(KVM_REQ_EVENT, vcpu);
		kvm_vcpu_kick(vcpu);
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		break;

736 737 738 739 740 741 742 743
	case APIC_DM_EXTINT:
		/*
		 * Should only be called by kvm_apic_local_deliver() with LVT0,
		 * before NMI watchdog was enabled. Already handled by
		 * kvm_apic_accept_pic_intr().
		 */
		break;

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	default:
		printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
		       delivery_mode);
		break;
	}
	return result;
}

752
int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
753
{
754
	return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
755 756
}

757 758 759 760 761 762 763 764 765
static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
{
	if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
	    kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
		int trigger_mode;
		if (apic_test_vector(vector, apic->regs + APIC_TMR))
			trigger_mode = IOAPIC_LEVEL_TRIG;
		else
			trigger_mode = IOAPIC_EDGE_TRIG;
766
		kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
767 768 769
	}
}

770
static int apic_set_eoi(struct kvm_lapic *apic)
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{
	int vector = apic_find_highest_isr(apic);
773 774 775

	trace_kvm_eoi(apic, vector);

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	/*
	 * Not every write EOI will has corresponding ISR,
	 * one example is when Kernel check timer on setup_IO_APIC
	 */
	if (vector == -1)
781
		return vector;
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M
Michael S. Tsirkin 已提交
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	apic_clear_isr(vector, apic);
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	apic_update_ppr(apic);

786
	kvm_ioapic_send_eoi(apic, vector);
787
	kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
788
	return vector;
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}

791 792 793 794 795 796 797 798 799 800 801 802 803 804 805
/*
 * this interface assumes a trap-like exit, which has already finished
 * desired side effect including vISR and vPPR update.
 */
void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
{
	struct kvm_lapic *apic = vcpu->arch.apic;

	trace_kvm_eoi(apic, vector);

	kvm_ioapic_send_eoi(apic, vector);
	kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
}
EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);

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static void apic_send_ipi(struct kvm_lapic *apic)
{
808 809
	u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
	u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
810
	struct kvm_lapic_irq irq;
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Eddie Dong 已提交
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812 813 814 815 816 817
	irq.vector = icr_low & APIC_VECTOR_MASK;
	irq.delivery_mode = icr_low & APIC_MODE_MASK;
	irq.dest_mode = icr_low & APIC_DEST_MASK;
	irq.level = icr_low & APIC_INT_ASSERT;
	irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
	irq.shorthand = icr_low & APIC_SHORT_MASK;
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	if (apic_x2apic_mode(apic))
		irq.dest_id = icr_high;
	else
		irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
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823 824
	trace_kvm_apic_ipi(icr_low, irq.dest_id);

E
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	apic_debug("icr_high 0x%x, icr_low 0x%x, "
		   "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
		   "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
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		   icr_high, icr_low, irq.shorthand, irq.dest_id,
829 830 831
		   irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
		   irq.vector);

832
	kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
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}

static u32 apic_get_tmcct(struct kvm_lapic *apic)
{
837 838
	ktime_t remaining;
	s64 ns;
839
	u32 tmcct;
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	ASSERT(apic != NULL);

843
	/* if initial count is 0, current count should also be 0 */
844
	if (kvm_apic_get_reg(apic, APIC_TMICT) == 0)
845 846
		return 0;

847
	remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
848 849 850
	if (ktime_to_ns(remaining) < 0)
		remaining = ktime_set(0, 0);

851 852 853
	ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
	tmcct = div64_u64(ns,
			 (APIC_BUS_CYCLE_NS * apic->divide_count));
E
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	return tmcct;
}

858 859 860 861 862
static void __report_tpr_access(struct kvm_lapic *apic, bool write)
{
	struct kvm_vcpu *vcpu = apic->vcpu;
	struct kvm_run *run = vcpu->run;

863
	kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
864
	run->tpr_access.rip = kvm_rip_read(vcpu);
865 866 867 868 869 870 871 872 873
	run->tpr_access.is_write = write;
}

static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
{
	if (apic->vcpu->arch.tpr_access_reporting)
		__report_tpr_access(apic, write);
}

E
Eddie Dong 已提交
874 875 876 877 878 879 880 881
static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
{
	u32 val = 0;

	if (offset >= LAPIC_MMIO_LENGTH)
		return 0;

	switch (offset) {
G
Gleb Natapov 已提交
882 883 884 885 886 887
	case APIC_ID:
		if (apic_x2apic_mode(apic))
			val = kvm_apic_id(apic);
		else
			val = kvm_apic_id(apic) << 24;
		break;
E
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888
	case APIC_ARBPRI:
889
		apic_debug("Access APIC ARBPRI register which is for P6\n");
E
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		break;

	case APIC_TMCCT:	/* Timer CCR */
893 894 895
		if (apic_lvtt_tscdeadline(apic))
			return 0;

E
Eddie Dong 已提交
896 897
		val = apic_get_tmcct(apic);
		break;
898 899
	case APIC_PROCPRI:
		apic_update_ppr(apic);
900
		val = kvm_apic_get_reg(apic, offset);
901
		break;
902 903 904
	case APIC_TASKPRI:
		report_tpr_access(apic, false);
		/* fall thru */
E
Eddie Dong 已提交
905
	default:
906
		val = kvm_apic_get_reg(apic, offset);
E
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907 908 909 910 911 912
		break;
	}

	return val;
}

G
Gregory Haskins 已提交
913 914 915 916 917
static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
{
	return container_of(dev, struct kvm_lapic, dev);
}

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static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
		void *data)
E
Eddie Dong 已提交
920 921 922
{
	unsigned char alignment = offset & 0xf;
	u32 result;
G
Guo Chao 已提交
923
	/* this bitmask has a bit cleared for each reserved register */
G
Gleb Natapov 已提交
924
	static const u64 rmask = 0x43ff01ffffffe70cULL;
E
Eddie Dong 已提交
925 926

	if ((alignment + len) > 4) {
927 928
		apic_debug("KVM_APIC_READ: alignment error %x %d\n",
			   offset, len);
G
Gleb Natapov 已提交
929
		return 1;
E
Eddie Dong 已提交
930
	}
G
Gleb Natapov 已提交
931 932

	if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
933 934
		apic_debug("KVM_APIC_READ: read reserved register %x\n",
			   offset);
G
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935 936 937
		return 1;
	}

E
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938 939
	result = __apic_read(apic, offset & ~0xf);

940 941
	trace_kvm_apic_read(offset, result);

E
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942 943 944 945 946 947 948 949 950 951 952
	switch (len) {
	case 1:
	case 2:
	case 4:
		memcpy(data, (char *)&result + alignment, len);
		break;
	default:
		printk(KERN_ERR "Local APIC read with len = %x, "
		       "should be 1,2, or 4 instead\n", len);
		break;
	}
953
	return 0;
E
Eddie Dong 已提交
954 955
}

G
Gleb Natapov 已提交
956 957
static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
{
958
	return kvm_apic_hw_enabled(apic) &&
G
Gleb Natapov 已提交
959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976
	    addr >= apic->base_address &&
	    addr < apic->base_address + LAPIC_MMIO_LENGTH;
}

static int apic_mmio_read(struct kvm_io_device *this,
			   gpa_t address, int len, void *data)
{
	struct kvm_lapic *apic = to_lapic(this);
	u32 offset = address - apic->base_address;

	if (!apic_mmio_in_range(apic, address))
		return -EOPNOTSUPP;

	apic_reg_read(apic, offset, len, data);

	return 0;
}

E
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977 978 979 980
static void update_divide_count(struct kvm_lapic *apic)
{
	u32 tmp1, tmp2, tdcr;

981
	tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
E
Eddie Dong 已提交
982 983
	tmp1 = tdcr & 0xf;
	tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
984
	apic->divide_count = 0x1 << (tmp2 & 0x7);
E
Eddie Dong 已提交
985 986

	apic_debug("timer divide count is 0x%x\n",
G
Glauber Costa 已提交
987
				   apic->divide_count);
E
Eddie Dong 已提交
988 989 990 991
}

static void start_apic_timer(struct kvm_lapic *apic)
{
992
	ktime_t now;
993
	atomic_set(&apic->lapic_timer.pending, 0);
994

995
	if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
G
Guo Chao 已提交
996
		/* lapic timer in oneshot or periodic mode */
997
		now = apic->lapic_timer.timer.base->get_time();
998
		apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018
			    * APIC_BUS_CYCLE_NS * apic->divide_count;

		if (!apic->lapic_timer.period)
			return;
		/*
		 * Do not allow the guest to program periodic timers with small
		 * interval, since the hrtimers are not throttled by the host
		 * scheduler.
		 */
		if (apic_lvtt_period(apic)) {
			s64 min_period = min_timer_period_us * 1000LL;

			if (apic->lapic_timer.period < min_period) {
				pr_info_ratelimited(
				    "kvm: vcpu %i: requested %lld ns "
				    "lapic timer period limited to %lld ns\n",
				    apic->vcpu->vcpu_id,
				    apic->lapic_timer.period, min_period);
				apic->lapic_timer.period = min_period;
			}
1019
		}
1020

1021 1022 1023
		hrtimer_start(&apic->lapic_timer.timer,
			      ktime_add_ns(now, apic->lapic_timer.period),
			      HRTIMER_MODE_ABS);
E
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1024

1025
		apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
E
Eddie Dong 已提交
1026 1027
			   PRIx64 ", "
			   "timer initial count 0x%x, period %lldns, "
1028
			   "expire @ 0x%016" PRIx64 ".\n", __func__,
E
Eddie Dong 已提交
1029
			   APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1030
			   kvm_apic_get_reg(apic, APIC_TMICT),
1031
			   apic->lapic_timer.period,
E
Eddie Dong 已提交
1032
			   ktime_to_ns(ktime_add_ns(now,
1033
					apic->lapic_timer.period)));
1034 1035 1036 1037 1038
	} else if (apic_lvtt_tscdeadline(apic)) {
		/* lapic timer in tsc deadline mode */
		u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
		u64 ns = 0;
		struct kvm_vcpu *vcpu = apic->vcpu;
1039
		unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1040 1041 1042 1043 1044 1045 1046 1047
		unsigned long flags;

		if (unlikely(!tscdeadline || !this_tsc_khz))
			return;

		local_irq_save(flags);

		now = apic->lapic_timer.timer.base->get_time();
1048
		guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1049 1050 1051 1052 1053 1054 1055 1056 1057
		if (likely(tscdeadline > guest_tsc)) {
			ns = (tscdeadline - guest_tsc) * 1000000ULL;
			do_div(ns, this_tsc_khz);
		}
		hrtimer_start(&apic->lapic_timer.timer,
			ktime_add_ns(now, ns), HRTIMER_MODE_ABS);

		local_irq_restore(flags);
	}
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}

1060 1061
static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
{
1062
	int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073

	if (apic_lvt_nmi_mode(lvt0_val)) {
		if (!nmi_wd_enabled) {
			apic_debug("Receive NMI setting on APIC_LVT0 "
				   "for cpu %d\n", apic->vcpu->vcpu_id);
			apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
		}
	} else if (nmi_wd_enabled)
		apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
}

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static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
E
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1075
{
G
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1076
	int ret = 0;
E
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1077

G
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1078
	trace_kvm_apic_write(reg, val);
E
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1079

G
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1080
	switch (reg) {
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1081
	case APIC_ID:		/* Local APIC ID */
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1082
		if (!apic_x2apic_mode(apic))
1083
			kvm_apic_set_id(apic, val >> 24);
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1084 1085
		else
			ret = 1;
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		break;

	case APIC_TASKPRI:
1089
		report_tpr_access(apic, true);
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		apic_set_tpr(apic, val & 0xff);
		break;

	case APIC_EOI:
		apic_set_eoi(apic);
		break;

	case APIC_LDR:
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		if (!apic_x2apic_mode(apic))
1099
			kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
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		else
			ret = 1;
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		break;

	case APIC_DFR:
1105
		if (!apic_x2apic_mode(apic)) {
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			apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1107 1108
			recalculate_apic_map(apic->vcpu->kvm);
		} else
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			ret = 1;
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		break;

1112 1113
	case APIC_SPIV: {
		u32 mask = 0x3ff;
1114
		if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1115
			mask |= APIC_SPIV_DIRECTED_EOI;
1116
		apic_set_spiv(apic, val & mask);
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1117 1118 1119 1120 1121
		if (!(val & APIC_SPIV_APIC_ENABLED)) {
			int i;
			u32 lvt_val;

			for (i = 0; i < APIC_LVT_NUM; i++) {
1122
				lvt_val = kvm_apic_get_reg(apic,
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1123 1124 1125 1126
						       APIC_LVTT + 0x10 * i);
				apic_set_reg(apic, APIC_LVTT + 0x10 * i,
					     lvt_val | APIC_LVT_MASKED);
			}
1127
			atomic_set(&apic->lapic_timer.pending, 0);
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		}
		break;
1131
	}
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	case APIC_ICR:
		/* No delay here, so we always clear the pending bit */
		apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
		apic_send_ipi(apic);
		break;

	case APIC_ICR2:
G
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		if (!apic_x2apic_mode(apic))
			val &= 0xff000000;
		apic_set_reg(apic, APIC_ICR2, val);
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		break;

1144
	case APIC_LVT0:
1145
		apic_manage_nmi_watchdog(apic, val);
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	case APIC_LVTTHMR:
	case APIC_LVTPC:
	case APIC_LVT1:
	case APIC_LVTERR:
		/* TODO: Check vector */
1151
		if (!kvm_apic_sw_enabled(apic))
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			val |= APIC_LVT_MASKED;

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		val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
		apic_set_reg(apic, reg, val);
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		break;

1159
	case APIC_LVTT:
1160
		if ((kvm_apic_get_reg(apic, APIC_LVTT) &
1161 1162 1163 1164
		    apic->lapic_timer.timer_mode_mask) !=
		   (val & apic->lapic_timer.timer_mode_mask))
			hrtimer_cancel(&apic->lapic_timer.timer);

1165
		if (!kvm_apic_sw_enabled(apic))
1166 1167 1168 1169 1170
			val |= APIC_LVT_MASKED;
		val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
		apic_set_reg(apic, APIC_LVTT, val);
		break;

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	case APIC_TMICT:
1172 1173 1174
		if (apic_lvtt_tscdeadline(apic))
			break;

1175
		hrtimer_cancel(&apic->lapic_timer.timer);
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		apic_set_reg(apic, APIC_TMICT, val);
		start_apic_timer(apic);
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		break;
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	case APIC_TDCR:
		if (val & 4)
1182
			apic_debug("KVM_WRITE:TDCR %x\n", val);
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		apic_set_reg(apic, APIC_TDCR, val);
		update_divide_count(apic);
		break;

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	case APIC_ESR:
		if (apic_x2apic_mode(apic) && val != 0) {
1189
			apic_debug("KVM_WRITE:ESR not zero %x\n", val);
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			ret = 1;
		}
		break;

	case APIC_SELF_IPI:
		if (apic_x2apic_mode(apic)) {
			apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
		} else
			ret = 1;
		break;
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1200
	default:
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1201
		ret = 1;
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		break;
	}
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	if (ret)
		apic_debug("Local APIC Write to read-only register %x\n", reg);
	return ret;
}

static int apic_mmio_write(struct kvm_io_device *this,
			    gpa_t address, int len, const void *data)
{
	struct kvm_lapic *apic = to_lapic(this);
	unsigned int offset = address - apic->base_address;
	u32 val;

	if (!apic_mmio_in_range(apic, address))
		return -EOPNOTSUPP;

	/*
	 * APIC register must be aligned on 128-bits boundary.
	 * 32/64/128 bits registers must be accessed thru 32 bits.
	 * Refer SDM 8.4.1
	 */
	if (len != 4 || (offset & 0xf)) {
		/* Don't shout loud, $infamous_os would cause only noise. */
		apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1227
		return 0;
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	}

	val = *(u32*)data;

	/* too common printing */
	if (offset != APIC_EOI)
		apic_debug("%s: offset 0x%x with length 0x%x, and value is "
			   "0x%x\n", __func__, offset, len, val);

	apic_reg_write(apic, offset & 0xff0, val);

1239
	return 0;
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}

1242 1243
void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
{
1244
	if (kvm_vcpu_has_lapic(vcpu))
1245 1246 1247 1248
		apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
}
EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);

1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263
/* emulate APIC access in a trap manner */
void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
{
	u32 val = 0;

	/* hw has done the conditional check and inst decode */
	offset &= 0xff0;

	apic_reg_read(vcpu->arch.apic, offset, 4, &val);

	/* TODO: optimize to just emulate side effect w/o one more write */
	apic_reg_write(vcpu->arch.apic, offset, val);
}
EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);

1264
void kvm_free_lapic(struct kvm_vcpu *vcpu)
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{
1266 1267
	struct kvm_lapic *apic = vcpu->arch.apic;

1268
	if (!vcpu->arch.apic)
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1269 1270
		return;

1271
	hrtimer_cancel(&apic->lapic_timer.timer);
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1273 1274 1275
	if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
		static_key_slow_dec_deferred(&apic_hw_disabled);

1276
	if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED))
1277
		static_key_slow_dec_deferred(&apic_sw_disabled);
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1279 1280 1281 1282
	if (apic->regs)
		free_page((unsigned long)apic->regs);

	kfree(apic);
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}

/*
 *----------------------------------------------------------------------
 * LAPIC interface
 *----------------------------------------------------------------------
 */

1291 1292 1293 1294
u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
{
	struct kvm_lapic *apic = vcpu->arch.apic;

1295
	if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1296
			apic_lvtt_period(apic))
1297 1298 1299 1300 1301 1302 1303 1304 1305
		return 0;

	return apic->lapic_timer.tscdeadline;
}

void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
{
	struct kvm_lapic *apic = vcpu->arch.apic;

1306
	if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1307
			apic_lvtt_period(apic))
1308 1309 1310 1311 1312 1313 1314
		return;

	hrtimer_cancel(&apic->lapic_timer.timer);
	apic->lapic_timer.tscdeadline = data;
	start_apic_timer(apic);
}

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void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
{
1317
	struct kvm_lapic *apic = vcpu->arch.apic;
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1319
	if (!kvm_vcpu_has_lapic(vcpu))
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1320
		return;
1321

A
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1322
	apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1323
		     | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
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}

u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
{
	u64 tpr;

1330
	if (!kvm_vcpu_has_lapic(vcpu))
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		return 0;
1332

1333
	tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
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	return (tpr & 0xf0) >> 4;
}

void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
{
1340
	u64 old_value = vcpu->arch.apic_base;
1341
	struct kvm_lapic *apic = vcpu->arch.apic;
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1342 1343 1344

	if (!apic) {
		value |= MSR_IA32_APICBASE_BSP;
1345
		vcpu->arch.apic_base = value;
E
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1346 1347
		return;
	}
1348

1349 1350 1351 1352 1353 1354
	/* update jump label if enable bit changes */
	if ((vcpu->arch.apic_base ^ value) & MSR_IA32_APICBASE_ENABLE) {
		if (value & MSR_IA32_APICBASE_ENABLE)
			static_key_slow_dec_deferred(&apic_hw_disabled);
		else
			static_key_slow_inc(&apic_hw_disabled.key);
1355
		recalculate_apic_map(vcpu->kvm);
1356 1357
	}

1358
	if (!kvm_vcpu_is_bsp(apic->vcpu))
E
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1359 1360
		value &= ~MSR_IA32_APICBASE_BSP;

1361
	vcpu->arch.apic_base = value;
1362 1363 1364 1365 1366 1367 1368 1369
	if ((old_value ^ value) & X2APIC_ENABLE) {
		if (value & X2APIC_ENABLE) {
			u32 id = kvm_apic_id(apic);
			u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
			kvm_apic_set_ldr(apic, ldr);
			kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
		} else
			kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
G
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1370
	}
1371

1372
	apic->base_address = apic->vcpu->arch.apic_base &
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			     MSR_IA32_APICBASE_BASE;

	/* with FSB delivery interrupt, we can restart APIC functionality */
	apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1377
		   "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
E
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1378 1379 1380

}

1381
void kvm_lapic_reset(struct kvm_vcpu *vcpu)
E
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1382 1383 1384 1385
{
	struct kvm_lapic *apic;
	int i;

1386
	apic_debug("%s\n", __func__);
E
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1387 1388

	ASSERT(vcpu);
1389
	apic = vcpu->arch.apic;
E
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1390 1391 1392
	ASSERT(apic != NULL);

	/* Stop the timer in case it's a reset to an active apic */
1393
	hrtimer_cancel(&apic->lapic_timer.timer);
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1394

1395
	kvm_apic_set_id(apic, vcpu->vcpu_id);
1396
	kvm_apic_set_version(apic->vcpu);
E
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	for (i = 0; i < APIC_LVT_NUM; i++)
		apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
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	apic_set_reg(apic, APIC_LVT0,
		     SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
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1402 1403

	apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1404
	apic_set_spiv(apic, 0xff);
E
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1405
	apic_set_reg(apic, APIC_TASKPRI, 0);
1406
	kvm_apic_set_ldr(apic, 0);
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	apic_set_reg(apic, APIC_ESR, 0);
	apic_set_reg(apic, APIC_ICR, 0);
	apic_set_reg(apic, APIC_ICR2, 0);
	apic_set_reg(apic, APIC_TDCR, 0);
	apic_set_reg(apic, APIC_TMICT, 0);
	for (i = 0; i < 8; i++) {
		apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
		apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
		apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
	}
1417 1418
	apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
	apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
M
Michael S. Tsirkin 已提交
1419
	apic->highest_isr_cache = -1;
1420
	update_divide_count(apic);
1421
	atomic_set(&apic->lapic_timer.pending, 0);
1422
	if (kvm_vcpu_is_bsp(vcpu))
1423 1424
		kvm_lapic_set_base(vcpu,
				vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1425
	vcpu->arch.pv_eoi.msr_val = 0;
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1426 1427
	apic_update_ppr(apic);

1428
	vcpu->arch.apic_arb_prio = 0;
1429
	vcpu->arch.apic_attention = 0;
1430

E
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	apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1432
		   "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
E
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1433
		   vcpu, kvm_apic_id(apic),
1434
		   vcpu->arch.apic_base, apic->base_address);
E
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1435 1436 1437 1438 1439 1440 1441
}

/*
 *----------------------------------------------------------------------
 * timer interface
 *----------------------------------------------------------------------
 */
1442

A
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1443
static bool lapic_is_periodic(struct kvm_lapic *apic)
E
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1444
{
1445
	return apic_lvtt_period(apic);
E
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1446 1447
}

1448 1449
int apic_has_pending_timer(struct kvm_vcpu *vcpu)
{
1450
	struct kvm_lapic *apic = vcpu->arch.apic;
1451

1452
	if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1453 1454
			apic_lvt_enabled(apic, APIC_LVTT))
		return atomic_read(&apic->lapic_timer.pending);
1455 1456 1457 1458

	return 0;
}

A
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1459
int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1460
{
1461
	u32 reg = kvm_apic_get_reg(apic, lvt_type);
1462 1463
	int vector, mode, trig_mode;

1464
	if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1465 1466 1467
		vector = reg & APIC_VECTOR_MASK;
		mode = reg & APIC_MODE_MASK;
		trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1468 1469
		return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
					NULL);
1470 1471 1472
	}
	return 0;
}
1473

1474
void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1475
{
1476 1477 1478 1479
	struct kvm_lapic *apic = vcpu->arch.apic;

	if (apic)
		kvm_apic_local_deliver(apic, APIC_LVT0);
1480 1481
}

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static const struct kvm_io_device_ops apic_mmio_ops = {
	.read     = apic_mmio_read,
	.write    = apic_mmio_write,
};

1487 1488 1489
static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
{
	struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
A
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1490 1491
	struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
	struct kvm_vcpu *vcpu = apic->vcpu;
1492 1493 1494 1495 1496 1497 1498 1499
	wait_queue_head_t *q = &vcpu->wq;

	/*
	 * There is a race window between reading and incrementing, but we do
	 * not care about potentially losing timer events in the !reinject
	 * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked
	 * in vcpu_enter_guest.
	 */
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Avi Kivity 已提交
1500
	if (!atomic_read(&ktimer->pending)) {
1501 1502 1503 1504 1505 1506 1507 1508
		atomic_inc(&ktimer->pending);
		/* FIXME: this code should not know anything about vcpus */
		kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
	}

	if (waitqueue_active(q))
		wake_up_interruptible(q);

A
Avi Kivity 已提交
1509
	if (lapic_is_periodic(apic)) {
1510 1511 1512 1513 1514 1515
		hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
		return HRTIMER_RESTART;
	} else
		return HRTIMER_NORESTART;
}

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int kvm_create_lapic(struct kvm_vcpu *vcpu)
{
	struct kvm_lapic *apic;

	ASSERT(vcpu != NULL);
	apic_debug("apic_init %d\n", vcpu->vcpu_id);

	apic = kzalloc(sizeof(*apic), GFP_KERNEL);
	if (!apic)
		goto nomem;

1527
	vcpu->arch.apic = apic;
E
Eddie Dong 已提交
1528

1529 1530
	apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
	if (!apic->regs) {
E
Eddie Dong 已提交
1531 1532
		printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
		       vcpu->vcpu_id);
1533
		goto nomem_free_apic;
E
Eddie Dong 已提交
1534 1535 1536
	}
	apic->vcpu = vcpu;

1537 1538
	hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
		     HRTIMER_MODE_ABS);
1539
	apic->lapic_timer.timer.function = apic_timer_fn;
1540

1541 1542 1543 1544 1545
	/*
	 * APIC is created enabled. This will prevent kvm_lapic_set_base from
	 * thinking that APIC satet has changed.
	 */
	vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1546 1547
	kvm_lapic_set_base(vcpu,
			APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
E
Eddie Dong 已提交
1548

1549
	static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1550
	kvm_lapic_reset(vcpu);
G
Gregory Haskins 已提交
1551
	kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
E
Eddie Dong 已提交
1552 1553

	return 0;
1554 1555
nomem_free_apic:
	kfree(apic);
E
Eddie Dong 已提交
1556 1557 1558 1559 1560 1561
nomem:
	return -ENOMEM;
}

int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
{
1562
	struct kvm_lapic *apic = vcpu->arch.apic;
E
Eddie Dong 已提交
1563 1564
	int highest_irr;

1565
	if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
E
Eddie Dong 已提交
1566 1567
		return -1;

1568
	apic_update_ppr(apic);
E
Eddie Dong 已提交
1569 1570
	highest_irr = apic_find_highest_irr(apic);
	if ((highest_irr == -1) ||
1571
	    ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
E
Eddie Dong 已提交
1572 1573 1574 1575
		return -1;
	return highest_irr;
}

Q
Qing He 已提交
1576 1577
int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
{
1578
	u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
Q
Qing He 已提交
1579 1580
	int r = 0;

1581
	if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1582 1583 1584 1585
		r = 1;
	if ((lvt0 & APIC_LVT_MASKED) == 0 &&
	    GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
		r = 1;
Q
Qing He 已提交
1586 1587 1588
	return r;
}

1589 1590
void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
{
1591
	struct kvm_lapic *apic = vcpu->arch.apic;
1592

1593
	if (!kvm_vcpu_has_lapic(vcpu))
1594 1595 1596
		return;

	if (atomic_read(&apic->lapic_timer.pending) > 0) {
1597 1598
		kvm_apic_local_deliver(apic, APIC_LVTT);
		atomic_set(&apic->lapic_timer.pending, 0);
1599 1600 1601
	}
}

E
Eddie Dong 已提交
1602 1603 1604
int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
{
	int vector = kvm_apic_has_interrupt(vcpu);
1605
	struct kvm_lapic *apic = vcpu->arch.apic;
E
Eddie Dong 已提交
1606 1607 1608 1609

	if (vector == -1)
		return -1;

M
Michael S. Tsirkin 已提交
1610
	apic_set_isr(vector, apic);
E
Eddie Dong 已提交
1611 1612 1613 1614
	apic_update_ppr(apic);
	apic_clear_irr(vector, apic);
	return vector;
}
1615

1616 1617
void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
		struct kvm_lapic_state *s)
1618
{
1619
	struct kvm_lapic *apic = vcpu->arch.apic;
1620

1621
	kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1622 1623 1624
	/* set SPIV separately to get count of SW disabled APICs right */
	apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
	memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1625 1626
	/* call kvm_apic_set_id() to put apic into apic_map */
	kvm_apic_set_id(apic, kvm_apic_id(apic));
1627 1628
	kvm_apic_set_version(vcpu);

1629
	apic_update_ppr(apic);
1630
	hrtimer_cancel(&apic->lapic_timer.timer);
1631 1632
	update_divide_count(apic);
	start_apic_timer(apic);
1633
	apic->irr_pending = true;
1634 1635
	apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
				1 : count_vectors(apic->regs + APIC_ISR);
M
Michael S. Tsirkin 已提交
1636
	apic->highest_isr_cache = -1;
1637
	kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1638
	kvm_make_request(KVM_REQ_EVENT, vcpu);
1639
	kvm_rtc_eoi_tracking_restore_one(vcpu);
1640
}
1641

1642
void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1643 1644 1645
{
	struct hrtimer *timer;

1646
	if (!kvm_vcpu_has_lapic(vcpu))
1647 1648
		return;

1649
	timer = &vcpu->arch.apic->lapic_timer.timer;
1650
	if (hrtimer_cancel(timer))
1651
		hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1652
}
A
Avi Kivity 已提交
1653

1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690
/*
 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
 *
 * Detect whether guest triggered PV EOI since the
 * last entry. If yes, set EOI on guests's behalf.
 * Clear PV EOI in guest memory in any case.
 */
static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
					struct kvm_lapic *apic)
{
	bool pending;
	int vector;
	/*
	 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
	 * and KVM_PV_EOI_ENABLED in guest memory as follows:
	 *
	 * KVM_APIC_PV_EOI_PENDING is unset:
	 * 	-> host disabled PV EOI.
	 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
	 * 	-> host enabled PV EOI, guest did not execute EOI yet.
	 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
	 * 	-> host enabled PV EOI, guest executed EOI.
	 */
	BUG_ON(!pv_eoi_enabled(vcpu));
	pending = pv_eoi_get_pending(vcpu);
	/*
	 * Clear pending bit in any case: it will be set again on vmentry.
	 * While this might not be ideal from performance point of view,
	 * this makes sure pv eoi is only enabled when we know it's safe.
	 */
	pv_eoi_clr_pending(vcpu);
	if (pending)
		return;
	vector = apic_set_eoi(apic);
	trace_kvm_pv_eoi(apic, vector);
}

A
Avi Kivity 已提交
1691 1692 1693 1694 1695
void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
{
	u32 data;
	void *vapic;

1696 1697 1698
	if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
		apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);

1699
	if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
A
Avi Kivity 已提交
1700 1701
		return;

1702
	vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
A
Avi Kivity 已提交
1703
	data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1704
	kunmap_atomic(vapic);
A
Avi Kivity 已提交
1705 1706 1707 1708

	apic_set_tpr(vcpu->arch.apic, data & 0xff);
}

1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734
/*
 * apic_sync_pv_eoi_to_guest - called before vmentry
 *
 * Detect whether it's safe to enable PV EOI and
 * if yes do so.
 */
static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
					struct kvm_lapic *apic)
{
	if (!pv_eoi_enabled(vcpu) ||
	    /* IRR set or many bits in ISR: could be nested. */
	    apic->irr_pending ||
	    /* Cache not set: could be safe but we don't bother. */
	    apic->highest_isr_cache == -1 ||
	    /* Need EOI to update ioapic. */
	    kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
		/*
		 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
		 * so we need not do anything here.
		 */
		return;
	}

	pv_eoi_set_pending(apic->vcpu);
}

A
Avi Kivity 已提交
1735 1736 1737 1738
void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
{
	u32 data, tpr;
	int max_irr, max_isr;
1739
	struct kvm_lapic *apic = vcpu->arch.apic;
A
Avi Kivity 已提交
1740 1741
	void *vapic;

1742 1743
	apic_sync_pv_eoi_to_guest(vcpu, apic);

1744
	if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
A
Avi Kivity 已提交
1745 1746
		return;

1747
	tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
A
Avi Kivity 已提交
1748 1749 1750 1751 1752 1753 1754 1755
	max_irr = apic_find_highest_irr(apic);
	if (max_irr < 0)
		max_irr = 0;
	max_isr = apic_find_highest_isr(apic);
	if (max_isr < 0)
		max_isr = 0;
	data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);

1756
	vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
A
Avi Kivity 已提交
1757
	*(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1758
	kunmap_atomic(vapic);
A
Avi Kivity 已提交
1759 1760 1761 1762 1763
}

void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
{
	vcpu->arch.apic->vapic_addr = vapic_addr;
1764 1765 1766 1767
	if (vapic_addr)
		__set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
	else
		__clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
A
Avi Kivity 已提交
1768
}
G
Gleb Natapov 已提交
1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800

int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
{
	struct kvm_lapic *apic = vcpu->arch.apic;
	u32 reg = (msr - APIC_BASE_MSR) << 4;

	if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
		return 1;

	/* if this is ICR write vector before command */
	if (msr == 0x830)
		apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
	return apic_reg_write(apic, reg, (u32)data);
}

int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
{
	struct kvm_lapic *apic = vcpu->arch.apic;
	u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;

	if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
		return 1;

	if (apic_reg_read(apic, reg, 4, &low))
		return 1;
	if (msr == 0x830)
		apic_reg_read(apic, APIC_ICR2, 4, &high);

	*data = (((u64)high) << 32) | low;

	return 0;
}
G
Gleb Natapov 已提交
1801 1802 1803 1804 1805

int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
{
	struct kvm_lapic *apic = vcpu->arch.apic;

1806
	if (!kvm_vcpu_has_lapic(vcpu))
G
Gleb Natapov 已提交
1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819
		return 1;

	/* if this is ICR write vector before command */
	if (reg == APIC_ICR)
		apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
	return apic_reg_write(apic, reg, (u32)data);
}

int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
{
	struct kvm_lapic *apic = vcpu->arch.apic;
	u32 low, high = 0;

1820
	if (!kvm_vcpu_has_lapic(vcpu))
G
Gleb Natapov 已提交
1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831
		return 1;

	if (apic_reg_read(apic, reg, 4, &low))
		return 1;
	if (reg == APIC_ICR)
		apic_reg_read(apic, APIC_ICR2, 4, &high);

	*data = (((u64)high) << 32) | low;

	return 0;
}
1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842

int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
{
	u64 addr = data & ~KVM_MSR_ENABLED;
	if (!IS_ALIGNED(addr, 4))
		return 1;

	vcpu->arch.pv_eoi.msr_val = data;
	if (!pv_eoi_enabled(vcpu))
		return 0;
	return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1843
					 addr, sizeof(u8));
1844
}
1845

1846 1847 1848 1849
void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
{
	struct kvm_lapic *apic = vcpu->arch.apic;
	unsigned int sipi_vector;
1850
	unsigned long pe;
1851

1852
	if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1853 1854
		return;

1855 1856 1857
	pe = xchg(&apic->pending_events, 0);

	if (test_bit(KVM_APIC_INIT, &pe)) {
1858 1859 1860 1861 1862 1863 1864
		kvm_lapic_reset(vcpu);
		kvm_vcpu_reset(vcpu);
		if (kvm_vcpu_is_bsp(apic->vcpu))
			vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
		else
			vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
	}
1865
	if (test_bit(KVM_APIC_SIPI, &pe) &&
1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876
	    vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
		/* evaluate pending_events before reading the vector */
		smp_rmb();
		sipi_vector = apic->sipi_vector;
		pr_debug("vcpu %d received sipi with vector # %x\n",
			 vcpu->vcpu_id, sipi_vector);
		kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
		vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
	}
}

1877 1878 1879 1880
void kvm_lapic_init(void)
{
	/* do not patch jump label more than once per second */
	jump_label_rate_limit(&apic_hw_disabled, HZ);
1881
	jump_label_rate_limit(&apic_sw_disabled, HZ);
1882
}