gef_sbc610.dts

/*
 * GE Fanuc SBC610 Device Tree Source
 *
 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Based on: SBS CM6 Device Tree Source
 * Copyright 2007 SBS Technologies GmbH & Co. KG
 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
 * Copyright 2006 Freescale Semiconductor Inc.
 */

/*
 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
 */

/dts-v1/;

/ {
	model = "GEF_SBC610";
	compatible = "gef,sbc610";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8641@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <32768>;		// L1, 32K
			i-cache-size = <32768>;		// L1, 32K
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
		PowerPC,8641@1 {
			device_type = "cpu";
			reg = <1>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <32768>;		// L1, 32K
			i-cache-size = <32768>;		// L1, 32K
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x40000000>;	// set by uboot
	};

	localbus@fef05000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8641-localbus", "simple-bus";
		reg = <0xf8005000 0x1000>;
		interrupts = <19 2>;
		interrupt-parent = <&mpic>;

		ranges = <0 0 0xff000000 0x01000000     // 16MB Boot flash
			  1 0 0xe8000000 0x08000000     // Paged Flash 0
			  2 0 0xe0000000 0x08000000     // Paged Flash 1
			  3 0 0xfc100000 0x00020000     // NVRAM
			  4 0 0xfc000000 0x00008000     // FPGA
			  5 0 0xfc008000 0x00008000     // AFIX FPGA
			  6 0 0xfd000000 0x00800000     // IO FPGA (8-bit)
			  7 0 0xfd800000 0x00800000>;   // IO FPGA (32-bit)

		fpga@4,0 {
			compatible = "gef,fpga-regs";
			reg = <0x4 0x0 0x40>;
		};
		gef_pic: pic@4,4000 {
			#interrupt-cells = <1>;
			interrupt-controller;
			compatible = "gef,fpga-pic";
			reg = <0x4 0x4000 0x20>;
			interrupts = <0x8
				      0x9>;
			interrupt-parent = <&mpic>;

		};
	};

	soc@fef00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xfef00000 0x00100000>;
		reg = <0xfef00000 0x100000>;	// CCSRBAR 1M
		bus-frequency = <33333333>;

		i2c1: i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			eti@6b {
				compatible = "dallas,ds1682";
				reg = <0x6b>;
			};
		};

		i2c2: i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8641-dma-channel",
					   "fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8641-dma-channel",
					   "fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8641-dma-channel",
					   "fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8641-dma-channel",
					   "fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;

			phy0: ethernet-phy@0 {
				interrupt-parent = <&gef_pic>;
				interrupts = <0x9 0x4>;
				reg = <1>;
			};
			phy2: ethernet-phy@2 {
				interrupt-parent = <&gef_pic>;
				interrupts = <0x8 0x4>;
				reg = <3>;
			};
		};

		enet0: ethernet@24000 {
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
			phy-connection-type = "gmii";
		};

		enet1: ethernet@26000 {
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy2>;
			phy-connection-type = "gmii";
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <0x2a 0x2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <0x1c 0x2>;
			interrupt-parent = <&mpic>;
		};

		mpic: pic@40000 {
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		global-utilities@e0000 {
			compatible = "fsl,mpc8641-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};
	};

	pci0: pcie@fef08000 {
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xfef08000 0x1000>;
		bus-range = <0x0 0xff>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
			  0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <0x18 0x2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
		>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0x80000000
				  0x02000000 0x0 0x80000000
				  0x0 0x40000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00400000>;
		};
	};
};