i915_irq.c 71.8 KB
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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/* For display hotplug interrupt */
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static void
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ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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	if ((dev_priv->irq_mask & mask) != 0) {
		dev_priv->irq_mask &= ~mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

static inline void
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ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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	if ((dev_priv->irq_mask & mask) != mask) {
		dev_priv->irq_mask |= mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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void
i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
{
	if ((dev_priv->pipestat[pipe] & mask) != mask) {
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		u32 reg = PIPESTAT(pipe);
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		dev_priv->pipestat[pipe] |= mask;
		/* Enable the interrupt, clear any pending status */
		I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
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		POSTING_READ(reg);
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	}
}

void
i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
{
	if ((dev_priv->pipestat[pipe] & mask) != 0) {
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		u32 reg = PIPESTAT(pipe);
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		dev_priv->pipestat[pipe] &= ~mask;
		I915_WRITE(reg, dev_priv->pipestat[pipe]);
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		POSTING_READ(reg);
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	}
}

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/**
 * intel_enable_asle - enable ASLE interrupt for OpRegion
 */
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void intel_enable_asle(struct drm_device *dev)
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{
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	drm_i915_private_t *dev_priv = dev->dev_private;
	unsigned long irqflags;

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	/* FIXME: opregion/asle for VLV */
	if (IS_VALLEYVIEW(dev))
		return;

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	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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	if (HAS_PCH_SPLIT(dev))
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		ironlake_enable_display_irq(dev_priv, DE_GSE);
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	else {
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		i915_enable_pipestat(dev_priv, 1,
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				     PIPE_LEGACY_BLC_EVENT_ENABLE);
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		if (INTEL_INFO(dev)->gen >= 4)
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			i915_enable_pipestat(dev_priv, 0,
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					     PIPE_LEGACY_BLC_EVENT_ENABLE);
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	}
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	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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}

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/**
 * i915_pipe_enabled - check if a pipe is enabled
 * @dev: DRM device
 * @pipe: pipe to check
 *
 * Reading certain registers when the pipe is disabled can hang the chip.
 * Use this routine to make sure the PLL is running and the pipe is active
 * before reading such registers if unsure.
 */
static int
i915_pipe_enabled(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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	return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
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}

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/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
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static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
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{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long high_frame;
	unsigned long low_frame;
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	u32 high1, high2, low;
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	if (!i915_pipe_enabled(dev, pipe)) {
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		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
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				"pipe %c\n", pipe_name(pipe));
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		return 0;
	}

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	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
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	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
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		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
		low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
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	} while (high1 != high2);

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	high1 >>= PIPE_FRAME_HIGH_SHIFT;
	low >>= PIPE_FRAME_LOW_SHIFT;
	return (high1 << 8) | low;
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}

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static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
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{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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	int reg = PIPE_FRMCOUNT_GM45(pipe);
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	if (!i915_pipe_enabled(dev, pipe)) {
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		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
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				 "pipe %c\n", pipe_name(pipe));
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		return 0;
	}

	return I915_READ(reg);
}

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static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
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			     int *vpos, int *hpos)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 vbl = 0, position = 0;
	int vbl_start, vbl_end, htotal, vtotal;
	bool in_vbl = true;
	int ret = 0;

	if (!i915_pipe_enabled(dev, pipe)) {
		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
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				 "pipe %c\n", pipe_name(pipe));
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		return 0;
	}

	/* Get vtotal. */
	vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);

	if (INTEL_INFO(dev)->gen >= 4) {
		/* No obvious pixelcount register. Only query vertical
		 * scanout position from Display scan line register.
		 */
		position = I915_READ(PIPEDSL(pipe));

		/* Decode into vertical scanout position. Don't have
		 * horizontal scanout position.
		 */
		*vpos = position & 0x1fff;
		*hpos = 0;
	} else {
		/* Have access to pixelcount since start of frame.
		 * We can split this into vertical and horizontal
		 * scanout position.
		 */
		position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;

		htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
		*vpos = position / htotal;
		*hpos = position - (*vpos * htotal);
	}

	/* Query vblank area. */
	vbl = I915_READ(VBLANK(pipe));

	/* Test position against vblank region. */
	vbl_start = vbl & 0x1fff;
	vbl_end = (vbl >> 16) & 0x1fff;

	if ((*vpos < vbl_start) || (*vpos > vbl_end))
		in_vbl = false;

	/* Inside "upper part" of vblank area? Apply corrective offset: */
	if (in_vbl && (*vpos >= vbl_start))
		*vpos = *vpos - vtotal;

	/* Readouts valid? */
	if (vbl > 0)
		ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;

	/* In vblank? */
	if (in_vbl)
		ret |= DRM_SCANOUTPOS_INVBL;

	return ret;
}

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static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
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			      int *max_error,
			      struct timeval *vblank_time,
			      unsigned flags)
{
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	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
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	if (pipe < 0 || pipe >= dev_priv->num_pipe) {
		DRM_ERROR("Invalid crtc %d\n", pipe);
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		return -EINVAL;
	}

	/* Get drm_crtc to timestamp: */
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	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc == NULL) {
		DRM_ERROR("Invalid crtc %d\n", pipe);
		return -EINVAL;
	}

	if (!crtc->enabled) {
		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
		return -EBUSY;
	}
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	/* Helper routine in DRM core does all the work: */
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	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
						     vblank_time, flags,
						     crtc);
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}

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/*
 * Handle hotplug events outside the interrupt handler proper.
 */
static void i915_hotplug_work_func(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
						    hotplug_work);
	struct drm_device *dev = dev_priv->dev;
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	struct drm_mode_config *mode_config = &dev->mode_config;
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	struct intel_encoder *encoder;

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	mutex_lock(&mode_config->mutex);
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	DRM_DEBUG_KMS("running encoder hotplug functions\n");

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	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
		if (encoder->hot_plug)
			encoder->hot_plug(encoder);

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	mutex_unlock(&mode_config->mutex);

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	/* Just fire off a uevent and let userspace tell us what to do */
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	drm_helper_hpd_irq_event(dev);
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}

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static void i915_handle_rps_change(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
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	u32 busy_up, busy_down, max_avg, min_avg;
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	u8 new_delay = dev_priv->cur_delay;

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	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
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	busy_up = I915_READ(RCPREVBSYTUPAVG);
	busy_down = I915_READ(RCPREVBSYTDNAVG);
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	max_avg = I915_READ(RCBMAXAVG);
	min_avg = I915_READ(RCBMINAVG);

	/* Handle RCS change request from hw */
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	if (busy_up > max_avg) {
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		if (dev_priv->cur_delay != dev_priv->max_delay)
			new_delay = dev_priv->cur_delay - 1;
		if (new_delay < dev_priv->max_delay)
			new_delay = dev_priv->max_delay;
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	} else if (busy_down < min_avg) {
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		if (dev_priv->cur_delay != dev_priv->min_delay)
			new_delay = dev_priv->cur_delay + 1;
		if (new_delay > dev_priv->min_delay)
			new_delay = dev_priv->min_delay;
	}

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	if (ironlake_set_drps(dev, new_delay))
		dev_priv->cur_delay = new_delay;
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	return;
}

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static void notify_ring(struct drm_device *dev,
			struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (ring->obj == NULL)
		return;

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	trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
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	wake_up_all(&ring->irq_queue);
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	if (i915_enable_hangcheck) {
		dev_priv->hangcheck_count = 0;
		mod_timer(&dev_priv->hangcheck_timer,
			  jiffies +
			  msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
	}
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}

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static void gen6_pm_rps_work(struct work_struct *work)
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{
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	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
						    rps_work);
	u32 pm_iir, pm_imr;
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	u8 new_delay;
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	spin_lock_irq(&dev_priv->rps_lock);
	pm_iir = dev_priv->pm_iir;
	dev_priv->pm_iir = 0;
	pm_imr = I915_READ(GEN6_PMIMR);
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	I915_WRITE(GEN6_PMIMR, 0);
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	spin_unlock_irq(&dev_priv->rps_lock);
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	if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
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		return;

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	mutex_lock(&dev_priv->dev->struct_mutex);
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	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
		new_delay = dev_priv->cur_delay + 1;
	else
		new_delay = dev_priv->cur_delay - 1;
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	gen6_set_rps(dev_priv->dev, new_delay);
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	mutex_unlock(&dev_priv->dev->struct_mutex);
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}

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static void snb_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{

	if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
		      GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
		notify_ring(dev, &dev_priv->ring[RCS]);
	if (gt_iir & GEN6_BSD_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[VCS]);
	if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[BCS]);

	if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
		      GT_GEN6_BSD_CS_ERROR_INTERRUPT |
		      GT_RENDER_CS_ERROR_INTERRUPT)) {
		DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
		i915_handle_error(dev, false);
	}
}

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static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
				u32 pm_iir)
{
	unsigned long flags;

	/*
	 * IIR bits should never already be set because IMR should
	 * prevent an interrupt from being shown in IIR. The warning
	 * displays a case where we've unsafely cleared
	 * dev_priv->pm_iir. Although missing an interrupt of the same
	 * type is not a problem, it displays a problem in the logic.
	 *
	 * The mask bit in IMR is cleared by rps_work.
	 */

	spin_lock_irqsave(&dev_priv->rps_lock, flags);
	WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
	dev_priv->pm_iir |= pm_iir;
	I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
	POSTING_READ(GEN6_PMIMR);
	spin_unlock_irqrestore(&dev_priv->rps_lock, flags);

	queue_work(dev_priv->wq, &dev_priv->rps_work);
}

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static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir, gt_iir, pm_iir;
	irqreturn_t ret = IRQ_NONE;
	unsigned long irqflags;
	int pipe;
	u32 pipe_stats[I915_MAX_PIPES];
	u32 vblank_status;
	int vblank = 0;
	bool blc_event;

	atomic_inc(&dev_priv->irq_received);

	vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
		PIPE_VBLANK_INTERRUPT_STATUS;

	while (true) {
		iir = I915_READ(VLV_IIR);
		gt_iir = I915_READ(GTIIR);
		pm_iir = I915_READ(GEN6_PMIIR);

		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
			goto out;

		ret = IRQ_HANDLED;

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		snb_gt_irq_handler(dev, dev_priv, gt_iir);
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		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		/* Consume port.  Then clear IIR or we'll miss events */
		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);

			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
					 hotplug_status);
			if (hotplug_status & dev_priv->hotplug_supported_mask)
				queue_work(dev_priv->wq,
					   &dev_priv->hotplug_work);

			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
			I915_READ(PORT_HOTPLUG_STAT);
		}


		if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
			drm_handle_vblank(dev, 0);
			vblank++;
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			intel_finish_page_flip(dev, 0);
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		}

		if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
			drm_handle_vblank(dev, 1);
			vblank++;
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			intel_finish_page_flip(dev, 0);
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		}

		if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
			blc_event = true;

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		if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
			gen6_queue_rps_work(dev_priv, pm_iir);
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		I915_WRITE(GTIIR, gt_iir);
		I915_WRITE(GEN6_PMIIR, pm_iir);
		I915_WRITE(VLV_IIR, iir);
	}

out:
	return ret;
}

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static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
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{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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	int pipe;
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	if (pch_iir & SDE_AUDIO_POWER_MASK)
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
				 (pch_iir & SDE_AUDIO_POWER_MASK) >>
				 SDE_AUDIO_POWER_SHIFT);

	if (pch_iir & SDE_GMBUS)
		DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");

	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");

	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");

	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");

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	if (pch_iir & SDE_FDI_MASK)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
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	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");

	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");

	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
		DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
		DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
}

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static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
				 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
				 SDE_AUDIO_POWER_SHIFT_CPT);

	if (pch_iir & SDE_AUX_MASK_CPT)
		DRM_DEBUG_DRIVER("AUX channel interrupt\n");

	if (pch_iir & SDE_GMBUS_CPT)
		DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");

	if (pch_iir & SDE_FDI_MASK_CPT)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
}

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static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
583 584 585
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
586 587 588
	u32 de_iir, gt_iir, de_ier, pm_iir;
	irqreturn_t ret = IRQ_NONE;
	int i;
589 590 591 592 593 594 595 596

	atomic_inc(&dev_priv->irq_received);

	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);

	gt_iir = I915_READ(GTIIR);
597 598 599 600
	if (gt_iir) {
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
601 602
	}

603 604 605 606 607 608 609 610 611 612 613 614 615
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
		if (de_iir & DE_GSE_IVB)
			intel_opregion_gse_intr(dev);

		for (i = 0; i < 3; i++) {
			if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
				intel_prepare_page_flip(dev, i);
				intel_finish_page_flip_plane(dev, i);
			}
			if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
				drm_handle_vblank(dev, i);
		}
616

617 618 619
		/* check event from PCH */
		if (de_iir & DE_PCH_EVENT_IVB) {
			u32 pch_iir = I915_READ(SDEIIR);
620

621 622
			if (pch_iir & SDE_HOTPLUG_MASK_CPT)
				queue_work(dev_priv->wq, &dev_priv->hotplug_work);
623
			cpt_irq_handler(dev, pch_iir);
624

625 626 627
			/* clear PCH hotplug event before clear CPU irq */
			I915_WRITE(SDEIIR, pch_iir);
		}
628

629 630
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
631 632
	}

633 634 635 636 637 638 639
	pm_iir = I915_READ(GEN6_PMIIR);
	if (pm_iir) {
		if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
			gen6_queue_rps_work(dev_priv, pm_iir);
		I915_WRITE(GEN6_PMIIR, pm_iir);
		ret = IRQ_HANDLED;
	}
640 641 642 643 644 645 646

	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);

	return ret;
}

647 648 649 650 651 652 653 654 655 656
static void ilk_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{
	if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
		notify_ring(dev, &dev_priv->ring[RCS]);
	if (gt_iir & GT_BSD_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[VCS]);
}

657
static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
658
{
659
	struct drm_device *dev = (struct drm_device *) arg;
660 661
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int ret = IRQ_NONE;
662
	u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
663
	u32 hotplug_mask;
664

665 666
	atomic_inc(&dev_priv->irq_received);

667 668 669
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
670
	POSTING_READ(DEIER);
671

672 673
	de_iir = I915_READ(DEIIR);
	gt_iir = I915_READ(GTIIR);
674
	pch_iir = I915_READ(SDEIIR);
675
	pm_iir = I915_READ(GEN6_PMIIR);
676

677 678
	if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
	    (!IS_GEN6(dev) || pm_iir == 0))
679
		goto done;
680

681 682 683 684 685
	if (HAS_PCH_CPT(dev))
		hotplug_mask = SDE_HOTPLUG_MASK_CPT;
	else
		hotplug_mask = SDE_HOTPLUG_MASK;

686
	ret = IRQ_HANDLED;
687

688 689 690 691
	if (IS_GEN5(dev))
		ilk_gt_irq_handler(dev, dev_priv, gt_iir);
	else
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
692

693
	if (de_iir & DE_GSE)
694
		intel_opregion_gse_intr(dev);
695

696
	if (de_iir & DE_PLANEA_FLIP_DONE) {
697
		intel_prepare_page_flip(dev, 0);
698
		intel_finish_page_flip_plane(dev, 0);
699
	}
700

701
	if (de_iir & DE_PLANEB_FLIP_DONE) {
702
		intel_prepare_page_flip(dev, 1);
703
		intel_finish_page_flip_plane(dev, 1);
704
	}
705

706
	if (de_iir & DE_PIPEA_VBLANK)
707 708
		drm_handle_vblank(dev, 0);

709
	if (de_iir & DE_PIPEB_VBLANK)
710 711
		drm_handle_vblank(dev, 1);

712
	/* check event from PCH */
713 714 715
	if (de_iir & DE_PCH_EVENT) {
		if (pch_iir & hotplug_mask)
			queue_work(dev_priv->wq, &dev_priv->hotplug_work);
716 717 718 719
		if (HAS_PCH_CPT(dev))
			cpt_irq_handler(dev, pch_iir);
		else
			ibx_irq_handler(dev, pch_iir);
720
	}
721

722
	if (de_iir & DE_PCU_EVENT) {
723
		I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
724 725 726
		i915_handle_rps_change(dev);
	}

727 728
	if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
		gen6_queue_rps_work(dev_priv, pm_iir);
729

730 731 732 733
	/* should clear PCH hotplug event before clear CPU irq */
	I915_WRITE(SDEIIR, pch_iir);
	I915_WRITE(GTIIR, gt_iir);
	I915_WRITE(DEIIR, de_iir);
734
	I915_WRITE(GEN6_PMIIR, pm_iir);
735 736

done:
737
	I915_WRITE(DEIER, de_ier);
738
	POSTING_READ(DEIER);
739

740 741 742
	return ret;
}

743 744 745 746 747 748 749 750 751 752 753 754
/**
 * i915_error_work_func - do process context error handling work
 * @work: work struct
 *
 * Fire an error uevent so userspace can see that a hang or error
 * was detected.
 */
static void i915_error_work_func(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
						    error_work);
	struct drm_device *dev = dev_priv->dev;
755 756 757
	char *error_event[] = { "ERROR=1", NULL };
	char *reset_event[] = { "RESET=1", NULL };
	char *reset_done_event[] = { "ERROR=0", NULL };
758

759 760
	kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);

761
	if (atomic_read(&dev_priv->mm.wedged)) {
762 763
		DRM_DEBUG_DRIVER("resetting chip\n");
		kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
764
		if (!i915_reset(dev)) {
765 766
			atomic_set(&dev_priv->mm.wedged, 0);
			kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
767
		}
768
		complete_all(&dev_priv->error_completion);
769
	}
770 771
}

772
#ifdef CONFIG_DEBUG_FS
773
static struct drm_i915_error_object *
774
i915_error_object_create(struct drm_i915_private *dev_priv,
775
			 struct drm_i915_gem_object *src)
776 777 778
{
	struct drm_i915_error_object *dst;
	int page, page_count;
779
	u32 reloc_offset;
780

781
	if (src == NULL || src->pages == NULL)
782 783
		return NULL;

784
	page_count = src->base.size / PAGE_SIZE;
785

786
	dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
787 788 789
	if (dst == NULL)
		return NULL;

790
	reloc_offset = src->gtt_offset;
791
	for (page = 0; page < page_count; page++) {
792
		unsigned long flags;
793
		void *d;
794

795
		d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
796 797
		if (d == NULL)
			goto unwind;
798

799
		local_irq_save(flags);
800 801
		if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
		    src->has_global_gtt_mapping) {
802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823
			void __iomem *s;

			/* Simply ignore tiling or any overlapping fence.
			 * It's part of the error state, and this hopefully
			 * captures what the GPU read.
			 */

			s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
						     reloc_offset);
			memcpy_fromio(d, s, PAGE_SIZE);
			io_mapping_unmap_atomic(s);
		} else {
			void *s;

			drm_clflush_pages(&src->pages[page], 1);

			s = kmap_atomic(src->pages[page]);
			memcpy(d, s, PAGE_SIZE);
			kunmap_atomic(s);

			drm_clflush_pages(&src->pages[page], 1);
		}
824
		local_irq_restore(flags);
825

826
		dst->pages[page] = d;
827 828

		reloc_offset += PAGE_SIZE;
829 830
	}
	dst->page_count = page_count;
831
	dst->gtt_offset = src->gtt_offset;
832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855

	return dst;

unwind:
	while (page--)
		kfree(dst->pages[page]);
	kfree(dst);
	return NULL;
}

static void
i915_error_object_free(struct drm_i915_error_object *obj)
{
	int page;

	if (obj == NULL)
		return;

	for (page = 0; page < obj->page_count; page++)
		kfree(obj->pages[page]);

	kfree(obj);
}

856 857
void
i915_error_state_free(struct kref *error_ref)
858
{
859 860
	struct drm_i915_error_state *error = container_of(error_ref,
							  typeof(*error), ref);
861 862
	int i;

863 864 865 866 867
	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		i915_error_object_free(error->ring[i].batchbuffer);
		i915_error_object_free(error->ring[i].ringbuffer);
		kfree(error->ring[i].requests);
	}
868

869
	kfree(error->active_bo);
870
	kfree(error->overlay);
871 872
	kfree(error);
}
873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893
static void capture_bo(struct drm_i915_error_buffer *err,
		       struct drm_i915_gem_object *obj)
{
	err->size = obj->base.size;
	err->name = obj->base.name;
	err->seqno = obj->last_rendering_seqno;
	err->gtt_offset = obj->gtt_offset;
	err->read_domains = obj->base.read_domains;
	err->write_domain = obj->base.write_domain;
	err->fence_reg = obj->fence_reg;
	err->pinned = 0;
	if (obj->pin_count > 0)
		err->pinned = 1;
	if (obj->user_pin_count > 0)
		err->pinned = -1;
	err->tiling = obj->tiling_mode;
	err->dirty = obj->dirty;
	err->purgeable = obj->madv != I915_MADV_WILLNEED;
	err->ring = obj->ring ? obj->ring->id : -1;
	err->cache_level = obj->cache_level;
}
894

895 896
static u32 capture_active_bo(struct drm_i915_error_buffer *err,
			     int count, struct list_head *head)
897 898 899 900 901
{
	struct drm_i915_gem_object *obj;
	int i = 0;

	list_for_each_entry(obj, head, mm_list) {
902
		capture_bo(err++, obj);
903 904
		if (++i == count)
			break;
905 906 907 908 909 910 911 912 913 914 915 916 917 918
	}

	return i;
}

static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
			     int count, struct list_head *head)
{
	struct drm_i915_gem_object *obj;
	int i = 0;

	list_for_each_entry(obj, head, gtt_list) {
		if (obj->pin_count == 0)
			continue;
919

920 921 922
		capture_bo(err++, obj);
		if (++i == count)
			break;
923 924 925 926 927
	}

	return i;
}

928 929 930 931 932 933 934 935
static void i915_gem_record_fences(struct drm_device *dev,
				   struct drm_i915_error_state *error)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	/* Fences */
	switch (INTEL_INFO(dev)->gen) {
936
	case 7:
937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957
	case 6:
		for (i = 0; i < 16; i++)
			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
		break;
	case 5:
	case 4:
		for (i = 0; i < 16; i++)
			error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
		break;
	case 3:
		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
			for (i = 0; i < 8; i++)
				error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
	case 2:
		for (i = 0; i < 8; i++)
			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
		break;

	}
}

958 959 960 961 962 963 964 965 966 967 968 969 970 971 972
static struct drm_i915_error_object *
i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
			     struct intel_ring_buffer *ring)
{
	struct drm_i915_gem_object *obj;
	u32 seqno;

	if (!ring->get_seqno)
		return NULL;

	seqno = ring->get_seqno(ring);
	list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
		if (obj->ring != ring)
			continue;

973
		if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
974 975 976 977 978 979 980 981 982 983 984 985 986 987
			continue;

		if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
			continue;

		/* We need to copy these to an anonymous buffer as the simplest
		 * method to avoid being overwritten by userspace.
		 */
		return i915_error_object_create(dev_priv, obj);
	}

	return NULL;
}

988 989 990 991 992 993
static void i915_record_ring_state(struct drm_device *dev,
				   struct drm_i915_error_state *error,
				   struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

994 995
	if (INTEL_INFO(dev)->gen >= 6) {
		error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
996 997 998 999
		error->semaphore_mboxes[ring->id][0]
			= I915_READ(RING_SYNC_0(ring->mmio_base));
		error->semaphore_mboxes[ring->id][1]
			= I915_READ(RING_SYNC_1(ring->mmio_base));
1000
	}
1001

1002
	if (INTEL_INFO(dev)->gen >= 4) {
1003
		error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1004 1005 1006
		error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
		error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
		error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1007
		error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1008 1009 1010 1011 1012
		if (ring->id == RCS) {
			error->instdone1 = I915_READ(INSTDONE1);
			error->bbaddr = I915_READ64(BB_ADDR);
		}
	} else {
1013
		error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1014 1015 1016 1017 1018
		error->ipeir[ring->id] = I915_READ(IPEIR);
		error->ipehr[ring->id] = I915_READ(IPEHR);
		error->instdone[ring->id] = I915_READ(INSTDONE);
	}

B
Ben Widawsky 已提交
1019
	error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1020
	error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1021 1022
	error->seqno[ring->id] = ring->get_seqno(ring);
	error->acthd[ring->id] = intel_ring_get_active_head(ring);
1023 1024
	error->head[ring->id] = I915_READ_HEAD(ring);
	error->tail[ring->id] = I915_READ_TAIL(ring);
1025 1026 1027

	error->cpu_ring_head[ring->id] = ring->head;
	error->cpu_ring_tail[ring->id] = ring->tail;
1028 1029
}

1030 1031 1032 1033
static void i915_gem_record_rings(struct drm_device *dev,
				  struct drm_i915_error_state *error)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1034
	struct intel_ring_buffer *ring;
1035 1036 1037
	struct drm_i915_gem_request *request;
	int i, count;

1038
	for_each_ring(ring, dev_priv, i) {
1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066
		i915_record_ring_state(dev, error, ring);

		error->ring[i].batchbuffer =
			i915_error_first_batchbuffer(dev_priv, ring);

		error->ring[i].ringbuffer =
			i915_error_object_create(dev_priv, ring->obj);

		count = 0;
		list_for_each_entry(request, &ring->request_list, list)
			count++;

		error->ring[i].num_requests = count;
		error->ring[i].requests =
			kmalloc(count*sizeof(struct drm_i915_error_request),
				GFP_ATOMIC);
		if (error->ring[i].requests == NULL) {
			error->ring[i].num_requests = 0;
			continue;
		}

		count = 0;
		list_for_each_entry(request, &ring->request_list, list) {
			struct drm_i915_error_request *erq;

			erq = &error->ring[i].requests[count++];
			erq->seqno = request->seqno;
			erq->jiffies = request->emitted_jiffies;
1067
			erq->tail = request->tail;
1068 1069 1070 1071
		}
	}
}

1072 1073 1074 1075 1076 1077 1078 1079 1080
/**
 * i915_capture_error_state - capture an error record for later analysis
 * @dev: drm device
 *
 * Should be called when an error is detected (either a hang or an error
 * interrupt) to capture error state from the time of the error.  Fills
 * out a structure which becomes available in debugfs for user level tools
 * to pick up.
 */
1081 1082 1083
static void i915_capture_error_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1084
	struct drm_i915_gem_object *obj;
1085 1086
	struct drm_i915_error_state *error;
	unsigned long flags;
1087
	int i, pipe;
1088 1089

	spin_lock_irqsave(&dev_priv->error_lock, flags);
1090 1091 1092 1093
	error = dev_priv->first_error;
	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
	if (error)
		return;
1094

1095
	/* Account for pipe specific data like PIPE*STAT */
1096
	error = kzalloc(sizeof(*error), GFP_ATOMIC);
1097
	if (!error) {
1098 1099
		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
		return;
1100 1101
	}

1102 1103
	DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
		 dev->primary->index);
1104

1105
	kref_init(&error->ref);
1106 1107
	error->eir = I915_READ(EIR);
	error->pgtbl_er = I915_READ(PGTBL_ER);
1108 1109 1110 1111 1112 1113 1114 1115 1116 1117

	if (HAS_PCH_SPLIT(dev))
		error->ier = I915_READ(DEIER) | I915_READ(GTIER);
	else if (IS_VALLEYVIEW(dev))
		error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
	else if (IS_GEN2(dev))
		error->ier = I915_READ16(IER);
	else
		error->ier = I915_READ(IER);

1118 1119
	for_each_pipe(pipe)
		error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1120

1121
	if (INTEL_INFO(dev)->gen >= 6) {
1122
		error->error = I915_READ(ERROR_GEN6);
1123 1124
		error->done_reg = I915_READ(DONE_REG);
	}
1125

1126
	i915_gem_record_fences(dev, error);
1127
	i915_gem_record_rings(dev, error);
1128

1129
	/* Record buffers on the active and pinned lists. */
1130
	error->active_bo = NULL;
1131
	error->pinned_bo = NULL;
1132

1133 1134 1135 1136
	i = 0;
	list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
		i++;
	error->active_bo_count = i;
1137 1138 1139
	list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
		if (obj->pin_count)
			i++;
1140
	error->pinned_bo_count = i - error->active_bo_count;
1141

1142 1143
	error->active_bo = NULL;
	error->pinned_bo = NULL;
1144 1145
	if (i) {
		error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1146
					   GFP_ATOMIC);
1147 1148 1149
		if (error->active_bo)
			error->pinned_bo =
				error->active_bo + error->active_bo_count;
1150 1151
	}

1152 1153
	if (error->active_bo)
		error->active_bo_count =
1154 1155 1156
			capture_active_bo(error->active_bo,
					  error->active_bo_count,
					  &dev_priv->mm.active_list);
1157 1158 1159

	if (error->pinned_bo)
		error->pinned_bo_count =
1160 1161 1162
			capture_pinned_bo(error->pinned_bo,
					  error->pinned_bo_count,
					  &dev_priv->mm.gtt_list);
1163

1164 1165
	do_gettimeofday(&error->time);

1166
	error->overlay = intel_overlay_capture_error_state(dev);
1167
	error->display = intel_display_capture_error_state(dev);
1168

1169 1170 1171 1172 1173
	spin_lock_irqsave(&dev_priv->error_lock, flags);
	if (dev_priv->first_error == NULL) {
		dev_priv->first_error = error;
		error = NULL;
	}
1174
	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1175 1176

	if (error)
1177
		i915_error_state_free(&error->ref);
1178 1179 1180 1181 1182 1183
}

void i915_destroy_error_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_error_state *error;
1184
	unsigned long flags;
1185

1186
	spin_lock_irqsave(&dev_priv->error_lock, flags);
1187 1188
	error = dev_priv->first_error;
	dev_priv->first_error = NULL;
1189
	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1190 1191

	if (error)
1192
		kref_put(&error->ref, i915_error_state_free);
1193
}
1194 1195 1196
#else
#define i915_capture_error_state(x)
#endif
1197

1198
static void i915_report_and_clear_eir(struct drm_device *dev)
1199 1200 1201
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 eir = I915_READ(EIR);
1202
	int pipe;
1203

1204 1205
	if (!eir)
		return;
1206

1207
	pr_err("render error detected, EIR: 0x%08x\n", eir);
1208 1209 1210 1211 1212

	if (IS_G4X(dev)) {
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);

1213 1214 1215
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTDONE: 0x%08x\n",
1216
			       I915_READ(INSTDONE_I965));
1217 1218 1219
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1220
			I915_WRITE(IPEIR_I965, ipeir);
1221
			POSTING_READ(IPEIR_I965);
1222 1223 1224
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
1225 1226
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1227
			I915_WRITE(PGTBL_ER, pgtbl_err);
1228
			POSTING_READ(PGTBL_ER);
1229 1230 1231
		}
	}

1232
	if (!IS_GEN2(dev)) {
1233 1234
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
1235 1236
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1237
			I915_WRITE(PGTBL_ER, pgtbl_err);
1238
			POSTING_READ(PGTBL_ER);
1239 1240 1241 1242
		}
	}

	if (eir & I915_ERROR_MEMORY_REFRESH) {
1243
		pr_err("memory refresh error:\n");
1244
		for_each_pipe(pipe)
1245
			pr_err("pipe %c stat: 0x%08x\n",
1246
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1247 1248 1249
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
1250 1251
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1252
		if (INTEL_INFO(dev)->gen < 4) {
1253 1254
			u32 ipeir = I915_READ(IPEIR);

1255 1256 1257 1258
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1259
			I915_WRITE(IPEIR, ipeir);
1260
			POSTING_READ(IPEIR);
1261 1262 1263
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);

1264 1265 1266
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTDONE: 0x%08x\n",
1267
			       I915_READ(INSTDONE_I965));
1268 1269 1270
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1271
			I915_WRITE(IPEIR_I965, ipeir);
1272
			POSTING_READ(IPEIR_I965);
1273 1274 1275 1276
		}
	}

	I915_WRITE(EIR, eir);
1277
	POSTING_READ(EIR);
1278 1279 1280 1281 1282 1283 1284 1285 1286 1287
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299
}

/**
 * i915_handle_error - handle an error interrupt
 * @dev: drm device
 *
 * Do some basic checking of regsiter state at error interrupt time and
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
 */
1300
void i915_handle_error(struct drm_device *dev, bool wedged)
1301 1302
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1303 1304
	struct intel_ring_buffer *ring;
	int i;
1305 1306 1307

	i915_capture_error_state(dev);
	i915_report_and_clear_eir(dev);
1308

1309
	if (wedged) {
1310
		INIT_COMPLETION(dev_priv->error_completion);
1311 1312
		atomic_set(&dev_priv->mm.wedged, 1);

1313 1314 1315
		/*
		 * Wakeup waiting processes so they don't hang
		 */
1316 1317
		for_each_ring(ring, dev_priv, i)
			wake_up_all(&ring->irq_queue);
1318 1319
	}

1320
	queue_work(dev_priv->wq, &dev_priv->error_work);
1321 1322
}

1323 1324 1325 1326 1327
static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1328
	struct drm_i915_gem_object *obj;
1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346
	struct intel_unpin_work *work;
	unsigned long flags;
	bool stall_detected;

	/* Ignore early vblank irqs */
	if (intel_crtc == NULL)
		return;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;

	if (work == NULL || work->pending || !work->enable_stall_check) {
		/* Either the pending flip IRQ arrived, or we're too early. Don't check */
		spin_unlock_irqrestore(&dev->event_lock, flags);
		return;
	}

	/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1347
	obj = work->pending_flip_obj;
1348
	if (INTEL_INFO(dev)->gen >= 4) {
1349
		int dspsurf = DSPSURF(intel_crtc->plane);
1350 1351
		stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
					obj->gtt_offset;
1352
	} else {
1353
		int dspaddr = DSPADDR(intel_crtc->plane);
1354
		stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1355
							crtc->y * crtc->fb->pitches[0] +
1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366
							crtc->x * crtc->fb->bits_per_pixel/8);
	}

	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (stall_detected) {
		DRM_DEBUG_DRIVER("Pageflip stall detected\n");
		intel_prepare_page_flip(dev, intel_crtc->plane);
	}
}

1367 1368 1369
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
1370
static int i915_enable_vblank(struct drm_device *dev, int pipe)
1371 1372
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1373
	unsigned long irqflags;
1374

1375
	if (!i915_pipe_enabled(dev, pipe))
1376
		return -EINVAL;
1377

1378
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1379
	if (INTEL_INFO(dev)->gen >= 4)
1380 1381
		i915_enable_pipestat(dev_priv, pipe,
				     PIPE_START_VBLANK_INTERRUPT_ENABLE);
1382
	else
1383 1384
		i915_enable_pipestat(dev_priv, pipe,
				     PIPE_VBLANK_INTERRUPT_ENABLE);
1385 1386 1387

	/* maintain vblank delivery even in deep C-states */
	if (dev_priv->info->gen == 3)
1388
		I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1389
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1390

1391 1392 1393
	return 0;
}

1394
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1395 1396 1397 1398 1399 1400 1401 1402 1403
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1404
				    DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1405 1406 1407 1408 1409
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

1410
static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1411 1412 1413 1414 1415 1416 1417 1418
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1419 1420
	ironlake_enable_display_irq(dev_priv,
				    DE_PIPEA_VBLANK_IVB << (5 * pipe));
1421 1422 1423 1424 1425
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

J
Jesse Barnes 已提交
1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451
static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
	u32 dpfl, imr;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	dpfl = I915_READ(VLV_DPFLIPSTAT);
	imr = I915_READ(VLV_IMR);
	if (pipe == 0) {
		dpfl |= PIPEA_VBLANK_INT_EN;
		imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
	} else {
		dpfl |= PIPEA_VBLANK_INT_EN;
		imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
	}
	I915_WRITE(VLV_DPFLIPSTAT, dpfl);
	I915_WRITE(VLV_IMR, imr);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

1452 1453 1454
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
1455
static void i915_disable_vblank(struct drm_device *dev, int pipe)
1456 1457
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1458
	unsigned long irqflags;
1459

1460
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1461
	if (dev_priv->info->gen == 3)
1462
		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1463

1464 1465 1466 1467 1468 1469
	i915_disable_pipestat(dev_priv, pipe,
			      PIPE_VBLANK_INTERRUPT_ENABLE |
			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

1470
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1471 1472 1473 1474 1475 1476
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1477
				     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1478
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1479 1480
}

1481
static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1482 1483 1484 1485 1486
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1487 1488
	ironlake_disable_display_irq(dev_priv,
				     DE_PIPEA_VBLANK_IVB << (pipe * 5));
1489 1490 1491
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

J
Jesse Barnes 已提交
1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512
static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
	u32 dpfl, imr;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	dpfl = I915_READ(VLV_DPFLIPSTAT);
	imr = I915_READ(VLV_IMR);
	if (pipe == 0) {
		dpfl &= ~PIPEA_VBLANK_INT_EN;
		imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
	} else {
		dpfl &= ~PIPEB_VBLANK_INT_EN;
		imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
	}
	I915_WRITE(VLV_IMR, imr);
	I915_WRITE(VLV_DPFLIPSTAT, dpfl);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

1513 1514
static u32
ring_last_seqno(struct intel_ring_buffer *ring)
1515
{
1516 1517 1518 1519 1520 1521 1522 1523 1524
	return list_entry(ring->request_list.prev,
			  struct drm_i915_gem_request, list)->seqno;
}

static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
{
	if (list_empty(&ring->request_list) ||
	    i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
		/* Issue a wake-up to catch stuck h/w. */
B
Ben Widawsky 已提交
1525 1526 1527
		if (waitqueue_active(&ring->irq_queue)) {
			DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
				  ring->name);
1528 1529 1530 1531 1532 1533
			wake_up_all(&ring->irq_queue);
			*err = true;
		}
		return true;
	}
	return false;
B
Ben Gamari 已提交
1534 1535
}

1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549
static bool kick_ring(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 tmp = I915_READ_CTL(ring);
	if (tmp & RING_WAIT) {
		DRM_ERROR("Kicking stuck wait on %s\n",
			  ring->name);
		I915_WRITE_CTL(ring, tmp);
		return true;
	}
	return false;
}

1550 1551 1552 1553 1554
static bool i915_hangcheck_hung(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;

	if (dev_priv->hangcheck_count++ > 1) {
1555 1556
		bool hung = true;

1557 1558 1559 1560
		DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
		i915_handle_error(dev, true);

		if (!IS_GEN2(dev)) {
1561 1562 1563
			struct intel_ring_buffer *ring;
			int i;

1564 1565 1566 1567 1568
			/* Is the chip hanging on a WAIT_FOR_EVENT?
			 * If so we can simply poke the RB_WAIT bit
			 * and break the hang. This should work on
			 * all but the second generation chipsets.
			 */
1569 1570
			for_each_ring(ring, dev_priv, i)
				hung &= !kick_ring(ring);
1571 1572
		}

1573
		return hung;
1574 1575 1576 1577 1578
	}

	return false;
}

B
Ben Gamari 已提交
1579 1580 1581 1582 1583 1584 1585 1586 1587 1588
/**
 * This is called when the chip hasn't reported back with completed
 * batchbuffers in a long time. The first time this is called we simply record
 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
 * again, we assume the chip is wedged and try to fix it.
 */
void i915_hangcheck_elapsed(unsigned long data)
{
	struct drm_device *dev = (struct drm_device *)data;
	drm_i915_private_t *dev_priv = dev->dev_private;
1589 1590 1591 1592
	uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
	struct intel_ring_buffer *ring;
	bool err = false, idle;
	int i;
1593

1594 1595 1596
	if (!i915_enable_hangcheck)
		return;

1597 1598 1599 1600 1601 1602 1603
	memset(acthd, 0, sizeof(acthd));
	idle = true;
	for_each_ring(ring, dev_priv, i) {
	    idle &= i915_hangcheck_ring_idle(ring, &err);
	    acthd[i] = intel_ring_get_active_head(ring);
	}

1604
	/* If all work is done then ACTHD clearly hasn't advanced. */
1605
	if (idle) {
1606 1607 1608 1609
		if (err) {
			if (i915_hangcheck_hung(dev))
				return;

1610
			goto repeat;
1611 1612 1613
		}

		dev_priv->hangcheck_count = 0;
1614 1615
		return;
	}
1616

1617
	if (INTEL_INFO(dev)->gen < 4) {
1618 1619 1620 1621 1622 1623
		instdone = I915_READ(INSTDONE);
		instdone1 = 0;
	} else {
		instdone = I915_READ(INSTDONE_I965);
		instdone1 = I915_READ(INSTDONE1);
	}
1624 1625

	if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1626 1627
	    dev_priv->last_instdone == instdone &&
	    dev_priv->last_instdone1 == instdone1) {
1628
		if (i915_hangcheck_hung(dev))
1629 1630 1631 1632
			return;
	} else {
		dev_priv->hangcheck_count = 0;

1633
		memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1634 1635 1636
		dev_priv->last_instdone = instdone;
		dev_priv->last_instdone1 = instdone1;
	}
B
Ben Gamari 已提交
1637

1638
repeat:
B
Ben Gamari 已提交
1639
	/* Reset timer case chip hangs without another request being added */
1640 1641
	mod_timer(&dev_priv->hangcheck_timer,
		  jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
B
Ben Gamari 已提交
1642 1643
}

L
Linus Torvalds 已提交
1644 1645
/* drm_dma.h hooks
*/
1646
static void ironlake_irq_preinstall(struct drm_device *dev)
1647 1648 1649
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

1650 1651 1652
	atomic_set(&dev_priv->irq_received, 0);


1653
	I915_WRITE(HWSTAM, 0xeffe);
1654

1655 1656 1657 1658
	/* XXX hotplug from PCH */

	I915_WRITE(DEIMR, 0xffffffff);
	I915_WRITE(DEIER, 0x0);
1659
	POSTING_READ(DEIER);
1660 1661 1662 1663

	/* and GT */
	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
1664
	POSTING_READ(GTIER);
1665 1666 1667 1668

	/* south display irq */
	I915_WRITE(SDEIMR, 0xffffffff);
	I915_WRITE(SDEIER, 0x0);
1669
	POSTING_READ(SDEIER);
1670 1671
}

J
Jesse Barnes 已提交
1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703
static void valleyview_irq_preinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	atomic_set(&dev_priv->irq_received, 0);

	/* VLV magic */
	I915_WRITE(VLV_IMR, 0);
	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);

	/* and GT */
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	POSTING_READ(GTIER);

	I915_WRITE(DPINVGTT, 0xff);

	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}

1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723
/*
 * Enable digital hotplug on the PCH, and configure the DP short pulse
 * duration to 2ms (which is the minimum in the Display Port spec)
 *
 * This register is the same on all known PCH chips.
 */

static void ironlake_enable_pch_hotplug(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32	hotplug;

	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}

1724
static int ironlake_irq_postinstall(struct drm_device *dev)
1725 1726 1727
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	/* enable kind of interrupts always enabled */
1728 1729
	u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
			   DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1730
	u32 render_irqs;
1731
	u32 hotplug_mask;
1732

1733
	dev_priv->irq_mask = ~display_mask;
1734 1735 1736

	/* should always can generate irq */
	I915_WRITE(DEIIR, I915_READ(DEIIR));
1737 1738
	I915_WRITE(DEIMR, dev_priv->irq_mask);
	I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1739
	POSTING_READ(DEIER);
1740

1741
	dev_priv->gt_irq_mask = ~0;
1742 1743

	I915_WRITE(GTIIR, I915_READ(GTIIR));
1744
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1745

1746 1747 1748
	if (IS_GEN6(dev))
		render_irqs =
			GT_USER_INTERRUPT |
B
Ben Widawsky 已提交
1749 1750
			GEN6_BSD_USER_INTERRUPT |
			GEN6_BLITTER_USER_INTERRUPT;
1751 1752
	else
		render_irqs =
1753
			GT_USER_INTERRUPT |
1754
			GT_PIPE_NOTIFY |
1755 1756
			GT_BSD_USER_INTERRUPT;
	I915_WRITE(GTIER, render_irqs);
1757
	POSTING_READ(GTIER);
1758

1759
	if (HAS_PCH_CPT(dev)) {
1760 1761 1762 1763
		hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
				SDE_PORTB_HOTPLUG_CPT |
				SDE_PORTC_HOTPLUG_CPT |
				SDE_PORTD_HOTPLUG_CPT);
1764
	} else {
1765 1766 1767 1768 1769
		hotplug_mask = (SDE_CRT_HOTPLUG |
				SDE_PORTB_HOTPLUG |
				SDE_PORTC_HOTPLUG |
				SDE_PORTD_HOTPLUG |
				SDE_AUX_MASK);
1770 1771
	}

1772
	dev_priv->pch_irq_mask = ~hotplug_mask;
1773 1774

	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1775 1776
	I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
	I915_WRITE(SDEIER, hotplug_mask);
1777
	POSTING_READ(SDEIER);
1778

1779 1780
	ironlake_enable_pch_hotplug(dev);

1781 1782 1783 1784 1785 1786 1787
	if (IS_IRONLAKE_M(dev)) {
		/* Clear & enable PCU event interrupts */
		I915_WRITE(DEIIR, DE_PCU_EVENT);
		I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
	}

1788 1789 1790
	return 0;
}

1791
static int ivybridge_irq_postinstall(struct drm_device *dev)
1792 1793 1794
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	/* enable kind of interrupts always enabled */
1795 1796 1797 1798 1799
	u32 display_mask =
		DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
		DE_PLANEC_FLIP_DONE_IVB |
		DE_PLANEB_FLIP_DONE_IVB |
		DE_PLANEA_FLIP_DONE_IVB;
1800 1801 1802 1803 1804 1805 1806 1807
	u32 render_irqs;
	u32 hotplug_mask;

	dev_priv->irq_mask = ~display_mask;

	/* should always can generate irq */
	I915_WRITE(DEIIR, I915_READ(DEIIR));
	I915_WRITE(DEIMR, dev_priv->irq_mask);
1808 1809 1810 1811 1812
	I915_WRITE(DEIER,
		   display_mask |
		   DE_PIPEC_VBLANK_IVB |
		   DE_PIPEB_VBLANK_IVB |
		   DE_PIPEA_VBLANK_IVB);
1813 1814 1815 1816 1817 1818 1819
	POSTING_READ(DEIER);

	dev_priv->gt_irq_mask = ~0;

	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);

B
Ben Widawsky 已提交
1820 1821
	render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
		GEN6_BLITTER_USER_INTERRUPT;
1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835
	I915_WRITE(GTIER, render_irqs);
	POSTING_READ(GTIER);

	hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
			SDE_PORTB_HOTPLUG_CPT |
			SDE_PORTC_HOTPLUG_CPT |
			SDE_PORTD_HOTPLUG_CPT);
	dev_priv->pch_irq_mask = ~hotplug_mask;

	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
	I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
	I915_WRITE(SDEIER, hotplug_mask);
	POSTING_READ(SDEIER);

1836 1837
	ironlake_enable_pch_hotplug(dev);

1838 1839 1840
	return 0;
}

J
Jesse Barnes 已提交
1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876
static int valleyview_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 render_irqs;
	u32 enable_mask;
	u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
	u16 msid;

	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
	enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;

	dev_priv->irq_mask = ~enable_mask;

	dev_priv->pipestat[0] = 0;
	dev_priv->pipestat[1] = 0;

	/* Hack for broken MSIs on VLV */
	pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
	pci_read_config_word(dev->pdev, 0x98, &msid);
	msid &= 0xff; /* mask out delivery bits */
	msid |= (1<<14);
	pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);

	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	I915_WRITE(VLV_IER, enable_mask);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(PIPESTAT(0), 0xffff);
	I915_WRITE(PIPESTAT(1), 0xffff);
	POSTING_READ(VLV_IER);

	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IIR, 0xffffffff);

	render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
		GT_GEN6_BLT_CS_ERROR_INTERRUPT |
B
Ben Widawsky 已提交
1877
		GT_GEN6_BLT_USER_INTERRUPT |
J
Jesse Barnes 已提交
1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945
		GT_GEN6_BSD_USER_INTERRUPT |
		GT_GEN6_BSD_CS_ERROR_INTERRUPT |
		GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
		GT_PIPE_NOTIFY |
		GT_RENDER_CS_ERROR_INTERRUPT |
		GT_SYNC_STATUS |
		GT_USER_INTERRUPT;

	dev_priv->gt_irq_mask = ~render_irqs;

	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIMR, 0);
	I915_WRITE(GTIER, render_irqs);
	POSTING_READ(GTIER);

	/* ack & enable invalid PTE error interrupts */
#if 0 /* FIXME: add support to irq handler for checking these bits */
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
#endif

	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
#if 0 /* FIXME: check register definitions; some have moved */
	/* Note HDMI and DP share bits */
	if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
		hotplug_en |= HDMIB_HOTPLUG_INT_EN;
	if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
		hotplug_en |= HDMIC_HOTPLUG_INT_EN;
	if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
		hotplug_en |= HDMID_HOTPLUG_INT_EN;
	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
		hotplug_en |= SDVOC_HOTPLUG_INT_EN;
	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
		hotplug_en |= SDVOB_HOTPLUG_INT_EN;
	if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
		hotplug_en |= CRT_HOTPLUG_INT_EN;
		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
	}
#endif

	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);

	return 0;
}

static void valleyview_irq_uninstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	if (!dev_priv)
		return;

	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);

	I915_WRITE(HWSTAM, 0xffffffff);
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}

1946
static void ironlake_irq_uninstall(struct drm_device *dev)
1947 1948
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1949 1950 1951 1952

	if (!dev_priv)
		return;

1953 1954 1955 1956 1957 1958 1959 1960 1961
	I915_WRITE(HWSTAM, 0xffffffff);

	I915_WRITE(DEIMR, 0xffffffff);
	I915_WRITE(DEIER, 0x0);
	I915_WRITE(DEIIR, I915_READ(DEIIR));

	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	I915_WRITE(GTIIR, I915_READ(GTIIR));
1962 1963 1964 1965

	I915_WRITE(SDEIMR, 0xffffffff);
	I915_WRITE(SDEIER, 0x0);
	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1966 1967
}

1968
static void i8xx_irq_preinstall(struct drm_device * dev)
L
Linus Torvalds 已提交
1969 1970
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1971
	int pipe;
1972

1973
	atomic_set(&dev_priv->irq_received, 0);
1974

1975 1976
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
1977 1978 1979
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
C
Chris Wilson 已提交
1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059
}

static int i8xx_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

	dev_priv->pipestat[0] = 0;
	dev_priv->pipestat[1] = 0;

	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	I915_WRITE16(IMR, dev_priv->irq_mask);

	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);

	return 0;
}

static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u16 iir, new_iir;
	u32 pipe_stats[2];
	unsigned long irqflags;
	int irq_received;
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;

	atomic_inc(&dev_priv->irq_received);

	iir = I915_READ16(IIR);
	if (iir == 0)
		return IRQ_NONE;

	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
				irq_received = 1;
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */

2060
		i915_update_dri1_breadcrumb(dev);
C
Chris Wilson 已提交
2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

		if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
		    drm_handle_vblank(dev, 0)) {
			if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
				intel_prepare_page_flip(dev, 0);
				intel_finish_page_flip(dev, 0);
				flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
			}
		}

		if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
		    drm_handle_vblank(dev, 1)) {
			if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
				intel_prepare_page_flip(dev, 1);
				intel_finish_page_flip(dev, 1);
				flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
			}
		}

		iir = new_iir;
	}

	return IRQ_HANDLED;
}

static void i8xx_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}

2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115
static void i915_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	atomic_set(&dev_priv->irq_received, 0);

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

2116
	I915_WRITE16(HWSTAM, 0xeffe);
2117 2118 2119 2120 2121 2122 2123 2124 2125 2126
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i915_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2127
	u32 enable_mask;
2128 2129 2130 2131

	dev_priv->pipestat[0] = 0;
	dev_priv->pipestat[1] = 0;

2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		I915_USER_INTERRUPT;

2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192
	if (I915_HAS_HOTPLUG(dev)) {
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

	if (I915_HAS_HOTPLUG(dev)) {
		u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);

		if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
			hotplug_en |= HDMIB_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
			hotplug_en |= HDMIC_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
			hotplug_en |= HDMID_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
			hotplug_en |= SDVOC_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
			hotplug_en |= SDVOB_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
			hotplug_en |= CRT_HOTPLUG_INT_EN;
			hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
		}

		/* Ignore TV since it's buggy */

		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
	}

	intel_opregion_enable_asle(dev);

	return 0;
}

static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2193
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2194
	unsigned long irqflags;
2195 2196 2197 2198 2199 2200 2201 2202
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	u32 flip[2] = {
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
	};
	int pipe, ret = IRQ_NONE;
2203 2204 2205 2206

	atomic_inc(&dev_priv->irq_received);

	iir = I915_READ(IIR);
2207 2208
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
2209
		bool blc_event = false;
2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

2224
			/* Clear the PIPE*STAT regs before the IIR */
2225 2226 2227 2228 2229
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
2230
				irq_received = true;
2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		if (!irq_received)
			break;

		/* Consume port.  Then clear IIR or we'll miss events */
		if ((I915_HAS_HOTPLUG(dev)) &&
		    (iir & I915_DISPLAY_PORT_INTERRUPT)) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);

			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
				  hotplug_status);
			if (hotplug_status & dev_priv->hotplug_supported_mask)
				queue_work(dev_priv->wq,
					   &dev_priv->hotplug_work);

			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2250
			POSTING_READ(PORT_HOTPLUG_STAT);
2251 2252
		}

2253
		I915_WRITE(IIR, iir & ~flip_mask);
2254 2255 2256 2257 2258 2259
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

		for_each_pipe(pipe) {
2260 2261 2262
			int plane = pipe;
			if (IS_MOBILE(dev))
				plane = !plane;
2263
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2264
			    drm_handle_vblank(dev, pipe)) {
2265 2266 2267 2268 2269
				if (iir & flip[plane]) {
					intel_prepare_page_flip(dev, plane);
					intel_finish_page_flip(dev, pipe);
					flip_mask &= ~flip[plane];
				}
2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293
			}

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
		}

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
2294
		ret = IRQ_HANDLED;
2295
		iir = new_iir;
2296
	} while (iir & ~flip_mask);
2297

2298
	i915_update_dri1_breadcrumb(dev);
2299

2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312
	return ret;
}

static void i915_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

2313
	I915_WRITE16(HWSTAM, 0xffff);
2314 2315
	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
2316
		I915_WRITE(PIPESTAT(pipe), 0);
2317 2318
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	I915_WRITE(IIR, I915_READ(IIR));
}

static void i965_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	atomic_set(&dev_priv->irq_received, 0);

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

	I915_WRITE(HWSTAM, 0xeffe);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i965_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2348
	u32 enable_mask;
2349 2350 2351
	u32 error_mask;

	/* Unmask the interrupts that we always want on. */
2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask = ~dev_priv->irq_mask;
	enable_mask |= I915_USER_INTERRUPT;

	if (IS_G4X(dev))
		enable_mask |= I915_BSD_USER_INTERRUPT;
2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444

	dev_priv->pipestat[0] = 0;
	dev_priv->pipestat[1] = 0;

	if (I915_HAS_HOTPLUG(dev)) {
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
	if (IS_G4X(dev)) {
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

	if (I915_HAS_HOTPLUG(dev)) {
		u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);

		/* Note HDMI and DP share bits */
		if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
			hotplug_en |= HDMIB_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
			hotplug_en |= HDMIC_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
			hotplug_en |= HDMID_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
			hotplug_en |= SDVOC_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
			hotplug_en |= SDVOB_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
			hotplug_en |= CRT_HOTPLUG_INT_EN;

			/* Programming the CRT detection parameters tends
			   to generate a spurious hotplug event about three
			   seconds later.  So just do it once.
			*/
			if (IS_G4X(dev))
				hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
			hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
		}

		/* Ignore TV since it's buggy */

		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
	}

	intel_opregion_enable_asle(dev);

	return 0;
}

static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	unsigned long irqflags;
	int irq_received;
	int ret = IRQ_NONE, pipe;

	atomic_inc(&dev_priv->irq_received);

	iir = I915_READ(IIR);

	for (;;) {
2445 2446
		bool blc_event = false;

2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502
		irq_received = iir != 0;

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
				irq_received = 1;
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		if (!irq_received)
			break;

		ret = IRQ_HANDLED;

		/* Consume port.  Then clear IIR or we'll miss events */
		if ((I915_HAS_HOTPLUG(dev)) &&
		    (iir & I915_DISPLAY_PORT_INTERRUPT)) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);

			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
				  hotplug_status);
			if (hotplug_status & dev_priv->hotplug_supported_mask)
				queue_work(dev_priv->wq,
					   &dev_priv->hotplug_work);

			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
			I915_READ(PORT_HOTPLUG_STAT);
		}

		I915_WRITE(IIR, iir);
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);
		if (iir & I915_BSD_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[VCS]);

2503
		if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2504 2505
			intel_prepare_page_flip(dev, 0);

2506
		if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2507 2508 2509
			intel_prepare_page_flip(dev, 1);

		for_each_pipe(pipe) {
2510
			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2511
			    drm_handle_vblank(dev, pipe)) {
2512 2513
				i915_pageflip_stall_check(dev, pipe);
				intel_finish_page_flip(dev, pipe);
2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541
			}

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
		}


		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}

2542
	i915_update_dri1_breadcrumb(dev);
2543

2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571
	return ret;
}

static void i965_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	if (!dev_priv)
		return;

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

	I915_WRITE(HWSTAM, 0xffffffff);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}

2572 2573
void intel_irq_init(struct drm_device *dev)
{
2574 2575 2576 2577 2578 2579
	struct drm_i915_private *dev_priv = dev->dev_private;

	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
	INIT_WORK(&dev_priv->error_work, i915_error_work_func);
	INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);

2580 2581
	dev->driver->get_vblank_counter = i915_get_vblank_counter;
	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2582
	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2583 2584 2585 2586
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
	}

2587 2588 2589 2590
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
	else
		dev->driver->get_vblank_timestamp = NULL;
2591 2592
	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;

J
Jesse Barnes 已提交
2593 2594 2595 2596 2597 2598 2599 2600
	if (IS_VALLEYVIEW(dev)) {
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev->driver->irq_uninstall = valleyview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
	} else if (IS_IVYBRIDGE(dev)) {
2601 2602 2603 2604 2605 2606 2607
		/* Share pre & uninstall handlers with ILK/SNB */
		dev->driver->irq_handler = ivybridge_irq_handler;
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
		dev->driver->irq_postinstall = ivybridge_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ivybridge_enable_vblank;
		dev->driver->disable_vblank = ivybridge_disable_vblank;
2608 2609 2610 2611 2612 2613 2614 2615
	} else if (IS_HASWELL(dev)) {
		/* Share interrupts handling with IVB */
		dev->driver->irq_handler = ivybridge_irq_handler;
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
		dev->driver->irq_postinstall = ivybridge_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ivybridge_enable_vblank;
		dev->driver->disable_vblank = ivybridge_disable_vblank;
2616 2617 2618 2619 2620 2621 2622 2623
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ironlake_enable_vblank;
		dev->driver->disable_vblank = ironlake_disable_vblank;
	} else {
C
Chris Wilson 已提交
2624 2625 2626 2627 2628
		if (INTEL_INFO(dev)->gen == 2) {
			dev->driver->irq_preinstall = i8xx_irq_preinstall;
			dev->driver->irq_postinstall = i8xx_irq_postinstall;
			dev->driver->irq_handler = i8xx_irq_handler;
			dev->driver->irq_uninstall = i8xx_irq_uninstall;
2629
		} else if (INTEL_INFO(dev)->gen == 3) {
2630 2631 2632
			/* IIR "flip pending" means done if this bit is set */
			I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));

2633 2634 2635 2636
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_uninstall = i915_irq_uninstall;
			dev->driver->irq_handler = i915_irq_handler;
C
Chris Wilson 已提交
2637
		} else {
2638 2639 2640 2641
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_uninstall = i965_irq_uninstall;
			dev->driver->irq_handler = i965_irq_handler;
C
Chris Wilson 已提交
2642
		}
2643 2644 2645 2646
		dev->driver->enable_vblank = i915_enable_vblank;
		dev->driver->disable_vblank = i915_disable_vblank;
	}
}