r8169.c 118.1 KB
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/*
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 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
 *
 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
 * Copyright (c) a lot of people too. Please respect their work.
 *
 * See MAINTAINERS file for support contact information.
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 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
#include <linux/crc32.h>
#include <linux/in.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
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#include <linux/pm_runtime.h>
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#include <asm/system.h>
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#include <asm/io.h>
#include <asm/irq.h>

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#define RTL8169_VERSION "2.3LK-NAPI"
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#define MODULENAME "r8169"
#define PFX MODULENAME ": "

#ifdef RTL8169_DEBUG
#define assert(expr) \
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	if (!(expr)) {					\
		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
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		#expr,__FILE__,__func__,__LINE__);		\
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	}
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#define dprintk(fmt, args...) \
	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
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#else
#define assert(expr) do {} while (0)
#define dprintk(fmt, args...)	do {} while (0)
#endif /* RTL8169_DEBUG */

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#define R8169_MSG_DEFAULT \
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	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
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#define TX_BUFFS_AVAIL(tp) \
	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
   The RTL chips use a 64 element hash table based on the Ethernet CRC. */
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static const int multicast_filter_limit = 32;
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/* MAC address length */
#define MAC_ADDR_LEN	6

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#define MAX_READ_REQUEST_SHIFT	12
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#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer. */
#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
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#define EarlyTxThld	0x3F	/* 0x3F means NO early transmit */
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#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */
#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

#define R8169_REGS_SIZE		256
#define R8169_NAPI_WEIGHT	64
#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */
#define NUM_RX_DESC	256	/* Number of Rx descriptor registers */
#define RX_BUF_SIZE	1536	/* Rx Buffer size */
#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))
#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

#define RTL8169_TX_TIMEOUT	(6*HZ)
#define RTL8169_PHY_TIMEOUT	(10*HZ)

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#define RTL_EEPROM_SIG		cpu_to_le32(0x8129)
#define RTL_EEPROM_SIG_MASK	cpu_to_le32(0xffff)
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#define RTL_EEPROM_SIG_ADDR	0x0000

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/* write/read MMIO register */
#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
#define RTL_R8(reg)		readb (ioaddr + (reg))
#define RTL_R16(reg)		readw (ioaddr + (reg))
#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))

enum mac_version {
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	RTL_GIGA_MAC_NONE   = 0x00,
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	RTL_GIGA_MAC_VER_01 = 0x01, // 8169
	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
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	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
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	RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
	RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
	RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
	RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
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	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
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	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
	RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
	RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
	RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
	RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
	RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
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	RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
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	RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
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	RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
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	RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
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	RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
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	RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
	RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
	RTL_GIGA_MAC_VER_27 = 0x1b  // 8168DP
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};

#define _R(NAME,MAC,MASK) \
	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }

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static const struct {
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	const char *name;
	u8 mac_version;
	u32 RxConfigMask;	/* Clears the bits supported by this chip */
} rtl_chip_info[] = {
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	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
	_R("RTL8169s",		RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
	_R("RTL8110s",		RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
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	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
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	_R("RTL8102e",		RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
	_R("RTL8102e",		RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
	_R("RTL8102e",		RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
	_R("RTL8101e",		RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
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	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
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	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
	_R("RTL8101e",		RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
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	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
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	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
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	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
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	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
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	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
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	_R("RTL8168d/8111d",	RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
	_R("RTL8168d/8111d",	RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
	_R("RTL8168dp/8111dp",	RTL_GIGA_MAC_VER_27, 0xff7e1880)  // PCI-E
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};
#undef _R

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enum cfg_version {
	RTL_CFG_0 = 0x00,
	RTL_CFG_1,
	RTL_CFG_2
};

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static void rtl_hw_start_8169(struct net_device *);
static void rtl_hw_start_8168(struct net_device *);
static void rtl_hw_start_8101(struct net_device *);

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static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },
	{ PCI_VENDOR_ID_LINKSYS,		0x1032,
		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
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	{ 0x0001,				0x8168,
		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
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	{0,},
};

MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

static int rx_copybreak = 200;
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static int use_dac = -1;
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static struct {
	u32 msg_enable;
} debug = { -1 };
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enum rtl_registers {
	MAC0		= 0,	/* Ethernet hardware address. */
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	MAC4		= 4,
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	MAR0		= 8,	/* Multicast filter. */
	CounterAddrLow		= 0x10,
	CounterAddrHigh		= 0x14,
	TxDescStartAddrLow	= 0x20,
	TxDescStartAddrHigh	= 0x24,
	TxHDescStartAddrLow	= 0x28,
	TxHDescStartAddrHigh	= 0x2c,
	FLASH		= 0x30,
	ERSR		= 0x36,
	ChipCmd		= 0x37,
	TxPoll		= 0x38,
	IntrMask	= 0x3c,
	IntrStatus	= 0x3e,
	TxConfig	= 0x40,
	RxConfig	= 0x44,
	RxMissed	= 0x4c,
	Cfg9346		= 0x50,
	Config0		= 0x51,
	Config1		= 0x52,
	Config2		= 0x53,
	Config3		= 0x54,
	Config4		= 0x55,
	Config5		= 0x56,
	MultiIntr	= 0x5c,
	PHYAR		= 0x60,
	PHYstatus	= 0x6c,
	RxMaxSize	= 0xda,
	CPlusCmd	= 0xe0,
	IntrMitigate	= 0xe2,
	RxDescAddrLow	= 0xe4,
	RxDescAddrHigh	= 0xe8,
	EarlyTxThres	= 0xec,
	FuncEvent	= 0xf0,
	FuncEventMask	= 0xf4,
	FuncPresetState	= 0xf8,
	FuncForceEvent	= 0xfc,
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};

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enum rtl8110_registers {
	TBICSR			= 0x64,
	TBI_ANAR		= 0x68,
	TBI_LPAR		= 0x6a,
};

enum rtl8168_8101_registers {
	CSIDR			= 0x64,
	CSIAR			= 0x68,
#define	CSIAR_FLAG			0x80000000
#define	CSIAR_WRITE_CMD			0x80000000
#define	CSIAR_BYTE_ENABLE		0x0f
#define	CSIAR_BYTE_ENABLE_SHIFT		12
#define	CSIAR_ADDR_MASK			0x0fff

	EPHYAR			= 0x80,
#define	EPHYAR_FLAG			0x80000000
#define	EPHYAR_WRITE_CMD		0x80000000
#define	EPHYAR_REG_MASK			0x1f
#define	EPHYAR_REG_SHIFT		16
#define	EPHYAR_DATA_MASK		0xffff
	DBG_REG			= 0xd1,
#define	FIX_NAK_1			(1 << 4)
#define	FIX_NAK_2			(1 << 3)
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	EFUSEAR			= 0xdc,
#define	EFUSEAR_FLAG			0x80000000
#define	EFUSEAR_WRITE_CMD		0x80000000
#define	EFUSEAR_READ_CMD		0x00000000
#define	EFUSEAR_REG_MASK		0x03ff
#define	EFUSEAR_REG_SHIFT		8
#define	EFUSEAR_DATA_MASK		0xff
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};

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enum rtl_register_content {
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	/* InterruptStatusBits */
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	SYSErr		= 0x8000,
	PCSTimeout	= 0x4000,
	SWInt		= 0x0100,
	TxDescUnavail	= 0x0080,
	RxFIFOOver	= 0x0040,
	LinkChg		= 0x0020,
	RxOverflow	= 0x0010,
	TxErr		= 0x0008,
	TxOK		= 0x0004,
	RxErr		= 0x0002,
	RxOK		= 0x0001,
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	/* RxStatusDesc */
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	RxFOVF	= (1 << 23),
	RxRWT	= (1 << 22),
	RxRES	= (1 << 21),
	RxRUNT	= (1 << 20),
	RxCRC	= (1 << 19),
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	/* ChipCmdBits */
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	CmdReset	= 0x10,
	CmdRxEnb	= 0x08,
	CmdTxEnb	= 0x04,
	RxBufEmpty	= 0x01,
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	/* TXPoll register p.5 */
	HPQ		= 0x80,		/* Poll cmd on the high prio queue */
	NPQ		= 0x40,		/* Poll cmd on the low prio queue */
	FSWInt		= 0x01,		/* Forced software interrupt */

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	/* Cfg9346Bits */
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	Cfg9346_Lock	= 0x00,
	Cfg9346_Unlock	= 0xc0,
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	/* rx_mode_bits */
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	AcceptErr	= 0x20,
	AcceptRunt	= 0x10,
	AcceptBroadcast	= 0x08,
	AcceptMulticast	= 0x04,
	AcceptMyPhys	= 0x02,
	AcceptAllPhys	= 0x01,
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	/* RxConfigBits */
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	RxCfgFIFOShift	= 13,
	RxCfgDMAShift	=  8,
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	/* TxConfigBits */
	TxInterFrameGapShift = 24,
	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

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	/* Config1 register p.24 */
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	LEDS1		= (1 << 7),
	LEDS0		= (1 << 6),
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	MSIEnable	= (1 << 5),	/* Enable Message Signaled Interrupt */
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	Speed_down	= (1 << 4),
	MEMMAP		= (1 << 3),
	IOMAP		= (1 << 2),
	VPD		= (1 << 1),
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	PMEnable	= (1 << 0),	/* Power Management Enable */

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	/* Config2 register p. 25 */
	PCI_Clock_66MHz = 0x01,
	PCI_Clock_33MHz = 0x00,

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	/* Config3 register p.25 */
	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */
	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */
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	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */
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	/* Config5 register p.27 */
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	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */
	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */
	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */
	LanWake		= (1 << 1),	/* LanWake enable/disable */
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	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */

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	/* TBICSR p.28 */
	TBIReset	= 0x80000000,
	TBILoopback	= 0x40000000,
	TBINwEnable	= 0x20000000,
	TBINwRestart	= 0x10000000,
	TBILinkOk	= 0x02000000,
	TBINwComplete	= 0x01000000,

	/* CPlusCmd p.31 */
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	EnableBist	= (1 << 15),	// 8168 8101
	Mac_dbgo_oe	= (1 << 14),	// 8168 8101
	Normal_mode	= (1 << 13),	// unused
	Force_half_dup	= (1 << 12),	// 8168 8101
	Force_rxflow_en	= (1 << 11),	// 8168 8101
	Force_txflow_en	= (1 << 10),	// 8168 8101
	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101
	ASF		= (1 << 8),	// 8168 8101
	PktCntrDisable	= (1 << 7),	// 8168 8101
	Mac_dbgo_sel	= 0x001c,	// 8168
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	RxVlan		= (1 << 6),
	RxChkSum	= (1 << 5),
	PCIDAC		= (1 << 4),
	PCIMulRW	= (1 << 3),
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	INTT_0		= 0x0000,	// 8168
	INTT_1		= 0x0001,	// 8168
	INTT_2		= 0x0002,	// 8168
	INTT_3		= 0x0003,	// 8168
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	/* rtl8169_PHYstatus */
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	TBI_Enable	= 0x80,
	TxFlowCtrl	= 0x40,
	RxFlowCtrl	= 0x20,
	_1000bpsF	= 0x10,
	_100bps		= 0x08,
	_10bps		= 0x04,
	LinkStatus	= 0x02,
	FullDup		= 0x01,
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	/* _TBICSRBit */
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	TBILinkOK	= 0x02000000,
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	/* DumpCounterCommand */
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	CounterDump	= 0x8,
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};

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enum desc_status_bit {
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	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */
	RingEnd		= (1 << 30), /* End of descriptor ring */
	FirstFrag	= (1 << 29), /* First segment of a packet */
	LastFrag	= (1 << 28), /* Final segment of a packet */

	/* Tx private */
	LargeSend	= (1 << 27), /* TCP Large Send Offload (TSO) */
	MSSShift	= 16,        /* MSS value position */
	MSSMask		= 0xfff,     /* MSS value + LargeSend bit: 12 bits */
	IPCS		= (1 << 18), /* Calculate IP checksum */
	UDPCS		= (1 << 17), /* Calculate UDP/IP checksum */
	TCPCS		= (1 << 16), /* Calculate TCP/IP checksum */
	TxVlanTag	= (1 << 17), /* Add VLAN tag */

	/* Rx private */
	PID1		= (1 << 18), /* Protocol ID bit 1/2 */
	PID0		= (1 << 17), /* Protocol ID bit 2/2 */

#define RxProtoUDP	(PID1)
#define RxProtoTCP	(PID0)
#define RxProtoIP	(PID1 | PID0)
#define RxProtoMask	RxProtoIP

	IPFail		= (1 << 16), /* IP checksum failed */
	UDPFail		= (1 << 15), /* UDP/IP checksum failed */
	TCPFail		= (1 << 14), /* TCP/IP checksum failed */
	RxVlanTag	= (1 << 16), /* VLAN tag available */
};

#define RsvdMask	0x3fffc000

struct TxDesc {
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	__le32 opts1;
	__le32 opts2;
	__le64 addr;
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};

struct RxDesc {
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	__le32 opts1;
	__le32 opts2;
	__le64 addr;
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};

struct ring_info {
	struct sk_buff	*skb;
	u32		len;
	u8		__pad[sizeof(void *) - sizeof(u32)];
};

443
enum features {
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	RTL_FEATURE_WOL		= (1 << 0),
	RTL_FEATURE_MSI		= (1 << 1),
	RTL_FEATURE_GMII	= (1 << 2),
447 448
};

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struct rtl8169_counters {
	__le64	tx_packets;
	__le64	rx_packets;
	__le64	tx_errors;
	__le32	rx_errors;
	__le16	rx_missed;
	__le16	align_errors;
	__le32	tx_one_collision;
	__le32	tx_multi_collision;
	__le64	rx_unicast;
	__le64	rx_broadcast;
	__le32	rx_multicast;
	__le16	tx_aborted;
	__le16	tx_underun;
};

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struct rtl8169_private {
	void __iomem *mmio_addr;	/* memory map physical address */
	struct pci_dev *pci_dev;	/* Index of PCI device */
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	struct net_device *dev;
469
	struct napi_struct napi;
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	spinlock_t lock;		/* spin lock flag */
471
	u32 msg_enable;
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	int chipset;
	int mac_version;
	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
	u32 dirty_rx;
	u32 dirty_tx;
	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */
	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */
	dma_addr_t TxPhyAddr;
	dma_addr_t RxPhyAddr;
	struct sk_buff *Rx_skbuff[NUM_RX_DESC];	/* Rx data buffers */
	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */
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	unsigned align;
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	unsigned rx_buf_sz;
	struct timer_list timer;
	u16 cp_cmd;
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	u16 intr_event;
	u16 napi_event;
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	u16 intr_mask;
	int phy_1000_ctrl_reg;
#ifdef CONFIG_R8169_VLAN
	struct vlan_group *vlgrp;
#endif
	int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
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	int (*get_settings)(struct net_device *, struct ethtool_cmd *);
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	void (*phy_reset_enable)(void __iomem *);
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	void (*hw_start)(struct net_device *);
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	unsigned int (*phy_reset_pending)(void __iomem *);
	unsigned int (*link_ok)(void __iomem *);
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	int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
502
	int pcie_cap;
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	struct delayed_work task;
504
	unsigned features;
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	struct mii_if_info mii;
507
	struct rtl8169_counters counters;
508
	u32 saved_wolopts;
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};

511
MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
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MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
module_param(rx_copybreak, int, 0);
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MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
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module_param(use_dac, int, 0);
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MODULE_PARM_DESC(use_dac, "Enable PCI DAC. -1 defaults on for PCI Express only."
" Unsafe on 32 bit PCI slot.");
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module_param_named(debug, debug.msg_enable, int, 0);
MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
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MODULE_LICENSE("GPL");
MODULE_VERSION(RTL8169_VERSION);

static int rtl8169_open(struct net_device *dev);
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static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
				      struct net_device *dev);
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static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
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static int rtl8169_init_ring(struct net_device *dev);
528
static void rtl_hw_start(struct net_device *dev);
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static int rtl8169_close(struct net_device *dev);
530
static void rtl_set_rx_mode(struct net_device *dev);
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static void rtl8169_tx_timeout(struct net_device *dev);
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static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
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static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
534
				void __iomem *, u32 budget);
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static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
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static void rtl8169_down(struct net_device *dev);
537
static void rtl8169_rx_clear(struct rtl8169_private *tp);
538
static int rtl8169_poll(struct napi_struct *napi, int budget);
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static const unsigned int rtl8169_rx_config =
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	(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
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static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
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{
	int i;

547
	RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
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549
	for (i = 20; i > 0; i--) {
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		/*
		 * Check if the RTL8169 has completed writing to the specified
		 * MII register.
		 */
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		if (!(RTL_R32(PHYAR) & 0x80000000))
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			break;
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		udelay(25);
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	}
}

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static int mdio_read(void __iomem *ioaddr, int reg_addr)
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{
	int i, value = -1;

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	RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
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	for (i = 20; i > 0; i--) {
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		/*
		 * Check if the RTL8169 has completed retrieving data from
		 * the specified MII register.
		 */
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		if (RTL_R32(PHYAR) & 0x80000000) {
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			value = RTL_R32(PHYAR) & 0xffff;
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			break;
		}
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		udelay(25);
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	}
	return value;
}

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static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
{
	mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
}

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static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
{
	int val;

	val = mdio_read(ioaddr, reg_addr);
	mdio_write(ioaddr, reg_addr, (val | p) & ~m);
}

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static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
			   int val)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;

	mdio_write(ioaddr, location, val);
}

static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;

	return mdio_read(ioaddr, location);
}

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static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
{
	unsigned int i;

	RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
		(reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);

	for (i = 0; i < 100; i++) {
		if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
			break;
		udelay(10);
	}
}

static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
{
	u16 value = 0xffff;
	unsigned int i;

	RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);

	for (i = 0; i < 100; i++) {
		if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
			value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
			break;
		}
		udelay(10);
	}

	return value;
}

static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
{
	unsigned int i;

	RTL_W32(CSIDR, value);
	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);

	for (i = 0; i < 100; i++) {
		if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
			break;
		udelay(10);
	}
}

static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
{
	u32 value = ~0x00;
	unsigned int i;

	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);

	for (i = 0; i < 100; i++) {
		if (RTL_R32(CSIAR) & CSIAR_FLAG) {
			value = RTL_R32(CSIDR);
			break;
		}
		udelay(10);
	}

	return value;
}

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static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
{
	u8 value = 0xff;
	unsigned int i;

	RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);

	for (i = 0; i < 300; i++) {
		if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
			value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
			break;
		}
		udelay(100);
	}

	return value;
}

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static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
{
	RTL_W16(IntrMask, 0x0000);

	RTL_W16(IntrStatus, 0xffff);
}

static void rtl8169_asic_down(void __iomem *ioaddr)
{
	RTL_W8(ChipCmd, 0x00);
	rtl8169_irq_mask_and_ack(ioaddr);
	RTL_R16(CPlusCmd);
}

static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
{
	return RTL_R32(TBICSR) & TBIReset;
}

static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
{
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	return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
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}

static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
{
	return RTL_R32(TBICSR) & TBILinkOk;
}

static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
{
	return RTL_R8(PHYstatus) & LinkStatus;
}

static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
{
	RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
}

static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
{
	unsigned int val;

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	val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
	mdio_write(ioaddr, MII_BMCR, val & 0xffff);
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}

static void rtl8169_check_link_status(struct net_device *dev,
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				      struct rtl8169_private *tp,
				      void __iomem *ioaddr)
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{
	unsigned long flags;

	spin_lock_irqsave(&tp->lock, flags);
	if (tp->link_ok(ioaddr)) {
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		/* This is to cancel a scheduled suspend if there's one. */
		pm_request_resume(&tp->pci_dev->dev);
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		netif_carrier_on(dev);
752
		netif_info(tp, ifup, dev, "link up\n");
753
	} else {
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		netif_carrier_off(dev);
755
		netif_info(tp, ifdown, dev, "link down\n");
756
		pm_schedule_suspend(&tp->pci_dev->dev, 100);
757
	}
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	spin_unlock_irqrestore(&tp->lock, flags);
}

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#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)

static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
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{
	void __iomem *ioaddr = tp->mmio_addr;
	u8 options;
767
	u32 wolopts = 0;
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	options = RTL_R8(Config1);
	if (!(options & PMEnable))
771
		return 0;
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	options = RTL_R8(Config3);
	if (options & LinkUp)
775
		wolopts |= WAKE_PHY;
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	if (options & MagicPacket)
777
		wolopts |= WAKE_MAGIC;
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	options = RTL_R8(Config5);
	if (options & UWF)
781
		wolopts |= WAKE_UCAST;
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	if (options & BWF)
783
		wolopts |= WAKE_BCAST;
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	if (options & MWF)
785
		wolopts |= WAKE_MCAST;
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787
	return wolopts;
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}

790
static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
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{
	struct rtl8169_private *tp = netdev_priv(dev);
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	spin_lock_irq(&tp->lock);

	wol->supported = WAKE_ANY;
	wol->wolopts = __rtl8169_get_wol(tp);

	spin_unlock_irq(&tp->lock);
}

static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
{
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	void __iomem *ioaddr = tp->mmio_addr;
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	unsigned int i;
806
	static const struct {
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		u32 opt;
		u16 reg;
		u8  mask;
	} cfg[] = {
		{ WAKE_ANY,   Config1, PMEnable },
		{ WAKE_PHY,   Config3, LinkUp },
		{ WAKE_MAGIC, Config3, MagicPacket },
		{ WAKE_UCAST, Config5, UWF },
		{ WAKE_BCAST, Config5, BWF },
		{ WAKE_MCAST, Config5, MWF },
		{ WAKE_ANY,   Config5, LanWake }
	};

	RTL_W8(Cfg9346, Cfg9346_Unlock);

	for (i = 0; i < ARRAY_SIZE(cfg); i++) {
		u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
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		if (wolopts & cfg[i].opt)
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			options |= cfg[i].mask;
		RTL_W8(cfg[i].reg, options);
	}

	RTL_W8(Cfg9346, Cfg9346_Lock);
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}

static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	spin_lock_irq(&tp->lock);
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	if (wol->wolopts)
		tp->features |= RTL_FEATURE_WOL;
	else
		tp->features &= ~RTL_FEATURE_WOL;
842
	__rtl8169_set_wol(tp, wol->wolopts);
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	device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
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	spin_unlock_irq(&tp->lock);

	return 0;
}

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static void rtl8169_get_drvinfo(struct net_device *dev,
				struct ethtool_drvinfo *info)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	strcpy(info->driver, MODULENAME);
	strcpy(info->version, RTL8169_VERSION);
	strcpy(info->bus_info, pci_name(tp->pci_dev));
}

static int rtl8169_get_regs_len(struct net_device *dev)
{
	return R8169_REGS_SIZE;
}

static int rtl8169_set_speed_tbi(struct net_device *dev,
				 u8 autoneg, u16 speed, u8 duplex)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	int ret = 0;
	u32 reg;

	reg = RTL_R32(TBICSR);
	if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
	    (duplex == DUPLEX_FULL)) {
		RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
	} else if (autoneg == AUTONEG_ENABLE)
		RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
	else {
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		netif_warn(tp, link, dev,
			   "incorrect speed setting refused in TBI mode\n");
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		ret = -EOPNOTSUPP;
	}

	return ret;
}

static int rtl8169_set_speed_xmii(struct net_device *dev,
				  u8 autoneg, u16 speed, u8 duplex)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
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	int giga_ctrl, bmcr;
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	if (autoneg == AUTONEG_ENABLE) {
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		int auto_nego;

		auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
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		auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
			      ADVERTISE_100HALF | ADVERTISE_100FULL);
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		auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
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		giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
		giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
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		/* The 8100e/8101e/8102e do Fast Ethernet only. */
		if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
		    (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
		    (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
		    (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
		    (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
		    (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
		    (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
		    (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
			giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
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		} else {
			netif_info(tp, link, dev,
				   "PHY does not support 1000Mbps\n");
919
		}
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		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;

		if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
		    (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
		    (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
			/*
			 * Wake up the PHY.
			 * Vendor specific (0x1f) and reserved (0x0e) MII
			 * registers.
			 */
			mdio_write(ioaddr, 0x1f, 0x0000);
			mdio_write(ioaddr, 0x0e, 0x0000);
		}

		mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
		mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
	} else {
		giga_ctrl = 0;

		if (speed == SPEED_10)
			bmcr = 0;
		else if (speed == SPEED_100)
			bmcr = BMCR_SPEED100;
		else
			return -EINVAL;

		if (duplex == DUPLEX_FULL)
			bmcr |= BMCR_FULLDPLX;
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		mdio_write(ioaddr, 0x1f, 0x0000);
	}

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	tp->phy_1000_ctrl_reg = giga_ctrl;

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	mdio_write(ioaddr, MII_BMCR, bmcr);

	if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
		if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
			mdio_write(ioaddr, 0x17, 0x2138);
			mdio_write(ioaddr, 0x0e, 0x0260);
		} else {
			mdio_write(ioaddr, 0x17, 0x2108);
			mdio_write(ioaddr, 0x0e, 0x0000);
		}
	}

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	return 0;
}

static int rtl8169_set_speed(struct net_device *dev,
			     u8 autoneg, u16 speed, u8 duplex)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	int ret;

	ret = tp->set_speed(dev, autoneg, speed, duplex);

979
	if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
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		mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);

	return ret;
}

static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&tp->lock, flags);
	ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
	spin_unlock_irqrestore(&tp->lock, flags);
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	return ret;
}

static u32 rtl8169_get_rx_csum(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	return tp->cp_cmd & RxChkSum;
}

static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	unsigned long flags;

	spin_lock_irqsave(&tp->lock, flags);

	if (data)
		tp->cp_cmd |= RxChkSum;
	else
		tp->cp_cmd &= ~RxChkSum;

	RTL_W16(CPlusCmd, tp->cp_cmd);
	RTL_R16(CPlusCmd);

	spin_unlock_irqrestore(&tp->lock, flags);

	return 0;
}

#ifdef CONFIG_R8169_VLAN

static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
				      struct sk_buff *skb)
{
	return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
		TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
}

static void rtl8169_vlan_rx_register(struct net_device *dev,
				     struct vlan_group *grp)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	unsigned long flags;

	spin_lock_irqsave(&tp->lock, flags);
	tp->vlgrp = grp;
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	/*
	 * Do not disable RxVlan on 8110SCd.
	 */
	if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
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		tp->cp_cmd |= RxVlan;
	else
		tp->cp_cmd &= ~RxVlan;
	RTL_W16(CPlusCmd, tp->cp_cmd);
	RTL_R16(CPlusCmd);
	spin_unlock_irqrestore(&tp->lock, flags);
}

static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
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			       struct sk_buff *skb, int polling)
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{
	u32 opts2 = le32_to_cpu(desc->opts2);
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	struct vlan_group *vlgrp = tp->vlgrp;
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	int ret;

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	if (vlgrp && (opts2 & RxVlanTag)) {
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		__vlan_hwaccel_rx(skb, vlgrp, swab16(opts2 & 0xffff), polling);
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		ret = 0;
	} else
		ret = -1;
	desc->opts2 = 0;
	return ret;
}

#else /* !CONFIG_R8169_VLAN */

static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
				      struct sk_buff *skb)
{
	return 0;
}

static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
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			       struct sk_buff *skb, int polling)
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{
	return -1;
}

#endif

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static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
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{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	u32 status;

	cmd->supported =
		SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
	cmd->port = PORT_FIBRE;
	cmd->transceiver = XCVR_INTERNAL;

	status = RTL_R32(TBICSR);
	cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
	cmd->autoneg = !!(status & TBINwEnable);

	cmd->speed = SPEED_1000;
	cmd->duplex = DUPLEX_FULL; /* Always set */
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	return 0;
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}

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static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
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{
	struct rtl8169_private *tp = netdev_priv(dev);
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	return mii_ethtool_gset(&tp->mii, cmd);
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}

static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	unsigned long flags;
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	int rc;
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	spin_lock_irqsave(&tp->lock, flags);

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	rc = tp->get_settings(dev, cmd);
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	spin_unlock_irqrestore(&tp->lock, flags);
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	return rc;
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}

static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
			     void *p)
{
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	struct rtl8169_private *tp = netdev_priv(dev);
	unsigned long flags;
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	if (regs->len > R8169_REGS_SIZE)
		regs->len = R8169_REGS_SIZE;
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	spin_lock_irqsave(&tp->lock, flags);
	memcpy_fromio(p, tp->mmio_addr, regs->len);
	spin_unlock_irqrestore(&tp->lock, flags);
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}

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static u32 rtl8169_get_msglevel(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	return tp->msg_enable;
}

static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	tp->msg_enable = value;
}

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static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
	"tx_packets",
	"rx_packets",
	"tx_errors",
	"rx_errors",
	"rx_missed",
	"align_errors",
	"tx_single_collisions",
	"tx_multi_collisions",
	"unicast",
	"broadcast",
	"multicast",
	"tx_aborted",
	"tx_underrun",
};

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static int rtl8169_get_sset_count(struct net_device *dev, int sset)
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{
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	switch (sset) {
	case ETH_SS_STATS:
		return ARRAY_SIZE(rtl8169_gstrings);
	default:
		return -EOPNOTSUPP;
	}
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}

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static void rtl8169_update_counters(struct net_device *dev)
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{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	struct rtl8169_counters *counters;
	dma_addr_t paddr;
	u32 cmd;
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	int wait = 1000;
1192

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	/*
	 * Some chips are unable to dump tally counters when the receiver
	 * is disabled.
	 */
	if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
		return;
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	counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
	if (!counters)
		return;

	RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
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	cmd = (u64)paddr & DMA_BIT_MASK(32);
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	RTL_W32(CounterAddrLow, cmd);
	RTL_W32(CounterAddrLow, cmd | CounterDump);

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	while (wait--) {
		if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
			/* copy updated counters */
			memcpy(&tp->counters, counters, sizeof(*counters));
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			break;
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		}
		udelay(10);
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	}

	RTL_W32(CounterAddrLow, 0);
	RTL_W32(CounterAddrHigh, 0);

	pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
}

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static void rtl8169_get_ethtool_stats(struct net_device *dev,
				      struct ethtool_stats *stats, u64 *data)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	ASSERT_RTNL();

	rtl8169_update_counters(dev);

	data[0] = le64_to_cpu(tp->counters.tx_packets);
	data[1] = le64_to_cpu(tp->counters.rx_packets);
	data[2] = le64_to_cpu(tp->counters.tx_errors);
	data[3] = le32_to_cpu(tp->counters.rx_errors);
	data[4] = le16_to_cpu(tp->counters.rx_missed);
	data[5] = le16_to_cpu(tp->counters.align_errors);
	data[6] = le32_to_cpu(tp->counters.tx_one_collision);
	data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
	data[8] = le64_to_cpu(tp->counters.rx_unicast);
	data[9] = le64_to_cpu(tp->counters.rx_broadcast);
	data[10] = le32_to_cpu(tp->counters.rx_multicast);
	data[11] = le16_to_cpu(tp->counters.tx_aborted);
	data[12] = le16_to_cpu(tp->counters.tx_underun);
}

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static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
{
	switch(stringset) {
	case ETH_SS_STATS:
		memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
		break;
	}
}

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static const struct ethtool_ops rtl8169_ethtool_ops = {
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	.get_drvinfo		= rtl8169_get_drvinfo,
	.get_regs_len		= rtl8169_get_regs_len,
	.get_link		= ethtool_op_get_link,
	.get_settings		= rtl8169_get_settings,
	.set_settings		= rtl8169_set_settings,
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	.get_msglevel		= rtl8169_get_msglevel,
	.set_msglevel		= rtl8169_set_msglevel,
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	.get_rx_csum		= rtl8169_get_rx_csum,
	.set_rx_csum		= rtl8169_set_rx_csum,
	.set_tx_csum		= ethtool_op_set_tx_csum,
	.set_sg			= ethtool_op_set_sg,
	.set_tso		= ethtool_op_set_tso,
	.get_regs		= rtl8169_get_regs,
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	.get_wol		= rtl8169_get_wol,
	.set_wol		= rtl8169_set_wol,
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	.get_strings		= rtl8169_get_strings,
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	.get_sset_count		= rtl8169_get_sset_count,
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	.get_ethtool_stats	= rtl8169_get_ethtool_stats,
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};

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static void rtl8169_get_mac_version(struct rtl8169_private *tp,
				    void __iomem *ioaddr)
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{
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	/*
	 * The driver currently handles the 8168Bf and the 8168Be identically
	 * but they can be identified more specifically through the test below
	 * if needed:
	 *
	 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
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	 *
	 * Same thing for the 8101Eb and the 8101Ec:
	 *
	 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
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	 */
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	static const struct {
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		u32 mask;
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		u32 val;
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		int mac_version;
	} mac_info[] = {
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		/* 8168D family. */
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		{ 0x7cf00000, 0x28300000,	RTL_GIGA_MAC_VER_26 },
		{ 0x7cf00000, 0x28100000,	RTL_GIGA_MAC_VER_25 },
		{ 0x7c800000, 0x28800000,	RTL_GIGA_MAC_VER_27 },
		{ 0x7c800000, 0x28000000,	RTL_GIGA_MAC_VER_26 },
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		/* 8168C family. */
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		{ 0x7cf00000, 0x3ca00000,	RTL_GIGA_MAC_VER_24 },
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		{ 0x7cf00000, 0x3c900000,	RTL_GIGA_MAC_VER_23 },
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		{ 0x7cf00000, 0x3c800000,	RTL_GIGA_MAC_VER_18 },
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		{ 0x7c800000, 0x3c800000,	RTL_GIGA_MAC_VER_24 },
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		{ 0x7cf00000, 0x3c000000,	RTL_GIGA_MAC_VER_19 },
		{ 0x7cf00000, 0x3c200000,	RTL_GIGA_MAC_VER_20 },
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		{ 0x7cf00000, 0x3c300000,	RTL_GIGA_MAC_VER_21 },
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		{ 0x7cf00000, 0x3c400000,	RTL_GIGA_MAC_VER_22 },
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		{ 0x7c800000, 0x3c000000,	RTL_GIGA_MAC_VER_22 },
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		/* 8168B family. */
		{ 0x7cf00000, 0x38000000,	RTL_GIGA_MAC_VER_12 },
		{ 0x7cf00000, 0x38500000,	RTL_GIGA_MAC_VER_17 },
		{ 0x7c800000, 0x38000000,	RTL_GIGA_MAC_VER_17 },
		{ 0x7c800000, 0x30000000,	RTL_GIGA_MAC_VER_11 },

		/* 8101 family. */
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		{ 0x7cf00000, 0x34a00000,	RTL_GIGA_MAC_VER_09 },
		{ 0x7cf00000, 0x24a00000,	RTL_GIGA_MAC_VER_09 },
		{ 0x7cf00000, 0x34900000,	RTL_GIGA_MAC_VER_08 },
		{ 0x7cf00000, 0x24900000,	RTL_GIGA_MAC_VER_08 },
		{ 0x7cf00000, 0x34800000,	RTL_GIGA_MAC_VER_07 },
		{ 0x7cf00000, 0x24800000,	RTL_GIGA_MAC_VER_07 },
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		{ 0x7cf00000, 0x34000000,	RTL_GIGA_MAC_VER_13 },
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		{ 0x7cf00000, 0x34300000,	RTL_GIGA_MAC_VER_10 },
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		{ 0x7cf00000, 0x34200000,	RTL_GIGA_MAC_VER_16 },
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		{ 0x7c800000, 0x34800000,	RTL_GIGA_MAC_VER_09 },
		{ 0x7c800000, 0x24800000,	RTL_GIGA_MAC_VER_09 },
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		{ 0x7c800000, 0x34000000,	RTL_GIGA_MAC_VER_16 },
		/* FIXME: where did these entries come from ? -- FR */
		{ 0xfc800000, 0x38800000,	RTL_GIGA_MAC_VER_15 },
		{ 0xfc800000, 0x30800000,	RTL_GIGA_MAC_VER_14 },

		/* 8110 family. */
		{ 0xfc800000, 0x98000000,	RTL_GIGA_MAC_VER_06 },
		{ 0xfc800000, 0x18000000,	RTL_GIGA_MAC_VER_05 },
		{ 0xfc800000, 0x10000000,	RTL_GIGA_MAC_VER_04 },
		{ 0xfc800000, 0x04000000,	RTL_GIGA_MAC_VER_03 },
		{ 0xfc800000, 0x00800000,	RTL_GIGA_MAC_VER_02 },
		{ 0xfc800000, 0x00000000,	RTL_GIGA_MAC_VER_01 },

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		/* Catch-all */
		{ 0x00000000, 0x00000000,	RTL_GIGA_MAC_NONE   }
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	}, *p = mac_info;
	u32 reg;

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	reg = RTL_R32(TxConfig);
	while ((reg & p->mask) != p->val)
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		p++;
	tp->mac_version = p->mac_version;
}

static void rtl8169_print_mac_version(struct rtl8169_private *tp)
{
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	dprintk("mac_version = 0x%02x\n", tp->mac_version);
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}

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struct phy_reg {
	u16 reg;
	u16 val;
};

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static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
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{
	while (len-- > 0) {
		mdio_write(ioaddr, regs->reg, regs->val);
		regs++;
	}
}

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static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
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{
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	static const struct phy_reg phy_reg_init[] = {
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		{ 0x1f, 0x0001 },
		{ 0x06, 0x006e },
		{ 0x08, 0x0708 },
		{ 0x15, 0x4000 },
		{ 0x18, 0x65c7 },
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		{ 0x1f, 0x0001 },
		{ 0x03, 0x00a1 },
		{ 0x02, 0x0008 },
		{ 0x01, 0x0120 },
		{ 0x00, 0x1000 },
		{ 0x04, 0x0800 },
		{ 0x04, 0x0000 },
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		{ 0x03, 0xff41 },
		{ 0x02, 0xdf60 },
		{ 0x01, 0x0140 },
		{ 0x00, 0x0077 },
		{ 0x04, 0x7800 },
		{ 0x04, 0x7000 },

		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf0f9 },
		{ 0x04, 0x9800 },
		{ 0x04, 0x9000 },

		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0xff95 },
		{ 0x00, 0xba00 },
		{ 0x04, 0xa800 },
		{ 0x04, 0xa000 },

		{ 0x03, 0xff41 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x0140 },
		{ 0x00, 0x00bb },
		{ 0x04, 0xb800 },
		{ 0x04, 0xb000 },

		{ 0x03, 0xdf41 },
		{ 0x02, 0xdc60 },
		{ 0x01, 0x6340 },
		{ 0x00, 0x007d },
		{ 0x04, 0xd800 },
		{ 0x04, 0xd000 },

		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x100a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0xf000 },

		{ 0x1f, 0x0000 },
		{ 0x0b, 0x0000 },
		{ 0x00, 0x9200 }
	};
L
Linus Torvalds 已提交
1437

F
françois romieu 已提交
1438
	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
L
Linus Torvalds 已提交
1439 1440
}

1441 1442
static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
{
1443
	static const struct phy_reg phy_reg_init[] = {
F
Francois Romieu 已提交
1444 1445 1446 1447 1448 1449
		{ 0x1f, 0x0002 },
		{ 0x01, 0x90d0 },
		{ 0x1f, 0x0000 }
	};

	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1450 1451
}

1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471
static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
					   void __iomem *ioaddr)
{
	struct pci_dev *pdev = tp->pci_dev;
	u16 vendor_id, device_id;

	pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
	pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);

	if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
		return;

	mdio_write(ioaddr, 0x1f, 0x0001);
	mdio_write(ioaddr, 0x10, 0xf01b);
	mdio_write(ioaddr, 0x1f, 0x0000);
}

static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
				     void __iomem *ioaddr)
{
1472
	static const struct phy_reg phy_reg_init[] = {
1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516
		{ 0x1f, 0x0001 },
		{ 0x04, 0x0000 },
		{ 0x03, 0x00a1 },
		{ 0x02, 0x0008 },
		{ 0x01, 0x0120 },
		{ 0x00, 0x1000 },
		{ 0x04, 0x0800 },
		{ 0x04, 0x9000 },
		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf099 },
		{ 0x04, 0x9800 },
		{ 0x04, 0xa000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0xff95 },
		{ 0x00, 0xba00 },
		{ 0x04, 0xa800 },
		{ 0x04, 0xf000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x101a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x10, 0xf41b },
		{ 0x14, 0xfb54 },
		{ 0x18, 0xf5c7 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
		{ 0x1f, 0x0000 }
	};

	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));

	rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
}

1517 1518
static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
{
1519
	static const struct phy_reg phy_reg_init[] = {
1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569
		{ 0x1f, 0x0001 },
		{ 0x04, 0x0000 },
		{ 0x03, 0x00a1 },
		{ 0x02, 0x0008 },
		{ 0x01, 0x0120 },
		{ 0x00, 0x1000 },
		{ 0x04, 0x0800 },
		{ 0x04, 0x9000 },
		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf099 },
		{ 0x04, 0x9800 },
		{ 0x04, 0xa000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0xff95 },
		{ 0x00, 0xba00 },
		{ 0x04, 0xa800 },
		{ 0x04, 0xf000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x101a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x0b, 0x8480 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x18, 0x67c7 },
		{ 0x04, 0x2000 },
		{ 0x03, 0x002f },
		{ 0x02, 0x4360 },
		{ 0x01, 0x0109 },
		{ 0x00, 0x3022 },
		{ 0x04, 0x2800 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
		{ 0x1f, 0x0000 }
	};

	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
}

1570 1571
static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
{
1572
	static const struct phy_reg phy_reg_init[] = {
1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584
		{ 0x10, 0xf41b },
		{ 0x1f, 0x0000 }
	};

	mdio_write(ioaddr, 0x1f, 0x0001);
	mdio_patch(ioaddr, 0x16, 1 << 0);

	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
}

static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
{
1585
	static const struct phy_reg phy_reg_init[] = {
1586 1587 1588 1589 1590 1591 1592 1593
		{ 0x1f, 0x0001 },
		{ 0x10, 0xf41b },
		{ 0x1f, 0x0000 }
	};

	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
}

F
Francois Romieu 已提交
1594
static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
F
Francois Romieu 已提交
1595
{
1596
	static const struct phy_reg phy_reg_init[] = {
F
Francois Romieu 已提交
1597 1598 1599 1600 1601 1602 1603 1604 1605 1606
		{ 0x1f, 0x0000 },
		{ 0x1d, 0x0f00 },
		{ 0x1f, 0x0002 },
		{ 0x0c, 0x1ec8 },
		{ 0x1f, 0x0000 }
	};

	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
}

F
Francois Romieu 已提交
1607 1608
static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
{
1609
	static const struct phy_reg phy_reg_init[] = {
F
Francois Romieu 已提交
1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621
		{ 0x1f, 0x0001 },
		{ 0x1d, 0x3d98 },
		{ 0x1f, 0x0000 }
	};

	mdio_write(ioaddr, 0x1f, 0x0000);
	mdio_patch(ioaddr, 0x14, 1 << 5);
	mdio_patch(ioaddr, 0x0d, 1 << 5);

	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
}

1622
static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
F
Francois Romieu 已提交
1623
{
1624
	static const struct phy_reg phy_reg_init[] = {
1625 1626
		{ 0x1f, 0x0001 },
		{ 0x12, 0x2300 },
F
Francois Romieu 已提交
1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637
		{ 0x1f, 0x0002 },
		{ 0x00, 0x88d4 },
		{ 0x01, 0x82b1 },
		{ 0x03, 0x7002 },
		{ 0x08, 0x9e30 },
		{ 0x09, 0x01f0 },
		{ 0x0a, 0x5500 },
		{ 0x0c, 0x00c8 },
		{ 0x1f, 0x0003 },
		{ 0x12, 0xc096 },
		{ 0x16, 0x000a },
1638 1639 1640 1641
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0000 },
		{ 0x09, 0x2000 },
		{ 0x09, 0x0000 }
F
Francois Romieu 已提交
1642 1643 1644
	};

	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1645 1646 1647 1648

	mdio_patch(ioaddr, 0x14, 1 << 5);
	mdio_patch(ioaddr, 0x0d, 1 << 5);
	mdio_write(ioaddr, 0x1f, 0x0000);
F
Francois Romieu 已提交
1649 1650
}

1651
static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1652
{
1653
	static const struct phy_reg phy_reg_init[] = {
1654
		{ 0x1f, 0x0001 },
1655
		{ 0x12, 0x2300 },
1656 1657 1658 1659 1660 1661 1662
		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf099 },
		{ 0x04, 0x9800 },
		{ 0x04, 0x9000 },
		{ 0x1d, 0x3d98 },
1663 1664
		{ 0x1f, 0x0002 },
		{ 0x0c, 0x7eb8 },
1665 1666 1667
		{ 0x06, 0x0761 },
		{ 0x1f, 0x0003 },
		{ 0x16, 0x0f0a },
1668 1669 1670 1671
		{ 0x1f, 0x0000 }
	};

	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1672 1673 1674 1675 1676

	mdio_patch(ioaddr, 0x16, 1 << 0);
	mdio_patch(ioaddr, 0x14, 1 << 5);
	mdio_patch(ioaddr, 0x0d, 1 << 5);
	mdio_write(ioaddr, 0x1f, 0x0000);
1677 1678
}

F
Francois Romieu 已提交
1679 1680
static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
{
1681
	static const struct phy_reg phy_reg_init[] = {
F
Francois Romieu 已提交
1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700
		{ 0x1f, 0x0001 },
		{ 0x12, 0x2300 },
		{ 0x1d, 0x3d98 },
		{ 0x1f, 0x0002 },
		{ 0x0c, 0x7eb8 },
		{ 0x06, 0x5461 },
		{ 0x1f, 0x0003 },
		{ 0x16, 0x0f0a },
		{ 0x1f, 0x0000 }
	};

	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));

	mdio_patch(ioaddr, 0x16, 1 << 0);
	mdio_patch(ioaddr, 0x14, 1 << 5);
	mdio_patch(ioaddr, 0x0d, 1 << 5);
	mdio_write(ioaddr, 0x1f, 0x0000);
}

1701 1702 1703 1704 1705
static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
{
	rtl8168c_3_hw_phy_config(ioaddr);
}

1706
static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
F
Francois Romieu 已提交
1707
{
1708
	static const struct phy_reg phy_reg_init_0[] = {
F
Francois Romieu 已提交
1709
		{ 0x1f, 0x0001 },
1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720
		{ 0x06, 0x4064 },
		{ 0x07, 0x2863 },
		{ 0x08, 0x059c },
		{ 0x09, 0x26b4 },
		{ 0x0a, 0x6a19 },
		{ 0x0b, 0xdcc8 },
		{ 0x10, 0xf06d },
		{ 0x14, 0x7f68 },
		{ 0x18, 0x7fd9 },
		{ 0x1c, 0xf0ff },
		{ 0x1d, 0x3d9c },
F
Francois Romieu 已提交
1721
		{ 0x1f, 0x0003 },
1722 1723 1724 1725 1726
		{ 0x12, 0xf49f },
		{ 0x13, 0x070b },
		{ 0x1a, 0x05ad },
		{ 0x14, 0x94c0 }
	};
1727
	static const struct phy_reg phy_reg_init_1[] = {
F
Francois Romieu 已提交
1728
		{ 0x1f, 0x0002 },
1729 1730 1731 1732 1733
		{ 0x06, 0x5561 },
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8332 },
		{ 0x06, 0x5561 }
	};
1734
	static const struct phy_reg phy_reg_init_2[] = {
1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082
		{ 0x1f, 0x0005 },
		{ 0x05, 0xffc2 },
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8000 },
		{ 0x06, 0xf8f9 },
		{ 0x06, 0xfaef },
		{ 0x06, 0x59ee },
		{ 0x06, 0xf8ea },
		{ 0x06, 0x00ee },
		{ 0x06, 0xf8eb },
		{ 0x06, 0x00e0 },
		{ 0x06, 0xf87c },
		{ 0x06, 0xe1f8 },
		{ 0x06, 0x7d59 },
		{ 0x06, 0x0fef },
		{ 0x06, 0x0139 },
		{ 0x06, 0x029e },
		{ 0x06, 0x06ef },
		{ 0x06, 0x1039 },
		{ 0x06, 0x089f },
		{ 0x06, 0x2aee },
		{ 0x06, 0xf8ea },
		{ 0x06, 0x00ee },
		{ 0x06, 0xf8eb },
		{ 0x06, 0x01e0 },
		{ 0x06, 0xf87c },
		{ 0x06, 0xe1f8 },
		{ 0x06, 0x7d58 },
		{ 0x06, 0x409e },
		{ 0x06, 0x0f39 },
		{ 0x06, 0x46aa },
		{ 0x06, 0x0bbf },
		{ 0x06, 0x8290 },
		{ 0x06, 0xd682 },
		{ 0x06, 0x9802 },
		{ 0x06, 0x014f },
		{ 0x06, 0xae09 },
		{ 0x06, 0xbf82 },
		{ 0x06, 0x98d6 },
		{ 0x06, 0x82a0 },
		{ 0x06, 0x0201 },
		{ 0x06, 0x4fef },
		{ 0x06, 0x95fe },
		{ 0x06, 0xfdfc },
		{ 0x06, 0x05f8 },
		{ 0x06, 0xf9fa },
		{ 0x06, 0xeef8 },
		{ 0x06, 0xea00 },
		{ 0x06, 0xeef8 },
		{ 0x06, 0xeb00 },
		{ 0x06, 0xe2f8 },
		{ 0x06, 0x7ce3 },
		{ 0x06, 0xf87d },
		{ 0x06, 0xa511 },
		{ 0x06, 0x1112 },
		{ 0x06, 0xd240 },
		{ 0x06, 0xd644 },
		{ 0x06, 0x4402 },
		{ 0x06, 0x8217 },
		{ 0x06, 0xd2a0 },
		{ 0x06, 0xd6aa },
		{ 0x06, 0xaa02 },
		{ 0x06, 0x8217 },
		{ 0x06, 0xae0f },
		{ 0x06, 0xa544 },
		{ 0x06, 0x4402 },
		{ 0x06, 0xae4d },
		{ 0x06, 0xa5aa },
		{ 0x06, 0xaa02 },
		{ 0x06, 0xae47 },
		{ 0x06, 0xaf82 },
		{ 0x06, 0x13ee },
		{ 0x06, 0x834e },
		{ 0x06, 0x00ee },
		{ 0x06, 0x834d },
		{ 0x06, 0x0fee },
		{ 0x06, 0x834c },
		{ 0x06, 0x0fee },
		{ 0x06, 0x834f },
		{ 0x06, 0x00ee },
		{ 0x06, 0x8351 },
		{ 0x06, 0x00ee },
		{ 0x06, 0x834a },
		{ 0x06, 0xffee },
		{ 0x06, 0x834b },
		{ 0x06, 0xffe0 },
		{ 0x06, 0x8330 },
		{ 0x06, 0xe183 },
		{ 0x06, 0x3158 },
		{ 0x06, 0xfee4 },
		{ 0x06, 0xf88a },
		{ 0x06, 0xe5f8 },
		{ 0x06, 0x8be0 },
		{ 0x06, 0x8332 },
		{ 0x06, 0xe183 },
		{ 0x06, 0x3359 },
		{ 0x06, 0x0fe2 },
		{ 0x06, 0x834d },
		{ 0x06, 0x0c24 },
		{ 0x06, 0x5af0 },
		{ 0x06, 0x1e12 },
		{ 0x06, 0xe4f8 },
		{ 0x06, 0x8ce5 },
		{ 0x06, 0xf88d },
		{ 0x06, 0xaf82 },
		{ 0x06, 0x13e0 },
		{ 0x06, 0x834f },
		{ 0x06, 0x10e4 },
		{ 0x06, 0x834f },
		{ 0x06, 0xe083 },
		{ 0x06, 0x4e78 },
		{ 0x06, 0x009f },
		{ 0x06, 0x0ae0 },
		{ 0x06, 0x834f },
		{ 0x06, 0xa010 },
		{ 0x06, 0xa5ee },
		{ 0x06, 0x834e },
		{ 0x06, 0x01e0 },
		{ 0x06, 0x834e },
		{ 0x06, 0x7805 },
		{ 0x06, 0x9e9a },
		{ 0x06, 0xe083 },
		{ 0x06, 0x4e78 },
		{ 0x06, 0x049e },
		{ 0x06, 0x10e0 },
		{ 0x06, 0x834e },
		{ 0x06, 0x7803 },
		{ 0x06, 0x9e0f },
		{ 0x06, 0xe083 },
		{ 0x06, 0x4e78 },
		{ 0x06, 0x019e },
		{ 0x06, 0x05ae },
		{ 0x06, 0x0caf },
		{ 0x06, 0x81f8 },
		{ 0x06, 0xaf81 },
		{ 0x06, 0xa3af },
		{ 0x06, 0x81dc },
		{ 0x06, 0xaf82 },
		{ 0x06, 0x13ee },
		{ 0x06, 0x8348 },
		{ 0x06, 0x00ee },
		{ 0x06, 0x8349 },
		{ 0x06, 0x00e0 },
		{ 0x06, 0x8351 },
		{ 0x06, 0x10e4 },
		{ 0x06, 0x8351 },
		{ 0x06, 0x5801 },
		{ 0x06, 0x9fea },
		{ 0x06, 0xd000 },
		{ 0x06, 0xd180 },
		{ 0x06, 0x1f66 },
		{ 0x06, 0xe2f8 },
		{ 0x06, 0xeae3 },
		{ 0x06, 0xf8eb },
		{ 0x06, 0x5af8 },
		{ 0x06, 0x1e20 },
		{ 0x06, 0xe6f8 },
		{ 0x06, 0xeae5 },
		{ 0x06, 0xf8eb },
		{ 0x06, 0xd302 },
		{ 0x06, 0xb3fe },
		{ 0x06, 0xe2f8 },
		{ 0x06, 0x7cef },
		{ 0x06, 0x325b },
		{ 0x06, 0x80e3 },
		{ 0x06, 0xf87d },
		{ 0x06, 0x9e03 },
		{ 0x06, 0x7dff },
		{ 0x06, 0xff0d },
		{ 0x06, 0x581c },
		{ 0x06, 0x551a },
		{ 0x06, 0x6511 },
		{ 0x06, 0xa190 },
		{ 0x06, 0xd3e2 },
		{ 0x06, 0x8348 },
		{ 0x06, 0xe383 },
		{ 0x06, 0x491b },
		{ 0x06, 0x56ab },
		{ 0x06, 0x08ef },
		{ 0x06, 0x56e6 },
		{ 0x06, 0x8348 },
		{ 0x06, 0xe783 },
		{ 0x06, 0x4910 },
		{ 0x06, 0xd180 },
		{ 0x06, 0x1f66 },
		{ 0x06, 0xa004 },
		{ 0x06, 0xb9e2 },
		{ 0x06, 0x8348 },
		{ 0x06, 0xe383 },
		{ 0x06, 0x49ef },
		{ 0x06, 0x65e2 },
		{ 0x06, 0x834a },
		{ 0x06, 0xe383 },
		{ 0x06, 0x4b1b },
		{ 0x06, 0x56aa },
		{ 0x06, 0x0eef },
		{ 0x06, 0x56e6 },
		{ 0x06, 0x834a },
		{ 0x06, 0xe783 },
		{ 0x06, 0x4be2 },
		{ 0x06, 0x834d },
		{ 0x06, 0xe683 },
		{ 0x06, 0x4ce0 },
		{ 0x06, 0x834d },
		{ 0x06, 0xa000 },
		{ 0x06, 0x0caf },
		{ 0x06, 0x81dc },
		{ 0x06, 0xe083 },
		{ 0x06, 0x4d10 },
		{ 0x06, 0xe483 },
		{ 0x06, 0x4dae },
		{ 0x06, 0x0480 },
		{ 0x06, 0xe483 },
		{ 0x06, 0x4de0 },
		{ 0x06, 0x834e },
		{ 0x06, 0x7803 },
		{ 0x06, 0x9e0b },
		{ 0x06, 0xe083 },
		{ 0x06, 0x4e78 },
		{ 0x06, 0x049e },
		{ 0x06, 0x04ee },
		{ 0x06, 0x834e },
		{ 0x06, 0x02e0 },
		{ 0x06, 0x8332 },
		{ 0x06, 0xe183 },
		{ 0x06, 0x3359 },
		{ 0x06, 0x0fe2 },
		{ 0x06, 0x834d },
		{ 0x06, 0x0c24 },
		{ 0x06, 0x5af0 },
		{ 0x06, 0x1e12 },
		{ 0x06, 0xe4f8 },
		{ 0x06, 0x8ce5 },
		{ 0x06, 0xf88d },
		{ 0x06, 0xe083 },
		{ 0x06, 0x30e1 },
		{ 0x06, 0x8331 },
		{ 0x06, 0x6801 },
		{ 0x06, 0xe4f8 },
		{ 0x06, 0x8ae5 },
		{ 0x06, 0xf88b },
		{ 0x06, 0xae37 },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4e03 },
		{ 0x06, 0xe083 },
		{ 0x06, 0x4ce1 },
		{ 0x06, 0x834d },
		{ 0x06, 0x1b01 },
		{ 0x06, 0x9e04 },
		{ 0x06, 0xaaa1 },
		{ 0x06, 0xaea8 },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4e04 },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4f00 },
		{ 0x06, 0xaeab },
		{ 0x06, 0xe083 },
		{ 0x06, 0x4f78 },
		{ 0x06, 0x039f },
		{ 0x06, 0x14ee },
		{ 0x06, 0x834e },
		{ 0x06, 0x05d2 },
		{ 0x06, 0x40d6 },
		{ 0x06, 0x5554 },
		{ 0x06, 0x0282 },
		{ 0x06, 0x17d2 },
		{ 0x06, 0xa0d6 },
		{ 0x06, 0xba00 },
		{ 0x06, 0x0282 },
		{ 0x06, 0x17fe },
		{ 0x06, 0xfdfc },
		{ 0x06, 0x05f8 },
		{ 0x06, 0xe0f8 },
		{ 0x06, 0x60e1 },
		{ 0x06, 0xf861 },
		{ 0x06, 0x6802 },
		{ 0x06, 0xe4f8 },
		{ 0x06, 0x60e5 },
		{ 0x06, 0xf861 },
		{ 0x06, 0xe0f8 },
		{ 0x06, 0x48e1 },
		{ 0x06, 0xf849 },
		{ 0x06, 0x580f },
		{ 0x06, 0x1e02 },
		{ 0x06, 0xe4f8 },
		{ 0x06, 0x48e5 },
		{ 0x06, 0xf849 },
		{ 0x06, 0xd000 },
		{ 0x06, 0x0282 },
		{ 0x06, 0x5bbf },
		{ 0x06, 0x8350 },
		{ 0x06, 0xef46 },
		{ 0x06, 0xdc19 },
		{ 0x06, 0xddd0 },
		{ 0x06, 0x0102 },
		{ 0x06, 0x825b },
		{ 0x06, 0x0282 },
		{ 0x06, 0x77e0 },
		{ 0x06, 0xf860 },
		{ 0x06, 0xe1f8 },
		{ 0x06, 0x6158 },
		{ 0x06, 0xfde4 },
		{ 0x06, 0xf860 },
		{ 0x06, 0xe5f8 },
		{ 0x06, 0x61fc },
		{ 0x06, 0x04f9 },
		{ 0x06, 0xfafb },
		{ 0x06, 0xc6bf },
		{ 0x06, 0xf840 },
		{ 0x06, 0xbe83 },
		{ 0x06, 0x50a0 },
		{ 0x06, 0x0101 },
		{ 0x06, 0x071b },
		{ 0x06, 0x89cf },
		{ 0x06, 0xd208 },
		{ 0x06, 0xebdb },
		{ 0x06, 0x19b2 },
		{ 0x06, 0xfbff },
		{ 0x06, 0xfefd },
		{ 0x06, 0x04f8 },
		{ 0x06, 0xe0f8 },
		{ 0x06, 0x48e1 },
		{ 0x06, 0xf849 },
		{ 0x06, 0x6808 },
		{ 0x06, 0xe4f8 },
		{ 0x06, 0x48e5 },
		{ 0x06, 0xf849 },
		{ 0x06, 0x58f7 },
		{ 0x06, 0xe4f8 },
		{ 0x06, 0x48e5 },
		{ 0x06, 0xf849 },
		{ 0x06, 0xfc04 },
		{ 0x06, 0x4d20 },
		{ 0x06, 0x0002 },
		{ 0x06, 0x4e22 },
		{ 0x06, 0x0002 },
		{ 0x06, 0x4ddf },
		{ 0x06, 0xff01 },
		{ 0x06, 0x4edd },
		{ 0x06, 0xff01 },
		{ 0x05, 0x83d4 },
		{ 0x06, 0x8000 },
		{ 0x05, 0x83d8 },
		{ 0x06, 0x8051 },
		{ 0x02, 0x6010 },
		{ 0x03, 0xdc00 },
		{ 0x05, 0xfff6 },
		{ 0x06, 0x00fc },
F
Francois Romieu 已提交
2083
		{ 0x1f, 0x0000 },
2084

F
Francois Romieu 已提交
2085
		{ 0x1f, 0x0000 },
2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098
		{ 0x0d, 0xf880 },
		{ 0x1f, 0x0000 }
	};

	rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));

	mdio_write(ioaddr, 0x1f, 0x0002);
	mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
	mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);

	rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));

	if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2099
		static const struct phy_reg phy_reg_init[] = {
2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113
			{ 0x1f, 0x0002 },
			{ 0x05, 0x669a },
			{ 0x1f, 0x0005 },
			{ 0x05, 0x8330 },
			{ 0x06, 0x669a },
			{ 0x1f, 0x0002 }
		};
		int val;

		rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));

		val = mdio_read(ioaddr, 0x0d);

		if ((val & 0x00ff) != 0x006c) {
2114
			static const u32 set[] = {
2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126
				0x0065, 0x0066, 0x0067, 0x0068,
				0x0069, 0x006a, 0x006b, 0x006c
			};
			int i;

			mdio_write(ioaddr, 0x1f, 0x0002);

			val &= 0xff00;
			for (i = 0; i < ARRAY_SIZE(set); i++)
				mdio_write(ioaddr, 0x0d, val | set[i]);
		}
	} else {
2127
		static const struct phy_reg phy_reg_init[] = {
2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150
			{ 0x1f, 0x0002 },
			{ 0x05, 0x6662 },
			{ 0x1f, 0x0005 },
			{ 0x05, 0x8330 },
			{ 0x06, 0x6662 }
		};

		rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
	}

	mdio_write(ioaddr, 0x1f, 0x0002);
	mdio_patch(ioaddr, 0x0d, 0x0300);
	mdio_patch(ioaddr, 0x0f, 0x0010);

	mdio_write(ioaddr, 0x1f, 0x0002);
	mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
	mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);

	rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
}

static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
{
2151
	static const struct phy_reg phy_reg_init_0[] = {
2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175
		{ 0x1f, 0x0001 },
		{ 0x06, 0x4064 },
		{ 0x07, 0x2863 },
		{ 0x08, 0x059c },
		{ 0x09, 0x26b4 },
		{ 0x0a, 0x6a19 },
		{ 0x0b, 0xdcc8 },
		{ 0x10, 0xf06d },
		{ 0x14, 0x7f68 },
		{ 0x18, 0x7fd9 },
		{ 0x1c, 0xf0ff },
		{ 0x1d, 0x3d9c },
		{ 0x1f, 0x0003 },
		{ 0x12, 0xf49f },
		{ 0x13, 0x070b },
		{ 0x1a, 0x05ad },
		{ 0x14, 0x94c0 },

		{ 0x1f, 0x0002 },
		{ 0x06, 0x5561 },
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8332 },
		{ 0x06, 0x5561 }
	};
2176
	static const struct phy_reg phy_reg_init_1[] = {
2177 2178
		{ 0x1f, 0x0005 },
		{ 0x05, 0xffc2 },
F
Francois Romieu 已提交
2179
		{ 0x1f, 0x0005 },
2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486
		{ 0x05, 0x8000 },
		{ 0x06, 0xf8f9 },
		{ 0x06, 0xfaee },
		{ 0x06, 0xf8ea },
		{ 0x06, 0x00ee },
		{ 0x06, 0xf8eb },
		{ 0x06, 0x00e2 },
		{ 0x06, 0xf87c },
		{ 0x06, 0xe3f8 },
		{ 0x06, 0x7da5 },
		{ 0x06, 0x1111 },
		{ 0x06, 0x12d2 },
		{ 0x06, 0x40d6 },
		{ 0x06, 0x4444 },
		{ 0x06, 0x0281 },
		{ 0x06, 0xc6d2 },
		{ 0x06, 0xa0d6 },
		{ 0x06, 0xaaaa },
		{ 0x06, 0x0281 },
		{ 0x06, 0xc6ae },
		{ 0x06, 0x0fa5 },
		{ 0x06, 0x4444 },
		{ 0x06, 0x02ae },
		{ 0x06, 0x4da5 },
		{ 0x06, 0xaaaa },
		{ 0x06, 0x02ae },
		{ 0x06, 0x47af },
		{ 0x06, 0x81c2 },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4e00 },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4d0f },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4c0f },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4f00 },
		{ 0x06, 0xee83 },
		{ 0x06, 0x5100 },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4aff },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4bff },
		{ 0x06, 0xe083 },
		{ 0x06, 0x30e1 },
		{ 0x06, 0x8331 },
		{ 0x06, 0x58fe },
		{ 0x06, 0xe4f8 },
		{ 0x06, 0x8ae5 },
		{ 0x06, 0xf88b },
		{ 0x06, 0xe083 },
		{ 0x06, 0x32e1 },
		{ 0x06, 0x8333 },
		{ 0x06, 0x590f },
		{ 0x06, 0xe283 },
		{ 0x06, 0x4d0c },
		{ 0x06, 0x245a },
		{ 0x06, 0xf01e },
		{ 0x06, 0x12e4 },
		{ 0x06, 0xf88c },
		{ 0x06, 0xe5f8 },
		{ 0x06, 0x8daf },
		{ 0x06, 0x81c2 },
		{ 0x06, 0xe083 },
		{ 0x06, 0x4f10 },
		{ 0x06, 0xe483 },
		{ 0x06, 0x4fe0 },
		{ 0x06, 0x834e },
		{ 0x06, 0x7800 },
		{ 0x06, 0x9f0a },
		{ 0x06, 0xe083 },
		{ 0x06, 0x4fa0 },
		{ 0x06, 0x10a5 },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4e01 },
		{ 0x06, 0xe083 },
		{ 0x06, 0x4e78 },
		{ 0x06, 0x059e },
		{ 0x06, 0x9ae0 },
		{ 0x06, 0x834e },
		{ 0x06, 0x7804 },
		{ 0x06, 0x9e10 },
		{ 0x06, 0xe083 },
		{ 0x06, 0x4e78 },
		{ 0x06, 0x039e },
		{ 0x06, 0x0fe0 },
		{ 0x06, 0x834e },
		{ 0x06, 0x7801 },
		{ 0x06, 0x9e05 },
		{ 0x06, 0xae0c },
		{ 0x06, 0xaf81 },
		{ 0x06, 0xa7af },
		{ 0x06, 0x8152 },
		{ 0x06, 0xaf81 },
		{ 0x06, 0x8baf },
		{ 0x06, 0x81c2 },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4800 },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4900 },
		{ 0x06, 0xe083 },
		{ 0x06, 0x5110 },
		{ 0x06, 0xe483 },
		{ 0x06, 0x5158 },
		{ 0x06, 0x019f },
		{ 0x06, 0xead0 },
		{ 0x06, 0x00d1 },
		{ 0x06, 0x801f },
		{ 0x06, 0x66e2 },
		{ 0x06, 0xf8ea },
		{ 0x06, 0xe3f8 },
		{ 0x06, 0xeb5a },
		{ 0x06, 0xf81e },
		{ 0x06, 0x20e6 },
		{ 0x06, 0xf8ea },
		{ 0x06, 0xe5f8 },
		{ 0x06, 0xebd3 },
		{ 0x06, 0x02b3 },
		{ 0x06, 0xfee2 },
		{ 0x06, 0xf87c },
		{ 0x06, 0xef32 },
		{ 0x06, 0x5b80 },
		{ 0x06, 0xe3f8 },
		{ 0x06, 0x7d9e },
		{ 0x06, 0x037d },
		{ 0x06, 0xffff },
		{ 0x06, 0x0d58 },
		{ 0x06, 0x1c55 },
		{ 0x06, 0x1a65 },
		{ 0x06, 0x11a1 },
		{ 0x06, 0x90d3 },
		{ 0x06, 0xe283 },
		{ 0x06, 0x48e3 },
		{ 0x06, 0x8349 },
		{ 0x06, 0x1b56 },
		{ 0x06, 0xab08 },
		{ 0x06, 0xef56 },
		{ 0x06, 0xe683 },
		{ 0x06, 0x48e7 },
		{ 0x06, 0x8349 },
		{ 0x06, 0x10d1 },
		{ 0x06, 0x801f },
		{ 0x06, 0x66a0 },
		{ 0x06, 0x04b9 },
		{ 0x06, 0xe283 },
		{ 0x06, 0x48e3 },
		{ 0x06, 0x8349 },
		{ 0x06, 0xef65 },
		{ 0x06, 0xe283 },
		{ 0x06, 0x4ae3 },
		{ 0x06, 0x834b },
		{ 0x06, 0x1b56 },
		{ 0x06, 0xaa0e },
		{ 0x06, 0xef56 },
		{ 0x06, 0xe683 },
		{ 0x06, 0x4ae7 },
		{ 0x06, 0x834b },
		{ 0x06, 0xe283 },
		{ 0x06, 0x4de6 },
		{ 0x06, 0x834c },
		{ 0x06, 0xe083 },
		{ 0x06, 0x4da0 },
		{ 0x06, 0x000c },
		{ 0x06, 0xaf81 },
		{ 0x06, 0x8be0 },
		{ 0x06, 0x834d },
		{ 0x06, 0x10e4 },
		{ 0x06, 0x834d },
		{ 0x06, 0xae04 },
		{ 0x06, 0x80e4 },
		{ 0x06, 0x834d },
		{ 0x06, 0xe083 },
		{ 0x06, 0x4e78 },
		{ 0x06, 0x039e },
		{ 0x06, 0x0be0 },
		{ 0x06, 0x834e },
		{ 0x06, 0x7804 },
		{ 0x06, 0x9e04 },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4e02 },
		{ 0x06, 0xe083 },
		{ 0x06, 0x32e1 },
		{ 0x06, 0x8333 },
		{ 0x06, 0x590f },
		{ 0x06, 0xe283 },
		{ 0x06, 0x4d0c },
		{ 0x06, 0x245a },
		{ 0x06, 0xf01e },
		{ 0x06, 0x12e4 },
		{ 0x06, 0xf88c },
		{ 0x06, 0xe5f8 },
		{ 0x06, 0x8de0 },
		{ 0x06, 0x8330 },
		{ 0x06, 0xe183 },
		{ 0x06, 0x3168 },
		{ 0x06, 0x01e4 },
		{ 0x06, 0xf88a },
		{ 0x06, 0xe5f8 },
		{ 0x06, 0x8bae },
		{ 0x06, 0x37ee },
		{ 0x06, 0x834e },
		{ 0x06, 0x03e0 },
		{ 0x06, 0x834c },
		{ 0x06, 0xe183 },
		{ 0x06, 0x4d1b },
		{ 0x06, 0x019e },
		{ 0x06, 0x04aa },
		{ 0x06, 0xa1ae },
		{ 0x06, 0xa8ee },
		{ 0x06, 0x834e },
		{ 0x06, 0x04ee },
		{ 0x06, 0x834f },
		{ 0x06, 0x00ae },
		{ 0x06, 0xabe0 },
		{ 0x06, 0x834f },
		{ 0x06, 0x7803 },
		{ 0x06, 0x9f14 },
		{ 0x06, 0xee83 },
		{ 0x06, 0x4e05 },
		{ 0x06, 0xd240 },
		{ 0x06, 0xd655 },
		{ 0x06, 0x5402 },
		{ 0x06, 0x81c6 },
		{ 0x06, 0xd2a0 },
		{ 0x06, 0xd6ba },
		{ 0x06, 0x0002 },
		{ 0x06, 0x81c6 },
		{ 0x06, 0xfefd },
		{ 0x06, 0xfc05 },
		{ 0x06, 0xf8e0 },
		{ 0x06, 0xf860 },
		{ 0x06, 0xe1f8 },
		{ 0x06, 0x6168 },
		{ 0x06, 0x02e4 },
		{ 0x06, 0xf860 },
		{ 0x06, 0xe5f8 },
		{ 0x06, 0x61e0 },
		{ 0x06, 0xf848 },
		{ 0x06, 0xe1f8 },
		{ 0x06, 0x4958 },
		{ 0x06, 0x0f1e },
		{ 0x06, 0x02e4 },
		{ 0x06, 0xf848 },
		{ 0x06, 0xe5f8 },
		{ 0x06, 0x49d0 },
		{ 0x06, 0x0002 },
		{ 0x06, 0x820a },
		{ 0x06, 0xbf83 },
		{ 0x06, 0x50ef },
		{ 0x06, 0x46dc },
		{ 0x06, 0x19dd },
		{ 0x06, 0xd001 },
		{ 0x06, 0x0282 },
		{ 0x06, 0x0a02 },
		{ 0x06, 0x8226 },
		{ 0x06, 0xe0f8 },
		{ 0x06, 0x60e1 },
		{ 0x06, 0xf861 },
		{ 0x06, 0x58fd },
		{ 0x06, 0xe4f8 },
		{ 0x06, 0x60e5 },
		{ 0x06, 0xf861 },
		{ 0x06, 0xfc04 },
		{ 0x06, 0xf9fa },
		{ 0x06, 0xfbc6 },
		{ 0x06, 0xbff8 },
		{ 0x06, 0x40be },
		{ 0x06, 0x8350 },
		{ 0x06, 0xa001 },
		{ 0x06, 0x0107 },
		{ 0x06, 0x1b89 },
		{ 0x06, 0xcfd2 },
		{ 0x06, 0x08eb },
		{ 0x06, 0xdb19 },
		{ 0x06, 0xb2fb },
		{ 0x06, 0xfffe },
		{ 0x06, 0xfd04 },
		{ 0x06, 0xf8e0 },
		{ 0x06, 0xf848 },
		{ 0x06, 0xe1f8 },
		{ 0x06, 0x4968 },
		{ 0x06, 0x08e4 },
		{ 0x06, 0xf848 },
		{ 0x06, 0xe5f8 },
		{ 0x06, 0x4958 },
		{ 0x06, 0xf7e4 },
		{ 0x06, 0xf848 },
		{ 0x06, 0xe5f8 },
		{ 0x06, 0x49fc },
		{ 0x06, 0x044d },
		{ 0x06, 0x2000 },
		{ 0x06, 0x024e },
		{ 0x06, 0x2200 },
		{ 0x06, 0x024d },
		{ 0x06, 0xdfff },
		{ 0x06, 0x014e },
		{ 0x06, 0xddff },
		{ 0x06, 0x0100 },
		{ 0x05, 0x83d8 },
		{ 0x06, 0x8000 },
		{ 0x03, 0xdc00 },
		{ 0x05, 0xfff6 },
		{ 0x06, 0x00fc },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0000 },
		{ 0x0d, 0xf880 },
		{ 0x1f, 0x0000 }
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	};

	rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));

2491
	if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2492
		static const struct phy_reg phy_reg_init[] = {
2493 2494
			{ 0x1f, 0x0002 },
			{ 0x05, 0x669a },
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			{ 0x1f, 0x0005 },
2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519
			{ 0x05, 0x8330 },
			{ 0x06, 0x669a },

			{ 0x1f, 0x0002 }
		};
		int val;

		rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));

		val = mdio_read(ioaddr, 0x0d);
		if ((val & 0x00ff) != 0x006c) {
			u32 set[] = {
				0x0065, 0x0066, 0x0067, 0x0068,
				0x0069, 0x006a, 0x006b, 0x006c
			};
			int i;

			mdio_write(ioaddr, 0x1f, 0x0002);

			val &= 0xff00;
			for (i = 0; i < ARRAY_SIZE(set); i++)
				mdio_write(ioaddr, 0x0d, val | set[i]);
		}
	} else {
2520
		static const struct phy_reg phy_reg_init[] = {
2521 2522
			{ 0x1f, 0x0002 },
			{ 0x05, 0x2642 },
F
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2523
			{ 0x1f, 0x0005 },
2524 2525
			{ 0x05, 0x8330 },
			{ 0x06, 0x2642 }
F
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2526 2527
		};

2528
		rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
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2529 2530
	}

2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545
	mdio_write(ioaddr, 0x1f, 0x0002);
	mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
	mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);

	mdio_write(ioaddr, 0x1f, 0x0001);
	mdio_write(ioaddr, 0x17, 0x0cc0);

	mdio_write(ioaddr, 0x1f, 0x0002);
	mdio_patch(ioaddr, 0x0f, 0x0017);

	rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
}

static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
{
2546
	static const struct phy_reg phy_reg_init[] = {
2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602
		{ 0x1f, 0x0002 },
		{ 0x10, 0x0008 },
		{ 0x0d, 0x006c },

		{ 0x1f, 0x0000 },
		{ 0x0d, 0xf880 },

		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },

		{ 0x1f, 0x0001 },
		{ 0x0b, 0xa4d8 },
		{ 0x09, 0x281c },
		{ 0x07, 0x2883 },
		{ 0x0a, 0x6b35 },
		{ 0x1d, 0x3da4 },
		{ 0x1c, 0xeffd },
		{ 0x14, 0x7f52 },
		{ 0x18, 0x7fc6 },
		{ 0x08, 0x0601 },
		{ 0x06, 0x4063 },
		{ 0x10, 0xf074 },
		{ 0x1f, 0x0003 },
		{ 0x13, 0x0789 },
		{ 0x12, 0xf4bd },
		{ 0x1a, 0x04fd },
		{ 0x14, 0x84b0 },
		{ 0x1f, 0x0000 },
		{ 0x00, 0x9200 },

		{ 0x1f, 0x0005 },
		{ 0x01, 0x0340 },
		{ 0x1f, 0x0001 },
		{ 0x04, 0x4000 },
		{ 0x03, 0x1d21 },
		{ 0x02, 0x0c32 },
		{ 0x01, 0x0200 },
		{ 0x00, 0x5554 },
		{ 0x04, 0x4800 },
		{ 0x04, 0x4000 },
		{ 0x04, 0xf000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x101a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0xf000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0007 },
		{ 0x1e, 0x0023 },
		{ 0x16, 0x0000 },
		{ 0x1f, 0x0000 }
	};

	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
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}

2605 2606
static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
{
2607
	static const struct phy_reg phy_reg_init[] = {
2608 2609 2610 2611 2612 2613 2614 2615 2616
		{ 0x1f, 0x0003 },
		{ 0x08, 0x441d },
		{ 0x01, 0x9100 },
		{ 0x1f, 0x0000 }
	};

	mdio_write(ioaddr, 0x1f, 0x0000);
	mdio_patch(ioaddr, 0x11, 1 << 12);
	mdio_patch(ioaddr, 0x19, 1 << 13);
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	mdio_patch(ioaddr, 0x10, 1 << 15);
2618 2619 2620 2621

	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
}

2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638
static void rtl_hw_phy_config(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;

	rtl8169_print_mac_version(tp);

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_01:
		break;
	case RTL_GIGA_MAC_VER_02:
	case RTL_GIGA_MAC_VER_03:
		rtl8169s_hw_phy_config(ioaddr);
		break;
	case RTL_GIGA_MAC_VER_04:
		rtl8169sb_hw_phy_config(ioaddr);
		break;
2639 2640 2641
	case RTL_GIGA_MAC_VER_05:
		rtl8169scd_hw_phy_config(tp, ioaddr);
		break;
2642 2643 2644
	case RTL_GIGA_MAC_VER_06:
		rtl8169sce_hw_phy_config(ioaddr);
		break;
2645 2646 2647 2648 2649
	case RTL_GIGA_MAC_VER_07:
	case RTL_GIGA_MAC_VER_08:
	case RTL_GIGA_MAC_VER_09:
		rtl8102e_hw_phy_config(ioaddr);
		break;
2650 2651 2652 2653 2654 2655 2656 2657 2658
	case RTL_GIGA_MAC_VER_11:
		rtl8168bb_hw_phy_config(ioaddr);
		break;
	case RTL_GIGA_MAC_VER_12:
		rtl8168bef_hw_phy_config(ioaddr);
		break;
	case RTL_GIGA_MAC_VER_17:
		rtl8168bef_hw_phy_config(ioaddr);
		break;
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	case RTL_GIGA_MAC_VER_18:
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2660
		rtl8168cp_1_hw_phy_config(ioaddr);
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2661 2662
		break;
	case RTL_GIGA_MAC_VER_19:
2663
		rtl8168c_1_hw_phy_config(ioaddr);
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		break;
2665
	case RTL_GIGA_MAC_VER_20:
2666
		rtl8168c_2_hw_phy_config(ioaddr);
2667
		break;
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	case RTL_GIGA_MAC_VER_21:
		rtl8168c_3_hw_phy_config(ioaddr);
		break;
2671 2672 2673
	case RTL_GIGA_MAC_VER_22:
		rtl8168c_4_hw_phy_config(ioaddr);
		break;
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	case RTL_GIGA_MAC_VER_23:
2675
	case RTL_GIGA_MAC_VER_24:
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		rtl8168cp_2_hw_phy_config(ioaddr);
		break;
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	case RTL_GIGA_MAC_VER_25:
2679 2680 2681 2682 2683 2684 2685
		rtl8168d_1_hw_phy_config(ioaddr);
		break;
	case RTL_GIGA_MAC_VER_26:
		rtl8168d_2_hw_phy_config(ioaddr);
		break;
	case RTL_GIGA_MAC_VER_27:
		rtl8168d_3_hw_phy_config(ioaddr);
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		break;
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2688 2689 2690 2691 2692
	default:
		break;
	}
}

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static void rtl8169_phy_timer(unsigned long __opaque)
{
	struct net_device *dev = (struct net_device *)__opaque;
	struct rtl8169_private *tp = netdev_priv(dev);
	struct timer_list *timer = &tp->timer;
	void __iomem *ioaddr = tp->mmio_addr;
	unsigned long timeout = RTL8169_PHY_TIMEOUT;

2701
	assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
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2702

2703
	if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
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2704 2705 2706 2707 2708
		return;

	spin_lock_irq(&tp->lock);

	if (tp->phy_reset_pending(ioaddr)) {
2709
		/*
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		 * A busy loop could burn quite a few cycles on nowadays CPU.
		 * Let's delay the execution of the timer for a few ticks.
		 */
		timeout = HZ/10;
		goto out_mod_timer;
	}

	if (tp->link_ok(ioaddr))
		goto out_unlock;

2720
	netif_warn(tp, link, dev, "PHY reset until link up\n");
L
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2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734

	tp->phy_reset_enable(ioaddr);

out_mod_timer:
	mod_timer(timer, jiffies + timeout);
out_unlock:
	spin_unlock_irq(&tp->lock);
}

static inline void rtl8169_delete_timer(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct timer_list *timer = &tp->timer;

F
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2735
	if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
L
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2736 2737 2738 2739 2740 2741 2742 2743 2744 2745
		return;

	del_timer_sync(timer);
}

static inline void rtl8169_request_timer(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct timer_list *timer = &tp->timer;

F
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2746
	if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
L
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2747 2748
		return;

2749
	mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
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2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763
}

#ifdef CONFIG_NET_POLL_CONTROLLER
/*
 * Polling 'interrupt' - used by things like netconsole to send skbs
 * without having to re-enable interrupts. It's not called while
 * the interrupt routine is executing.
 */
static void rtl8169_netpoll(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct pci_dev *pdev = tp->pci_dev;

	disable_irq(pdev->irq);
2764
	rtl8169_interrupt(pdev->irq, dev);
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	enable_irq(pdev->irq);
}
#endif

static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
				  void __iomem *ioaddr)
{
	iounmap(ioaddr);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	free_netdev(dev);
}

2778 2779 2780 2781
static void rtl8169_phy_reset(struct net_device *dev,
			      struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
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Francois Romieu 已提交
2782
	unsigned int i;
2783 2784 2785 2786 2787 2788 2789

	tp->phy_reset_enable(ioaddr);
	for (i = 0; i < 100; i++) {
		if (!tp->phy_reset_pending(ioaddr))
			return;
		msleep(1);
	}
2790
	netif_err(tp, link, dev, "PHY reset failed\n");
2791 2792
}

2793 2794 2795 2796
static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

2797
	rtl_hw_phy_config(dev);
2798

2799 2800 2801 2802
	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
		RTL_W8(0x82, 0x01);
	}
2803

2804 2805 2806 2807
	pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);

	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2808

2809
	if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2810 2811 2812 2813 2814 2815
		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
		RTL_W8(0x82, 0x01);
		dprintk("Set PHY Reg 0x0bh = 0x00h\n");
		mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
	}

2816 2817
	rtl8169_phy_reset(dev, tp);

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	/*
	 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
	 * only 8101. Don't panic.
	 */
	rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2823

2824 2825
	if (RTL_R8(PHYstatus) & TBI_Enable)
		netif_info(tp, link, dev, "TBI auto-negotiating\n");
2826 2827
}

2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861
static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
{
	void __iomem *ioaddr = tp->mmio_addr;
	u32 high;
	u32 low;

	low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
	high = addr[4] | (addr[5] << 8);

	spin_lock_irq(&tp->lock);

	RTL_W8(Cfg9346, Cfg9346_Unlock);
	RTL_W32(MAC0, low);
	RTL_W32(MAC4, high);
	RTL_W8(Cfg9346, Cfg9346_Lock);

	spin_unlock_irq(&tp->lock);
}

static int rtl_set_mac_address(struct net_device *dev, void *p)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct sockaddr *addr = p;

	if (!is_valid_ether_addr(addr->sa_data))
		return -EADDRNOTAVAIL;

	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);

	rtl_rar_set(tp, dev->dev_addr);

	return 0;
}

2862 2863 2864 2865 2866
static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct mii_ioctl_data *data = if_mii(ifr);

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2867 2868
	return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
}
2869

F
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2870 2871
static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
{
2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887
	switch (cmd) {
	case SIOCGMIIPHY:
		data->phy_id = 32; /* Internal PHY */
		return 0;

	case SIOCGMIIREG:
		data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
		return 0;

	case SIOCSMIIREG:
		mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
		return 0;
	}
	return -EOPNOTSUPP;
}

F
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2888 2889 2890 2891 2892
static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
{
	return -EOPNOTSUPP;
}

2893 2894 2895 2896 2897 2898
static const struct rtl_cfg_info {
	void (*hw_start)(struct net_device *);
	unsigned int region;
	unsigned int align;
	u16 intr_event;
	u16 napi_event;
2899
	unsigned features;
2900
	u8 default_ver;
2901 2902 2903 2904
} rtl_cfg_infos [] = {
	[RTL_CFG_0] = {
		.hw_start	= rtl_hw_start_8169,
		.region		= 1,
2905
		.align		= 0,
2906 2907
		.intr_event	= SYSErr | LinkChg | RxOverflow |
				  RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
F
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		.napi_event	= RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2909 2910
		.features	= RTL_FEATURE_GMII,
		.default_ver	= RTL_GIGA_MAC_VER_01,
2911 2912 2913 2914 2915 2916 2917
	},
	[RTL_CFG_1] = {
		.hw_start	= rtl_hw_start_8168,
		.region		= 2,
		.align		= 8,
		.intr_event	= SYSErr | LinkChg | RxOverflow |
				  TxErr | TxOK | RxOK | RxErr,
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		.napi_event	= TxErr | TxOK | RxOK | RxOverflow,
2919 2920
		.features	= RTL_FEATURE_GMII | RTL_FEATURE_MSI,
		.default_ver	= RTL_GIGA_MAC_VER_11,
2921 2922 2923 2924 2925 2926 2927
	},
	[RTL_CFG_2] = {
		.hw_start	= rtl_hw_start_8101,
		.region		= 2,
		.align		= 8,
		.intr_event	= SYSErr | LinkChg | RxOverflow | PCSTimeout |
				  RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
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2928
		.napi_event	= RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2929 2930
		.features	= RTL_FEATURE_MSI,
		.default_ver	= RTL_GIGA_MAC_VER_13,
2931 2932 2933
	}
};

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2934 2935 2936 2937 2938 2939 2940 2941
/* Cfg9346_Unlock assumed. */
static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
			    const struct rtl_cfg_info *cfg)
{
	unsigned msi = 0;
	u8 cfg2;

	cfg2 = RTL_R8(Config2) & ~MSIEnable;
2942
	if (cfg->features & RTL_FEATURE_MSI) {
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2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961
		if (pci_enable_msi(pdev)) {
			dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
		} else {
			cfg2 |= MSIEnable;
			msi = RTL_FEATURE_MSI;
		}
	}
	RTL_W8(Config2, cfg2);
	return msi;
}

static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
{
	if (tp->features & RTL_FEATURE_MSI) {
		pci_disable_msi(pdev);
		tp->features &= ~RTL_FEATURE_MSI;
	}
}

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static const struct net_device_ops rtl8169_netdev_ops = {
	.ndo_open		= rtl8169_open,
	.ndo_stop		= rtl8169_close,
	.ndo_get_stats		= rtl8169_get_stats,
2966
	.ndo_start_xmit		= rtl8169_start_xmit,
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2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981
	.ndo_tx_timeout		= rtl8169_tx_timeout,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_change_mtu		= rtl8169_change_mtu,
	.ndo_set_mac_address	= rtl_set_mac_address,
	.ndo_do_ioctl		= rtl8169_ioctl,
	.ndo_set_multicast_list	= rtl_set_rx_mode,
#ifdef CONFIG_R8169_VLAN
	.ndo_vlan_rx_register	= rtl8169_vlan_rx_register,
#endif
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller	= rtl8169_netpoll,
#endif

};

L
Linus Torvalds 已提交
2982
static int __devinit
2983
rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
L
Linus Torvalds 已提交
2984
{
2985 2986
	const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
	const unsigned int region = cfg->region;
L
Linus Torvalds 已提交
2987
	struct rtl8169_private *tp;
2988
	struct mii_if_info *mii;
2989 2990
	struct net_device *dev;
	void __iomem *ioaddr;
F
Francois Romieu 已提交
2991 2992
	unsigned int i;
	int rc;
2993
	int this_use_dac = use_dac;
L
Linus Torvalds 已提交
2994

2995 2996 2997 2998
	if (netif_msg_drv(&debug)) {
		printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
		       MODULENAME, RTL8169_VERSION);
	}
L
Linus Torvalds 已提交
2999 3000

	dev = alloc_etherdev(sizeof (*tp));
3001
	if (!dev) {
3002
		if (netif_msg_drv(&debug))
3003
			dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3004 3005
		rc = -ENOMEM;
		goto out;
L
Linus Torvalds 已提交
3006 3007 3008
	}

	SET_NETDEV_DEV(dev, &pdev->dev);
F
Francois Romieu 已提交
3009
	dev->netdev_ops = &rtl8169_netdev_ops;
L
Linus Torvalds 已提交
3010
	tp = netdev_priv(dev);
D
David Howells 已提交
3011
	tp->dev = dev;
3012
	tp->pci_dev = pdev;
3013
	tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
L
Linus Torvalds 已提交
3014

3015 3016 3017 3018 3019 3020 3021 3022
	mii = &tp->mii;
	mii->dev = dev;
	mii->mdio_read = rtl_mdio_read;
	mii->mdio_write = rtl_mdio_write;
	mii->phy_id_mask = 0x1f;
	mii->reg_num_mask = 0x1f;
	mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);

L
Linus Torvalds 已提交
3023 3024
	/* enable device (incl. PCI PM wakeup and hotplug setup) */
	rc = pci_enable_device(pdev);
3025
	if (rc < 0) {
3026
		netif_err(tp, probe, dev, "enable failure\n");
3027
		goto err_out_free_dev_1;
L
Linus Torvalds 已提交
3028 3029 3030 3031
	}

	rc = pci_set_mwi(pdev);
	if (rc < 0)
3032
		goto err_out_disable_2;
L
Linus Torvalds 已提交
3033 3034

	/* make sure PCI base addr 1 is MMIO */
3035
	if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3036 3037 3038
		netif_err(tp, probe, dev,
			  "region #%d not an MMIO resource, aborting\n",
			  region);
L
Linus Torvalds 已提交
3039
		rc = -ENODEV;
3040
		goto err_out_mwi_3;
L
Linus Torvalds 已提交
3041
	}
3042

L
Linus Torvalds 已提交
3043
	/* check for weird/broken PCI region reporting */
3044
	if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3045 3046
		netif_err(tp, probe, dev,
			  "Invalid PCI region size(s), aborting\n");
L
Linus Torvalds 已提交
3047
		rc = -ENODEV;
3048
		goto err_out_mwi_3;
L
Linus Torvalds 已提交
3049 3050 3051
	}

	rc = pci_request_regions(pdev, MODULENAME);
3052
	if (rc < 0) {
3053
		netif_err(tp, probe, dev, "could not request regions\n");
3054
		goto err_out_mwi_3;
L
Linus Torvalds 已提交
3055 3056 3057 3058
	}

	tp->cp_cmd = PCIMulRW | RxChkSum;

3059 3060 3061 3062 3063 3064 3065
	tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
	if (!tp->pcie_cap)
		netif_info(tp, probe, dev, "no PCI Express capability\n");

	if (this_use_dac < 0)
		this_use_dac = tp->pcie_cap != 0;

L
Linus Torvalds 已提交
3066
	if ((sizeof(dma_addr_t) > 4) &&
3067 3068 3069
	    this_use_dac &&
	    !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
		netif_info(tp, probe, dev, "using 64-bit DMA\n");
L
Linus Torvalds 已提交
3070 3071 3072
		tp->cp_cmd |= PCIDAC;
		dev->features |= NETIF_F_HIGHDMA;
	} else {
3073
		rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
L
Linus Torvalds 已提交
3074
		if (rc < 0) {
3075
			netif_err(tp, probe, dev, "DMA configuration failed\n");
3076
			goto err_out_free_res_4;
L
Linus Torvalds 已提交
3077 3078 3079 3080
		}
	}

	/* ioremap MMIO region */
3081
	ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3082
	if (!ioaddr) {
3083
		netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
L
Linus Torvalds 已提交
3084
		rc = -EIO;
3085
		goto err_out_free_res_4;
L
Linus Torvalds 已提交
3086 3087
	}

3088
	RTL_W16(IntrMask, 0x0000);
L
Linus Torvalds 已提交
3089 3090 3091 3092 3093

	/* Soft reset the chip. */
	RTL_W8(ChipCmd, CmdReset);

	/* Check that the chip has finished the reset. */
F
Francois Romieu 已提交
3094
	for (i = 0; i < 100; i++) {
L
Linus Torvalds 已提交
3095 3096
		if ((RTL_R8(ChipCmd) & CmdReset) == 0)
			break;
F
Francois Romieu 已提交
3097
		msleep_interruptible(1);
L
Linus Torvalds 已提交
3098 3099
	}

3100 3101
	RTL_W16(IntrStatus, 0xffff);

3102 3103
	pci_set_master(pdev);

L
Linus Torvalds 已提交
3104 3105 3106
	/* Identify chip attached to board */
	rtl8169_get_mac_version(tp, ioaddr);

3107 3108
	/* Use appropriate default if unknown */
	if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3109 3110
		netif_notice(tp, probe, dev,
			     "unknown MAC, using family default\n");
3111 3112 3113
		tp->mac_version = cfg->default_ver;
	}

L
Linus Torvalds 已提交
3114 3115
	rtl8169_print_mac_version(tp);

3116
	for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
L
Linus Torvalds 已提交
3117 3118 3119
		if (tp->mac_version == rtl_chip_info[i].mac_version)
			break;
	}
3120
	if (i == ARRAY_SIZE(rtl_chip_info)) {
3121 3122 3123
		dev_err(&pdev->dev,
			"driver bug, MAC version not found in rtl_chip_info\n");
		goto err_out_msi_5;
L
Linus Torvalds 已提交
3124 3125 3126
	}
	tp->chipset = i;

3127 3128 3129
	RTL_W8(Cfg9346, Cfg9346_Unlock);
	RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
	RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
B
Bruno Prémont 已提交
3130 3131 3132 3133
	if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
		tp->features |= RTL_FEATURE_WOL;
	if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
		tp->features |= RTL_FEATURE_WOL;
F
Francois Romieu 已提交
3134
	tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3135 3136
	RTL_W8(Cfg9346, Cfg9346_Lock);

3137 3138
	if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
	    (RTL_R8(PHYstatus) & TBI_Enable)) {
L
Linus Torvalds 已提交
3139 3140 3141 3142 3143
		tp->set_speed = rtl8169_set_speed_tbi;
		tp->get_settings = rtl8169_gset_tbi;
		tp->phy_reset_enable = rtl8169_tbi_reset_enable;
		tp->phy_reset_pending = rtl8169_tbi_reset_pending;
		tp->link_ok = rtl8169_tbi_link_ok;
F
Francois Romieu 已提交
3144
		tp->do_ioctl = rtl_tbi_ioctl;
L
Linus Torvalds 已提交
3145

3146
		tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
L
Linus Torvalds 已提交
3147 3148 3149 3150 3151 3152
	} else {
		tp->set_speed = rtl8169_set_speed_xmii;
		tp->get_settings = rtl8169_gset_xmii;
		tp->phy_reset_enable = rtl8169_xmii_reset_enable;
		tp->phy_reset_pending = rtl8169_xmii_reset_pending;
		tp->link_ok = rtl8169_xmii_link_ok;
F
Francois Romieu 已提交
3153
		tp->do_ioctl = rtl_xmii_ioctl;
L
Linus Torvalds 已提交
3154 3155
	}

F
Francois Romieu 已提交
3156 3157
	spin_lock_init(&tp->lock);

3158 3159
	tp->mmio_addr = ioaddr;

3160
	/* Get MAC address */
L
Linus Torvalds 已提交
3161 3162
	for (i = 0; i < MAC_ADDR_LEN; i++)
		dev->dev_addr[i] = RTL_R8(MAC0 + i);
3163
	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
L
Linus Torvalds 已提交
3164 3165 3166 3167 3168 3169

	SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
	dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
	dev->irq = pdev->irq;
	dev->base_addr = (unsigned long) ioaddr;

3170
	netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
L
Linus Torvalds 已提交
3171 3172 3173 3174 3175 3176

#ifdef CONFIG_R8169_VLAN
	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
#endif

	tp->intr_mask = 0xffff;
3177 3178 3179 3180
	tp->align = cfg->align;
	tp->hw_start = cfg->hw_start;
	tp->intr_event = cfg->intr_event;
	tp->napi_event = cfg->napi_event;
L
Linus Torvalds 已提交
3181

3182 3183 3184 3185
	init_timer(&tp->timer);
	tp->timer.data = (unsigned long) dev;
	tp->timer.function = rtl8169_phy_timer;

L
Linus Torvalds 已提交
3186
	rc = register_netdev(dev);
3187
	if (rc < 0)
F
Francois Romieu 已提交
3188
		goto err_out_msi_5;
L
Linus Torvalds 已提交
3189 3190 3191

	pci_set_drvdata(pdev, dev);

3192 3193 3194 3195
	netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
		   rtl_chip_info[tp->chipset].name,
		   dev->base_addr, dev->dev_addr,
		   (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
L
Linus Torvalds 已提交
3196

3197
	rtl8169_init_phy(dev, tp);
3198 3199 3200 3201 3202 3203 3204 3205

	/*
	 * Pretend we are using VLANs; This bypasses a nasty bug where
	 * Interrupts stop flowing on high load on 8110SCd controllers.
	 */
	if (tp->mac_version == RTL_GIGA_MAC_VER_05)
		RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);

B
Bruno Prémont 已提交
3206
	device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
L
Linus Torvalds 已提交
3207

3208 3209 3210 3211 3212 3213
	if (pci_dev_run_wake(pdev)) {
		pm_runtime_set_active(&pdev->dev);
		pm_runtime_enable(&pdev->dev);
	}
	pm_runtime_idle(&pdev->dev);

3214 3215
out:
	return rc;
L
Linus Torvalds 已提交
3216

F
Francois Romieu 已提交
3217 3218
err_out_msi_5:
	rtl_disable_msi(pdev, tp);
3219 3220 3221 3222 3223 3224 3225 3226 3227 3228
	iounmap(ioaddr);
err_out_free_res_4:
	pci_release_regions(pdev);
err_out_mwi_3:
	pci_clear_mwi(pdev);
err_out_disable_2:
	pci_disable_device(pdev);
err_out_free_dev_1:
	free_netdev(dev);
	goto out;
L
Linus Torvalds 已提交
3229 3230
}

F
Francois Romieu 已提交
3231
static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
L
Linus Torvalds 已提交
3232 3233 3234 3235
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

3236 3237
	pm_runtime_get_sync(&pdev->dev);

3238 3239
	flush_scheduled_work();

L
Linus Torvalds 已提交
3240
	unregister_netdev(dev);
3241

3242 3243 3244 3245 3246 3247
	if (pci_dev_run_wake(pdev)) {
		pm_runtime_disable(&pdev->dev);
		pm_runtime_set_suspended(&pdev->dev);
	}
	pm_runtime_put_noidle(&pdev->dev);

3248 3249 3250
	/* restore original MAC address */
	rtl_rar_set(tp, dev->perm_addr);

F
Francois Romieu 已提交
3251
	rtl_disable_msi(pdev, tp);
L
Linus Torvalds 已提交
3252 3253 3254 3255 3256 3257 3258
	rtl8169_release_board(pdev, dev, tp->mmio_addr);
	pci_set_drvdata(pdev, NULL);
}

static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
				  struct net_device *dev)
{
3259
	unsigned int max_frame = dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
L
Linus Torvalds 已提交
3260

3261
	tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
L
Linus Torvalds 已提交
3262 3263 3264 3265 3266 3267
}

static int rtl8169_open(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct pci_dev *pdev = tp->pci_dev;
3268
	int retval = -ENOMEM;
L
Linus Torvalds 已提交
3269

3270
	pm_runtime_get_sync(&pdev->dev);
L
Linus Torvalds 已提交
3271

3272
	rtl8169_set_rxbufsize(tp, dev);
L
Linus Torvalds 已提交
3273 3274 3275 3276 3277 3278 3279 3280

	/*
	 * Rx and Tx desscriptors needs 256 bytes alignment.
	 * pci_alloc_consistent provides more.
	 */
	tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
					       &tp->TxPhyAddr);
	if (!tp->TxDescArray)
3281
		goto err_pm_runtime_put;
L
Linus Torvalds 已提交
3282 3283 3284 3285

	tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
					       &tp->RxPhyAddr);
	if (!tp->RxDescArray)
3286
		goto err_free_tx_0;
L
Linus Torvalds 已提交
3287 3288 3289

	retval = rtl8169_init_ring(dev);
	if (retval < 0)
3290
		goto err_free_rx_1;
L
Linus Torvalds 已提交
3291

D
David Howells 已提交
3292
	INIT_DELAYED_WORK(&tp->task, NULL);
L
Linus Torvalds 已提交
3293

3294 3295
	smp_mb();

F
Francois Romieu 已提交
3296 3297
	retval = request_irq(dev->irq, rtl8169_interrupt,
			     (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3298 3299 3300 3301
			     dev->name, dev);
	if (retval < 0)
		goto err_release_ring_2;

3302 3303
	napi_enable(&tp->napi);

3304
	rtl_hw_start(dev);
L
Linus Torvalds 已提交
3305 3306 3307

	rtl8169_request_timer(dev);

3308 3309 3310
	tp->saved_wolopts = 0;
	pm_runtime_put_noidle(&pdev->dev);

L
Linus Torvalds 已提交
3311 3312 3313 3314
	rtl8169_check_link_status(dev, tp, tp->mmio_addr);
out:
	return retval;

3315 3316 3317
err_release_ring_2:
	rtl8169_rx_clear(tp);
err_free_rx_1:
L
Linus Torvalds 已提交
3318 3319
	pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
			    tp->RxPhyAddr);
3320
	tp->RxDescArray = NULL;
3321
err_free_tx_0:
L
Linus Torvalds 已提交
3322 3323
	pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
			    tp->TxPhyAddr);
3324 3325 3326
	tp->TxDescArray = NULL;
err_pm_runtime_put:
	pm_runtime_put_noidle(&pdev->dev);
L
Linus Torvalds 已提交
3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341
	goto out;
}

static void rtl8169_hw_reset(void __iomem *ioaddr)
{
	/* Disable interrupts */
	rtl8169_irq_mask_and_ack(ioaddr);

	/* Reset the chipset */
	RTL_W8(ChipCmd, CmdReset);

	/* PCI commit */
	RTL_R8(ChipCmd);
}

3342
static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354
{
	void __iomem *ioaddr = tp->mmio_addr;
	u32 cfg = rtl8169_rx_config;

	cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
	RTL_W32(RxConfig, cfg);

	/* Set DMA burst size and Interframe Gap Time */
	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
		(InterFrameGap << TxInterFrameGapShift));
}

3355
static void rtl_hw_start(struct net_device *dev)
L
Linus Torvalds 已提交
3356 3357 3358
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
F
Francois Romieu 已提交
3359
	unsigned int i;
L
Linus Torvalds 已提交
3360 3361 3362 3363 3364

	/* Soft reset the chip. */
	RTL_W8(ChipCmd, CmdReset);

	/* Check that the chip has finished the reset. */
F
Francois Romieu 已提交
3365
	for (i = 0; i < 100; i++) {
L
Linus Torvalds 已提交
3366 3367
		if ((RTL_R8(ChipCmd) & CmdReset) == 0)
			break;
F
Francois Romieu 已提交
3368
		msleep_interruptible(1);
L
Linus Torvalds 已提交
3369 3370
	}

3371 3372 3373 3374 3375 3376
	tp->hw_start(dev);

	netif_start_queue(dev);
}


3377 3378 3379 3380 3381 3382 3383 3384 3385
static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
					 void __iomem *ioaddr)
{
	/*
	 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
	 * register to be written before TxDescAddrLow to work.
	 * Switching from MMIO to I/O access fixes the issue as well.
	 */
	RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3386
	RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3387
	RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3388
	RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399
}

static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
{
	u16 cmd;

	cmd = RTL_R16(CPlusCmd);
	RTL_W16(CPlusCmd, cmd);
	return cmd;
}

3400
static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3401 3402
{
	/* Low hurts. Let's disable the filtering. */
3403
	RTL_W16(RxMaxSize, rx_buf_sz + 1);
3404 3405
}

3406 3407
static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
{
3408
	static const struct {
3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421
		u32 mac_version;
		u32 clk;
		u32 val;
	} cfg2_info [] = {
		{ RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
		{ RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
		{ RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
		{ RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
	}, *p = cfg2_info;
	unsigned int i;
	u32 clk;

	clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3422
	for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3423 3424 3425 3426 3427 3428 3429
		if ((p->mac_version == mac_version) && (p->clk == clk)) {
			RTL_W32(0x7c, p->val);
			break;
		}
	}
}

3430 3431 3432 3433 3434 3435
static void rtl_hw_start_8169(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

3436 3437 3438 3439 3440
	if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
		RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
	}

L
Linus Torvalds 已提交
3441
	RTL_W8(Cfg9346, Cfg9346_Unlock);
3442 3443 3444 3445 3446 3447
	if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_04))
		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

L
Linus Torvalds 已提交
3448 3449
	RTL_W8(EarlyTxThres, EarlyTxThld);

3450
	rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
L
Linus Torvalds 已提交
3451

3452 3453 3454 3455 3456
	if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_04))
		rtl_set_rx_tx_config_registers(tp);
L
Linus Torvalds 已提交
3457

3458
	tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
L
Linus Torvalds 已提交
3459

3460 3461
	if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3462
		dprintk("Set MAC Reg C+CR Offset 0xE0. "
L
Linus Torvalds 已提交
3463
			"Bit-3 and bit-14 MUST be 1\n");
3464
		tp->cp_cmd |= (1 << 14);
L
Linus Torvalds 已提交
3465 3466
	}

3467 3468
	RTL_W16(CPlusCmd, tp->cp_cmd);

3469 3470
	rtl8169_set_magic_reg(ioaddr, tp->mac_version);

L
Linus Torvalds 已提交
3471 3472 3473 3474 3475 3476
	/*
	 * Undocumented corner. Supposedly:
	 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
	 */
	RTL_W16(IntrMitigate, 0x0000);

3477
	rtl_set_rx_tx_desc_registers(tp, ioaddr);
3478

3479 3480 3481 3482 3483 3484 3485 3486
	if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
	    (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
	    (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
	    (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
		rtl_set_rx_tx_config_registers(tp);
	}

L
Linus Torvalds 已提交
3487
	RTL_W8(Cfg9346, Cfg9346_Lock);
F
Francois Romieu 已提交
3488 3489 3490

	/* Initially a 10 us delay. Turned it into a PCI commit. - FR */
	RTL_R8(IntrMask);
L
Linus Torvalds 已提交
3491 3492 3493

	RTL_W32(RxMissed, 0);

3494
	rtl_set_rx_mode(dev);
L
Linus Torvalds 已提交
3495 3496 3497

	/* no early-rx interrupts */
	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3498 3499

	/* Enable all known interrupts by setting the interrupt mask. */
3500
	RTL_W16(IntrMask, tp->intr_event);
3501
}
L
Linus Torvalds 已提交
3502

3503
static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3504
{
3505 3506 3507 3508 3509 3510
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);
	int cap = tp->pcie_cap;

	if (cap) {
		u16 ctl;
3511

3512 3513 3514 3515
		pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
		ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
		pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
	}
3516 3517
}

3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531
static void rtl_csi_access_enable(void __iomem *ioaddr)
{
	u32 csi;

	csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
	rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
}

struct ephy_info {
	unsigned int offset;
	u16 mask;
	u16 bits;
};

3532
static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3533 3534 3535 3536 3537 3538 3539 3540 3541 3542
{
	u16 w;

	while (len-- > 0) {
		w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
		rtl_ephy_write(ioaddr, e->offset, w);
		e++;
	}
}

3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568
static void rtl_disable_clock_request(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);
	int cap = tp->pcie_cap;

	if (cap) {
		u16 ctl;

		pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
		ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
		pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
	}
}

#define R8168_CPCMD_QUIRK_MASK (\
	EnableBist | \
	Mac_dbgo_oe | \
	Force_half_dup | \
	Force_rxflow_en | \
	Force_txflow_en | \
	Cxpl_dbg_sel | \
	ASF | \
	PktCntrDisable | \
	Mac_dbgo_sel)

3569 3570
static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
{
3571 3572 3573 3574
	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);

3575 3576
	rtl_tx_performance_tweak(pdev,
		(0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3577 3578 3579 3580 3581
}

static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
{
	rtl_hw_start_8168bb(ioaddr, pdev);
3582 3583 3584 3585

	RTL_W8(EarlyTxThres, EarlyTxThld);

	RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3586 3587 3588 3589
}

static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
{
3590 3591 3592 3593
	RTL_W8(Config1, RTL_R8(Config1) | Speed_down);

	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

3594
	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3595 3596 3597 3598

	rtl_disable_clock_request(pdev);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3599 3600
}

F
Francois Romieu 已提交
3601
static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3602
{
3603
	static const struct ephy_info e_info_8168cp[] = {
3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614
		{ 0x01, 0,	0x0001 },
		{ 0x02, 0x0800,	0x1000 },
		{ 0x03, 0,	0x0042 },
		{ 0x06, 0x0080,	0x0000 },
		{ 0x07, 0,	0x2000 }
	};

	rtl_csi_access_enable(ioaddr);

	rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));

3615 3616 3617
	__rtl_hw_start_8168cp(ioaddr, pdev);
}

F
Francois Romieu 已提交
3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628
static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
{
	rtl_csi_access_enable(ioaddr);

	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}

3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644
static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
{
	rtl_csi_access_enable(ioaddr);

	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	/* Magic. */
	RTL_W8(DBG_REG, 0x20);

	RTL_W8(EarlyTxThres, EarlyTxThld);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}

3645 3646
static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
{
3647
	static const struct ephy_info e_info_8168c_1[] = {
3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658
		{ 0x02, 0x0800,	0x1000 },
		{ 0x03, 0,	0x0002 },
		{ 0x06, 0x0080,	0x0000 }
	};

	rtl_csi_access_enable(ioaddr);

	RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);

	rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));

3659 3660 3661 3662 3663
	__rtl_hw_start_8168cp(ioaddr, pdev);
}

static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
{
3664
	static const struct ephy_info e_info_8168c_2[] = {
3665 3666 3667 3668 3669 3670 3671 3672
		{ 0x01, 0,	0x0001 },
		{ 0x03, 0x0400,	0x0220 }
	};

	rtl_csi_access_enable(ioaddr);

	rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));

3673 3674 3675
	__rtl_hw_start_8168cp(ioaddr, pdev);
}

F
Francois Romieu 已提交
3676 3677 3678 3679 3680
static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
{
	rtl_hw_start_8168c_2(ioaddr, pdev);
}

3681 3682 3683 3684 3685 3686 3687
static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
{
	rtl_csi_access_enable(ioaddr);

	__rtl_hw_start_8168cp(ioaddr, pdev);
}

F
Francois Romieu 已提交
3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700
static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
{
	rtl_csi_access_enable(ioaddr);

	rtl_disable_clock_request(pdev);

	RTL_W8(EarlyTxThres, EarlyTxThld);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}

3701 3702
static void rtl_hw_start_8168(struct net_device *dev)
{
3703 3704
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
3705
	struct pci_dev *pdev = tp->pci_dev;
3706 3707 3708 3709 3710

	RTL_W8(Cfg9346, Cfg9346_Unlock);

	RTL_W8(EarlyTxThres, EarlyTxThld);

3711
	rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3712

3713
	tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3714 3715 3716

	RTL_W16(CPlusCmd, tp->cp_cmd);

3717
	RTL_W16(IntrMitigate, 0x5151);
3718

3719 3720 3721 3722 3723 3724 3725
	/* Work around for RxFIFO overflow. */
	if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
		tp->intr_event |= RxFIFOOver | PCSTimeout;
		tp->intr_event &= ~RxOverflow;
	}

	rtl_set_rx_tx_desc_registers(tp, ioaddr);
3726

3727 3728 3729 3730
	rtl_set_rx_mode(dev);

	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
		(InterFrameGap << TxInterFrameGapShift));
3731 3732 3733

	RTL_R8(IntrMask);

3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
		rtl_hw_start_8168bb(ioaddr, pdev);
	break;

	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
		rtl_hw_start_8168bef(ioaddr, pdev);
	break;

	case RTL_GIGA_MAC_VER_18:
F
Francois Romieu 已提交
3745
		rtl_hw_start_8168cp_1(ioaddr, pdev);
3746 3747 3748 3749 3750 3751 3752 3753 3754 3755
	break;

	case RTL_GIGA_MAC_VER_19:
		rtl_hw_start_8168c_1(ioaddr, pdev);
	break;

	case RTL_GIGA_MAC_VER_20:
		rtl_hw_start_8168c_2(ioaddr, pdev);
	break;

F
Francois Romieu 已提交
3756 3757 3758 3759
	case RTL_GIGA_MAC_VER_21:
		rtl_hw_start_8168c_3(ioaddr, pdev);
	break;

3760 3761 3762 3763
	case RTL_GIGA_MAC_VER_22:
		rtl_hw_start_8168c_4(ioaddr, pdev);
	break;

F
Francois Romieu 已提交
3764 3765 3766 3767
	case RTL_GIGA_MAC_VER_23:
		rtl_hw_start_8168cp_2(ioaddr, pdev);
	break;

3768 3769 3770 3771
	case RTL_GIGA_MAC_VER_24:
		rtl_hw_start_8168cp_3(ioaddr, pdev);
	break;

F
Francois Romieu 已提交
3772
	case RTL_GIGA_MAC_VER_25:
3773 3774
	case RTL_GIGA_MAC_VER_26:
	case RTL_GIGA_MAC_VER_27:
F
Francois Romieu 已提交
3775 3776 3777
		rtl_hw_start_8168d(ioaddr, pdev);
	break;

3778 3779 3780 3781 3782
	default:
		printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
			dev->name, tp->mac_version);
	break;
	}
3783

3784 3785
	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

3786 3787
	RTL_W8(Cfg9346, Cfg9346_Lock);

3788
	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3789

3790
	RTL_W16(IntrMask, tp->intr_event);
3791
}
L
Linus Torvalds 已提交
3792

3793 3794 3795 3796
#define R810X_CPCMD_QUIRK_MASK (\
	EnableBist | \
	Mac_dbgo_oe | \
	Force_half_dup | \
F
françois romieu 已提交
3797
	Force_rxflow_en | \
3798 3799 3800 3801 3802 3803 3804 3805 3806
	Force_txflow_en | \
	Cxpl_dbg_sel | \
	ASF | \
	PktCntrDisable | \
	PCIDAC | \
	PCIMulRW)

static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
{
3807
	static const struct ephy_info e_info_8102e_1[] = {
3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856
		{ 0x01,	0, 0x6e65 },
		{ 0x02,	0, 0x091f },
		{ 0x03,	0, 0xc2f9 },
		{ 0x06,	0, 0xafb5 },
		{ 0x07,	0, 0x0e00 },
		{ 0x19,	0, 0xec80 },
		{ 0x01,	0, 0x2e65 },
		{ 0x01,	0, 0x6e65 }
	};
	u8 cfg1;

	rtl_csi_access_enable(ioaddr);

	RTL_W8(DBG_REG, FIX_NAK_1);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W8(Config1,
	       LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	cfg1 = RTL_R8(Config1);
	if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
		RTL_W8(Config1, cfg1 & ~LEDS0);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);

	rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
}

static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
{
	rtl_csi_access_enable(ioaddr);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
}

static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
{
	rtl_hw_start_8102e_2(ioaddr, pdev);

	rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
}

3857 3858
static void rtl_hw_start_8101(struct net_device *dev)
{
3859 3860 3861 3862
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

F
Francois Romieu 已提交
3863 3864
	if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3865 3866 3867 3868 3869 3870
		int cap = tp->pcie_cap;

		if (cap) {
			pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
					      PCI_EXP_DEVCTL_NOSNOOP_EN);
		}
3871 3872
	}

3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_07:
		rtl_hw_start_8102e_1(ioaddr, pdev);
		break;

	case RTL_GIGA_MAC_VER_08:
		rtl_hw_start_8102e_3(ioaddr, pdev);
		break;

	case RTL_GIGA_MAC_VER_09:
		rtl_hw_start_8102e_2(ioaddr, pdev);
		break;
3885 3886 3887 3888 3889 3890
	}

	RTL_W8(Cfg9346, Cfg9346_Unlock);

	RTL_W8(EarlyTxThres, EarlyTxThld);

3891
	rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909

	tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;

	RTL_W16(CPlusCmd, tp->cp_cmd);

	RTL_W16(IntrMitigate, 0x0000);

	rtl_set_rx_tx_desc_registers(tp, ioaddr);

	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
	rtl_set_rx_tx_config_registers(tp);

	RTL_W8(Cfg9346, Cfg9346_Lock);

	RTL_R8(IntrMask);

	rtl_set_rx_mode(dev);

3910 3911
	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

3912
	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3913

3914
	RTL_W16(IntrMask, tp->intr_event);
L
Linus Torvalds 已提交
3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937
}

static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	int ret = 0;

	if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
		return -EINVAL;

	dev->mtu = new_mtu;

	if (!netif_running(dev))
		goto out;

	rtl8169_down(dev);

	rtl8169_set_rxbufsize(tp, dev);

	ret = rtl8169_init_ring(dev);
	if (ret < 0)
		goto out;

3938
	napi_enable(&tp->napi);
L
Linus Torvalds 已提交
3939

3940
	rtl_hw_start(dev);
L
Linus Torvalds 已提交
3941 3942 3943 3944 3945 3946 3947 3948 3949

	rtl8169_request_timer(dev);

out:
	return ret;
}

static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
{
A
Al Viro 已提交
3950
	desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
L
Linus Torvalds 已提交
3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980
	desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
}

static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
				struct sk_buff **sk_buff, struct RxDesc *desc)
{
	struct pci_dev *pdev = tp->pci_dev;

	pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
			 PCI_DMA_FROMDEVICE);
	dev_kfree_skb(*sk_buff);
	*sk_buff = NULL;
	rtl8169_make_unusable_by_asic(desc);
}

static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
{
	u32 eor = le32_to_cpu(desc->opts1) & RingEnd;

	desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
}

static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
				       u32 rx_buf_sz)
{
	desc->addr = cpu_to_le64(mapping);
	wmb();
	rtl8169_mark_to_asic(desc, rx_buf_sz);
}

S
Stephen Hemminger 已提交
3981 3982 3983 3984
static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
					    struct net_device *dev,
					    struct RxDesc *desc, int rx_buf_sz,
					    unsigned int align)
L
Linus Torvalds 已提交
3985 3986 3987
{
	struct sk_buff *skb;
	dma_addr_t mapping;
3988
	unsigned int pad;
L
Linus Torvalds 已提交
3989

3990 3991 3992
	pad = align ? align : NET_IP_ALIGN;

	skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
L
Linus Torvalds 已提交
3993 3994 3995
	if (!skb)
		goto err_out;

3996
	skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
L
Linus Torvalds 已提交
3997

3998
	mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
L
Linus Torvalds 已提交
3999 4000 4001 4002
				 PCI_DMA_FROMDEVICE);

	rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
out:
S
Stephen Hemminger 已提交
4003
	return skb;
L
Linus Torvalds 已提交
4004 4005 4006 4007 4008 4009 4010 4011

err_out:
	rtl8169_make_unusable_by_asic(desc);
	goto out;
}

static void rtl8169_rx_clear(struct rtl8169_private *tp)
{
F
Francois Romieu 已提交
4012
	unsigned int i;
L
Linus Torvalds 已提交
4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025

	for (i = 0; i < NUM_RX_DESC; i++) {
		if (tp->Rx_skbuff[i]) {
			rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
					    tp->RxDescArray + i);
		}
	}
}

static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
			   u32 start, u32 end)
{
	u32 cur;
4026

4027
	for (cur = start; end - cur != 0; cur++) {
S
Stephen Hemminger 已提交
4028 4029
		struct sk_buff *skb;
		unsigned int i = cur % NUM_RX_DESC;
L
Linus Torvalds 已提交
4030

4031 4032
		WARN_ON((s32)(end - cur) < 0);

L
Linus Torvalds 已提交
4033 4034
		if (tp->Rx_skbuff[i])
			continue;
4035

S
Stephen Hemminger 已提交
4036 4037 4038 4039
		skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
					   tp->RxDescArray + i,
					   tp->rx_buf_sz, tp->align);
		if (!skb)
L
Linus Torvalds 已提交
4040
			break;
S
Stephen Hemminger 已提交
4041 4042

		tp->Rx_skbuff[i] = skb;
L
Linus Torvalds 已提交
4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107
	}
	return cur - start;
}

static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
{
	desc->opts1 |= cpu_to_le32(RingEnd);
}

static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
{
	tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
}

static int rtl8169_init_ring(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl8169_init_ring_indexes(tp);

	memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
	memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));

	if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
		goto err_out;

	rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);

	return 0;

err_out:
	rtl8169_rx_clear(tp);
	return -ENOMEM;
}

static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
				 struct TxDesc *desc)
{
	unsigned int len = tx_skb->len;

	pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
	desc->opts1 = 0x00;
	desc->opts2 = 0x00;
	desc->addr = 0x00;
	tx_skb->len = 0;
}

static void rtl8169_tx_clear(struct rtl8169_private *tp)
{
	unsigned int i;

	for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
		unsigned int entry = i % NUM_TX_DESC;
		struct ring_info *tx_skb = tp->tx_skb + entry;
		unsigned int len = tx_skb->len;

		if (len) {
			struct sk_buff *skb = tx_skb->skb;

			rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
					     tp->TxDescArray + entry);
			if (skb) {
				dev_kfree_skb(skb);
				tx_skb->skb = NULL;
			}
4108
			tp->dev->stats.tx_dropped++;
L
Linus Torvalds 已提交
4109 4110 4111 4112 4113
		}
	}
	tp->cur_tx = tp->dirty_tx = 0;
}

D
David Howells 已提交
4114
static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
L
Linus Torvalds 已提交
4115 4116 4117
{
	struct rtl8169_private *tp = netdev_priv(dev);

D
David Howells 已提交
4118
	PREPARE_DELAYED_WORK(&tp->task, task);
L
Linus Torvalds 已提交
4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129
	schedule_delayed_work(&tp->task, 4);
}

static void rtl8169_wait_for_quiescence(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;

	synchronize_irq(dev->irq);

	/* Wait for any pending NAPI task to complete */
4130
	napi_disable(&tp->napi);
L
Linus Torvalds 已提交
4131 4132 4133

	rtl8169_irq_mask_and_ack(ioaddr);

4134 4135
	tp->intr_mask = 0xffff;
	RTL_W16(IntrMask, tp->intr_event);
4136
	napi_enable(&tp->napi);
L
Linus Torvalds 已提交
4137 4138
}

D
David Howells 已提交
4139
static void rtl8169_reinit_task(struct work_struct *work)
L
Linus Torvalds 已提交
4140
{
D
David Howells 已提交
4141 4142 4143
	struct rtl8169_private *tp =
		container_of(work, struct rtl8169_private, task.work);
	struct net_device *dev = tp->dev;
L
Linus Torvalds 已提交
4144 4145
	int ret;

4146 4147 4148 4149 4150 4151 4152
	rtnl_lock();

	if (!netif_running(dev))
		goto out_unlock;

	rtl8169_wait_for_quiescence(dev);
	rtl8169_close(dev);
L
Linus Torvalds 已提交
4153 4154 4155

	ret = rtl8169_open(dev);
	if (unlikely(ret < 0)) {
4156 4157 4158 4159
		if (net_ratelimit())
			netif_err(tp, drv, dev,
				  "reinit failure (status = %d). Rescheduling\n",
				  ret);
L
Linus Torvalds 已提交
4160 4161
		rtl8169_schedule_work(dev, rtl8169_reinit_task);
	}
4162 4163 4164

out_unlock:
	rtnl_unlock();
L
Linus Torvalds 已提交
4165 4166
}

D
David Howells 已提交
4167
static void rtl8169_reset_task(struct work_struct *work)
L
Linus Torvalds 已提交
4168
{
D
David Howells 已提交
4169 4170 4171
	struct rtl8169_private *tp =
		container_of(work, struct rtl8169_private, task.work);
	struct net_device *dev = tp->dev;
L
Linus Torvalds 已提交
4172

4173 4174
	rtnl_lock();

L
Linus Torvalds 已提交
4175
	if (!netif_running(dev))
4176
		goto out_unlock;
L
Linus Torvalds 已提交
4177 4178 4179

	rtl8169_wait_for_quiescence(dev);

4180
	rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
L
Linus Torvalds 已提交
4181 4182 4183 4184
	rtl8169_tx_clear(tp);

	if (tp->dirty_rx == tp->cur_rx) {
		rtl8169_init_ring_indexes(tp);
4185
		rtl_hw_start(dev);
L
Linus Torvalds 已提交
4186
		netif_wake_queue(dev);
4187
		rtl8169_check_link_status(dev, tp, tp->mmio_addr);
L
Linus Torvalds 已提交
4188
	} else {
4189 4190
		if (net_ratelimit())
			netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
L
Linus Torvalds 已提交
4191 4192
		rtl8169_schedule_work(dev, rtl8169_reset_task);
	}
4193 4194 4195

out_unlock:
	rtnl_unlock();
L
Linus Torvalds 已提交
4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212
}

static void rtl8169_tx_timeout(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl8169_hw_reset(tp->mmio_addr);

	/* Let's wait a bit while any (async) irq lands on */
	rtl8169_schedule_work(dev, rtl8169_reset_task);
}

static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
			      u32 opts1)
{
	struct skb_shared_info *info = skb_shinfo(skb);
	unsigned int cur_frag, entry;
4213
	struct TxDesc * uninitialized_var(txd);
L
Linus Torvalds 已提交
4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248

	entry = tp->cur_tx;
	for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
		skb_frag_t *frag = info->frags + cur_frag;
		dma_addr_t mapping;
		u32 status, len;
		void *addr;

		entry = (entry + 1) % NUM_TX_DESC;

		txd = tp->TxDescArray + entry;
		len = frag->size;
		addr = ((void *) page_address(frag->page)) + frag->page_offset;
		mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);

		/* anti gcc 2.95.3 bugware (sic) */
		status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));

		txd->opts1 = cpu_to_le32(status);
		txd->addr = cpu_to_le64(mapping);

		tp->tx_skb[entry].len = len;
	}

	if (cur_frag) {
		tp->tx_skb[entry].skb = skb;
		txd->opts1 |= cpu_to_le32(LastFrag);
	}

	return cur_frag;
}

static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
{
	if (dev->features & NETIF_F_TSO) {
4249
		u32 mss = skb_shinfo(skb)->gso_size;
L
Linus Torvalds 已提交
4250 4251 4252 4253

		if (mss)
			return LargeSend | ((mss & MSSMask) << MSSShift);
	}
4254
	if (skb->ip_summed == CHECKSUM_PARTIAL) {
4255
		const struct iphdr *ip = ip_hdr(skb);
L
Linus Torvalds 已提交
4256 4257 4258 4259 4260 4261 4262 4263 4264 4265

		if (ip->protocol == IPPROTO_TCP)
			return IPCS | TCPCS;
		else if (ip->protocol == IPPROTO_UDP)
			return IPCS | UDPCS;
		WARN_ON(1);	/* we need a WARN() */
	}
	return 0;
}

4266 4267
static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
				      struct net_device *dev)
L
Linus Torvalds 已提交
4268 4269 4270 4271 4272 4273 4274 4275
{
	struct rtl8169_private *tp = netdev_priv(dev);
	unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
	struct TxDesc *txd = tp->TxDescArray + entry;
	void __iomem *ioaddr = tp->mmio_addr;
	dma_addr_t mapping;
	u32 status, len;
	u32 opts1;
4276

L
Linus Torvalds 已提交
4277
	if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4278
		netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
L
Linus Torvalds 已提交
4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310
		goto err_stop;
	}

	if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
		goto err_stop;

	opts1 = DescOwn | rtl8169_tso_csum(skb, dev);

	frags = rtl8169_xmit_frags(tp, skb, opts1);
	if (frags) {
		len = skb_headlen(skb);
		opts1 |= FirstFrag;
	} else {
		len = skb->len;
		opts1 |= FirstFrag | LastFrag;
		tp->tx_skb[entry].skb = skb;
	}

	mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);

	tp->tx_skb[entry].len = len;
	txd->addr = cpu_to_le64(mapping);
	txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));

	wmb();

	/* anti gcc 2.95.3 bugware (sic) */
	status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
	txd->opts1 = cpu_to_le32(status);

	tp->cur_tx += frags + 1;

4311
	wmb();
L
Linus Torvalds 已提交
4312

4313
	RTL_W8(TxPoll, NPQ);	/* set polling bit */
L
Linus Torvalds 已提交
4314 4315 4316 4317 4318 4319 4320 4321

	if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
		netif_stop_queue(dev);
		smp_rmb();
		if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
			netif_wake_queue(dev);
	}

4322
	return NETDEV_TX_OK;
L
Linus Torvalds 已提交
4323 4324 4325

err_stop:
	netif_stop_queue(dev);
4326
	dev->stats.tx_dropped++;
4327
	return NETDEV_TX_BUSY;
L
Linus Torvalds 已提交
4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339
}

static void rtl8169_pcierr_interrupt(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct pci_dev *pdev = tp->pci_dev;
	void __iomem *ioaddr = tp->mmio_addr;
	u16 pci_status, pci_cmd;

	pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
	pci_read_config_word(pdev, PCI_STATUS, &pci_status);

4340 4341
	netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
		  pci_cmd, pci_status);
L
Linus Torvalds 已提交
4342 4343 4344 4345

	/*
	 * The recovery sequence below admits a very elaborated explanation:
	 * - it seems to work;
4346 4347
	 * - I did not see what else could be done;
	 * - it makes iop3xx happy.
L
Linus Torvalds 已提交
4348 4349 4350
	 *
	 * Feel free to adjust to your needs.
	 */
4351
	if (pdev->broken_parity_status)
4352 4353 4354 4355 4356
		pci_cmd &= ~PCI_COMMAND_PARITY;
	else
		pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;

	pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
L
Linus Torvalds 已提交
4357 4358 4359 4360 4361 4362 4363 4364

	pci_write_config_word(pdev, PCI_STATUS,
		pci_status & (PCI_STATUS_DETECTED_PARITY |
		PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
		PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));

	/* The infamous DAC f*ckup only happens at boot time */
	if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4365
		netif_info(tp, intr, dev, "disabling PCI DAC\n");
L
Linus Torvalds 已提交
4366 4367 4368 4369 4370 4371
		tp->cp_cmd &= ~PCIDAC;
		RTL_W16(CPlusCmd, tp->cp_cmd);
		dev->features &= ~NETIF_F_HIGHDMA;
	}

	rtl8169_hw_reset(ioaddr);
4372 4373

	rtl8169_schedule_work(dev, rtl8169_reinit_task);
L
Linus Torvalds 已提交
4374 4375
}

F
Francois Romieu 已提交
4376 4377 4378
static void rtl8169_tx_interrupt(struct net_device *dev,
				 struct rtl8169_private *tp,
				 void __iomem *ioaddr)
L
Linus Torvalds 已提交
4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396
{
	unsigned int dirty_tx, tx_left;

	dirty_tx = tp->dirty_tx;
	smp_rmb();
	tx_left = tp->cur_tx - dirty_tx;

	while (tx_left > 0) {
		unsigned int entry = dirty_tx % NUM_TX_DESC;
		struct ring_info *tx_skb = tp->tx_skb + entry;
		u32 len = tx_skb->len;
		u32 status;

		rmb();
		status = le32_to_cpu(tp->TxDescArray[entry].opts1);
		if (status & DescOwn)
			break;

4397 4398
		dev->stats.tx_bytes += len;
		dev->stats.tx_packets++;
L
Linus Torvalds 已提交
4399 4400 4401 4402

		rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);

		if (status & LastFrag) {
4403
			dev_kfree_skb(tx_skb->skb);
L
Linus Torvalds 已提交
4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416
			tx_skb->skb = NULL;
		}
		dirty_tx++;
		tx_left--;
	}

	if (tp->dirty_tx != dirty_tx) {
		tp->dirty_tx = dirty_tx;
		smp_wmb();
		if (netif_queue_stopped(dev) &&
		    (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
			netif_wake_queue(dev);
		}
4417 4418 4419 4420 4421 4422 4423 4424 4425
		/*
		 * 8168 hack: TxPoll requests are lost when the Tx packets are
		 * too close. Let's kick an extra TxPoll request when a burst
		 * of start_xmit activity is detected (if it is not detected,
		 * it is slow enough). -- FR
		 */
		smp_rmb();
		if (tp->cur_tx != dirty_tx)
			RTL_W8(TxPoll, NPQ);
L
Linus Torvalds 已提交
4426 4427 4428
	}
}

4429 4430 4431 4432 4433
static inline int rtl8169_fragmented_frame(u32 status)
{
	return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
}

L
Linus Torvalds 已提交
4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446
static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
{
	u32 opts1 = le32_to_cpu(desc->opts1);
	u32 status = opts1 & RxProtoMask;

	if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
	    ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
	    ((status == RxProtoIP) && !(opts1 & IPFail)))
		skb->ip_summed = CHECKSUM_UNNECESSARY;
	else
		skb->ip_summed = CHECKSUM_NONE;
}

F
Francois Romieu 已提交
4447 4448 4449
static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
				       struct rtl8169_private *tp, int pkt_size,
				       dma_addr_t addr)
L
Linus Torvalds 已提交
4450
{
S
Stephen Hemminger 已提交
4451 4452
	struct sk_buff *skb;
	bool done = false;
L
Linus Torvalds 已提交
4453

S
Stephen Hemminger 已提交
4454 4455
	if (pkt_size >= rx_copybreak)
		goto out;
L
Linus Torvalds 已提交
4456

4457
	skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
S
Stephen Hemminger 已提交
4458 4459 4460
	if (!skb)
		goto out;

F
Francois Romieu 已提交
4461 4462
	pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
				    PCI_DMA_FROMDEVICE);
S
Stephen Hemminger 已提交
4463 4464 4465 4466 4467
	skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
	*sk_buff = skb;
	done = true;
out:
	return done;
L
Linus Torvalds 已提交
4468 4469
}

E
Eric Dumazet 已提交
4470 4471 4472 4473 4474 4475 4476
/*
 * Warning : rtl8169_rx_interrupt() might be called :
 * 1) from NAPI (softirq) context
 *	(polling = 1 : we should call netif_receive_skb())
 * 2) from process context (rtl8169_reset_task())
 *	(polling = 0 : we must call netif_rx() instead)
 */
F
Francois Romieu 已提交
4477 4478
static int rtl8169_rx_interrupt(struct net_device *dev,
				struct rtl8169_private *tp,
4479
				void __iomem *ioaddr, u32 budget)
L
Linus Torvalds 已提交
4480 4481 4482
{
	unsigned int cur_rx, rx_left;
	unsigned int delta, count;
E
Eric Dumazet 已提交
4483
	int polling = (budget != ~(u32)0) ? 1 : 0;
L
Linus Torvalds 已提交
4484 4485 4486

	cur_rx = tp->cur_rx;
	rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
F
Francois Romieu 已提交
4487
	rx_left = min(rx_left, budget);
L
Linus Torvalds 已提交
4488

R
Richard Dawe 已提交
4489
	for (; rx_left > 0; rx_left--, cur_rx++) {
L
Linus Torvalds 已提交
4490
		unsigned int entry = cur_rx % NUM_RX_DESC;
4491
		struct RxDesc *desc = tp->RxDescArray + entry;
L
Linus Torvalds 已提交
4492 4493 4494
		u32 status;

		rmb();
4495
		status = le32_to_cpu(desc->opts1);
L
Linus Torvalds 已提交
4496 4497 4498

		if (status & DescOwn)
			break;
R
Richard Dawe 已提交
4499
		if (unlikely(status & RxRES)) {
4500 4501
			netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
				   status);
4502
			dev->stats.rx_errors++;
L
Linus Torvalds 已提交
4503
			if (status & (RxRWT | RxRUNT))
4504
				dev->stats.rx_length_errors++;
L
Linus Torvalds 已提交
4505
			if (status & RxCRC)
4506
				dev->stats.rx_crc_errors++;
4507 4508
			if (status & RxFOVF) {
				rtl8169_schedule_work(dev, rtl8169_reset_task);
4509
				dev->stats.rx_fifo_errors++;
4510
			}
4511
			rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
L
Linus Torvalds 已提交
4512 4513
		} else {
			struct sk_buff *skb = tp->Rx_skbuff[entry];
S
Stephen Hemminger 已提交
4514
			dma_addr_t addr = le64_to_cpu(desc->addr);
L
Linus Torvalds 已提交
4515
			int pkt_size = (status & 0x00001FFF) - 4;
S
Stephen Hemminger 已提交
4516
			struct pci_dev *pdev = tp->pci_dev;
L
Linus Torvalds 已提交
4517

4518 4519 4520 4521 4522 4523
			/*
			 * The driver does not support incoming fragmented
			 * frames. They are seen as a symptom of over-mtu
			 * sized frames.
			 */
			if (unlikely(rtl8169_fragmented_frame(status))) {
4524 4525
				dev->stats.rx_dropped++;
				dev->stats.rx_length_errors++;
4526
				rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
R
Richard Dawe 已提交
4527
				continue;
4528 4529
			}

L
Linus Torvalds 已提交
4530
			rtl8169_rx_csum(skb, desc);
4531

F
Francois Romieu 已提交
4532
			if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
S
Stephen Hemminger 已提交
4533 4534 4535 4536
				pci_dma_sync_single_for_device(pdev, addr,
					pkt_size, PCI_DMA_FROMDEVICE);
				rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
			} else {
4537
				pci_unmap_single(pdev, addr, tp->rx_buf_sz,
S
Stephen Hemminger 已提交
4538
						 PCI_DMA_FROMDEVICE);
L
Linus Torvalds 已提交
4539 4540 4541 4542 4543 4544
				tp->Rx_skbuff[entry] = NULL;
			}

			skb_put(skb, pkt_size);
			skb->protocol = eth_type_trans(skb, dev);

E
Eric Dumazet 已提交
4545 4546 4547 4548 4549 4550
			if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
				if (likely(polling))
					netif_receive_skb(skb);
				else
					netif_rx(skb);
			}
L
Linus Torvalds 已提交
4551

4552 4553
			dev->stats.rx_bytes += pkt_size;
			dev->stats.rx_packets++;
L
Linus Torvalds 已提交
4554
		}
4555 4556

		/* Work around for AMD plateform. */
A
Al Viro 已提交
4557
		if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4558 4559 4560 4561
		    (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
			desc->opts2 = 0;
			cur_rx++;
		}
L
Linus Torvalds 已提交
4562 4563 4564 4565 4566 4567
	}

	count = cur_rx - tp->cur_rx;
	tp->cur_rx = cur_rx;

	delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
4568 4569
	if (!delta && count)
		netif_info(tp, intr, dev, "no Rx buffer allocated\n");
L
Linus Torvalds 已提交
4570 4571 4572 4573 4574 4575 4576 4577 4578
	tp->dirty_rx += delta;

	/*
	 * FIXME: until there is periodic timer to try and refill the ring,
	 * a temporary shortage may definitely kill the Rx process.
	 * - disable the asic to try and avoid an overflow and kick it again
	 *   after refill ?
	 * - how do others driver handle this condition (Uh oh...).
	 */
4579 4580
	if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
		netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
L
Linus Torvalds 已提交
4581 4582 4583 4584

	return count;
}

F
Francois Romieu 已提交
4585
static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
L
Linus Torvalds 已提交
4586
{
F
Francois Romieu 已提交
4587
	struct net_device *dev = dev_instance;
L
Linus Torvalds 已提交
4588 4589 4590
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	int handled = 0;
F
Francois Romieu 已提交
4591
	int status;
L
Linus Torvalds 已提交
4592

4593 4594 4595
	/* loop handling interrupts until we have no new ones or
	 * we hit a invalid/hotplug case.
	 */
F
Francois Romieu 已提交
4596
	status = RTL_R16(IntrStatus);
4597 4598
	while (status && status != 0xffff) {
		handled = 1;
L
Linus Torvalds 已提交
4599

4600 4601 4602 4603 4604 4605 4606
		/* Handle all of the error cases first. These will reset
		 * the chip, so just exit the loop.
		 */
		if (unlikely(!netif_running(dev))) {
			rtl8169_asic_down(ioaddr);
			break;
		}
L
Linus Torvalds 已提交
4607

4608 4609 4610 4611 4612 4613 4614
		/* Work around for rx fifo overflow */
		if (unlikely(status & RxFIFOOver) &&
		(tp->mac_version == RTL_GIGA_MAC_VER_11)) {
			netif_stop_queue(dev);
			rtl8169_tx_timeout(dev);
			break;
		}
L
Linus Torvalds 已提交
4615

4616 4617 4618 4619
		if (unlikely(status & SYSErr)) {
			rtl8169_pcierr_interrupt(dev);
			break;
		}
L
Linus Torvalds 已提交
4620

4621 4622
		if (status & LinkChg)
			rtl8169_check_link_status(dev, tp, ioaddr);
4623

4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634
		/* We need to see the lastest version of tp->intr_mask to
		 * avoid ignoring an MSI interrupt and having to wait for
		 * another event which may never come.
		 */
		smp_rmb();
		if (status & tp->intr_mask & tp->napi_event) {
			RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
			tp->intr_mask = ~tp->napi_event;

			if (likely(napi_schedule_prep(&tp->napi)))
				__napi_schedule(&tp->napi);
4635 4636 4637
			else
				netif_info(tp, intr, dev,
					   "interrupt %04x in poll\n", status);
4638
		}
L
Linus Torvalds 已提交
4639

4640 4641 4642 4643 4644 4645 4646 4647
		/* We only get a new MSI interrupt when all active irq
		 * sources on the chip have been acknowledged. So, ack
		 * everything we've seen and check if new sources have become
		 * active to avoid blocking all interrupts from the chip.
		 */
		RTL_W16(IntrStatus,
			(status & RxFIFOOver) ? (status | RxOverflow) : status);
		status = RTL_R16(IntrStatus);
F
Francois Romieu 已提交
4648
	}
L
Linus Torvalds 已提交
4649 4650 4651 4652

	return IRQ_RETVAL(handled);
}

4653
static int rtl8169_poll(struct napi_struct *napi, int budget)
L
Linus Torvalds 已提交
4654
{
4655 4656
	struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
	struct net_device *dev = tp->dev;
L
Linus Torvalds 已提交
4657
	void __iomem *ioaddr = tp->mmio_addr;
4658
	int work_done;
L
Linus Torvalds 已提交
4659

4660
	work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
L
Linus Torvalds 已提交
4661 4662
	rtl8169_tx_interrupt(dev, tp, ioaddr);

4663
	if (work_done < budget) {
4664
		napi_complete(napi);
4665 4666 4667 4668 4669 4670 4671

		/* We need for force the visibility of tp->intr_mask
		 * for other CPUs, as we can loose an MSI interrupt
		 * and potentially wait for a retransmit timeout if we don't.
		 * The posted write to IntrMask is safe, as it will
		 * eventually make it to the chip and we won't loose anything
		 * until it does.
L
Linus Torvalds 已提交
4672
		 */
4673
		tp->intr_mask = 0xffff;
4674
		wmb();
4675
		RTL_W16(IntrMask, tp->intr_event);
L
Linus Torvalds 已提交
4676 4677
	}

4678
	return work_done;
L
Linus Torvalds 已提交
4679 4680
}

4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691
static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	if (tp->mac_version > RTL_GIGA_MAC_VER_06)
		return;

	dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
	RTL_W32(RxMissed, 0);
}

L
Linus Torvalds 已提交
4692 4693 4694 4695
static void rtl8169_down(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
4696
	unsigned int intrmask;
L
Linus Torvalds 已提交
4697 4698 4699 4700 4701

	rtl8169_delete_timer(dev);

	netif_stop_queue(dev);

4702 4703
	napi_disable(&tp->napi);

L
Linus Torvalds 已提交
4704 4705 4706 4707 4708
core_down:
	spin_lock_irq(&tp->lock);

	rtl8169_asic_down(ioaddr);

4709
	rtl8169_rx_missed(dev, ioaddr);
L
Linus Torvalds 已提交
4710 4711 4712 4713 4714 4715

	spin_unlock_irq(&tp->lock);

	synchronize_irq(dev->irq);

	/* Give a racing hard_start_xmit a few cycles to complete. */
4716
	synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
L
Linus Torvalds 已提交
4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727

	/*
	 * And now for the 50k$ question: are IRQ disabled or not ?
	 *
	 * Two paths lead here:
	 * 1) dev->close
	 *    -> netif_running() is available to sync the current code and the
	 *       IRQ handler. See rtl8169_interrupt for details.
	 * 2) dev->change_mtu
	 *    -> rtl8169_poll can not be issued again and re-enable the
	 *       interruptions. Let's simply issue the IRQ down sequence again.
4728 4729
	 *
	 * No loop if hotpluged or major error (0xffff).
L
Linus Torvalds 已提交
4730
	 */
4731 4732
	intrmask = RTL_R16(IntrMask);
	if (intrmask && (intrmask != 0xffff))
L
Linus Torvalds 已提交
4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744
		goto core_down;

	rtl8169_tx_clear(tp);

	rtl8169_rx_clear(tp);
}

static int rtl8169_close(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct pci_dev *pdev = tp->pci_dev;

4745 4746
	pm_runtime_get_sync(&pdev->dev);

4747 4748 4749
	/* update counters before going down */
	rtl8169_update_counters(dev);

L
Linus Torvalds 已提交
4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760
	rtl8169_down(dev);

	free_irq(dev->irq, dev);

	pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
			    tp->RxPhyAddr);
	pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
			    tp->TxPhyAddr);
	tp->TxDescArray = NULL;
	tp->RxDescArray = NULL;

4761 4762
	pm_runtime_put_sync(&pdev->dev);

L
Linus Torvalds 已提交
4763 4764 4765
	return 0;
}

4766
static void rtl_set_rx_mode(struct net_device *dev)
L
Linus Torvalds 已提交
4767 4768 4769 4770 4771
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	unsigned long flags;
	u32 mc_filter[2];	/* Multicast hash filter */
F
Francois Romieu 已提交
4772
	int rx_mode;
L
Linus Torvalds 已提交
4773 4774 4775 4776
	u32 tmp = 0;

	if (dev->flags & IFF_PROMISC) {
		/* Unconditionally log net taps. */
4777
		netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
L
Linus Torvalds 已提交
4778 4779 4780 4781
		rx_mode =
		    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
		    AcceptAllPhys;
		mc_filter[1] = mc_filter[0] = 0xffffffff;
4782
	} else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4783
		   (dev->flags & IFF_ALLMULTI)) {
L
Linus Torvalds 已提交
4784 4785 4786 4787
		/* Too many to filter perfectly -- accept all multicasts. */
		rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
		mc_filter[1] = mc_filter[0] = 0xffffffff;
	} else {
4788
		struct netdev_hw_addr *ha;
F
Francois Romieu 已提交
4789

L
Linus Torvalds 已提交
4790 4791
		rx_mode = AcceptBroadcast | AcceptMyPhys;
		mc_filter[1] = mc_filter[0] = 0;
4792 4793
		netdev_for_each_mc_addr(ha, dev) {
			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
L
Linus Torvalds 已提交
4794 4795 4796 4797 4798 4799 4800 4801 4802 4803
			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
			rx_mode |= AcceptMulticast;
		}
	}

	spin_lock_irqsave(&tp->lock, flags);

	tmp = rtl8169_rx_config | rx_mode |
	      (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);

4804
	if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4805 4806 4807 4808
		u32 data = mc_filter[0];

		mc_filter[0] = swab32(mc_filter[1]);
		mc_filter[1] = swab32(data);
4809 4810
	}

L
Linus Torvalds 已提交
4811 4812 4813
	RTL_W32(MAR0 + 0, mc_filter[0]);
	RTL_W32(MAR0 + 4, mc_filter[1]);

4814 4815
	RTL_W32(RxConfig, tmp);

L
Linus Torvalds 已提交
4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832
	spin_unlock_irqrestore(&tp->lock, flags);
}

/**
 *  rtl8169_get_stats - Get rtl8169 read/write statistics
 *  @dev: The Ethernet Device to get statistics for
 *
 *  Get TX/RX statistics for rtl8169
 */
static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	unsigned long flags;

	if (netif_running(dev)) {
		spin_lock_irqsave(&tp->lock, flags);
4833
		rtl8169_rx_missed(dev, ioaddr);
L
Linus Torvalds 已提交
4834 4835
		spin_unlock_irqrestore(&tp->lock, flags);
	}
4836

4837
	return &dev->stats;
L
Linus Torvalds 已提交
4838 4839
}

4840
static void rtl8169_net_suspend(struct net_device *dev)
4841 4842
{
	if (!netif_running(dev))
4843
		return;
4844 4845 4846

	netif_device_detach(dev);
	netif_stop_queue(dev);
4847 4848 4849 4850 4851 4852 4853 4854
}

#ifdef CONFIG_PM

static int rtl8169_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
4855

4856
	rtl8169_net_suspend(dev);
4857

4858 4859 4860
	return 0;
}

4861 4862 4863 4864 4865 4866
static void __rtl8169_resume(struct net_device *dev)
{
	netif_device_attach(dev);
	rtl8169_schedule_work(dev, rtl8169_reset_task);
}

4867
static int rtl8169_resume(struct device *device)
4868
{
4869
	struct pci_dev *pdev = to_pci_dev(device);
4870 4871
	struct net_device *dev = pci_get_drvdata(pdev);

4872 4873
	if (netif_running(dev))
		__rtl8169_resume(dev);
4874

4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911
	return 0;
}

static int rtl8169_runtime_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

	if (!tp->TxDescArray)
		return 0;

	spin_lock_irq(&tp->lock);
	tp->saved_wolopts = __rtl8169_get_wol(tp);
	__rtl8169_set_wol(tp, WAKE_ANY);
	spin_unlock_irq(&tp->lock);

	rtl8169_net_suspend(dev);

	return 0;
}

static int rtl8169_runtime_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

	if (!tp->TxDescArray)
		return 0;

	spin_lock_irq(&tp->lock);
	__rtl8169_set_wol(tp, tp->saved_wolopts);
	tp->saved_wolopts = 0;
	spin_unlock_irq(&tp->lock);

	__rtl8169_resume(dev);
4912 4913 4914 4915

	return 0;
}

4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928
static int rtl8169_runtime_idle(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

	if (!tp->TxDescArray)
		return 0;

	rtl8169_check_link_status(dev, tp, tp->mmio_addr);
	return -EBUSY;
}

4929
static const struct dev_pm_ops rtl8169_pm_ops = {
4930 4931 4932 4933 4934 4935
	.suspend = rtl8169_suspend,
	.resume = rtl8169_resume,
	.freeze = rtl8169_suspend,
	.thaw = rtl8169_resume,
	.poweroff = rtl8169_suspend,
	.restore = rtl8169_resume,
4936 4937 4938
	.runtime_suspend = rtl8169_runtime_suspend,
	.runtime_resume = rtl8169_runtime_resume,
	.runtime_idle = rtl8169_runtime_idle,
4939 4940 4941 4942 4943 4944 4945 4946 4947 4948
};

#define RTL8169_PM_OPS	(&rtl8169_pm_ops)

#else /* !CONFIG_PM */

#define RTL8169_PM_OPS	NULL

#endif /* !CONFIG_PM */

F
Francois Romieu 已提交
4949 4950
static void rtl_shutdown(struct pci_dev *pdev)
{
4951
	struct net_device *dev = pci_get_drvdata(pdev);
4952 4953
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
4954 4955

	rtl8169_net_suspend(dev);
F
Francois Romieu 已提交
4956

4957 4958 4959
	/* restore original MAC address */
	rtl_rar_set(tp, dev->perm_addr);

4960 4961 4962 4963 4964 4965
	spin_lock_irq(&tp->lock);

	rtl8169_asic_down(ioaddr);

	spin_unlock_irq(&tp->lock);

4966
	if (system_state == SYSTEM_POWER_OFF) {
4967 4968 4969 4970 4971 4972 4973 4974 4975
		/* WoL fails with some 8168 when the receiver is disabled. */
		if (tp->features & RTL_FEATURE_WOL) {
			pci_clear_master(pdev);

			RTL_W8(ChipCmd, CmdRxEnb);
			/* PCI commit */
			RTL_R8(ChipCmd);
		}

4976 4977 4978 4979
		pci_wake_from_d3(pdev, true);
		pci_set_power_state(pdev, PCI_D3hot);
	}
}
4980

L
Linus Torvalds 已提交
4981 4982 4983 4984 4985
static struct pci_driver rtl8169_pci_driver = {
	.name		= MODULENAME,
	.id_table	= rtl8169_pci_tbl,
	.probe		= rtl8169_init_one,
	.remove		= __devexit_p(rtl8169_remove_one),
F
Francois Romieu 已提交
4986
	.shutdown	= rtl_shutdown,
4987
	.driver.pm	= RTL8169_PM_OPS,
L
Linus Torvalds 已提交
4988 4989
};

F
Francois Romieu 已提交
4990
static int __init rtl8169_init_module(void)
L
Linus Torvalds 已提交
4991
{
4992
	return pci_register_driver(&rtl8169_pci_driver);
L
Linus Torvalds 已提交
4993 4994
}

F
Francois Romieu 已提交
4995
static void __exit rtl8169_cleanup_module(void)
L
Linus Torvalds 已提交
4996 4997 4998 4999 5000 5001
{
	pci_unregister_driver(&rtl8169_pci_driver);
}

module_init(rtl8169_init_module);
module_exit(rtl8169_cleanup_module);