radeon_device.c 36.7 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include <linux/console.h>
29
#include <linux/slab.h>
30 31 32
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/radeon_drm.h>
33
#include <linux/vgaarb.h>
34
#include <linux/vga_switcheroo.h>
35
#include <linux/efi.h>
36 37 38 39
#include "radeon_reg.h"
#include "radeon.h"
#include "atom.h"

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
static const char radeon_family_name[][16] = {
	"R100",
	"RV100",
	"RS100",
	"RV200",
	"RS200",
	"R200",
	"RV250",
	"RS300",
	"RV280",
	"R300",
	"R350",
	"RV350",
	"RV380",
	"R420",
	"R423",
	"RV410",
	"RS400",
	"RS480",
	"RS600",
	"RS690",
	"RS740",
	"RV515",
	"R520",
	"RV530",
	"RV560",
	"RV570",
	"R580",
	"R600",
	"RV610",
	"RV630",
	"RV670",
	"RV620",
	"RV635",
	"RS780",
	"RS880",
	"RV770",
	"RV730",
	"RV710",
	"RV740",
	"CEDAR",
	"REDWOOD",
	"JUNIPER",
	"CYPRESS",
	"HEMLOCK",
85
	"PALM",
86 87
	"SUMO",
	"SUMO2",
88 89 90
	"BARTS",
	"TURKS",
	"CAICOS",
91
	"CAYMAN",
92
	"ARUBA",
93 94 95
	"TAHITI",
	"PITCAIRN",
	"VERDE",
96 97 98
	"LAST",
};

99 100 101 102 103 104
/**
 * radeon_surface_init - Clear GPU surface registers.
 *
 * @rdev: radeon_device pointer
 *
 * Clear GPU surface registers (r1xx-r5xx).
105
 */
106
void radeon_surface_init(struct radeon_device *rdev)
107 108 109 110 111
{
	/* FIXME: check this out */
	if (rdev->family < CHIP_R600) {
		int i;

112 113 114 115 116
		for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
			if (rdev->surface_regs[i].bo)
				radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
			else
				radeon_clear_surface_reg(rdev, i);
117
		}
118 119
		/* enable surfaces */
		WREG32(RADEON_SURFACE_CNTL, 0);
120 121 122
	}
}

123 124 125
/*
 * GPU scratch registers helpers function.
 */
126 127 128 129 130 131 132
/**
 * radeon_scratch_init - Init scratch register driver information.
 *
 * @rdev: radeon_device pointer
 *
 * Init CP scratch register driver information (r1xx-r5xx)
 */
133
void radeon_scratch_init(struct radeon_device *rdev)
134 135 136 137 138 139 140 141 142
{
	int i;

	/* FIXME: check this out */
	if (rdev->family < CHIP_R300) {
		rdev->scratch.num_reg = 5;
	} else {
		rdev->scratch.num_reg = 7;
	}
143
	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
144 145
	for (i = 0; i < rdev->scratch.num_reg; i++) {
		rdev->scratch.free[i] = true;
146
		rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
147 148 149
	}
}

150 151 152 153 154 155 156 157 158
/**
 * radeon_scratch_get - Allocate a scratch register
 *
 * @rdev: radeon_device pointer
 * @reg: scratch register mmio offset
 *
 * Allocate a CP scratch register for use by the driver (all asics).
 * Returns 0 on success or -EINVAL on failure.
 */
159 160 161 162 163 164 165 166 167 168 169 170 171 172
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
{
	int i;

	for (i = 0; i < rdev->scratch.num_reg; i++) {
		if (rdev->scratch.free[i]) {
			rdev->scratch.free[i] = false;
			*reg = rdev->scratch.reg[i];
			return 0;
		}
	}
	return -EINVAL;
}

173 174 175 176 177 178 179 180
/**
 * radeon_scratch_free - Free a scratch register
 *
 * @rdev: radeon_device pointer
 * @reg: scratch register mmio offset
 *
 * Free a CP scratch register allocated for use by the driver (all asics)
 */
181 182 183 184 185 186 187 188 189 190 191 192
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
{
	int i;

	for (i = 0; i < rdev->scratch.num_reg; i++) {
		if (rdev->scratch.reg[i] == reg) {
			rdev->scratch.free[i] = true;
			return;
		}
	}
}

193 194 195 196 197 198 199 200 201 202 203 204 205 206
/*
 * radeon_wb_*()
 * Writeback is the the method by which the the GPU updates special pages
 * in memory with the status of certain GPU events (fences, ring pointers,
 * etc.).
 */

/**
 * radeon_wb_disable - Disable Writeback
 *
 * @rdev: radeon_device pointer
 *
 * Disables Writeback (all asics).  Used for suspend.
 */
207 208 209 210 211 212 213 214 215 216 217 218 219 220 221
void radeon_wb_disable(struct radeon_device *rdev)
{
	int r;

	if (rdev->wb.wb_obj) {
		r = radeon_bo_reserve(rdev->wb.wb_obj, false);
		if (unlikely(r != 0))
			return;
		radeon_bo_kunmap(rdev->wb.wb_obj);
		radeon_bo_unpin(rdev->wb.wb_obj);
		radeon_bo_unreserve(rdev->wb.wb_obj);
	}
	rdev->wb.enabled = false;
}

222 223 224 225 226 227 228 229
/**
 * radeon_wb_fini - Disable Writeback and free memory
 *
 * @rdev: radeon_device pointer
 *
 * Disables Writeback and frees the Writeback memory (all asics).
 * Used at driver shutdown.
 */
230 231 232 233 234 235 236 237 238 239
void radeon_wb_fini(struct radeon_device *rdev)
{
	radeon_wb_disable(rdev);
	if (rdev->wb.wb_obj) {
		radeon_bo_unref(&rdev->wb.wb_obj);
		rdev->wb.wb = NULL;
		rdev->wb.wb_obj = NULL;
	}
}

240 241 242 243 244 245 246 247 248
/**
 * radeon_wb_init- Init Writeback driver info and allocate memory
 *
 * @rdev: radeon_device pointer
 *
 * Disables Writeback and frees the Writeback memory (all asics).
 * Used at driver startup.
 * Returns 0 on success or an -error on failure.
 */
249 250 251 252 253
int radeon_wb_init(struct radeon_device *rdev)
{
	int r;

	if (rdev->wb.wb_obj == NULL) {
254
		r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
255
				     RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281
		if (r) {
			dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
			return r;
		}
	}
	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
	if (unlikely(r != 0)) {
		radeon_wb_fini(rdev);
		return r;
	}
	r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
			  &rdev->wb.gpu_addr);
	if (r) {
		radeon_bo_unreserve(rdev->wb.wb_obj);
		dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
		radeon_wb_fini(rdev);
		return r;
	}
	r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
	radeon_bo_unreserve(rdev->wb.wb_obj);
	if (r) {
		dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
		radeon_wb_fini(rdev);
		return r;
	}

282 283
	/* clear wb memory */
	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
284 285
	/* disable event_write fences */
	rdev->wb.use_event = false;
286
	/* disabled via module param */
287
	if (radeon_no_wb == 1) {
288
		rdev->wb.enabled = false;
289
	} else {
290
		if (rdev->flags & RADEON_IS_AGP) {
291 292 293 294
			/* often unreliable on AGP */
			rdev->wb.enabled = false;
		} else if (rdev->family < CHIP_R300) {
			/* often unreliable on pre-r300 */
295
			rdev->wb.enabled = false;
296
		} else {
297
			rdev->wb.enabled = true;
298
			/* event_write fences are only available on r600+ */
299
			if (rdev->family >= CHIP_R600) {
300
				rdev->wb.use_event = true;
301
			}
302
		}
303
	}
304 305
	/* always use writeback/events on NI, APUs */
	if (rdev->family >= CHIP_PALM) {
306 307 308
		rdev->wb.enabled = true;
		rdev->wb.use_event = true;
	}
309 310 311 312 313 314

	dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");

	return 0;
}

315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336
/**
 * radeon_vram_location - try to find VRAM location
 * @rdev: radeon device structure holding all necessary informations
 * @mc: memory controller structure holding memory informations
 * @base: base address at which to put VRAM
 *
 * Function will place try to place VRAM at base address provided
 * as parameter (which is so far either PCI aperture address or
 * for IGP TOM base address).
 *
 * If there is not enough space to fit the unvisible VRAM in the 32bits
 * address space then we limit the VRAM size to the aperture.
 *
 * If we are using AGP and if the AGP aperture doesn't allow us to have
 * room for all the VRAM than we restrict the VRAM to the PCI aperture
 * size and print a warning.
 *
 * This function will never fails, worst case are limiting VRAM.
 *
 * Note: GTT start, end, size should be initialized before calling this
 * function on AGP platform.
 *
L
Lucas De Marchi 已提交
337
 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354
 * this shouldn't be a problem as we are using the PCI aperture as a reference.
 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 * not IGP.
 *
 * Note: we use mc_vram_size as on some board we need to program the mc to
 * cover the whole aperture even if VRAM size is inferior to aperture size
 * Novell bug 204882 + along with lots of ubuntu ones
 *
 * Note: when limiting vram it's safe to overwritte real_vram_size because
 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 * ones)
 *
 * Note: IGP TOM addr should be the same as the aperture addr, we don't
 * explicitly check for that thought.
 *
 * FIXME: when reducing VRAM size align new size on power of 2.
355
 */
356
void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
357
{
358 359 360 361 362 363 364
	mc->vram_start = base;
	if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
		mc->real_vram_size = mc->aper_size;
		mc->mc_vram_size = mc->aper_size;
	}
	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
365
	if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
366 367 368 369 370
		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
		mc->real_vram_size = mc->aper_size;
		mc->mc_vram_size = mc->aper_size;
	}
	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
371 372
	if (radeon_vram_limit && radeon_vram_limit < mc->real_vram_size)
		mc->real_vram_size = radeon_vram_limit;
373
	dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
374 375 376
			mc->mc_vram_size >> 20, mc->vram_start,
			mc->vram_end, mc->real_vram_size >> 20);
}
377

378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393
/**
 * radeon_gtt_location - try to find GTT location
 * @rdev: radeon device structure holding all necessary informations
 * @mc: memory controller structure holding memory informations
 *
 * Function will place try to place GTT before or after VRAM.
 *
 * If GTT size is bigger than space left then we ajust GTT size.
 * Thus function will never fails.
 *
 * FIXME: when reducing GTT size align new size on power of 2.
 */
void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
{
	u64 size_af, size_bf;

394 395
	size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
	size_bf = mc->vram_start & ~mc->gtt_base_align;
396 397 398 399
	if (size_bf > size_af) {
		if (mc->gtt_size > size_bf) {
			dev_warn(rdev->dev, "limiting GTT\n");
			mc->gtt_size = size_bf;
400
		}
401
		mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
402
	} else {
403 404 405 406
		if (mc->gtt_size > size_af) {
			dev_warn(rdev->dev, "limiting GTT\n");
			mc->gtt_size = size_af;
		}
407
		mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
408
	}
409
	mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
410
	dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
411
			mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
412 413 414 415 416
}

/*
 * GPU helpers function.
 */
417 418 419 420 421 422 423 424 425
/**
 * radeon_card_posted - check if the hw has already been initialized
 *
 * @rdev: radeon_device pointer
 *
 * Check if the asic has been initialized (all asics).
 * Used at driver startup.
 * Returns true if initialized or false if not.
 */
426
bool radeon_card_posted(struct radeon_device *rdev)
427 428 429
{
	uint32_t reg;

430 431 432
	if (efi_enabled && rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)
		return false;

433
	/* first check CRTCs */
434 435 436 437 438 439
	if (ASIC_IS_DCE41(rdev)) {
		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
		if (reg & EVERGREEN_CRTC_MASTER_EN)
			return true;
	} else if (ASIC_IS_DCE4(rdev)) {
440 441 442 443 444 445 446 447 448
		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
		if (reg & EVERGREEN_CRTC_MASTER_EN)
			return true;
	} else if (ASIC_IS_AVIVO(rdev)) {
449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474
		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
		      RREG32(AVIVO_D2CRTC_CONTROL);
		if (reg & AVIVO_CRTC_EN) {
			return true;
		}
	} else {
		reg = RREG32(RADEON_CRTC_GEN_CNTL) |
		      RREG32(RADEON_CRTC2_GEN_CNTL);
		if (reg & RADEON_CRTC_EN) {
			return true;
		}
	}

	/* then check MEM_SIZE, in case the crtcs are off */
	if (rdev->family >= CHIP_R600)
		reg = RREG32(R600_CONFIG_MEMSIZE);
	else
		reg = RREG32(RADEON_CONFIG_MEMSIZE);

	if (reg)
		return true;

	return false;

}

475 476 477 478 479 480 481 482
/**
 * radeon_update_bandwidth_info - update display bandwidth params
 *
 * @rdev: radeon_device pointer
 *
 * Used when sclk/mclk are switched or display modes are set.
 * params are used to calculate display watermarks (all asics)
 */
483 484 485
void radeon_update_bandwidth_info(struct radeon_device *rdev)
{
	fixed20_12 a;
486 487
	u32 sclk = rdev->pm.current_sclk;
	u32 mclk = rdev->pm.current_mclk;
488

489 490 491 492 493 494
	/* sclk/mclk in Mhz */
	a.full = dfixed_const(100);
	rdev->pm.sclk.full = dfixed_const(sclk);
	rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
	rdev->pm.mclk.full = dfixed_const(mclk);
	rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
495

496
	if (rdev->flags & RADEON_IS_IGP) {
497
		a.full = dfixed_const(16);
498
		/* core_bandwidth = sclk(Mhz) * 16 */
499
		rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
500 501 502
	}
}

503 504 505 506 507 508 509 510 511
/**
 * radeon_boot_test_post_card - check and possibly initialize the hw
 *
 * @rdev: radeon_device pointer
 *
 * Check if the asic is initialized and if not, attempt to initialize
 * it (all asics).
 * Returns true if initialized or false if not.
 */
512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529
bool radeon_boot_test_post_card(struct radeon_device *rdev)
{
	if (radeon_card_posted(rdev))
		return true;

	if (rdev->bios) {
		DRM_INFO("GPU not posted. posting now...\n");
		if (rdev->is_atom_bios)
			atom_asic_init(rdev->mode_info.atom_context);
		else
			radeon_combios_asic_init(rdev->ddev);
		return true;
	} else {
		dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
		return false;
	}
}

530 531 532 533 534 535 536 537 538 539
/**
 * radeon_dummy_page_init - init dummy page used by the driver
 *
 * @rdev: radeon_device pointer
 *
 * Allocate the dummy page used by the driver (all asics).
 * This dummy page is used by the driver as a filler for gart entries
 * when pages are taken out of the GART
 * Returns 0 on sucess, -ENOMEM on failure.
 */
540 541
int radeon_dummy_page_init(struct radeon_device *rdev)
{
542 543
	if (rdev->dummy_page.page)
		return 0;
544 545 546 547 548
	rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
	if (rdev->dummy_page.page == NULL)
		return -ENOMEM;
	rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
					0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
549 550
	if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
		dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
551 552 553 554 555 556 557
		__free_page(rdev->dummy_page.page);
		rdev->dummy_page.page = NULL;
		return -ENOMEM;
	}
	return 0;
}

558 559 560 561 562 563 564
/**
 * radeon_dummy_page_fini - free dummy page used by the driver
 *
 * @rdev: radeon_device pointer
 *
 * Frees the dummy page used by the driver (all asics).
 */
565 566 567 568 569 570 571 572 573 574
void radeon_dummy_page_fini(struct radeon_device *rdev)
{
	if (rdev->dummy_page.page == NULL)
		return;
	pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
			PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
	__free_page(rdev->dummy_page.page);
	rdev->dummy_page.page = NULL;
}

575 576

/* ATOM accessor methods */
577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593
/*
 * ATOM is an interpreted byte code stored in tables in the vbios.  The
 * driver registers callbacks to access registers and the interpreter
 * in the driver parses the tables and executes then to program specific
 * actions (set display modes, asic init, etc.).  See radeon_atombios.c,
 * atombios.h, and atom.c
 */

/**
 * cail_pll_read - read PLL register
 *
 * @info: atom card_info pointer
 * @reg: PLL register offset
 *
 * Provides a PLL register accessor for the atom interpreter (r4xx+).
 * Returns the value of the PLL register.
 */
594 595 596 597 598 599 600 601 602
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
{
	struct radeon_device *rdev = info->dev->dev_private;
	uint32_t r;

	r = rdev->pll_rreg(rdev, reg);
	return r;
}

603 604 605 606 607 608 609 610 611
/**
 * cail_pll_write - write PLL register
 *
 * @info: atom card_info pointer
 * @reg: PLL register offset
 * @val: value to write to the pll register
 *
 * Provides a PLL register accessor for the atom interpreter (r4xx+).
 */
612 613 614 615 616 617 618
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
{
	struct radeon_device *rdev = info->dev->dev_private;

	rdev->pll_wreg(rdev, reg, val);
}

619 620 621 622 623 624 625 626 627
/**
 * cail_mc_read - read MC (Memory Controller) register
 *
 * @info: atom card_info pointer
 * @reg: MC register offset
 *
 * Provides an MC register accessor for the atom interpreter (r4xx+).
 * Returns the value of the MC register.
 */
628 629 630 631 632 633 634 635 636
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
{
	struct radeon_device *rdev = info->dev->dev_private;
	uint32_t r;

	r = rdev->mc_rreg(rdev, reg);
	return r;
}

637 638 639 640 641 642 643 644 645
/**
 * cail_mc_write - write MC (Memory Controller) register
 *
 * @info: atom card_info pointer
 * @reg: MC register offset
 * @val: value to write to the pll register
 *
 * Provides a MC register accessor for the atom interpreter (r4xx+).
 */
646 647 648 649 650 651 652
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
{
	struct radeon_device *rdev = info->dev->dev_private;

	rdev->mc_wreg(rdev, reg, val);
}

653 654 655 656 657 658 659 660 661
/**
 * cail_reg_write - write MMIO register
 *
 * @info: atom card_info pointer
 * @reg: MMIO register offset
 * @val: value to write to the pll register
 *
 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 */
662 663 664 665 666 667 668
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
{
	struct radeon_device *rdev = info->dev->dev_private;

	WREG32(reg*4, val);
}

669 670 671 672 673 674 675 676 677
/**
 * cail_reg_read - read MMIO register
 *
 * @info: atom card_info pointer
 * @reg: MMIO register offset
 *
 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 * Returns the value of the MMIO register.
 */
678 679 680 681 682 683 684 685 686
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
{
	struct radeon_device *rdev = info->dev->dev_private;
	uint32_t r;

	r = RREG32(reg*4);
	return r;
}

687 688 689 690 691 692 693 694 695
/**
 * cail_ioreg_write - write IO register
 *
 * @info: atom card_info pointer
 * @reg: IO register offset
 * @val: value to write to the pll register
 *
 * Provides a IO register accessor for the atom interpreter (r4xx+).
 */
696 697 698 699 700 701 702
static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
{
	struct radeon_device *rdev = info->dev->dev_private;

	WREG32_IO(reg*4, val);
}

703 704 705 706 707 708 709 710 711
/**
 * cail_ioreg_read - read IO register
 *
 * @info: atom card_info pointer
 * @reg: IO register offset
 *
 * Provides an IO register accessor for the atom interpreter (r4xx+).
 * Returns the value of the IO register.
 */
712 713 714 715 716 717 718 719 720
static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
{
	struct radeon_device *rdev = info->dev->dev_private;
	uint32_t r;

	r = RREG32_IO(reg*4);
	return r;
}

721 722 723 724 725 726 727 728 729 730
/**
 * radeon_atombios_init - init the driver info and callbacks for atombios
 *
 * @rdev: radeon_device pointer
 *
 * Initializes the driver info and register access callbacks for the
 * ATOM interpreter (r4xx+).
 * Returns 0 on sucess, -ENOMEM on failure.
 * Called at driver startup.
 */
731 732
int radeon_atombios_init(struct radeon_device *rdev)
{
733 734 735 736 737 738 739 740 741 742
	struct card_info *atom_card_info =
	    kzalloc(sizeof(struct card_info), GFP_KERNEL);

	if (!atom_card_info)
		return -ENOMEM;

	rdev->mode_info.atom_card_info = atom_card_info;
	atom_card_info->dev = rdev->ddev;
	atom_card_info->reg_read = cail_reg_read;
	atom_card_info->reg_write = cail_reg_write;
743 744 745 746 747 748 749 750 751
	/* needed for iio ops */
	if (rdev->rio_mem) {
		atom_card_info->ioreg_read = cail_ioreg_read;
		atom_card_info->ioreg_write = cail_ioreg_write;
	} else {
		DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
		atom_card_info->ioreg_read = cail_reg_read;
		atom_card_info->ioreg_write = cail_reg_write;
	}
752 753 754 755 756 757
	atom_card_info->mc_read = cail_mc_read;
	atom_card_info->mc_write = cail_mc_write;
	atom_card_info->pll_read = cail_pll_read;
	atom_card_info->pll_write = cail_pll_write;

	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
758
	mutex_init(&rdev->mode_info.atom_context->mutex);
759
	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
760
	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
761 762 763
	return 0;
}

764 765 766 767 768 769 770 771 772
/**
 * radeon_atombios_fini - free the driver info and callbacks for atombios
 *
 * @rdev: radeon_device pointer
 *
 * Frees the driver info and register access callbacks for the ATOM
 * interpreter (r4xx+).
 * Called at driver shutdown.
 */
773 774
void radeon_atombios_fini(struct radeon_device *rdev)
{
775 776 777 778
	if (rdev->mode_info.atom_context) {
		kfree(rdev->mode_info.atom_context->scratch);
		kfree(rdev->mode_info.atom_context);
	}
779
	kfree(rdev->mode_info.atom_card_info);
780 781
}

782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797
/* COMBIOS */
/*
 * COMBIOS is the bios format prior to ATOM. It provides
 * command tables similar to ATOM, but doesn't have a unified
 * parser.  See radeon_combios.c
 */

/**
 * radeon_combios_init - init the driver info for combios
 *
 * @rdev: radeon_device pointer
 *
 * Initializes the driver info for combios (r1xx-r3xx).
 * Returns 0 on sucess.
 * Called at driver startup.
 */
798 799 800 801 802 803
int radeon_combios_init(struct radeon_device *rdev)
{
	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
	return 0;
}

804 805 806 807 808 809 810 811
/**
 * radeon_combios_fini - free the driver info for combios
 *
 * @rdev: radeon_device pointer
 *
 * Frees the driver info for combios (r1xx-r3xx).
 * Called at driver shutdown.
 */
812 813 814 815
void radeon_combios_fini(struct radeon_device *rdev)
{
}

816 817 818 819 820 821 822 823 824 825
/* if we get transitioned to only one device, take VGA back */
/**
 * radeon_vga_set_decode - enable/disable vga decode
 *
 * @cookie: radeon_device pointer
 * @state: enable/disable vga decode
 *
 * Enable/disable vga decode (all asics).
 * Returns VGA resource flags.
 */
826 827 828 829 830 831 832 833 834 835
static unsigned int radeon_vga_set_decode(void *cookie, bool state)
{
	struct radeon_device *rdev = cookie;
	radeon_vga_set_state(rdev, state);
	if (state)
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
	else
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
}
836

837 838 839 840 841 842 843 844
/**
 * radeon_check_arguments - validate module params
 *
 * @rdev: radeon_device pointer
 *
 * Validates certain module parameters and updates
 * the associated values used by the driver (all asics).
 */
845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910
void radeon_check_arguments(struct radeon_device *rdev)
{
	/* vramlimit must be a power of two */
	switch (radeon_vram_limit) {
	case 0:
	case 4:
	case 8:
	case 16:
	case 32:
	case 64:
	case 128:
	case 256:
	case 512:
	case 1024:
	case 2048:
	case 4096:
		break;
	default:
		dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
				radeon_vram_limit);
		radeon_vram_limit = 0;
		break;
	}
	radeon_vram_limit = radeon_vram_limit << 20;
	/* gtt size must be power of two and greater or equal to 32M */
	switch (radeon_gart_size) {
	case 4:
	case 8:
	case 16:
		dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
				radeon_gart_size);
		radeon_gart_size = 512;
		break;
	case 32:
	case 64:
	case 128:
	case 256:
	case 512:
	case 1024:
	case 2048:
	case 4096:
		break;
	default:
		dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
				radeon_gart_size);
		radeon_gart_size = 512;
		break;
	}
	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
	/* AGP mode can only be -1, 1, 2, 4, 8 */
	switch (radeon_agpmode) {
	case -1:
	case 0:
	case 1:
	case 2:
	case 4:
	case 8:
		break;
	default:
		dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
				"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
		radeon_agpmode = 0;
		break;
	}
}

911 912 913 914 915 916 917 918 919
/**
 * radeon_switcheroo_set_state - set switcheroo state
 *
 * @pdev: pci dev pointer
 * @state: vga switcheroo state
 *
 * Callback for the switcheroo driver.  Suspends or resumes the
 * the asics before or after it is powered up using ACPI methods.
 */
920 921 922 923 924 925 926
static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
	if (state == VGA_SWITCHEROO_ON) {
		printk(KERN_INFO "radeon: switched on\n");
		/* don't suspend or resume card normally */
927
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
928
		radeon_resume_kms(dev);
929
		dev->switch_power_state = DRM_SWITCH_POWER_ON;
930
		drm_kms_helper_poll_enable(dev);
931 932
	} else {
		printk(KERN_INFO "radeon: switched off\n");
933
		drm_kms_helper_poll_disable(dev);
934
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
935
		radeon_suspend_kms(dev, pmm);
936
		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
937 938 939
	}
}

940 941 942 943 944 945 946 947 948
/**
 * radeon_switcheroo_can_switch - see if switcheroo state can change
 *
 * @pdev: pci dev pointer
 *
 * Callback for the switcheroo driver.  Check of the switcheroo
 * state can be changed.
 * Returns true if the state can be changed, false if not.
 */
949 950 951 952 953 954 955 956 957 958 959
static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	bool can_switch;

	spin_lock(&dev->count_lock);
	can_switch = (dev->open_count == 0);
	spin_unlock(&dev->count_lock);
	return can_switch;
}

960 961 962 963 964
static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
	.set_gpu_state = radeon_switcheroo_set_state,
	.reprobe = NULL,
	.can_switch = radeon_switcheroo_can_switch,
};
965

966 967 968 969 970 971 972 973 974 975 976 977
/**
 * radeon_device_init - initialize the driver
 *
 * @rdev: radeon_device pointer
 * @pdev: drm dev pointer
 * @pdev: pci dev pointer
 * @flags: driver flags
 *
 * Initializes the driver info and hw (all asics).
 * Returns 0 for success or an error on failure.
 * Called at driver startup.
 */
978 979 980 981 982
int radeon_device_init(struct radeon_device *rdev,
		       struct drm_device *ddev,
		       struct pci_dev *pdev,
		       uint32_t flags)
{
983
	int r, i;
D
Dave Airlie 已提交
984
	int dma_bits;
985 986

	rdev->shutdown = false;
987
	rdev->dev = &pdev->dev;
988 989 990 991 992 993 994
	rdev->ddev = ddev;
	rdev->pdev = pdev;
	rdev->flags = flags;
	rdev->family = flags & RADEON_FAMILY_MASK;
	rdev->is_atom_bios = false;
	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
995
	rdev->accel_working = false;
996 997 998 999
	/* set up ring ids */
	for (i = 0; i < RADEON_NUM_RINGS; i++) {
		rdev->ring[i].idx = i;
	}
1000

1001 1002 1003
	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
		radeon_family_name[rdev->family], pdev->vendor, pdev->device,
		pdev->subsystem_vendor, pdev->subsystem_device);
1004

1005 1006
	/* mutex initialization are all done here so we
	 * can recall function without having locking issues */
1007
	mutex_init(&rdev->ring_lock);
1008
	mutex_init(&rdev->dc_hw_i2c_mutex);
1009
	atomic_set(&rdev->ih.lock, 0);
1010
	mutex_init(&rdev->gem.mutex);
1011
	mutex_init(&rdev->pm.mutex);
1012
	mutex_init(&rdev->gpu_clock_mutex);
1013
	init_rwsem(&rdev->pm.mclk_lock);
1014
	init_rwsem(&rdev->exclusive_lock);
1015
	init_waitqueue_head(&rdev->irq.vblank_queue);
1016
	init_waitqueue_head(&rdev->irq.idle_queue);
1017 1018 1019
	r = radeon_gem_init(rdev);
	if (r)
		return r;
1020
	/* initialize vm here */
1021
	mutex_init(&rdev->vm_manager.lock);
1022 1023 1024
	rdev->vm_manager.use_bitmap = 1;
	rdev->vm_manager.max_pfn = 1 << 20;
	INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1025

1026 1027
	/* Set asic functions */
	r = radeon_asic_init(rdev);
1028
	if (r)
1029
		return r;
1030
	radeon_check_arguments(rdev);
1031

1032 1033 1034 1035 1036 1037 1038 1039
	/* all of the newer IGP chips have an internal gart
	 * However some rs4xx report as AGP, so remove that here.
	 */
	if ((rdev->family >= CHIP_RS400) &&
	    (rdev->flags & RADEON_IS_IGP)) {
		rdev->flags &= ~RADEON_IS_AGP;
	}

1040
	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1041
		radeon_agp_disable(rdev);
1042 1043
	}

D
Dave Airlie 已提交
1044 1045
	/* set DMA mask + need_dma32 flags.
	 * PCIE - can handle 40-bits.
1046
	 * IGP - can handle 40-bits
D
Dave Airlie 已提交
1047
	 * AGP - generally dma32 is safest
1048
	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
D
Dave Airlie 已提交
1049 1050 1051 1052
	 */
	rdev->need_dma32 = false;
	if (rdev->flags & RADEON_IS_AGP)
		rdev->need_dma32 = true;
1053
	if ((rdev->flags & RADEON_IS_PCI) &&
1054
	    (rdev->family <= CHIP_RS740))
D
Dave Airlie 已提交
1055 1056 1057 1058
		rdev->need_dma32 = true;

	dma_bits = rdev->need_dma32 ? 32 : 40;
	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1059
	if (r) {
1060
		rdev->need_dma32 = true;
1061
		dma_bits = 32;
1062 1063
		printk(KERN_WARNING "radeon: No suitable DMA available.\n");
	}
1064 1065 1066 1067 1068
	r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
	if (r) {
		pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
		printk(KERN_WARNING "radeon: No coherent DMA available.\n");
	}
1069 1070 1071

	/* Registers mapping */
	/* TODO: block userspace mapping of io register */
1072 1073
	rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
	rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1074 1075 1076 1077 1078 1079 1080
	rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
	if (rdev->rmmio == NULL) {
		return -ENOMEM;
	}
	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
	DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);

1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091
	/* io port mapping */
	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
		if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
			rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
			rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
			break;
		}
	}
	if (rdev->rio_mem == NULL)
		DRM_ERROR("Unable to find PCI I/O BAR\n");

1092
	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
1093 1094 1095
	/* this will fail for cards that aren't VGA class devices, just
	 * ignore it */
	vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1096
	vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops);
1097

1098
	r = radeon_init(rdev);
1099
	if (r)
1100 1101
		return r;

1102 1103 1104 1105
	r = radeon_ib_ring_tests(rdev);
	if (r)
		DRM_ERROR("ib ring test failed (%d).\n", r);

1106 1107 1108 1109
	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
		/* Acceleration not working on AGP card try again
		 * with fallback to PCI or PCIE GART
		 */
1110
		radeon_asic_reset(rdev);
1111 1112 1113
		radeon_fini(rdev);
		radeon_agp_disable(rdev);
		r = radeon_init(rdev);
1114 1115
		if (r)
			return r;
1116
	}
1117
	if ((radeon_testing & 1)) {
1118 1119
		radeon_test_moves(rdev);
	}
1120 1121 1122
	if ((radeon_testing & 2)) {
		radeon_test_syncing(rdev);
	}
1123
	if (radeon_benchmarking) {
1124
		radeon_benchmark(rdev, radeon_benchmarking);
1125
	}
1126
	return 0;
1127 1128
}

1129 1130
static void radeon_debugfs_remove_files(struct radeon_device *rdev);

1131 1132 1133 1134 1135 1136 1137 1138
/**
 * radeon_device_fini - tear down the driver
 *
 * @rdev: radeon_device pointer
 *
 * Tear down the driver info (all asics).
 * Called at driver shutdown.
 */
1139 1140 1141 1142
void radeon_device_fini(struct radeon_device *rdev)
{
	DRM_INFO("radeon: finishing device.\n");
	rdev->shutdown = true;
1143 1144
	/* evict vram memory */
	radeon_bo_evict_vram(rdev);
1145
	radeon_fini(rdev);
1146
	vga_switcheroo_unregister_client(rdev->pdev);
1147
	vga_client_register(rdev->pdev, NULL, NULL, NULL);
1148 1149
	if (rdev->rio_mem)
		pci_iounmap(rdev->pdev, rdev->rio_mem);
1150
	rdev->rio_mem = NULL;
1151 1152
	iounmap(rdev->rmmio);
	rdev->rmmio = NULL;
1153
	radeon_debugfs_remove_files(rdev);
1154 1155 1156 1157 1158 1159
}


/*
 * Suspend & resume.
 */
1160 1161 1162 1163 1164 1165 1166 1167 1168 1169
/**
 * radeon_suspend_kms - initiate device suspend
 *
 * @pdev: drm dev pointer
 * @state: suspend state
 *
 * Puts the hw in the suspend state (all asics).
 * Returns 0 for success or an error on failure.
 * Called at driver suspend.
 */
1170 1171
int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
{
1172
	struct radeon_device *rdev;
1173
	struct drm_crtc *crtc;
1174
	struct drm_connector *connector;
1175
	int i, r;
1176

1177
	if (dev == NULL || dev->dev_private == NULL) {
1178 1179 1180 1181 1182
		return -ENODEV;
	}
	if (state.event == PM_EVENT_PRETHAW) {
		return 0;
	}
1183 1184
	rdev = dev->dev_private;

1185
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1186
		return 0;
1187

1188 1189
	drm_kms_helper_poll_disable(dev);

1190 1191 1192 1193 1194
	/* turn off display hw */
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
	}

1195 1196 1197
	/* unpin the front buffers */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
1198
		struct radeon_bo *robj;
1199 1200 1201 1202

		if (rfb == NULL || rfb->obj == NULL) {
			continue;
		}
1203
		robj = gem_to_radeon_bo(rfb->obj);
1204 1205
		/* don't unpin kernel fb objects */
		if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1206
			r = radeon_bo_reserve(robj, false);
1207
			if (r == 0) {
1208 1209 1210
				radeon_bo_unpin(robj);
				radeon_bo_unreserve(robj);
			}
1211 1212 1213
		}
	}
	/* evict vram memory */
1214
	radeon_bo_evict_vram(rdev);
1215 1216

	mutex_lock(&rdev->ring_lock);
1217
	/* wait for gpu to finish processing current batch */
1218
	for (i = 0; i < RADEON_NUM_RINGS; i++)
1219 1220
		radeon_fence_wait_empty_locked(rdev, i);
	mutex_unlock(&rdev->ring_lock);
1221

1222 1223
	radeon_save_bios_scratch_regs(rdev);

1224
	radeon_pm_suspend(rdev);
1225
	radeon_suspend(rdev);
A
Alex Deucher 已提交
1226
	radeon_hpd_fini(rdev);
1227
	/* evict remaining vram memory */
1228
	radeon_bo_evict_vram(rdev);
1229

1230 1231
	radeon_agp_suspend(rdev);

1232 1233 1234 1235 1236 1237
	pci_save_state(dev->pdev);
	if (state.event == PM_EVENT_SUSPEND) {
		/* Shut down the device */
		pci_disable_device(dev->pdev);
		pci_set_power_state(dev->pdev, PCI_D3hot);
	}
1238
	console_lock();
1239
	radeon_fbdev_set_suspend(rdev, 1);
1240
	console_unlock();
1241 1242 1243
	return 0;
}

1244 1245 1246 1247 1248 1249 1250 1251 1252
/**
 * radeon_resume_kms - initiate device resume
 *
 * @pdev: drm dev pointer
 *
 * Bring the hw back to operating state (all asics).
 * Returns 0 for success or an error on failure.
 * Called at driver resume.
 */
1253 1254
int radeon_resume_kms(struct drm_device *dev)
{
1255
	struct drm_connector *connector;
1256
	struct radeon_device *rdev = dev->dev_private;
1257
	int r;
1258

1259
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1260 1261
		return 0;

1262
	console_lock();
1263 1264 1265
	pci_set_power_state(dev->pdev, PCI_D0);
	pci_restore_state(dev->pdev);
	if (pci_enable_device(dev->pdev)) {
1266
		console_unlock();
1267 1268
		return -1;
	}
1269 1270
	/* resume AGP if in use */
	radeon_agp_resume(rdev);
1271
	radeon_resume(rdev);
1272 1273 1274 1275 1276

	r = radeon_ib_ring_tests(rdev);
	if (r)
		DRM_ERROR("ib ring test failed (%d).\n", r);

1277
	radeon_pm_resume(rdev);
1278
	radeon_restore_bios_scratch_regs(rdev);
1279

1280
	radeon_fbdev_set_suspend(rdev, 0);
1281
	console_unlock();
1282

1283 1284
	/* init dig PHYs, disp eng pll */
	if (rdev->is_atom_bios) {
1285
		radeon_atom_encoder_init(rdev);
1286
		radeon_atom_disp_eng_pll_init(rdev);
1287
	}
A
Alex Deucher 已提交
1288 1289
	/* reset hpd state */
	radeon_hpd_init(rdev);
1290 1291
	/* blat the mode back in */
	drm_helper_resume_force_mode(dev);
1292 1293 1294 1295
	/* turn on display hw */
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
	}
1296 1297

	drm_kms_helper_poll_enable(dev);
1298 1299 1300
	return 0;
}

1301 1302 1303 1304 1305 1306 1307 1308
/**
 * radeon_gpu_reset - reset the asic
 *
 * @rdev: radeon device pointer
 *
 * Attempt the reset the GPU if it has hung (all asics).
 * Returns 0 for success or an error on failure.
 */
1309 1310
int radeon_gpu_reset(struct radeon_device *rdev)
{
1311 1312 1313 1314 1315 1316
	unsigned ring_sizes[RADEON_NUM_RINGS];
	uint32_t *ring_data[RADEON_NUM_RINGS];

	bool saved = false;

	int i, r;
1317
	int resched;
1318

1319
	down_write(&rdev->exclusive_lock);
1320
	radeon_save_bios_scratch_regs(rdev);
1321 1322
	/* block TTM */
	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1323 1324
	radeon_suspend(rdev);

1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335
	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
		ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
						   &ring_data[i]);
		if (ring_sizes[i]) {
			saved = true;
			dev_info(rdev->dev, "Saved %d dwords of commands "
				 "on ring %d.\n", ring_sizes[i], i);
		}
	}

retry:
1336 1337
	r = radeon_asic_reset(rdev);
	if (!r) {
1338
		dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1339
		radeon_resume(rdev);
1340
	}
1341

1342 1343
	radeon_restore_bios_scratch_regs(rdev);
	drm_helper_resume_force_mode(rdev->ddev);
1344

1345 1346 1347 1348
	if (!r) {
		for (i = 0; i < RADEON_NUM_RINGS; ++i) {
			radeon_ring_restore(rdev, &rdev->ring[i],
					    ring_sizes[i], ring_data[i]);
1349 1350
			ring_sizes[i] = 0;
			ring_data[i] = NULL;
1351 1352 1353 1354 1355 1356
		}

		r = radeon_ib_ring_tests(rdev);
		if (r) {
			dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
			if (saved) {
1357
				saved = false;
1358 1359 1360 1361 1362 1363 1364 1365
				radeon_suspend(rdev);
				goto retry;
			}
		}
	} else {
		for (i = 0; i < RADEON_NUM_RINGS; ++i) {
			kfree(ring_data[i]);
		}
1366
	}
1367

1368
	ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1369 1370 1371 1372 1373
	if (r) {
		/* bad news, how to tell it to userspace ? */
		dev_info(rdev->dev, "GPU reset failed\n");
	}

1374
	up_write(&rdev->exclusive_lock);
1375 1376 1377
	return r;
}

1378 1379 1380 1381 1382 1383 1384 1385 1386 1387

/*
 * Debugfs
 */
int radeon_debugfs_add_files(struct radeon_device *rdev,
			     struct drm_info_list *files,
			     unsigned nfiles)
{
	unsigned i;

1388 1389
	for (i = 0; i < rdev->debugfs_count; i++) {
		if (rdev->debugfs[i].files == files) {
1390 1391 1392 1393
			/* Already registered */
			return 0;
		}
	}
1394

1395
	i = rdev->debugfs_count + 1;
1396 1397 1398 1399
	if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
		DRM_ERROR("Reached maximum number of debugfs components.\n");
		DRM_ERROR("Report so we increase "
		          "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1400 1401
		return -EINVAL;
	}
1402 1403 1404
	rdev->debugfs[rdev->debugfs_count].files = files;
	rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
	rdev->debugfs_count = i;
1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415
#if defined(CONFIG_DEBUG_FS)
	drm_debugfs_create_files(files, nfiles,
				 rdev->ddev->control->debugfs_root,
				 rdev->ddev->control);
	drm_debugfs_create_files(files, nfiles,
				 rdev->ddev->primary->debugfs_root,
				 rdev->ddev->primary);
#endif
	return 0;
}

1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431
static void radeon_debugfs_remove_files(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	unsigned i;

	for (i = 0; i < rdev->debugfs_count; i++) {
		drm_debugfs_remove_files(rdev->debugfs[i].files,
					 rdev->debugfs[i].num_files,
					 rdev->ddev->control);
		drm_debugfs_remove_files(rdev->debugfs[i].files,
					 rdev->debugfs[i].num_files,
					 rdev->ddev->primary);
	}
#endif
}

1432 1433 1434 1435 1436 1437 1438 1439 1440 1441
#if defined(CONFIG_DEBUG_FS)
int radeon_debugfs_init(struct drm_minor *minor)
{
	return 0;
}

void radeon_debugfs_cleanup(struct drm_minor *minor)
{
}
#endif