setup-bus.c 43.6 KB
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/*
 *	drivers/pci/setup-bus.c
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Support routines for initializing a PCI subsystem.
 */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     PCI-PCI bridges cleanup, sorted resource allocation.
 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Converted to allocation in 3 passes, which gives
 *	     tighter packing. Prefetchable range support.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
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#include <asm-generic/pci-bridge.h>
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#include "pci.h"
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unsigned int pci_flags;
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struct pci_dev_resource {
	struct list_head list;
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	struct resource *res;
	struct pci_dev *dev;
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	resource_size_t start;
	resource_size_t end;
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	resource_size_t add_size;
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	resource_size_t min_align;
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	unsigned long flags;
};

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static void free_list(struct list_head *head)
{
	struct pci_dev_resource *dev_res, *tmp;

	list_for_each_entry_safe(dev_res, tmp, head, list) {
		list_del(&dev_res->list);
		kfree(dev_res);
	}
}
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/**
 * add_to_list() - add a new resource tracker to the list
 * @head:	Head of the list
 * @dev:	device corresponding to which the resource
 *		belongs
 * @res:	The resource to be tracked
 * @add_size:	additional size to be optionally added
 *              to the resource
 */
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static int add_to_list(struct list_head *head,
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		 struct pci_dev *dev, struct resource *res,
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		 resource_size_t add_size, resource_size_t min_align)
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{
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	struct pci_dev_resource *tmp;
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	tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
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	if (!tmp) {
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		pr_warning("add_to_list: kmalloc() failed!\n");
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		return -ENOMEM;
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	}

	tmp->res = res;
	tmp->dev = dev;
	tmp->start = res->start;
	tmp->end = res->end;
	tmp->flags = res->flags;
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	tmp->add_size = add_size;
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	tmp->min_align = min_align;
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	list_add(&tmp->list, head);
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	return 0;
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}

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static void remove_from_list(struct list_head *head,
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				 struct resource *res)
{
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	struct pci_dev_resource *dev_res, *tmp;
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	list_for_each_entry_safe(dev_res, tmp, head, list) {
		if (dev_res->res == res) {
			list_del(&dev_res->list);
			kfree(dev_res);
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			break;
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		}
	}
}

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static resource_size_t get_res_add_size(struct list_head *head,
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					struct resource *res)
{
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	struct pci_dev_resource *dev_res;
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	list_for_each_entry(dev_res, head, list) {
		if (dev_res->res == res) {
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			int idx = res - &dev_res->dev->resource[0];

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			dev_printk(KERN_DEBUG, &dev_res->dev->dev,
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				 "res[%d]=%pR get_res_add_size add_size %llx\n",
				 idx, dev_res->res,
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				 (unsigned long long)dev_res->add_size);
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			return dev_res->add_size;
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		}
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	}
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	return 0;
}

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/* Sort resources by alignment */
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static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
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{
	int i;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		struct resource *r;
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		struct pci_dev_resource *dev_res, *tmp;
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		resource_size_t r_align;
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		struct list_head *n;
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		r = &dev->resource[i];

		if (r->flags & IORESOURCE_PCI_FIXED)
			continue;

		if (!(r->flags) || r->parent)
			continue;

		r_align = pci_resource_alignment(dev, r);
		if (!r_align) {
			dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
				 i, r);
			continue;
		}

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		tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
		if (!tmp)
			panic("pdev_sort_resources(): "
			      "kmalloc() failed!\n");
		tmp->res = r;
		tmp->dev = dev;

		/* fallback is smallest one or list is empty*/
		n = head;
		list_for_each_entry(dev_res, head, list) {
			resource_size_t align;

			align = pci_resource_alignment(dev_res->dev,
							 dev_res->res);
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			if (r_align > align) {
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				n = &dev_res->list;
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				break;
			}
		}
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		/* Insert it just before n*/
		list_add_tail(&tmp->list, n);
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	}
}

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static void __dev_sort_resources(struct pci_dev *dev,
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				 struct list_head *head)
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{
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	u16 class = dev->class >> 8;
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	/* Don't touch classless devices or host bridges or ioapics.  */
	if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
		return;
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	/* Don't touch ioapic devices already enabled by firmware */
	if (class == PCI_CLASS_SYSTEM_PIC) {
		u16 command;
		pci_read_config_word(dev, PCI_COMMAND, &command);
		if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
			return;
	}
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	pdev_sort_resources(dev, head);
}
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static inline void reset_resource(struct resource *res)
{
	res->start = 0;
	res->end = 0;
	res->flags = 0;
}

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/**
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 * reassign_resources_sorted() - satisfy any additional resource requests
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 *
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 * @realloc_head : head of the list tracking requests requiring additional
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 *             resources
 * @head     : head of the list tracking requests with allocated
 *             resources
 *
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 * Walk through each element of the realloc_head and try to procure
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 * additional resources for the element, provided the element
 * is in the head list.
 */
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static void reassign_resources_sorted(struct list_head *realloc_head,
		struct list_head *head)
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{
	struct resource *res;
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	struct pci_dev_resource *add_res, *tmp;
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	struct pci_dev_resource *dev_res;
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	resource_size_t add_size;
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	int idx;
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	list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
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		bool found_match = false;

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		res = add_res->res;
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		/* skip resource that has been reset */
		if (!res->flags)
			goto out;

		/* skip this resource if not found in head list */
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		list_for_each_entry(dev_res, head, list) {
			if (dev_res->res == res) {
				found_match = true;
				break;
			}
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		}
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		if (!found_match)/* just skip */
			continue;
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		idx = res - &add_res->dev->resource[0];
		add_size = add_res->add_size;
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		if (!resource_size(res)) {
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			res->start = add_res->start;
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			res->end = res->start + add_size - 1;
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			if (pci_assign_resource(add_res->dev, idx))
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				reset_resource(res);
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		} else {
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			resource_size_t align = add_res->min_align;
			res->flags |= add_res->flags &
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				 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
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			if (pci_reassign_resource(add_res->dev, idx,
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						  add_size, align))
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				dev_printk(KERN_DEBUG, &add_res->dev->dev,
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					   "failed to add %llx res[%d]=%pR\n",
					   (unsigned long long)add_size,
					   idx, res);
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		}
out:
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		list_del(&add_res->list);
		kfree(add_res);
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	}
}

/**
 * assign_requested_resources_sorted() - satisfy resource requests
 *
 * @head : head of the list tracking requests for resources
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 * @fail_head : head of the list tracking requests that could
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 *		not be allocated
 *
 * Satisfy resource requests of each element in the list. Add
 * requests that could not satisfied to the failed_list.
 */
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static void assign_requested_resources_sorted(struct list_head *head,
				 struct list_head *fail_head)
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{
	struct resource *res;
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	struct pci_dev_resource *dev_res;
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	int idx;
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	list_for_each_entry(dev_res, head, list) {
		res = dev_res->res;
		idx = res - &dev_res->dev->resource[0];
		if (resource_size(res) &&
		    pci_assign_resource(dev_res->dev, idx)) {
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			if (fail_head) {
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				/*
				 * if the failed res is for ROM BAR, and it will
				 * be enabled later, don't add it to the list
				 */
				if (!((idx == PCI_ROM_RESOURCE) &&
				      (!(res->flags & IORESOURCE_ROM_ENABLE))))
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					add_to_list(fail_head,
						    dev_res->dev, res,
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						    0 /* don't care */,
						    0 /* don't care */);
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			}
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			reset_resource(res);
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		}
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	}
}

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static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
{
	struct pci_dev_resource *fail_res;
	unsigned long mask = 0;

	/* check failed type */
	list_for_each_entry(fail_res, fail_head, list)
		mask |= fail_res->flags;

	/*
	 * one pref failed resource will set IORESOURCE_MEM,
	 * as we can allocate pref in non-pref range.
	 * Will release all assigned non-pref sibling resources
	 * according to that bit.
	 */
	return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
}

static bool pci_need_to_release(unsigned long mask, struct resource *res)
{
	if (res->flags & IORESOURCE_IO)
		return !!(mask & IORESOURCE_IO);

	/* check pref at first */
	if (res->flags & IORESOURCE_PREFETCH) {
		if (mask & IORESOURCE_PREFETCH)
			return true;
		/* count pref if its parent is non-pref */
		else if ((mask & IORESOURCE_MEM) &&
			 !(res->parent->flags & IORESOURCE_PREFETCH))
			return true;
		else
			return false;
	}

	if (res->flags & IORESOURCE_MEM)
		return !!(mask & IORESOURCE_MEM);

	return false;	/* should not get here */
}

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static void __assign_resources_sorted(struct list_head *head,
				 struct list_head *realloc_head,
				 struct list_head *fail_head)
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{
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	/*
	 * Should not assign requested resources at first.
	 *   they could be adjacent, so later reassign can not reallocate
	 *   them one by one in parent resource window.
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	 * Try to assign requested + add_size at beginning
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	 *  if could do that, could get out early.
	 *  if could not do that, we still try to assign requested at first,
	 *    then try to reassign add_size for some resources.
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	 *
	 * Separate three resource type checking if we need to release
	 * assigned resource after requested + add_size try.
	 *	1. if there is io port assign fail, will release assigned
	 *	   io port.
	 *	2. if there is pref mmio assign fail, release assigned
	 *	   pref mmio.
	 *	   if assigned pref mmio's parent is non-pref mmio and there
	 *	   is non-pref mmio assign fail, will release that assigned
	 *	   pref mmio.
	 *	3. if there is non-pref mmio assign fail or pref mmio
	 *	   assigned fail, will release assigned non-pref mmio.
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	 */
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	LIST_HEAD(save_head);
	LIST_HEAD(local_fail_head);
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	struct pci_dev_resource *save_res;
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	struct pci_dev_resource *dev_res, *tmp_res;
	unsigned long fail_type;
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	/* Check if optional add_size is there */
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	if (!realloc_head || list_empty(realloc_head))
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		goto requested_and_reassign;

	/* Save original start, end, flags etc at first */
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	list_for_each_entry(dev_res, head, list) {
		if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
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			free_list(&save_head);
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			goto requested_and_reassign;
		}
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	}
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	/* Update res in head list with add_size in realloc_head list */
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	list_for_each_entry(dev_res, head, list)
		dev_res->res->end += get_res_add_size(realloc_head,
							dev_res->res);
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	/* Try updated head list with add_size added */
	assign_requested_resources_sorted(head, &local_fail_head);

	/* all assigned with add_size ? */
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	if (list_empty(&local_fail_head)) {
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		/* Remove head list from realloc_head list */
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		list_for_each_entry(dev_res, head, list)
			remove_from_list(realloc_head, dev_res->res);
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		free_list(&save_head);
		free_list(head);
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		return;
	}

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	/* check failed type */
	fail_type = pci_fail_res_type_mask(&local_fail_head);
	/* remove not need to be released assigned res from head list etc */
	list_for_each_entry_safe(dev_res, tmp_res, head, list)
		if (dev_res->res->parent &&
		    !pci_need_to_release(fail_type, dev_res->res)) {
			/* remove it from realloc_head list */
			remove_from_list(realloc_head, dev_res->res);
			remove_from_list(&save_head, dev_res->res);
			list_del(&dev_res->list);
			kfree(dev_res);
		}

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	free_list(&local_fail_head);
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	/* Release assigned resource */
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	list_for_each_entry(dev_res, head, list)
		if (dev_res->res->parent)
			release_resource(dev_res->res);
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	/* Restore start/end/flags from saved list */
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	list_for_each_entry(save_res, &save_head, list) {
		struct resource *res = save_res->res;
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		res->start = save_res->start;
		res->end = save_res->end;
		res->flags = save_res->flags;
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	}
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	free_list(&save_head);
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requested_and_reassign:
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	/* Satisfy the must-have resource requests */
	assign_requested_resources_sorted(head, fail_head);

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	/* Try to satisfy any additional optional resource
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		requests */
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	if (realloc_head)
		reassign_resources_sorted(realloc_head, head);
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	free_list(head);
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}

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static void pdev_assign_resources_sorted(struct pci_dev *dev,
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				 struct list_head *add_head,
				 struct list_head *fail_head)
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{
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	LIST_HEAD(head);
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	__dev_sort_resources(dev, &head);
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	__assign_resources_sorted(&head, add_head, fail_head);
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}

static void pbus_assign_resources_sorted(const struct pci_bus *bus,
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					 struct list_head *realloc_head,
					 struct list_head *fail_head)
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{
	struct pci_dev *dev;
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	LIST_HEAD(head);
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	list_for_each_entry(dev, &bus->devices, bus_list)
		__dev_sort_resources(dev, &head);

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	__assign_resources_sorted(&head, realloc_head, fail_head);
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}

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void pci_setup_cardbus(struct pci_bus *bus)
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{
	struct pci_dev *bridge = bus->self;
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	struct resource *res;
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	struct pci_bus_region region;

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	dev_info(&bridge->dev, "CardBus bridge to %pR\n",
		 &bus->busn_res);
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	res = bus->resource[0];
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	pcibios_resource_to_bus(bridge->bus, &region, res);
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	if (res->flags & IORESOURCE_IO) {
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		/*
		 * The IO resource is allocated a range twice as large as it
		 * would normally need.  This allows us to set both IO regs.
		 */
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		dev_info(&bridge->dev, "  bridge window %pR\n", res);
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		pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
					region.end);
	}

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	res = bus->resource[1];
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	pcibios_resource_to_bus(bridge->bus, &region, res);
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	if (res->flags & IORESOURCE_IO) {
		dev_info(&bridge->dev, "  bridge window %pR\n", res);
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		pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
					region.end);
	}

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	res = bus->resource[2];
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	pcibios_resource_to_bus(bridge->bus, &region, res);
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	if (res->flags & IORESOURCE_MEM) {
		dev_info(&bridge->dev, "  bridge window %pR\n", res);
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		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
					region.end);
	}

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	res = bus->resource[3];
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	pcibios_resource_to_bus(bridge->bus, &region, res);
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	if (res->flags & IORESOURCE_MEM) {
		dev_info(&bridge->dev, "  bridge window %pR\n", res);
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		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
					region.end);
	}
}
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EXPORT_SYMBOL(pci_setup_cardbus);
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/* Initialize bridges with base/limit values we have collected.
   PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
   requires that if there is no I/O ports or memory behind the
   bridge, corresponding range must be turned off by writing base
   value greater than limit to the bridge's base/limit registers.

   Note: care must be taken when updating I/O base/limit registers
   of bridges which support 32-bit I/O. This update requires two
   config space writes, so it's quite possible that an I/O window of
   the bridge will have some undesirable address (e.g. 0) after the
   first write. Ditto 64-bit prefetchable MMIO.  */
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static void pci_setup_bridge_io(struct pci_bus *bus)
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{
	struct pci_dev *bridge = bus->self;
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	struct resource *res;
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	struct pci_bus_region region;
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	unsigned long io_mask;
	u8 io_base_lo, io_limit_lo;
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	u16 l;
	u32 io_upper16;
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	io_mask = PCI_IO_RANGE_MASK;
	if (bridge->io_window_1k)
		io_mask = PCI_IO_1K_RANGE_MASK;

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	/* Set up the top and bottom of the PCI I/O segment for this bus. */
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	res = bus->resource[0];
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	pcibios_resource_to_bus(bridge->bus, &region, res);
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	if (res->flags & IORESOURCE_IO) {
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		pci_read_config_word(bridge, PCI_IO_BASE, &l);
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		io_base_lo = (region.start >> 8) & io_mask;
		io_limit_lo = (region.end >> 8) & io_mask;
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		l = ((u16) io_limit_lo << 8) | io_base_lo;
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		/* Set up upper 16 bits of I/O base/limit. */
		io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
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		dev_info(&bridge->dev, "  bridge window %pR\n", res);
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	} else {
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		/* Clear upper 16 bits of I/O base/limit. */
		io_upper16 = 0;
		l = 0x00f0;
	}
	/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
	/* Update lower 16 bits of I/O base/limit. */
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	pci_write_config_word(bridge, PCI_IO_BASE, l);
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	/* Update upper 16 bits of I/O base/limit. */
	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
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}

static void pci_setup_bridge_mmio(struct pci_bus *bus)
{
	struct pci_dev *bridge = bus->self;
	struct resource *res;
	struct pci_bus_region region;
	u32 l;
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	/* Set up the top and bottom of the PCI Memory segment for this bus. */
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	res = bus->resource[1];
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	pcibios_resource_to_bus(bridge->bus, &region, res);
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	if (res->flags & IORESOURCE_MEM) {
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		l = (region.start >> 16) & 0xfff0;
		l |= region.end & 0xfff00000;
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		dev_info(&bridge->dev, "  bridge window %pR\n", res);
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	} else {
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		l = 0x0000fff0;
	}
	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
590 591 592 593 594 595 596 597
}

static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
{
	struct pci_dev *bridge = bus->self;
	struct resource *res;
	struct pci_bus_region region;
	u32 l, bu, lu;
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	/* Clear out the upper 32 bits of PREF limit.
	   If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
	   disables PREF range, which is ok. */
	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);

	/* Set up PREF base/limit. */
605
	bu = lu = 0;
606
	res = bus->resource[2];
607
	pcibios_resource_to_bus(bridge->bus, &region, res);
608
	if (res->flags & IORESOURCE_PREFETCH) {
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		l = (region.start >> 16) & 0xfff0;
		l |= region.end & 0xfff00000;
611
		if (res->flags & IORESOURCE_MEM_64) {
612 613 614
			bu = upper_32_bits(region.start);
			lu = upper_32_bits(region.end);
		}
615
		dev_info(&bridge->dev, "  bridge window %pR\n", res);
616
	} else {
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		l = 0x0000fff0;
	}
	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);

621 622 623
	/* Set the upper 32 bits of PREF base & limit. */
	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
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}

static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
{
	struct pci_dev *bridge = bus->self;

630 631
	dev_info(&bridge->dev, "PCI bridge to %pR\n",
		 &bus->busn_res);
632 633 634 635 636 637 638 639 640

	if (type & IORESOURCE_IO)
		pci_setup_bridge_io(bus);

	if (type & IORESOURCE_MEM)
		pci_setup_bridge_mmio(bus);

	if (type & IORESOURCE_PREFETCH)
		pci_setup_bridge_mmio_pref(bus);
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	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
}

645
void pci_setup_bridge(struct pci_bus *bus)
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{
	unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
				  IORESOURCE_PREFETCH;

	__pci_setup_bridge(bus, type);
}

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/* Check whether the bridge supports optional I/O and
   prefetchable memory ranges. If not, the respective
   base/limit registers must be read-only and read as 0. */
656
static void pci_bridge_check_ranges(struct pci_bus *bus)
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{
	u16 io;
	u32 pmem;
	struct pci_dev *bridge = bus->self;
	struct resource *b_res;

	b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
	b_res[1].flags |= IORESOURCE_MEM;

	pci_read_config_word(bridge, PCI_IO_BASE, &io);
	if (!io) {
668
		pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
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		pci_read_config_word(bridge, PCI_IO_BASE, &io);
670 671 672
		pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
	}
	if (io)
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		b_res[0].flags |= IORESOURCE_IO;
674

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	/*  DECchip 21050 pass 2 errata: the bridge may miss an address
	    disconnect boundary by one PCI data phase.
	    Workaround: do not use prefetching on this device. */
	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
		return;
680

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	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
	if (!pmem) {
		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
684
					       0xffe0fff0);
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		pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
	}
688
	if (pmem) {
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		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
690 691
		if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
		    PCI_PREF_RANGE_TYPE_64) {
692
			b_res[2].flags |= IORESOURCE_MEM_64;
693 694
			b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
		}
695 696 697 698 699 700 701 702 703 704 705 706 707 708 709
	}

	/* double check if bridge does support 64 bit pref */
	if (b_res[2].flags & IORESOURCE_MEM_64) {
		u32 mem_base_hi, tmp;
		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
					 &mem_base_hi);
		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
					       0xffffffff);
		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
		if (!tmp)
			b_res[2].flags &= ~IORESOURCE_MEM_64;
		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
				       mem_base_hi);
	}
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}

/* Helper function for sizing routines: find first available
   bus resource of a given type. Note: we intentionally skip
   the bus resources which have already been assigned (that is,
   have non-NULL parent resource). */
716
static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
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{
	int i;
	struct resource *r;
	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
				  IORESOURCE_PREFETCH;

723
	pci_bus_for_each_resource(bus, r, i) {
724 725
		if (r == &ioport_resource || r == &iomem_resource)
			continue;
726 727
		if (r && (r->flags & type_mask) == type && !r->parent)
			return r;
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	}
	return NULL;
}

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static resource_size_t calculate_iosize(resource_size_t size,
		resource_size_t min_size,
		resource_size_t size1,
		resource_size_t old_size,
		resource_size_t align)
{
	if (size < min_size)
		size = min_size;
	if (old_size == 1 )
		old_size = 0;
	/* To be fixed in 2.5: we should have sort of HAVE_ISA
	   flag in the struct pci_bus. */
#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
	size = (size & 0xff) + ((size & ~0xffUL) << 2);
#endif
	size = ALIGN(size + size1, align);
	if (size < old_size)
		size = old_size;
	return size;
}

static resource_size_t calculate_memsize(resource_size_t size,
		resource_size_t min_size,
		resource_size_t size1,
		resource_size_t old_size,
		resource_size_t align)
{
	if (size < min_size)
		size = min_size;
	if (old_size == 1 )
		old_size = 0;
	if (size < old_size)
		size = old_size;
	size = ALIGN(size + size1, align);
	return size;
}

769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800
resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
						unsigned long type)
{
	return 1;
}

#define PCI_P2P_DEFAULT_MEM_ALIGN	0x100000	/* 1MiB */
#define PCI_P2P_DEFAULT_IO_ALIGN	0x1000		/* 4KiB */
#define PCI_P2P_DEFAULT_IO_ALIGN_1K	0x400		/* 1KiB */

static resource_size_t window_alignment(struct pci_bus *bus,
					unsigned long type)
{
	resource_size_t align = 1, arch_align;

	if (type & IORESOURCE_MEM)
		align = PCI_P2P_DEFAULT_MEM_ALIGN;
	else if (type & IORESOURCE_IO) {
		/*
		 * Per spec, I/O windows are 4K-aligned, but some
		 * bridges have an extension to support 1K alignment.
		 */
		if (bus->self->io_window_1k)
			align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
		else
			align = PCI_P2P_DEFAULT_IO_ALIGN;
	}

	arch_align = pcibios_window_alignment(bus, type);
	return max(align, arch_align);
}

801 802 803 804 805 806
/**
 * pbus_size_io() - size the io window of a given bus
 *
 * @bus : the bus
 * @min_size : the minimum io window that must to be allocated
 * @add_size : additional optional io window
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 * @realloc_head : track the additional io window on this list
808 809
 *
 * Sizing the IO windows of the PCI-PCI bridge is trivial,
810
 * since these windows have 1K or 4K granularity and the IO ranges
811 812 813 814
 * of non-bridge PCI devices are limited to 256 bytes.
 * We must be careful with the ISA aliasing though.
 */
static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
815
		resource_size_t add_size, struct list_head *realloc_head)
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{
	struct pci_dev *dev;
	struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
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	resource_size_t size = 0, size0 = 0, size1 = 0;
820
	resource_size_t children_add_size = 0;
821
	resource_size_t min_align, align;
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	if (!b_res)
824
		return;
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826
	min_align = window_alignment(bus, IORESOURCE_IO);
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	list_for_each_entry(dev, &bus->devices, bus_list) {
		int i;

		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			struct resource *r = &dev->resource[i];
			unsigned long r_size;

			if (r->parent || !(r->flags & IORESOURCE_IO))
				continue;
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			r_size = resource_size(r);
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			if (r_size < 0x400)
				/* Might be re-aligned for ISA */
				size += r_size;
			else
				size1 += r_size;
843

844 845 846 847
			align = pci_resource_alignment(dev, r);
			if (align > min_align)
				min_align = align;

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			if (realloc_head)
				children_add_size += get_res_add_size(realloc_head, r);
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		}
	}
852

853
	size0 = calculate_iosize(size, min_size, size1,
854
			resource_size(b_res), min_align);
855 856
	if (children_add_size > add_size)
		add_size = children_add_size;
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	size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
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		calculate_iosize(size, min_size, add_size + size1,
859
			resource_size(b_res), min_align);
860
	if (!size0 && !size1) {
861 862
		if (b_res->start || b_res->end)
			dev_info(&bus->self->dev, "disabling bridge window "
863 864
				 "%pR to %pR (unused)\n", b_res,
				 &bus->busn_res);
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		b_res->flags = 0;
		return;
	}
868 869

	b_res->start = min_align;
870
	b_res->end = b_res->start + size0 - 1;
871
	b_res->flags |= IORESOURCE_STARTALIGN;
872
	if (size1 > size0 && realloc_head) {
873 874
		add_to_list(realloc_head, bus->self, b_res, size1-size0,
			    min_align);
875
		dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
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				 "%pR to %pR add_size %llx\n", b_res,
				 &bus->busn_res,
				 (unsigned long long)size1-size0);
879
	}
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}

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static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
						  int max_order)
{
	resource_size_t align = 0;
	resource_size_t min_align = 0;
	int order;

	for (order = 0; order <= max_order; order++) {
		resource_size_t align1 = 1;

		align1 <<= (order + 20);

		if (!align)
			min_align = align1;
		else if (ALIGN(align + min_align, min_align) < align1)
			min_align = align1 >> 1;
		align += aligns[order];
	}

	return min_align;
}

904 905 906 907
/**
 * pbus_size_mem() - size the memory window of a given bus
 *
 * @bus : the bus
908 909
 * @mask: mask the resource flag, then compare it with type
 * @type: the type of free resource from bridge
910 911
 * @min_size : the minimum memory window that must to be allocated
 * @add_size : additional optional memory window
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 * @realloc_head : track the additional memory window on this list
913 914 915 916
 *
 * Calculate the size of the bus and minimal alignment which
 * guarantees that all child resources fit in this size.
 */
917
static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
918 919
			 unsigned long type, resource_size_t min_size,
			resource_size_t add_size,
920
			struct list_head *realloc_head)
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{
	struct pci_dev *dev;
923
	resource_size_t min_align, align, size, size0, size1;
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	resource_size_t aligns[14];	/* Alignments from 1Mb to 8Gb */
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	int order, max_order;
	struct resource *b_res = find_free_bus_resource(bus, type);
927
	unsigned int mem64_mask = 0;
928
	resource_size_t children_add_size = 0;
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	if (!b_res)
		return 0;

	memset(aligns, 0, sizeof(aligns));
	max_order = 0;
	size = 0;

937 938 939
	mem64_mask = b_res->flags & IORESOURCE_MEM_64;
	b_res->flags &= ~IORESOURCE_MEM_64;

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	list_for_each_entry(dev, &bus->devices, bus_list) {
		int i;
942

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		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			struct resource *r = &dev->resource[i];
945
			resource_size_t r_size;
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			if (r->parent || (r->flags & mask) != type)
				continue;
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			r_size = resource_size(r);
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#ifdef CONFIG_PCI_IOV
			/* put SRIOV requested res to the optional list */
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			if (realloc_head && i >= PCI_IOV_RESOURCES &&
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					i <= PCI_IOV_RESOURCE_END) {
				r->end = r->start - 1;
955
				add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
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				children_add_size += r_size;
				continue;
			}
#endif
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			/*
			 * aligns[0] is for 1MB (since bridge memory
			 * windows are always at least 1MB aligned), so
			 * keep "order" from being negative for smaller
			 * resources.
			 */
966
			align = pci_resource_alignment(dev, r);
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			order = __ffs(align) - 20;
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			if (order < 0)
				order = 0;
			if (order >= ARRAY_SIZE(aligns)) {
971 972 973
				dev_warn(&dev->dev, "disabling BAR %d: %pR "
					 "(bad alignment %#llx)\n", i, r,
					 (unsigned long long) align);
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				r->flags = 0;
				continue;
			}
			size += r_size;
			/* Exclude ranges with size > align from
			   calculation of the alignment. */
			if (r_size == align)
				aligns[order] += align;
			if (order > max_order)
				max_order = order;
984
			mem64_mask &= r->flags & IORESOURCE_MEM_64;
985

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			if (realloc_head)
				children_add_size += get_res_add_size(realloc_head, r);
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		}
	}
990

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	min_align = calculate_mem_align(aligns, max_order);
992
	min_align = max(min_align, window_alignment(bus, b_res->flags));
993
	size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
994 995
	if (children_add_size > add_size)
		add_size = children_add_size;
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	size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
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		calculate_memsize(size, min_size, add_size,
998
				resource_size(b_res), min_align);
999
	if (!size0 && !size1) {
1000 1001
		if (b_res->start || b_res->end)
			dev_info(&bus->self->dev, "disabling bridge window "
1002 1003
				 "%pR to %pR (unused)\n", b_res,
				 &bus->busn_res);
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		b_res->flags = 0;
		return 1;
	}
	b_res->start = min_align;
1008 1009
	b_res->end = size0 + min_align - 1;
	b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
1010
	if (size1 > size0 && realloc_head) {
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		add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
1012
		dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
1013 1014
				 "%pR to %pR add_size %llx\n", b_res,
				 &bus->busn_res, (unsigned long long)size1-size0);
1015
	}
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	return 1;
}

1019 1020 1021 1022 1023 1024 1025 1026 1027 1028
unsigned long pci_cardbus_resource_alignment(struct resource *res)
{
	if (res->flags & IORESOURCE_IO)
		return pci_cardbus_io_size;
	if (res->flags & IORESOURCE_MEM)
		return pci_cardbus_mem_size;
	return 0;
}

static void pci_bus_size_cardbus(struct pci_bus *bus,
1029
			struct list_head *realloc_head)
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{
	struct pci_dev *bridge = bus->self;
	struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1033
	resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
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	u16 ctrl;

1036 1037
	if (b_res[0].parent)
		goto handle_b_res_1;
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	/*
	 * Reserve some resources for CardBus.  We reserve
	 * a fixed amount of bus space for CardBus bridges.
	 */
1042 1043 1044 1045 1046 1047 1048 1049
	b_res[0].start = pci_cardbus_io_size;
	b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
	b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
	if (realloc_head) {
		b_res[0].end -= pci_cardbus_io_size;
		add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
				pci_cardbus_io_size);
	}
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1051 1052 1053
handle_b_res_1:
	if (b_res[1].parent)
		goto handle_b_res_2;
1054 1055 1056 1057 1058 1059 1060 1061
	b_res[1].start = pci_cardbus_io_size;
	b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
	b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
	if (realloc_head) {
		b_res[1].end -= pci_cardbus_io_size;
		add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
				 pci_cardbus_io_size);
	}
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1063
handle_b_res_2:
1064 1065 1066 1067 1068 1069 1070 1071
	/* MEM1 must not be pref mmio */
	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
		ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	}

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	/*
	 * Check whether prefetchable memory is supported
	 * by this bridge.
	 */
	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
		ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	}

1083 1084
	if (b_res[2].parent)
		goto handle_b_res_3;
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1085 1086 1087 1088 1089 1090
	/*
	 * If we have prefetchable memory support, allocate
	 * two regions.  Otherwise, allocate one region of
	 * twice the size.
	 */
	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104
		b_res[2].start = pci_cardbus_mem_size;
		b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
				  IORESOURCE_STARTALIGN;
		if (realloc_head) {
			b_res[2].end -= pci_cardbus_mem_size;
			add_to_list(realloc_head, bridge, b_res+2,
				 pci_cardbus_mem_size, pci_cardbus_mem_size);
		}

		/* reduce that to half */
		b_res_3_size = pci_cardbus_mem_size;
	}

1105 1106 1107
handle_b_res_3:
	if (b_res[3].parent)
		goto handle_done;
1108 1109 1110 1111 1112 1113 1114 1115
	b_res[3].start = pci_cardbus_mem_size;
	b_res[3].end = b_res[3].start + b_res_3_size - 1;
	b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
	if (realloc_head) {
		b_res[3].end -= b_res_3_size;
		add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
				 pci_cardbus_mem_size);
	}
1116 1117 1118

handle_done:
	;
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1119 1120
}

1121
void __ref __pci_bus_size_bridges(struct pci_bus *bus,
1122
			struct list_head *realloc_head)
L
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1123 1124 1125
{
	struct pci_dev *dev;
	unsigned long mask, prefmask;
1126
	resource_size_t additional_mem_size = 0, additional_io_size = 0;
L
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1127 1128 1129 1130 1131 1132 1133 1134

	list_for_each_entry(dev, &bus->devices, bus_list) {
		struct pci_bus *b = dev->subordinate;
		if (!b)
			continue;

		switch (dev->class >> 8) {
		case PCI_CLASS_BRIDGE_CARDBUS:
R
Ram Pai 已提交
1135
			pci_bus_size_cardbus(b, realloc_head);
L
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1136 1137 1138 1139
			break;

		case PCI_CLASS_BRIDGE_PCI:
		default:
R
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1140
			__pci_bus_size_bridges(b, realloc_head);
L
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1141 1142 1143 1144 1145
			break;
		}
	}

	/* The root bus? */
1146
	if (pci_is_root_bus(bus))
L
Linus Torvalds 已提交
1147 1148 1149 1150 1151 1152 1153 1154 1155
		return;

	switch (bus->self->class >> 8) {
	case PCI_CLASS_BRIDGE_CARDBUS:
		/* don't size cardbuses yet. */
		break;

	case PCI_CLASS_BRIDGE_PCI:
		pci_bridge_check_ranges(bus);
1156
		if (bus->self->is_hotplug_bridge) {
1157 1158
			additional_io_size  = pci_hotplug_io_size;
			additional_mem_size = pci_hotplug_mem_size;
1159
		}
1160 1161 1162
		/*
		 * Follow thru
		 */
L
Linus Torvalds 已提交
1163
	default:
1164 1165
		pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
			     additional_io_size, realloc_head);
L
Linus Torvalds 已提交
1166 1167 1168 1169 1170 1171 1172
		/* If the bridge supports prefetchable range, size it
		   separately. If it doesn't, or its prefetchable window
		   has already been allocated by arch code, try
		   non-prefetchable range for both types of PCI memory
		   resources. */
		mask = IORESOURCE_MEM;
		prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1173 1174 1175
		if (pbus_size_mem(bus, prefmask, prefmask,
				  realloc_head ? 0 : additional_mem_size,
				  additional_mem_size, realloc_head))
L
Linus Torvalds 已提交
1176
			mask = prefmask; /* Success, size non-prefetch only. */
1177
		else
1178
			additional_mem_size += additional_mem_size;
1179 1180 1181
		pbus_size_mem(bus, mask, IORESOURCE_MEM,
				realloc_head ? 0 : additional_mem_size,
				additional_mem_size, realloc_head);
L
Linus Torvalds 已提交
1182 1183 1184
		break;
	}
}
1185 1186 1187 1188 1189

void __ref pci_bus_size_bridges(struct pci_bus *bus)
{
	__pci_bus_size_bridges(bus, NULL);
}
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1190 1191
EXPORT_SYMBOL(pci_bus_size_bridges);

1192 1193 1194
void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
				      struct list_head *realloc_head,
				      struct list_head *fail_head)
L
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1195 1196 1197 1198
{
	struct pci_bus *b;
	struct pci_dev *dev;

R
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1199
	pbus_assign_resources_sorted(bus, realloc_head, fail_head);
L
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1200 1201 1202 1203 1204 1205

	list_for_each_entry(dev, &bus->devices, bus_list) {
		b = dev->subordinate;
		if (!b)
			continue;

R
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		__pci_bus_assign_resources(b, realloc_head, fail_head);
L
Linus Torvalds 已提交
1207 1208 1209

		switch (dev->class >> 8) {
		case PCI_CLASS_BRIDGE_PCI:
1210 1211
			if (!pci_is_enabled(dev))
				pci_setup_bridge(b);
L
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1212 1213 1214 1215 1216 1217 1218
			break;

		case PCI_CLASS_BRIDGE_CARDBUS:
			pci_setup_cardbus(b);
			break;

		default:
1219 1220
			dev_info(&dev->dev, "not setting up bridge for bus "
				 "%04x:%02x\n", pci_domain_nr(b), b->number);
L
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1221 1222 1223 1224
			break;
		}
	}
}
1225 1226 1227

void __ref pci_bus_assign_resources(const struct pci_bus *bus)
{
1228
	__pci_bus_assign_resources(bus, NULL, NULL);
1229
}
L
Linus Torvalds 已提交
1230 1231
EXPORT_SYMBOL(pci_bus_assign_resources);

1232
static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
1233 1234
					 struct list_head *add_head,
					 struct list_head *fail_head)
1235 1236 1237
{
	struct pci_bus *b;

1238 1239
	pdev_assign_resources_sorted((struct pci_dev *)bridge,
					 add_head, fail_head);
1240 1241 1242 1243 1244

	b = bridge->subordinate;
	if (!b)
		return;

1245
	__pci_bus_assign_resources(b, add_head, fail_head);
1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261

	switch (bridge->class >> 8) {
	case PCI_CLASS_BRIDGE_PCI:
		pci_setup_bridge(b);
		break;

	case PCI_CLASS_BRIDGE_CARDBUS:
		pci_setup_cardbus(b);
		break;

	default:
		dev_info(&bridge->dev, "not setting up bridge for bus "
			 "%04x:%02x\n", pci_domain_nr(b), b->number);
		break;
	}
}
1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343
static void pci_bridge_release_resources(struct pci_bus *bus,
					  unsigned long type)
{
	int idx;
	bool changed = false;
	struct pci_dev *dev;
	struct resource *r;
	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
				  IORESOURCE_PREFETCH;

	dev = bus->self;
	for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
	     idx++) {
		r = &dev->resource[idx];
		if ((r->flags & type_mask) != type)
			continue;
		if (!r->parent)
			continue;
		/*
		 * if there are children under that, we should release them
		 *  all
		 */
		release_child_resources(r);
		if (!release_resource(r)) {
			dev_printk(KERN_DEBUG, &dev->dev,
				 "resource %d %pR released\n", idx, r);
			/* keep the old size */
			r->end = resource_size(r) - 1;
			r->start = 0;
			r->flags = 0;
			changed = true;
		}
	}

	if (changed) {
		/* avoiding touch the one without PREF */
		if (type & IORESOURCE_PREFETCH)
			type = IORESOURCE_PREFETCH;
		__pci_setup_bridge(bus, type);
	}
}

enum release_type {
	leaf_only,
	whole_subtree,
};
/*
 * try to release pci bridge resources that is from leaf bridge,
 * so we can allocate big new one later
 */
static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
						   unsigned long type,
						   enum release_type rel_type)
{
	struct pci_dev *dev;
	bool is_leaf_bridge = true;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		struct pci_bus *b = dev->subordinate;
		if (!b)
			continue;

		is_leaf_bridge = false;

		if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
			continue;

		if (rel_type == whole_subtree)
			pci_bus_release_bridge_resources(b, type,
						 whole_subtree);
	}

	if (pci_is_root_bus(bus))
		return;

	if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
		return;

	if ((rel_type == whole_subtree) || is_leaf_bridge)
		pci_bridge_release_resources(bus, type);
}

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1344 1345
static void pci_bus_dump_res(struct pci_bus *bus)
{
1346 1347
	struct resource *res;
	int i;
1348

1349
	pci_bus_for_each_resource(bus, res, i) {
1350
		if (!res || !res->end || !res->flags)
Y
Yinghai Lu 已提交
1351 1352
                        continue;

1353
		dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
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1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373
        }
}

static void pci_bus_dump_resources(struct pci_bus *bus)
{
	struct pci_bus *b;
	struct pci_dev *dev;


	pci_bus_dump_res(bus);

	list_for_each_entry(dev, &bus->devices, bus_list) {
		b = dev->subordinate;
		if (!b)
			continue;

		pci_bus_dump_resources(b);
	}
}

1374
static int pci_bus_get_depth(struct pci_bus *bus)
1375 1376
{
	int depth = 0;
1377
	struct pci_bus *child_bus;
1378

1379
	list_for_each_entry(child_bus, &bus->children, node){
1380 1381
		int ret;

1382
		ret = pci_bus_get_depth(child_bus);
1383 1384 1385 1386 1387 1388 1389
		if (ret + 1 > depth)
			depth = ret + 1;
	}

	return depth;
}

1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404
/*
 * -1: undefined, will auto detect later
 *  0: disabled by user
 *  1: disabled by auto detect
 *  2: enabled by user
 *  3: enabled by auto detect
 */
enum enable_type {
	undefined = -1,
	user_disabled,
	auto_disabled,
	user_enabled,
	auto_enabled,
};

1405
static enum enable_type pci_realloc_enable = undefined;
1406 1407 1408 1409 1410 1411 1412
void __init pci_realloc_get_opt(char *str)
{
	if (!strncmp(str, "off", 3))
		pci_realloc_enable = user_disabled;
	else if (!strncmp(str, "on", 2))
		pci_realloc_enable = user_enabled;
}
1413
static bool pci_realloc_enabled(enum enable_type enable)
1414
{
1415
	return enable >= user_enabled;
1416
}
1417

1418
#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1419
static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1420 1421 1422
{
	int i;
	bool *unassigned = data;
1423

1424 1425
	for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
		struct resource *r = &dev->resource[i];
1426
		struct pci_bus_region region;
1427

1428
		/* Not assigned or rejected by kernel? */
1429 1430
		if (!r->flags)
			continue;
1431

1432
		pcibios_resource_to_bus(dev->bus, &region, r);
1433
		if (!region.start) {
1434 1435
			*unassigned = true;
			return 1; /* return early from pci_walk_bus() */
1436 1437 1438
		}
	}

1439
	return 0;
1440 1441
}

1442
static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1443
			 enum enable_type enable_local)
1444 1445
{
	bool unassigned = false;
1446

1447 1448
	if (enable_local != undefined)
		return enable_local;
1449

1450 1451 1452 1453 1454
	pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
	if (unassigned)
		return auto_enabled;

	return enable_local;
1455
}
1456
#else
1457
static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1458 1459 1460
			 enum enable_type enable_local)
{
	return enable_local;
1461
}
1462
#endif
1463

1464 1465
/*
 * first try will not touch pci bridge res
1466 1467
 * second and later try will clear small leaf bridge res
 * will stop till to the max depth if can not find good one
1468
 */
1469
void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
L
Linus Torvalds 已提交
1470
{
1471
	LIST_HEAD(realloc_head); /* list of resources that
1472
					want additional resources */
1473
	struct list_head *add_list = NULL;
1474 1475
	int tried_times = 0;
	enum release_type rel_type = leaf_only;
1476
	LIST_HEAD(fail_head);
1477
	struct pci_dev_resource *fail_res;
1478 1479
	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
				  IORESOURCE_PREFETCH;
1480
	int pci_try_num = 1;
1481
	enum enable_type enable_local;
1482

1483
	/* don't realloc if asked to do so */
1484
	enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1485
	if (pci_realloc_enabled(enable_local)) {
1486
		int max_depth = pci_bus_get_depth(bus);
1487 1488

		pci_try_num = max_depth + 1;
1489 1490 1491
		dev_printk(KERN_DEBUG, &bus->dev,
			   "max bus depth: %d pci_try_num: %d\n",
			   max_depth, pci_try_num);
1492
	}
1493 1494

again:
1495 1496 1497 1498 1499
	/*
	 * last try will use add_list, otherwise will try good to have as
	 * must have, so can realloc parent bridge resource
	 */
	if (tried_times + 1 == pci_try_num)
1500
		add_list = &realloc_head;
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Linus Torvalds 已提交
1501 1502
	/* Depth first, calculate sizes and alignments of all
	   subordinate buses. */
1503
	__pci_bus_size_bridges(bus, add_list);
1504

L
Linus Torvalds 已提交
1505
	/* Depth last, allocate resources and update the hardware. */
1506
	__pci_bus_assign_resources(bus, add_list, &fail_head);
1507
	if (add_list)
1508
		BUG_ON(!list_empty(add_list));
1509 1510 1511
	tried_times++;

	/* any device complain? */
1512
	if (list_empty(&fail_head))
1513
		goto dump;
1514

1515
	if (tried_times >= pci_try_num) {
1516
		if (enable_local == undefined)
1517
			dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1518
		else if (enable_local == auto_enabled)
1519
			dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1520

1521
		free_list(&fail_head);
1522
		goto dump;
1523 1524
	}

1525 1526
	dev_printk(KERN_DEBUG, &bus->dev,
		   "No. %d try to assign unassigned res\n", tried_times + 1);
1527 1528 1529 1530 1531 1532 1533 1534 1535

	/* third times and later will not check if it is leaf */
	if ((tried_times + 1) > 2)
		rel_type = whole_subtree;

	/*
	 * Try to release leaf bridge's resources that doesn't fit resource of
	 * child device under that bridge
	 */
1536 1537
	list_for_each_entry(fail_res, &fail_head, list)
		pci_bus_release_bridge_resources(fail_res->dev->bus,
1538
						 fail_res->flags & type_mask,
1539
						 rel_type);
1540

1541
	/* restore size and flags */
1542 1543
	list_for_each_entry(fail_res, &fail_head, list) {
		struct resource *res = fail_res->res;
1544

1545 1546 1547 1548
		res->start = fail_res->start;
		res->end = fail_res->end;
		res->flags = fail_res->flags;
		if (fail_res->dev->subordinate)
1549 1550
			res->flags = 0;
	}
1551
	free_list(&fail_head);
1552 1553 1554

	goto again;

1555
dump:
Y
Yinghai Lu 已提交
1556
	/* dump the resource on buses */
1557 1558 1559 1560 1561 1562 1563 1564 1565
	pci_bus_dump_resources(bus);
}

void __init pci_assign_unassigned_resources(void)
{
	struct pci_bus *root_bus;

	list_for_each_entry(root_bus, &pci_root_buses, node)
		pci_assign_unassigned_root_bus_resources(root_bus);
L
Linus Torvalds 已提交
1566
}
1567 1568 1569 1570

void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
{
	struct pci_bus *parent = bridge->subordinate;
1571
	LIST_HEAD(add_list); /* list of resources that
1572
					want additional resources */
1573
	int tried_times = 0;
1574
	LIST_HEAD(fail_head);
1575
	struct pci_dev_resource *fail_res;
1576
	int retval;
1577 1578 1579 1580
	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
				  IORESOURCE_PREFETCH;

again:
1581
	__pci_bus_size_bridges(parent, &add_list);
1582 1583
	__pci_bridge_assign_resources(bridge, &add_list, &fail_head);
	BUG_ON(!list_empty(&add_list));
1584 1585
	tried_times++;

1586
	if (list_empty(&fail_head))
1587
		goto enable_all;
1588 1589 1590

	if (tried_times >= 2) {
		/* still fail, don't need to try more */
1591
		free_list(&fail_head);
1592
		goto enable_all;
1593 1594 1595 1596 1597 1598 1599 1600 1601
	}

	printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
			 tried_times + 1);

	/*
	 * Try to release leaf bridge's resources that doesn't fit resource of
	 * child device under that bridge
	 */
1602 1603 1604
	list_for_each_entry(fail_res, &fail_head, list)
		pci_bus_release_bridge_resources(fail_res->dev->bus,
						 fail_res->flags & type_mask,
1605
						 whole_subtree);
1606

1607
	/* restore size and flags */
1608 1609
	list_for_each_entry(fail_res, &fail_head, list) {
		struct resource *res = fail_res->res;
1610

1611 1612 1613 1614
		res->start = fail_res->start;
		res->end = fail_res->end;
		res->flags = fail_res->flags;
		if (fail_res->dev->subordinate)
1615 1616
			res->flags = 0;
	}
1617
	free_list(&fail_head);
1618 1619

	goto again;
1620 1621 1622

enable_all:
	retval = pci_reenable_device(bridge);
1623 1624
	if (retval)
		dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval);
1625
	pci_set_master(bridge);
1626 1627
}
EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
1628

1629
void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
1630 1631
{
	struct pci_dev *dev;
1632
	LIST_HEAD(add_list); /* list of resources that
1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643
					want additional resources */

	down_read(&pci_bus_sem);
	list_for_each_entry(dev, &bus->devices, bus_list)
		if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
		    dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
			if (dev->subordinate)
				__pci_bus_size_bridges(dev->subordinate,
							 &add_list);
	up_read(&pci_bus_sem);
	__pci_bus_assign_resources(bus, &add_list, NULL);
1644
	BUG_ON(!list_empty(&add_list));
1645
}