dcn10_opp.h

/* Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DC_OPP_DCN10_H__
#define __DC_OPP_DCN10_H__

#include "opp.h"

#define TO_DCN10_OPP(opp)\
	container_of(opp, struct dcn10_opp, base)

#define OPP_SF(reg_name, field_name, post_fix)\
	.field_name = reg_name ## __ ## field_name ## post_fix

#define OPP_REG_LIST_DCN(id) \
	SRI(OBUF_CONTROL, DSCL, id), \
	SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
	SRI(FMT_CONTROL, FMT, id), \
	SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
	SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
	SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
	SRI(FMT_CLAMP_CNTL, FMT, id), \
	SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
	SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id)

#define OPP_REG_LIST_DCN10(id) \
	OPP_REG_LIST_DCN(id), \
	SRI(CM_OCSC_C11_C12, CM, id), \
	SRI(CM_OCSC_C13_C14, CM, id), \
	SRI(CM_OCSC_C21_C22, CM, id), \
	SRI(CM_OCSC_C23_C24, CM, id), \
	SRI(CM_OCSC_C31_C32, CM, id), \
	SRI(CM_OCSC_C33_C34, CM, id), \
	SRI(CM_COMB_C11_C12, CM, id), \
	SRI(CM_COMB_C13_C14, CM, id), \
	SRI(CM_COMB_C21_C22, CM, id), \
	SRI(CM_COMB_C23_C24, CM, id), \
	SRI(CM_COMB_C31_C32, CM, id), \
	SRI(CM_COMB_C33_C34, CM, id), \
	SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id), \
	SRI(CM_RGAM_CONTROL, CM, id), \
	SRI(CM_OCSC_CONTROL, CM, id), \
	SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \
	SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \
	SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \
	SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \
	SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \
	SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \
	SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \
	SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \
	SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \
	SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \
	SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \
	SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_2_3, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_4_5, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_6_7, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_8_9, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_10_11, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_12_13, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_14_15, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_16_17, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_18_19, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_20_21, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_22_23, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_24_25, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_26_27, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_28_29, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_30_31, CM, id), \
	SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \
	SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \
	SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \
	SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \
	SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \
	SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \
	SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \
	SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \
	SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \
	SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \
	SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \
	SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \
	SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_2_3, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_4_5, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_6_7, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_8_9, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_10_11, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_12_13, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_14_15, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_16_17, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_18_19, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_20_21, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_22_23, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_24_25, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_26_27, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_28_29, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_30_31, CM, id), \
	SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \
	SRI(CM_RGAM_LUT_INDEX, CM, id), \
	SRI(CM_MEM_PWR_CTRL, CM, id), \
	SRI(CM_RGAM_LUT_DATA, CM, id)


#define OPP_MASK_SH_LIST_DCN(mask_sh) \
	OPP_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \
	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \
	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \
	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh), \
	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh), \
	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh), \
	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh), \
	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \
	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \
	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \
	OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \
	OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \
	OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \
	OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \
	OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \
	OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \
	OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \
	OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \
	OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \
	OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \
	OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh)

#define OPP_MASK_SH_LIST_DCN10(mask_sh) \
	OPP_MASK_SH_LIST_DCN(mask_sh), \
	OPP_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \
	OPP_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \
	OPP_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
	OPP_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C13, mask_sh), \
	OPP_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C14, mask_sh), \
	OPP_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C21, mask_sh), \
	OPP_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C22, mask_sh), \
	OPP_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C23, mask_sh), \
	OPP_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C24, mask_sh), \
	OPP_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C31, mask_sh), \
	OPP_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C32, mask_sh), \
	OPP_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
	OPP_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
	OPP_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh), \
	OPP_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh), \
	OPP_SF(CM0_CM_COMB_C13_C14, CM_COMB_C13, mask_sh), \
	OPP_SF(CM0_CM_COMB_C13_C14, CM_COMB_C14, mask_sh), \
	OPP_SF(CM0_CM_COMB_C21_C22, CM_COMB_C21, mask_sh), \
	OPP_SF(CM0_CM_COMB_C21_C22, CM_COMB_C22, mask_sh), \
	OPP_SF(CM0_CM_COMB_C23_C24, CM_COMB_C23, mask_sh), \
	OPP_SF(CM0_CM_COMB_C23_C24, CM_COMB_C24, mask_sh), \
	OPP_SF(CM0_CM_COMB_C31_C32, CM_COMB_C31, mask_sh), \
	OPP_SF(CM0_CM_COMB_C31_C32, CM_COMB_C32, mask_sh), \
	OPP_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh), \
	OPP_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh), \
	OPP_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
	OPP_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
	OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
	OPP_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \
	OPP_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \
	OPP_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \
	OPP_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
	OPP_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \
	OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)

#define OPP_DCN10_REG_FIELD_LIST(type) \
	type CM_OCSC_C11; \
	type CM_OCSC_C12; \
	type CM_OCSC_C13; \
	type CM_OCSC_C14; \
	type CM_OCSC_C21; \
	type CM_OCSC_C22; \
	type CM_OCSC_C23; \
	type CM_OCSC_C24; \
	type CM_OCSC_C31; \
	type CM_OCSC_C32; \
	type CM_OCSC_C33; \
	type CM_OCSC_C34; \
	type CM_COMB_C11; \
	type CM_COMB_C12; \
	type CM_COMB_C13; \
	type CM_COMB_C14; \
	type CM_COMB_C21; \
	type CM_COMB_C22; \
	type CM_COMB_C23; \
	type CM_COMB_C24; \
	type CM_COMB_C31; \
	type CM_COMB_C32; \
	type CM_COMB_C33; \
	type CM_COMB_C34; \
	type CM_RGAM_LUT_MODE; \
	type OBUF_BYPASS; \
	type OBUF_H_2X_UPSCALE_EN; \
	type FMT_TRUNCATE_EN; \
	type FMT_TRUNCATE_DEPTH; \
	type FMT_TRUNCATE_MODE; \
	type FMT_SPATIAL_DITHER_EN; \
	type FMT_SPATIAL_DITHER_MODE; \
	type FMT_SPATIAL_DITHER_DEPTH; \
	type FMT_TEMPORAL_DITHER_EN; \
	type FMT_HIGHPASS_RANDOM_ENABLE; \
	type FMT_FRAME_RANDOM_ENABLE; \
	type FMT_RGB_RANDOM_ENABLE; \
	type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \
	type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \
	type FMT_RAND_R_SEED; \
	type FMT_RAND_G_SEED; \
	type FMT_RAND_B_SEED; \
	type FMT_PIXEL_ENCODING; \
	type FMT_CLAMP_DATA_EN; \
	type FMT_CLAMP_COLOR_FORMAT; \
	type FMT_DYNAMIC_EXP_EN; \
	type FMT_DYNAMIC_EXP_MODE; \
	type FMT_MAP420MEM_PWR_FORCE; \
	type CM_OCSC_MODE; \
	type CM_RGAM_RAMB_EXP_REGION_START_B; \
	type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
	type CM_RGAM_RAMB_EXP_REGION_START_G; \
	type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
	type CM_RGAM_RAMB_EXP_REGION_START_R; \
	type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
	type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
	type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
	type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
	type CM_RGAM_RAMB_EXP_REGION_END_B; \
	type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; \
	type CM_RGAM_RAMB_EXP_REGION_END_BASE_B; \
	type CM_RGAM_RAMB_EXP_REGION_END_G; \
	type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G; \
	type CM_RGAM_RAMB_EXP_REGION_END_BASE_G; \
	type CM_RGAM_RAMB_EXP_REGION_END_R; \
	type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R; \
	type CM_RGAM_RAMB_EXP_REGION_END_BASE_R; \
	type CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \
	type CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET; \
	type CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION_START_B; \
	type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
	type CM_RGAM_RAMA_EXP_REGION_START_G; \
	type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
	type CM_RGAM_RAMA_EXP_REGION_START_R; \
	type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
	type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
	type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
	type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
	type CM_RGAM_RAMA_EXP_REGION_END_B; \
	type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B; \
	type CM_RGAM_RAMA_EXP_REGION_END_BASE_B; \
	type CM_RGAM_RAMA_EXP_REGION_END_G; \
	type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G; \
	type CM_RGAM_RAMA_EXP_REGION_END_BASE_G; \
	type CM_RGAM_RAMA_EXP_REGION_END_R; \
	type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R; \
	type CM_RGAM_RAMA_EXP_REGION_END_BASE_R; \
	type CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \
	type CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET; \
	type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
	type CM_RGAM_LUT_WRITE_EN_MASK; \
	type CM_RGAM_LUT_WRITE_SEL; \
	type CM_RGAM_LUT_INDEX; \
	type RGAM_MEM_PWR_FORCE; \
	type CM_RGAM_LUT_DATA; \
	type FMT_STEREOSYNC_OVERRIDE

struct dcn10_opp_shift {
	OPP_DCN10_REG_FIELD_LIST(uint8_t);
};

struct dcn10_opp_mask {
	OPP_DCN10_REG_FIELD_LIST(uint32_t);
};

struct dcn10_opp_registers {
	uint32_t CM_OCSC_C11_C12;
	uint32_t CM_OCSC_C13_C14;
	uint32_t CM_OCSC_C21_C22;
	uint32_t CM_OCSC_C23_C24;
	uint32_t CM_OCSC_C31_C32;
	uint32_t CM_OCSC_C33_C34;
	uint32_t CM_COMB_C11_C12;
	uint32_t CM_COMB_C13_C14;
	uint32_t CM_COMB_C21_C22;
	uint32_t CM_COMB_C23_C24;
	uint32_t CM_COMB_C31_C32;
	uint32_t CM_COMB_C33_C34;
	uint32_t CM_RGAM_LUT_WRITE_EN_MASK;
	uint32_t CM_RGAM_CONTROL;
	uint32_t OBUF_CONTROL;
	uint32_t FMT_BIT_DEPTH_CONTROL;
	uint32_t FMT_CONTROL;
	uint32_t FMT_DITHER_RAND_R_SEED;
	uint32_t FMT_DITHER_RAND_G_SEED;
	uint32_t FMT_DITHER_RAND_B_SEED;
	uint32_t FMT_CLAMP_CNTL;
	uint32_t FMT_DYNAMIC_EXP_CNTL;
	uint32_t FMT_MAP420_MEMORY_CONTROL;
	uint32_t CM_OCSC_CONTROL;
	uint32_t CM_RGAM_RAMB_START_CNTL_B;
	uint32_t CM_RGAM_RAMB_START_CNTL_G;
	uint32_t CM_RGAM_RAMB_START_CNTL_R;
	uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B;
	uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G;
	uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R;
	uint32_t CM_RGAM_RAMB_END_CNTL1_B;
	uint32_t CM_RGAM_RAMB_END_CNTL2_B;
	uint32_t CM_RGAM_RAMB_END_CNTL1_G;
	uint32_t CM_RGAM_RAMB_END_CNTL2_G;
	uint32_t CM_RGAM_RAMB_END_CNTL1_R;
	uint32_t CM_RGAM_RAMB_END_CNTL2_R;
	uint32_t CM_RGAM_RAMB_REGION_0_1;
	uint32_t CM_RGAM_RAMB_REGION_2_3;
	uint32_t CM_RGAM_RAMB_REGION_4_5;
	uint32_t CM_RGAM_RAMB_REGION_6_7;
	uint32_t CM_RGAM_RAMB_REGION_8_9;
	uint32_t CM_RGAM_RAMB_REGION_10_11;
	uint32_t CM_RGAM_RAMB_REGION_12_13;
	uint32_t CM_RGAM_RAMB_REGION_14_15;
	uint32_t CM_RGAM_RAMB_REGION_16_17;
	uint32_t CM_RGAM_RAMB_REGION_18_19;
	uint32_t CM_RGAM_RAMB_REGION_20_21;
	uint32_t CM_RGAM_RAMB_REGION_22_23;
	uint32_t CM_RGAM_RAMB_REGION_24_25;
	uint32_t CM_RGAM_RAMB_REGION_26_27;
	uint32_t CM_RGAM_RAMB_REGION_28_29;
	uint32_t CM_RGAM_RAMB_REGION_30_31;
	uint32_t CM_RGAM_RAMB_REGION_32_33;
	uint32_t CM_RGAM_RAMA_START_CNTL_B;
	uint32_t CM_RGAM_RAMA_START_CNTL_G;
	uint32_t CM_RGAM_RAMA_START_CNTL_R;
	uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B;
	uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G;
	uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R;
	uint32_t CM_RGAM_RAMA_END_CNTL1_B;
	uint32_t CM_RGAM_RAMA_END_CNTL2_B;
	uint32_t CM_RGAM_RAMA_END_CNTL1_G;
	uint32_t CM_RGAM_RAMA_END_CNTL2_G;
	uint32_t CM_RGAM_RAMA_END_CNTL1_R;
	uint32_t CM_RGAM_RAMA_END_CNTL2_R;
	uint32_t CM_RGAM_RAMA_REGION_0_1;
	uint32_t CM_RGAM_RAMA_REGION_2_3;
	uint32_t CM_RGAM_RAMA_REGION_4_5;
	uint32_t CM_RGAM_RAMA_REGION_6_7;
	uint32_t CM_RGAM_RAMA_REGION_8_9;
	uint32_t CM_RGAM_RAMA_REGION_10_11;
	uint32_t CM_RGAM_RAMA_REGION_12_13;
	uint32_t CM_RGAM_RAMA_REGION_14_15;
	uint32_t CM_RGAM_RAMA_REGION_16_17;
	uint32_t CM_RGAM_RAMA_REGION_18_19;
	uint32_t CM_RGAM_RAMA_REGION_20_21;
	uint32_t CM_RGAM_RAMA_REGION_22_23;
	uint32_t CM_RGAM_RAMA_REGION_24_25;
	uint32_t CM_RGAM_RAMA_REGION_26_27;
	uint32_t CM_RGAM_RAMA_REGION_28_29;
	uint32_t CM_RGAM_RAMA_REGION_30_31;
	uint32_t CM_RGAM_RAMA_REGION_32_33;
	uint32_t CM_RGAM_LUT_INDEX;
	uint32_t CM_MEM_PWR_CTRL;
	uint32_t CM_RGAM_LUT_DATA;
};

struct dcn10_opp {
	struct output_pixel_processor base;

	const struct dcn10_opp_registers *regs;
	const struct dcn10_opp_shift *opp_shift;
	const struct dcn10_opp_mask *opp_mask;

	bool is_write_to_ram_a_safe;
};

void dcn10_opp_construct(struct dcn10_opp *oppn10,
	struct dc_context *ctx,
	uint32_t inst,
	const struct dcn10_opp_registers *regs,
	const struct dcn10_opp_shift *opp_shift,
	const struct dcn10_opp_mask *opp_mask);

#endif