ct-ca9x4.c 5.1 KB
Newer Older
1 2 3 4
/*
 * Versatile Express Core Tile Cortex A9x4 Support
 */
#include <linux/init.h>
T
Tejun Heo 已提交
5
#include <linux/gfp.h>
6 7
#include <linux/device.h>
#include <linux/dma-mapping.h>
8
#include <linux/platform_device.h>
9 10
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
11
#include <linux/clkdev.h>
12 13 14 15

#include <asm/hardware/arm_timer.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
16
#include <asm/pmu.h>
17
#include <asm/smp_scu.h>
18
#include <asm/smp_twd.h>
19 20 21

#include <mach/ct-ca9x4.h>

22
#include <asm/hardware/timer-sp.h>
23 24 25 26 27 28 29 30

#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include "core.h"

#include <mach/motherboard.h>

31 32
#include <plat/clcd.h>

33 34
static struct map_desc ct_ca9x4_io_desc[] __initdata = {
	{
P
Pawel Moll 已提交
35 36 37 38
		.virtual        = V2T_PERIPH,
		.pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
		.length         = SZ_8K,
		.type           = MT_DEVICE,
39 40 41 42 43
	},
};

static void __init ct_ca9x4_map_io(void)
{
P
Pawel Moll 已提交
44
	iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
45 46
}

47 48 49 50 51 52 53 54 55 56 57 58 59
#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);

static void __init ca9x4_twd_init(void)
{
	int err = twd_local_timer_register(&twd_local_timer);
	if (err)
		pr_err("twd_local_timer_register failed %d\n", err);
}
#else
#define ca9x4_twd_init()	do {} while(0)
#endif

60 61
static void __init ct_ca9x4_init_irq(void)
{
P
Pawel Moll 已提交
62 63
	gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
		 ioremap(A9_MPCORE_GIC_CPU, SZ_256));
64
	ca9x4_twd_init();
65 66 67 68
}

static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
69 70 71 72 73 74 75 76 77
	u32 site = v2m_get_master_site();

	/*
	 * Old firmware was using the "site" component of the command
	 * to control the DVI muxer (while it should be always 0 ie. MB).
	 * Newer firmware uses the data register. Keep both for compatibility.
	 */
	v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site);
	v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2);
78 79 80 81 82 83
}

static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
{
	unsigned long framesize = 1024 * 768 * 2;

84 85 86
	fb->panel = versatile_clcd_get_panel("XVGA");
	if (!fb->panel)
		return -EINVAL;
87

88
	return versatile_clcd_setup_dma(fb, framesize);
89 90 91 92
}

static struct clcd_board ct_ca9x4_clcd_data = {
	.name		= "CT-CA9X4",
93
	.caps		= CLCD_CAP_5551 | CLCD_CAP_565,
94 95 96 97
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= ct_ca9x4_clcd_enable,
	.setup		= ct_ca9x4_clcd_setup,
98 99
	.mmap		= versatile_clcd_mmap_dma,
	.remove		= versatile_clcd_remove_dma,
100 101
};

102 103 104 105
static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);
static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);
static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);
106 107 108 109 110 111 112 113 114

static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
	&clcd_device,
	&dmc_device,
	&smc_device,
	&gpio_device,
};


115 116 117 118 119
static struct v2m_osc ct_osc1 = {
	.osc = 1,
	.rate_min = 10000000,
	.rate_max = 80000000,
	.rate_default = 23750000,
120 121
};

122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151
static struct resource pmu_resources[] = {
	[0] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU0,
		.end	= IRQ_CT_CA9X4_PMU_CPU0,
		.flags	= IORESOURCE_IRQ,
	},
	[1] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU1,
		.end	= IRQ_CT_CA9X4_PMU_CPU1,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU2,
		.end	= IRQ_CT_CA9X4_PMU_CPU2,
		.flags	= IORESOURCE_IRQ,
	},
	[3] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU3,
		.end	= IRQ_CT_CA9X4_PMU_CPU3,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device pmu_device = {
	.name		= "arm-pmu",
	.id		= ARM_PMU_DEVICE_CPU,
	.num_resources	= ARRAY_SIZE(pmu_resources),
	.resource	= pmu_resources,
};

152
static void __init ct_ca9x4_init(void)
153 154
{
	int i;
155
	struct clk *clk;
156 157

#ifdef CONFIG_CACHE_L2X0
P
Pawel Moll 已提交
158
	void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
159 160 161 162 163 164

	/* set RAM latencies to 1 cycle for this core tile. */
	writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
	writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);

	l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
165 166
#endif

167 168 169 170
	ct_osc1.site = v2m_get_master_site();
	clk = v2m_osc_register("ct:osc1", &ct_osc1);
	clk_register_clkdev(clk, NULL, "ct:clcd");

171 172
	for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
		amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
173 174

	platform_device_register(&pmu_device);
175 176
}

177
#ifdef CONFIG_SMP
P
Pawel Moll 已提交
178 179
static void *ct_ca9x4_scu_base __initdata;

180
static void __init ct_ca9x4_init_cpu_map(void)
181
{
P
Pawel Moll 已提交
182 183 184 185 186 187 188
	int i, ncores;

	ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);
	if (WARN_ON(!ct_ca9x4_scu_base))
		return;

	ncores = scu_get_core_count(ct_ca9x4_scu_base);
189

190 191 192 193 194 195
	if (ncores > nr_cpu_ids) {
		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
			ncores, nr_cpu_ids);
		ncores = nr_cpu_ids;
	}

196 197
	for (i = 0; i < ncores; ++i)
		set_cpu_possible(i, true);
198 199

	set_smp_cross_call(gic_raise_softirq);
200 201
}

202
static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
203
{
P
Pawel Moll 已提交
204
	scu_enable(ct_ca9x4_scu_base);
205 206 207 208 209 210
}
#endif

struct ct_desc ct_ca9x4_desc __initdata = {
	.id		= V2M_CT_ID_CA9,
	.name		= "CA9x4",
211
	.map_io		= ct_ca9x4_map_io,
212 213 214 215 216
	.init_irq	= ct_ca9x4_init_irq,
	.init_tile	= ct_ca9x4_init,
#ifdef CONFIG_SMP
	.init_cpu_map	= ct_ca9x4_init_cpu_map,
	.smp_enable	= ct_ca9x4_smp_enable,
217
#endif
218
};