Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes
Reviewed-by: iveresov, phh, twisti

Reviewed-by: kvn, never, bdelsart

Summary: Use new short branch instruction in C2 generated code.
Reviewed-by: never

Summary: replace MemBarAcquire/MemBarRelease nodes on the monitor enter/exit code paths with new MemBarAcquireLock/MemBarReleaseLock nodes
Reviewed-by: kvn, twisti

Reviewed-by: kvn, twisti

Reviewed-by: gbenson, twisti
Contributed-by: NChris Phillips <chphilli@redhat.com>

Reviewed-by: jrose, twisti
Contributed-by: NXerxes Ranby <xerxes@zafena.se>

Summary: Remove flags which duplicate information in Node::NodeClasses.
Reviewed-by: never

Summary: Add new short branch instruction to Hotspot sparc assembler.
Reviewed-by: never, twisti, jrose

Summary: check for single stepping when dispatching invokes from method handles
Reviewed-by: coleenp, twisti, kvn, dsamersoff

Summary: Use new VIS3 mov instructions on T4 for move data between general and float registers.
Reviewed-by: never, twisti

Summary: correct Icache::line_size for x64 and add verification code into vm_version_x86.
Reviewed-by: never, phh

Reviewed-by: never

Summary: code was using andq reg, imm instead of addq addr, imm
Reviewed-by: kvn, jrose, twisti

Reviewed-by: jrose, twisti, bdelsart

Reviewed-by: twisti, kvn, jrose

Reviewed-by: never, twisti

Reviewed-by: kvn, jrose

Summary: Save and restore the argument registers around the call to checkcast_arraycopy
Reviewed-by: never, roland

Summary: Use ins_encode %{ %} form to encode cadd_cmpLTMask() instruction and remove unused code.
Reviewed-by: never

Summary: Fixed invalid casts in address computation
Reviewed-by: kvn, never
Contributed-by: thomas.salter@unisys.com

Reviewed-by: jrose

Reviewed-by: jrose, kvn, never

Reviewed-by: kvn, coleenp

Reviewed-by: kvn

Reviewed-by: twisti, jrose

Summary: Fix integer overflow problem in the code generated by loop optimizer.
Reviewed-by: never

Reviewed-by: iveresov, kvn, never

Reviewed-by: kvn, twisti

Reviewed-by: kvn, never

Reviewed-by: kvn, jrose, twisti

Summary: use PREFETCHW as default prefetch instruction, set UseXMMForArrayCopy and UseUnalignedLoadStores to true by default.
Reviewed-by: kvn
Contributed-by: tom.deneau@amd.com

Summary: Use LIR_OprDesc::as_pointer_register() instead as_register/as_register_lo combination in the code changes for 7035117.
Reviewed-by: iveresov

Reviewed-by: kvn, iveresov

Summary: Allow long type for offset in G1 code in compiler implementations of Unsafe.getObject
Reviewed-by: never, iveresov

Summary: This adds support for JSR 292 to Zero.
Reviewed-by: twisti
Contributed-by: NGary Benson <gbenson@redhat.com>

Summary: The upcoming processors from AMD are the first that support 3dnow prefetch without supporting the 3dnow instruction set.
Reviewed-by: kvn
Contributed-by: tom.deneau@amd.com

Summary: Fix -XX:+VerifyOops
Reviewed-by: kvn, never

Summary: A referent object that is only weakly reachable at the start of concurrent marking but is re-attached to the strongly reachable object graph during marking may not be marked as live. This can cause the reference object to be processed prematurely and leave dangling pointers to the referent object. Implement a read barrier for the java.lang.ref.Reference::referent field by intrinsifying the Reference.get() method, and intercepting accesses though JNI, reflection, and Unsafe, so that when a non-null referent object is read it is also logged in an SATB buffer.
Reviewed-by: kvn, iveresov, never, tonyp, dholmes

7010070: Update all 2010 Oracle-changed OpenJDK files to have the proper copyright dates - second pass
Summary: Update the copyright to be 2010 on all changed files in OpenJDK
Reviewed-by: ohair