Summary: HotSpot changes to support @Contended annotation.
Reviewed-by: coleenp, kvn, jrose
Contributed-by: NAleksey Shipilev <aleksey.shipilev@oracle.com>

Summary: Enable AES intrinsics on non-AVX cpus, group together aes instructions in crypto stubs.
Reviewed-by: roland, twisti

Reviewed-by: kvn

Summary: Add missing UseSSE check for AES intrinsics.
Reviewed-by: roland, twisti

Summary: Use new x86 AES instructions for AESCrypt.
Reviewed-by: twisti, kvn, roland
Contributed-by: tom.deneau@amd.com

Summary: renamed mach nodes which use scalar AVX instructions, added integer vectors shuffling instructions
Reviewed-by: twisti

Summary: Increase vector size up to 256-bits for YMM AVX registers on x86.
Reviewed-by: never, twisti, roland

Summary: use shorter instruction sequences for atomic add and atomic exchange when possible.
Reviewed-by: kvn, jrose

Summary: Fixed vectors alignment when several arrays are accessed in one loop.
Reviewed-by: roland, twisti

Summary: Change OSThread to use mach thread_t
Reviewed-by: phh, dcubed

Summary: Add rdtsc detection and inline generation.
Reviewed-by: kamg, dholmes
Contributed-by: karen.kinnear@oracle.com

Summary: Added support for AVX extension to the x86 instruction set.
Reviewed-by: never

Reviewed-by: kvn, twisti, jrose
Contributed-by: NKurt Miller &lt;kurt@intricatesoftware.com&gt;, Greg Lewis &lt;glewis@eyesbeyond.com&gt;, Jung-uk Kim &lt;jkim@freebsd.org&gt;, Christos Zoulas &lt;christos@zoulas.com&gt;, Landon Fuller &lt;landonf@plausible.coop&gt;, The FreeBSD Foundation &lt;board@freebsdfoundation.org&gt;, Michael Franz &lt;mvfranz@gmail.com&gt;, Roger Hoover &lt;rhoover@apple.com&gt;, Alexander Strange <astrange@apple.com>

Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes
Reviewed-by: iveresov, phh, twisti

Summary: correct Icache::line_size for x64 and add verification code into vm_version_x86.
Reviewed-by: never, phh

Summary: use PREFETCHW as default prefetch instruction, set UseXMMForArrayCopy and UseUnalignedLoadStores to true by default.
Reviewed-by: kvn
Contributed-by: tom.deneau@amd.com

7044486: open jdk repos have files with incorrect copyright headers, which can end up in src bundles
Reviewed-by: ohair, trims

Summary: The upcoming processors from AMD are the first that support 3dnow prefetch without supporting the 3dnow instruction set.
Reviewed-by: kvn
Contributed-by: tom.deneau@amd.com

7010070: Update all 2010 Oracle-changed OpenJDK files to have the proper copyright dates - second pass
Summary: Update the copyright to be 2010 on all changed files in OpenJDK
Reviewed-by: ohair

Summary: New AMD processors support sse4.2. Enable corresponding instructions in Hotspot.
Reviewed-by: kvn
Contributed-by: eric.caspole@amd.com

Summary: This new default has shown improvement across many workloads.
Reviewed-by: kvn
Contributed-by: tom.deneau@amd.com

Summary: Replaced MakeDeps and the includeDB files with more standardized solutions.
Reviewed-by: coleenp, kvn, kamg

Summary: This is the renaming part of 6961697 to keep the actual changes small for review.
Reviewed-by: kvn, never

Reviewed-by: kvn

Summary: Adjust performance flags settings.
Reviewed-by: never, phh

Summary: Change all the Sun copyrights to Oracle copyright
Reviewed-by: ohair

Reviewed-by: never

Summary: These methods can be instrinsified by using bit scan, bit test, and population count instructions.
Reviewed-by: kvn, never

Summary: Use SSE 4.2 in intrinsics for String.{compareTo/equals/indexOf} and Arrays.equals.
Reviewed-by: kvn, never, jrose

Summary: bitCount() should use POPC on SPARC processors where POPC is implemented directly in hardware.
Reviewed-by: kvn, never

Summary: There is very much duplicated code in vm_version_x86_{32,64}.{cpp,hpp}.  Refactoring these would help maintainability.
Reviewed-by: kvn, never

Summary: Use SSE2 movdqu in arraycopy stubs on newest Intel's cpus
Reviewed-by: rasbold

6459804: Want client (c1) compiler for x86_64 (amd64) for faster start-up
Reviewed-by: kvn

Summary: Update copyright year for files that have been modified in 2008
Reviewed-by: ohair, tbell

Summary: For small (1-3 bits) left long shifts in 32-bits VM use sets of add+addc instructions instead of shld+shl on new AMD cpus.
Reviewed-by: never
Contributed-by: shrinivas.joshi@amd.com

Summary: Use CVTDQ2PS and CVTDQ2PD for integer values conversions to float and double values on new AMD cpu.
Reviewed-by: sgoldman, never